Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/mips/vm/assembler_mips.cpp	Mon Oct 23 17:07:19 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/assembler_mips.cpp	Tue Oct 24 14:04:09 2017 +0800
     1.3 @@ -319,11 +319,46 @@
     1.4    lw(rt, src.base(), src.disp());
     1.5  }
     1.6  void Assembler::lea(Register rt, Address src) {
     1.7 -#ifdef _LP64
     1.8 -  daddi(rt, src.base(), src.disp());
     1.9 -#else
    1.10 -  addi(rt, src.base(), src.disp());
    1.11 -#endif
    1.12 +  Register dst   = rt;
    1.13 +  Register base  = src.base();
    1.14 +  Register index = src.index();
    1.15 +
    1.16 +  int scale = src.scale();
    1.17 +  int disp  = src.disp();
    1.18 +
    1.19 +  if (index == noreg) {
    1.20 +    if (is_simm16(disp)) {
    1.21 +      daddiu(dst, base, disp);
    1.22 +    } else {
    1.23 +      lui(AT, split_low(disp >> 16));
    1.24 +      if (split_low(disp)) ori(AT, AT, split_low(disp));
    1.25 +      daddu(dst, base, AT);
    1.26 +    }
    1.27 +  } else {
    1.28 +    if (scale == 0) {
    1.29 +      if (is_simm16(disp)) {
    1.30 +        daddu(AT, base, index);
    1.31 +        daddiu(dst, AT, disp);
    1.32 +      } else {
    1.33 +        lui(AT, split_low(disp >> 16));
    1.34 +        if (split_low(disp)) ori(AT, AT, split_low(disp));
    1.35 +        daddu(AT, base, AT);
    1.36 +        daddu(dst, AT, index);
    1.37 +      }
    1.38 +    } else {
    1.39 +      if (is_simm16(disp)) {
    1.40 +        dsll(AT, index, scale);
    1.41 +        daddu(AT, AT, base);
    1.42 +        daddiu(dst, AT, disp);
    1.43 +      } else {
    1.44 +        lui(AT, split_low(disp >> 16));
    1.45 +        if (split_low(disp)) ori(AT, AT, split_low(disp));
    1.46 +        daddu(AT, AT, base);
    1.47 +        dsll(dst, index, scale);
    1.48 +        daddu(dst, dst, AT);
    1.49 +      }
    1.50 +    }
    1.51 +  } 
    1.52  }
    1.53  
    1.54  void Assembler::lwl(Register rt, Address src){
    1.55 @@ -351,7 +386,70 @@
    1.56  }
    1.57  
    1.58  void Assembler::sd(Register rt, Address dst) {
    1.59 -  sd(rt, dst.base(), dst.disp());
    1.60 +  Register src   = rt;
    1.61 +  Register base  = dst.base();
    1.62 +  Register index = dst.index();
    1.63 +
    1.64 +  int scale = dst.scale();
    1.65 +  int disp  = dst.disp();
    1.66 +
    1.67 +  if(index != noreg) {
    1.68 +    if(is_simm16(disp)) {
    1.69 +      if( UseLoongsonISA && is_simm(disp, 8)) {
    1.70 +        if (scale == 0) {
    1.71 +          gssdx(src, base, index, disp);
    1.72 +        } else {
    1.73 +          dsll(AT, index, scale);
    1.74 +          gssdx(src, base, AT, disp);
    1.75 +        }
    1.76 +      } else {
    1.77 +        if (scale == 0) {
    1.78 +          daddu(AT, base, index);
    1.79 +        } else {
    1.80 +          dsll(AT, index, scale);
    1.81 +          daddu(AT, base, AT);
    1.82 +        }
    1.83 +        sd(src, AT, disp);
    1.84 +      }
    1.85 +    } else {
    1.86 +      if (scale == 0) {
    1.87 +        lui(AT, split_low(disp >> 16));
    1.88 +        if (split_low(disp)) ori(AT, AT, split_low(disp));
    1.89 +        daddu(AT, AT, base);
    1.90 +        if(UseLoongsonISA) {
    1.91 +          gssdx(src, AT, index, 0);
    1.92 +        } else {
    1.93 +          daddu(AT, AT, index);
    1.94 +          sd(src, AT, 0);
    1.95 +        }
    1.96 +      } else {
    1.97 +        dsll(AT, index, scale);
    1.98 +        daddu(AT, base, AT);
    1.99 +        lui(T9, split_low(disp >> 16));
   1.100 +        if (split_low(disp)) ori(T9, T9, split_low(disp));
   1.101 +        if(UseLoongsonISA) {
   1.102 +          gssdx(src, AT, T9, 0);
   1.103 +        } else {
   1.104 +          daddu(AT, AT, T9);
   1.105 +          sd(src, AT, 0);
   1.106 +        }
   1.107 +      }
   1.108 +    }
   1.109 +  } else {
   1.110 +    if(is_simm16(disp)) {
   1.111 +      sd(src, base, disp);
   1.112 +    } else {
   1.113 +      lui(AT, split_low(disp >> 16));
   1.114 +      if (split_low(disp)) ori(AT, AT, split_low(disp));
   1.115 +
   1.116 +      if(UseLoongsonISA) {
   1.117 +        gssdx(src, base, AT, 0);
   1.118 +      } else {
   1.119 +        daddu(AT, base, AT);
   1.120 +        sd(src, AT, 0);
   1.121 +      }
   1.122 +    }
   1.123 +  }
   1.124  }
   1.125  
   1.126  void Assembler::sdl(Register rt, Address dst) {
   1.127 @@ -367,7 +465,70 @@
   1.128  }
   1.129  
   1.130  void Assembler::sw(Register rt, Address dst) {
   1.131 -  sw(rt, dst.base(), dst.disp());
   1.132 +  Register src   = rt;
   1.133 +  Register base  = dst.base();
   1.134 +  Register index = dst.index();
   1.135 +
   1.136 +  int scale = dst.scale();
   1.137 +  int disp  = dst.disp();
   1.138 +
   1.139 +  if(index != noreg) {
   1.140 +    if( Assembler::is_simm16(disp) ) {
   1.141 +      if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
   1.142 +        if (scale == 0) {
   1.143 +          gsswx(src, base, index, disp);
   1.144 +        } else {
   1.145 +          dsll(AT, index, scale);
   1.146 +          gsswx(src, base, AT, disp);
   1.147 +        }
   1.148 +      } else {
   1.149 +        if (scale == 0) {
   1.150 +          daddu(AT, base, index);
   1.151 +        } else {
   1.152 +          dsll(AT, index, scale);
   1.153 +          daddu(AT, base, AT);
   1.154 +        }
   1.155 +        sw(src, AT, disp);
   1.156 +      }
   1.157 +    } else {
   1.158 +      if (scale == 0) {
   1.159 +        lui(AT, split_low(disp >> 16));
   1.160 +        if (split_low(disp)) ori(AT, AT, split_low(disp));
   1.161 +        daddu(AT, AT, base);
   1.162 +        if( UseLoongsonISA ) {
   1.163 +          gsswx(src, AT, index, 0);
   1.164 +        } else {
   1.165 +          daddu(AT, AT, index);
   1.166 +          sw(src, AT, 0);
   1.167 +        }
   1.168 +      } else {
   1.169 +        dsll(AT, index, scale);
   1.170 +        daddu(AT, base, AT);
   1.171 +        lui(T9, split_low(disp >> 16));
   1.172 +        if (split_low(disp)) ori(T9, T9, split_low(disp));
   1.173 +        if( UseLoongsonISA ) {
   1.174 +          gsswx(src, AT, T9, 0);
   1.175 +        } else {
   1.176 +          daddu(AT, AT, T9);
   1.177 +          sw(src, AT, 0);
   1.178 +        }
   1.179 +      }
   1.180 +    }
   1.181 +  } else {
   1.182 +    if( Assembler::is_simm16(disp) ) {
   1.183 +      sw(src, base, disp);
   1.184 +    } else {
   1.185 +      lui(AT, split_low(disp >> 16));
   1.186 +      if (split_low(disp)) ori(AT, AT, split_low(disp));
   1.187 +
   1.188 +      if( UseLoongsonISA ) {
   1.189 +        gsswx(src, base, AT, 0);
   1.190 +      } else {
   1.191 +        daddu(AT, base, AT);
   1.192 +        sw(src, AT, 0);
   1.193 +      }
   1.194 +    }
   1.195 +  }
   1.196  }
   1.197  
   1.198  void Assembler::swl(Register rt, Address dst) {

     2.1 --- a/src/cpu/mips/vm/macroAssembler_mips.cpp	Mon Oct 23 17:07:19 2017 +0800
     2.2 +++ b/src/cpu/mips/vm/macroAssembler_mips.cpp	Tue Oct 24 14:04:09 2017 +0800
     2.3 @@ -3323,6 +3323,14 @@
     2.4      }
     2.5  }
     2.6  
     2.7 +void MacroAssembler::store_heap_oop_null(Address dst){
     2.8 +    if(UseCompressedOops){
     2.9 +       sw(R0, dst);
    2.10 +    } else{
    2.11 +       sd(R0, dst);
    2.12 +    }
    2.13 +}
    2.14 +
    2.15  #ifdef ASSERT
    2.16  void MacroAssembler::verify_heapbase(const char* msg) {
    2.17    assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");

     3.1 --- a/src/cpu/mips/vm/macroAssembler_mips.hpp	Mon Oct 23 17:07:19 2017 +0800
     3.2 +++ b/src/cpu/mips/vm/macroAssembler_mips.hpp	Tue Oct 24 14:04:09 2017 +0800
     3.3 @@ -249,6 +249,7 @@
     3.4  
     3.5    void load_heap_oop(Register dst, Address src);
     3.6    void store_heap_oop(Address dst, Register src);
     3.7 +  void store_heap_oop_null(Address dst);
     3.8    void encode_heap_oop(Register r);
     3.9    void encode_heap_oop(Register dst, Register src);
    3.10    void decode_heap_oop(Register r);

     4.1 --- a/src/cpu/mips/vm/templateTable_mips_64.cpp	Mon Oct 23 17:07:19 2017 +0800
     4.2 +++ b/src/cpu/mips/vm/templateTable_mips_64.cpp	Tue Oct 24 14:04:09 2017 +0800
     4.3 @@ -101,6 +101,85 @@
     4.4    return Address(BCP, offset);
     4.5  }
     4.6  
     4.7 +// Miscelaneous helper routines
     4.8 +// Store an oop (or NULL) at the address described by obj.
     4.9 +// If val == noreg this means store a NULL
    4.10 +
    4.11 +static void do_oop_store(InterpreterMacroAssembler* _masm,
    4.12 +                         Address obj,
    4.13 +                         Register val,
    4.14 +                         BarrierSet::Name barrier,
    4.15 +                         bool precise) {
    4.16 +  assert(val == noreg || val == V0, "parameter is just for looks");
    4.17 +  switch (barrier) {
    4.18 +#if INCLUDE_ALL_GCS
    4.19 +//    case BarrierSet::G1SATBCT:
    4.20 +//    case BarrierSet::G1SATBCTLogging:
    4.21 +//      {
    4.22 +//        // flatten object address if needed
    4.23 +//        if (obj.index() == noreg && obj.disp() == 0) {
    4.24 +//          if (obj.base() != rdx) {
    4.25 +//            __ movq(rdx, obj.base());
    4.26 +//          }
    4.27 +//        } else {
    4.28 +//          __ leaq(rdx, obj);
    4.29 +//        }
    4.30 +//        __ g1_write_barrier_pre(rdx /* obj */,
    4.31 +//                                rbx /* pre_val */,
    4.32 +//                                r15_thread /* thread */,
    4.33 +//                                r8  /* tmp */,
    4.34 +//                                val != noreg /* tosca_live */,
    4.35 +//                                false /* expand_call */);
    4.36 +//        if (val == noreg) {
    4.37 +//          __ store_heap_oop_null(Address(rdx, 0));
    4.38 +//        } else {
    4.39 +//          // G1 barrier needs uncompressed oop for region cross check.
    4.40 +//          Register new_val = val;
    4.41 +//          if (UseCompressedOops) {
    4.42 +//            new_val = rbx;
    4.43 +//            __ movptr(new_val, val);
    4.44 +//          }
    4.45 +//          __ store_heap_oop(Address(rdx, 0), val);
    4.46 +//          __ g1_write_barrier_post(rdx /* store_adr */,
    4.47 +//                                   new_val /* new_val */,
    4.48 +//                                   r15_thread /* thread */,
    4.49 +//                                   r8 /* tmp */,
    4.50 +//                                   rbx /* tmp2 */);
    4.51 +//        }
    4.52 +//      }
    4.53 +      break;
    4.54 +#endif // INCLUDE_ALL_GCS
    4.55 +    case BarrierSet::CardTableModRef:
    4.56 +    case BarrierSet::CardTableExtension:
    4.57 +      {
    4.58 +        if (val == noreg) {
    4.59 +          __ store_heap_oop_null(obj);
    4.60 +        } else {
    4.61 +          __ store_heap_oop(obj, val);
    4.62 +          // flatten object address if needed
    4.63 +          if (!precise || (obj.index() == noreg && obj.disp() == 0)) {
    4.64 +            __ store_check(obj.base());
    4.65 +          } else {
    4.66 +            //__ leaq(rdx, obj);
    4.67 +            //__ store_check(rdx);
    4.68 +          }
    4.69 +        }
    4.70 +      }
    4.71 +      break;
    4.72 +    case BarrierSet::ModRef:
    4.73 +    case BarrierSet::Other:
    4.74 +      if (val == noreg) {
    4.75 +        __ store_heap_oop_null(obj);
    4.76 +      } else {
    4.77 +        __ store_heap_oop(obj, val);
    4.78 +      }
    4.79 +      break;
    4.80 +    default      :
    4.81 +      ShouldNotReachHere();
    4.82 +
    4.83 +  }
    4.84 +}
    4.85 +
    4.86  // bytecode folding
    4.87  void TemplateTable::patch_bytecode(Bytecodes::Code bc, Register bc_reg,
    4.88                                     Register tmp_reg, bool load_bc_into_bc_reg/*=true*/,