Tue, 04 Feb 2020 18:13:14 +0800
Merge
duke@435 | 1 | /* |
mchinnathamb@9311 | 2 | * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
stefank@2314 | 25 | #include "precompiled.hpp" |
twisti@4323 | 26 | #include "asm/macroAssembler.inline.hpp" |
stefank@2314 | 27 | #include "memory/resourceArea.hpp" |
stefank@2314 | 28 | #include "runtime/java.hpp" |
stefank@2314 | 29 | #include "runtime/stubCodeGenerator.hpp" |
stefank@2314 | 30 | #include "vm_version_sparc.hpp" |
stefank@2314 | 31 | #ifdef TARGET_OS_FAMILY_linux |
stefank@2314 | 32 | # include "os_linux.inline.hpp" |
stefank@2314 | 33 | #endif |
stefank@2314 | 34 | #ifdef TARGET_OS_FAMILY_solaris |
stefank@2314 | 35 | # include "os_solaris.inline.hpp" |
stefank@2314 | 36 | #endif |
duke@435 | 37 | |
duke@435 | 38 | int VM_Version::_features = VM_Version::unknown_m; |
duke@435 | 39 | const char* VM_Version::_features_str = ""; |
iveresov@7767 | 40 | unsigned int VM_Version::_L2_data_cache_line_size = 0; |
duke@435 | 41 | |
duke@435 | 42 | void VM_Version::initialize() { |
poonam@8329 | 43 | |
poonam@8329 | 44 | assert(_features != VM_Version::unknown_m, "System pre-initialization is not complete."); |
poonam@8329 | 45 | guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); |
poonam@8329 | 46 | |
duke@435 | 47 | PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); |
duke@435 | 48 | PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); |
duke@435 | 49 | PrefetchFieldsAhead = prefetch_fields_ahead(); |
duke@435 | 50 | |
kvn@3052 | 51 | assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value"); |
kvn@3052 | 52 | if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; |
kvn@3052 | 53 | if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0; |
kvn@3052 | 54 | |
duke@435 | 55 | // Allocation prefetch settings |
kvn@3052 | 56 | intx cache_line_size = prefetch_data_size(); |
duke@435 | 57 | if( cache_line_size > AllocatePrefetchStepSize ) |
duke@435 | 58 | AllocatePrefetchStepSize = cache_line_size; |
kvn@3052 | 59 | |
kvn@3052 | 60 | assert(AllocatePrefetchLines > 0, "invalid value"); |
kvn@3052 | 61 | if( AllocatePrefetchLines < 1 ) // set valid value in product VM |
kvn@3052 | 62 | AllocatePrefetchLines = 3; |
kvn@3052 | 63 | assert(AllocateInstancePrefetchLines > 0, "invalid value"); |
kvn@3052 | 64 | if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM |
kvn@3052 | 65 | AllocateInstancePrefetchLines = 1; |
duke@435 | 66 | |
duke@435 | 67 | AllocatePrefetchDistance = allocate_prefetch_distance(); |
duke@435 | 68 | AllocatePrefetchStyle = allocate_prefetch_style(); |
duke@435 | 69 | |
kvn@3052 | 70 | assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 && |
kvn@3052 | 71 | (AllocatePrefetchDistance > 0), "invalid value"); |
kvn@3052 | 72 | if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 || |
kvn@3052 | 73 | (AllocatePrefetchDistance <= 0)) { |
kvn@3052 | 74 | AllocatePrefetchDistance = AllocatePrefetchStepSize; |
kvn@3052 | 75 | } |
duke@435 | 76 | |
vkempik@8944 | 77 | if (AllocatePrefetchStyle == 3 && (!has_blk_init() || cache_line_size <= 0)) { |
kvn@3037 | 78 | warning("BIS instructions are not available on this CPU"); |
kvn@3037 | 79 | FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); |
kvn@3037 | 80 | } |
kvn@3037 | 81 | |
morris@5283 | 82 | assert(ArraycopySrcPrefetchDistance < 4096, "invalid value"); |
morris@5283 | 83 | if (ArraycopySrcPrefetchDistance >= 4096) |
morris@5283 | 84 | ArraycopySrcPrefetchDistance = 4064; |
morris@5283 | 85 | assert(ArraycopyDstPrefetchDistance < 4096, "invalid value"); |
morris@5283 | 86 | if (ArraycopyDstPrefetchDistance >= 4096) |
morris@5283 | 87 | ArraycopyDstPrefetchDistance = 4064; |
kvn@3103 | 88 | |
duke@435 | 89 | UseSSE = 0; // Only on x86 and x64 |
duke@435 | 90 | |
kvn@3052 | 91 | _supports_cx8 = has_v9(); |
roland@4106 | 92 | _supports_atomic_getset4 = true; // swap instruction |
duke@435 | 93 | |
simonis@6154 | 94 | // There are Fujitsu Sparc64 CPUs which support blk_init as well so |
simonis@6154 | 95 | // we have to take this check out of the 'is_niagara()' block below. |
simonis@6154 | 96 | if (has_blk_init()) { |
simonis@6154 | 97 | // When using CMS or G1, we cannot use memset() in BOT updates |
simonis@6154 | 98 | // because the sun4v/CMT version in libc_psr uses BIS which |
simonis@6154 | 99 | // exposes "phantom zeros" to concurrent readers. See 6948537. |
simonis@6154 | 100 | if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) { |
simonis@6154 | 101 | FLAG_SET_DEFAULT(UseMemSetInBOT, false); |
simonis@6154 | 102 | } |
simonis@6154 | 103 | // Issue a stern warning if the user has explicitly set |
simonis@6154 | 104 | // UseMemSetInBOT (it is known to cause issues), but allow |
simonis@6154 | 105 | // use for experimentation and debugging. |
simonis@6154 | 106 | if (UseConcMarkSweepGC || UseG1GC) { |
simonis@6154 | 107 | if (UseMemSetInBOT) { |
simonis@6154 | 108 | assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error"); |
simonis@6154 | 109 | warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability" |
simonis@6154 | 110 | " on sun4v; please understand that you are using at your own risk!"); |
simonis@6154 | 111 | } |
simonis@6154 | 112 | } |
simonis@6154 | 113 | } |
simonis@6154 | 114 | |
kvn@2403 | 115 | if (is_niagara()) { |
duke@435 | 116 | // Indirect branch is the same cost as direct |
duke@435 | 117 | if (FLAG_IS_DEFAULT(UseInlineCaches)) { |
kvn@1110 | 118 | FLAG_SET_DEFAULT(UseInlineCaches, false); |
duke@435 | 119 | } |
kvn@2403 | 120 | // Align loops on a single instruction boundary. |
kvn@2403 | 121 | if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { |
kvn@2403 | 122 | FLAG_SET_DEFAULT(OptoLoopAlignment, 4); |
kvn@2403 | 123 | } |
coleenp@548 | 124 | #ifdef _LP64 |
kvn@1077 | 125 | // 32-bit oops don't make sense for the 64-bit VM on sparc |
kvn@1077 | 126 | // since the 32-bit VM has the same registers and smaller objects. |
kvn@1077 | 127 | Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); |
roland@4159 | 128 | Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes); |
coleenp@548 | 129 | #endif // _LP64 |
duke@435 | 130 | #ifdef COMPILER2 |
duke@435 | 131 | // Indirect branch is the same cost as direct |
duke@435 | 132 | if (FLAG_IS_DEFAULT(UseJumpTables)) { |
kvn@1110 | 133 | FLAG_SET_DEFAULT(UseJumpTables, true); |
duke@435 | 134 | } |
duke@435 | 135 | // Single-issue, so entry and loop tops are |
duke@435 | 136 | // aligned on a single instruction boundary |
duke@435 | 137 | if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { |
kvn@1110 | 138 | FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); |
duke@435 | 139 | } |
kvn@2403 | 140 | if (is_niagara_plus()) { |
vkempik@8944 | 141 | if (has_blk_init() && (cache_line_size > 0) && UseTLAB && |
kvn@3052 | 142 | FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
mchinnathamb@9311 | 143 | if (!has_sparc5_instr()) { |
mchinnathamb@9311 | 144 | // Use BIS instruction for TLAB allocation prefetch |
mchinnathamb@9311 | 145 | // on Niagara plus processors other than those based on CoreS4. |
mchinnathamb@9311 | 146 | FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1); |
mchinnathamb@9311 | 147 | } else { |
mchinnathamb@9311 | 148 | // On CoreS4 processors use prefetch instruction |
mchinnathamb@9311 | 149 | // to avoid partial RAW issue, also use prefetch style 3. |
mchinnathamb@9311 | 150 | FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0); |
mchinnathamb@9311 | 151 | if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
mchinnathamb@9311 | 152 | FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3); |
mchinnathamb@9311 | 153 | } |
kvn@3052 | 154 | } |
kvn@1802 | 155 | if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
kvn@3052 | 156 | // Use smaller prefetch distance with BIS |
kvn@1802 | 157 | FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); |
kvn@1802 | 158 | } |
kvn@1802 | 159 | } |
kvn@3052 | 160 | if (is_T4()) { |
kvn@3052 | 161 | // Double number of prefetched cache lines on T4 |
kvn@3052 | 162 | // since L2 cache line size is smaller (32 bytes). |
kvn@3052 | 163 | if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { |
kvn@3052 | 164 | FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2); |
kvn@3052 | 165 | } |
kvn@3052 | 166 | if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { |
kvn@3052 | 167 | FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2); |
kvn@3052 | 168 | } |
kvn@3052 | 169 | } |
kvn@1802 | 170 | if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
kvn@1802 | 171 | // Use different prefetch distance without BIS |
kvn@1802 | 172 | FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); |
kvn@1802 | 173 | } |
kvn@3052 | 174 | if (AllocatePrefetchInstr == 1) { |
mchinnathamb@9311 | 175 | |
mchinnathamb@9311 | 176 | // Use allocation prefetch style 3 because BIS instructions |
mchinnathamb@9311 | 177 | // require aligned memory addresses. |
mchinnathamb@9311 | 178 | FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3); |
mchinnathamb@9311 | 179 | |
kvn@3052 | 180 | // Need a space at the end of TLAB for BIS since it |
kvn@3052 | 181 | // will fault when accessing memory outside of heap. |
kvn@3052 | 182 | |
kvn@3052 | 183 | // +1 for rounding up to next cache line, +1 to be safe |
kvn@3052 | 184 | int lines = AllocatePrefetchLines + 2; |
kvn@3052 | 185 | int step_size = AllocatePrefetchStepSize; |
kvn@3052 | 186 | int distance = AllocatePrefetchDistance; |
kvn@3052 | 187 | _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize; |
kvn@3052 | 188 | } |
duke@435 | 189 | } |
duke@435 | 190 | #endif |
duke@435 | 191 | } |
duke@435 | 192 | |
twisti@1078 | 193 | // Use hardware population count instruction if available. |
twisti@1078 | 194 | if (has_hardware_popc()) { |
twisti@1078 | 195 | if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
kvn@1110 | 196 | FLAG_SET_DEFAULT(UsePopCountInstruction, true); |
twisti@1078 | 197 | } |
kvn@3037 | 198 | } else if (UsePopCountInstruction) { |
kvn@3037 | 199 | warning("POPC instruction is not available on this CPU"); |
kvn@3037 | 200 | FLAG_SET_DEFAULT(UsePopCountInstruction, false); |
kvn@3037 | 201 | } |
kvn@3037 | 202 | |
kvn@3037 | 203 | // T4 and newer Sparc cpus have new compare and branch instruction. |
kvn@3037 | 204 | if (has_cbcond()) { |
kvn@3037 | 205 | if (FLAG_IS_DEFAULT(UseCBCond)) { |
kvn@3037 | 206 | FLAG_SET_DEFAULT(UseCBCond, true); |
kvn@3037 | 207 | } |
kvn@3037 | 208 | } else if (UseCBCond) { |
kvn@3037 | 209 | warning("CBCOND instruction is not available on this CPU"); |
kvn@3037 | 210 | FLAG_SET_DEFAULT(UseCBCond, false); |
twisti@1078 | 211 | } |
twisti@1078 | 212 | |
kvn@3092 | 213 | assert(BlockZeroingLowLimit > 0, "invalid value"); |
iveresov@7135 | 214 | if (has_block_zeroing() && cache_line_size > 0) { |
kvn@3092 | 215 | if (FLAG_IS_DEFAULT(UseBlockZeroing)) { |
kvn@3092 | 216 | FLAG_SET_DEFAULT(UseBlockZeroing, true); |
kvn@3092 | 217 | } |
kvn@3092 | 218 | } else if (UseBlockZeroing) { |
kvn@3092 | 219 | warning("BIS zeroing instructions are not available on this CPU"); |
kvn@3092 | 220 | FLAG_SET_DEFAULT(UseBlockZeroing, false); |
kvn@3092 | 221 | } |
kvn@3092 | 222 | |
kvn@3103 | 223 | assert(BlockCopyLowLimit > 0, "invalid value"); |
iveresov@7135 | 224 | if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache |
kvn@3103 | 225 | if (FLAG_IS_DEFAULT(UseBlockCopy)) { |
kvn@3103 | 226 | FLAG_SET_DEFAULT(UseBlockCopy, true); |
kvn@3103 | 227 | } |
kvn@3103 | 228 | } else if (UseBlockCopy) { |
kvn@3103 | 229 | warning("BIS instructions are not available or expensive on this CPU"); |
kvn@3103 | 230 | FLAG_SET_DEFAULT(UseBlockCopy, false); |
kvn@3103 | 231 | } |
kvn@3103 | 232 | |
never@2085 | 233 | #ifdef COMPILER2 |
kvn@3037 | 234 | // T4 and newer Sparc cpus have fast RDPC. |
kvn@3037 | 235 | if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { |
twisti@3249 | 236 | FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); |
kvn@3037 | 237 | } |
kvn@3037 | 238 | |
never@2085 | 239 | // Currently not supported anywhere. |
never@2085 | 240 | FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
kvn@3049 | 241 | |
kvn@3882 | 242 | MaxVectorSize = 8; |
kvn@3882 | 243 | |
kvn@3049 | 244 | assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
never@2085 | 245 | #endif |
never@2085 | 246 | |
kvn@3049 | 247 | assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
kvn@3049 | 248 | assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
kvn@3049 | 249 | |
duke@435 | 250 | char buf[512]; |
kevinw@8969 | 251 | jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
kvn@3037 | 252 | (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), |
twisti@1078 | 253 | (has_hardware_popc() ? ", popc" : ""), |
kvn@3037 | 254 | (has_vis1() ? ", vis1" : ""), |
kvn@3037 | 255 | (has_vis2() ? ", vis2" : ""), |
kvn@3037 | 256 | (has_vis3() ? ", vis3" : ""), |
kvn@3037 | 257 | (has_blk_init() ? ", blk_init" : ""), |
kvn@3037 | 258 | (has_cbcond() ? ", cbcond" : ""), |
kvn@6312 | 259 | (has_aes() ? ", aes" : ""), |
kvn@7027 | 260 | (has_sha1() ? ", sha1" : ""), |
kvn@7027 | 261 | (has_sha256() ? ", sha256" : ""), |
kvn@7027 | 262 | (has_sha512() ? ", sha512" : ""), |
kvn@3037 | 263 | (is_ultra3() ? ", ultra3" : ""), |
kevinw@8969 | 264 | (has_sparc5_instr() ? ", sparc5" : ""), |
kvn@3037 | 265 | (is_sun4v() ? ", sun4v" : ""), |
kvn@3037 | 266 | (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), |
kvn@3037 | 267 | (is_sparc64() ? ", sparc64" : ""), |
twisti@1076 | 268 | (!has_hardware_mul32() ? ", no-mul32" : ""), |
twisti@1076 | 269 | (!has_hardware_div32() ? ", no-div32" : ""), |
duke@435 | 270 | (!has_hardware_fsmuld() ? ", no-fsmuld" : "")); |
duke@435 | 271 | |
duke@435 | 272 | // buf is started with ", " or is empty |
duke@435 | 273 | _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); |
duke@435 | 274 | |
kvn@3001 | 275 | // UseVIS is set to the smallest of what hardware supports and what |
kvn@3001 | 276 | // the command line requires. I.e., you cannot set UseVIS to 3 on |
kvn@3001 | 277 | // older UltraSparc which do not support it. |
kvn@3001 | 278 | if (UseVIS > 3) UseVIS=3; |
kvn@3001 | 279 | if (UseVIS < 0) UseVIS=0; |
kvn@3001 | 280 | if (!has_vis3()) // Drop to 2 if no VIS3 support |
kvn@3001 | 281 | UseVIS = MIN2((intx)2,UseVIS); |
kvn@3001 | 282 | if (!has_vis2()) // Drop to 1 if no VIS2 support |
kvn@3001 | 283 | UseVIS = MIN2((intx)1,UseVIS); |
kvn@3001 | 284 | if (!has_vis1()) // Drop to 0 if no VIS1 support |
kvn@3001 | 285 | UseVIS = 0; |
kvn@3001 | 286 | |
kvn@6653 | 287 | // SPARC T4 and above should have support for AES instructions |
kvn@6312 | 288 | if (has_aes()) { |
kshefov@9795 | 289 | if (FLAG_IS_DEFAULT(UseAES)) { |
kshefov@9795 | 290 | FLAG_SET_DEFAULT(UseAES, true); |
kshefov@9795 | 291 | } |
kshefov@9795 | 292 | if (!UseAES) { |
kshefov@9795 | 293 | if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
kshefov@9795 | 294 | warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled."); |
kvn@6312 | 295 | } |
kshefov@9795 | 296 | FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
kshefov@9795 | 297 | } else { |
kshefov@9795 | 298 | // The AES intrinsic stubs require AES instruction support (of course) |
kshefov@9795 | 299 | // but also require VIS3 mode or higher for instructions it use. |
kshefov@9795 | 300 | if (UseVIS > 2) { |
kshefov@9795 | 301 | if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
kshefov@9795 | 302 | FLAG_SET_DEFAULT(UseAESIntrinsics, true); |
kshefov@9795 | 303 | } |
kshefov@9795 | 304 | } else { |
kshefov@9795 | 305 | if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
kshefov@9795 | 306 | warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled."); |
kshefov@9795 | 307 | } |
kvn@6312 | 308 | FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
kvn@6312 | 309 | } |
kvn@6312 | 310 | } |
kvn@6312 | 311 | } else if (UseAES || UseAESIntrinsics) { |
kshefov@9795 | 312 | if (UseAES && !FLAG_IS_DEFAULT(UseAES)) { |
kshefov@9795 | 313 | warning("AES instructions are not available on this CPU"); |
kvn@6312 | 314 | FLAG_SET_DEFAULT(UseAES, false); |
kvn@6312 | 315 | } |
kshefov@9795 | 316 | if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
kshefov@9795 | 317 | warning("AES intrinsics are not available on this CPU"); |
kvn@6312 | 318 | FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
kvn@6312 | 319 | } |
kvn@6312 | 320 | } |
kvn@6312 | 321 | |
ascarpino@9788 | 322 | // GHASH/GCM intrinsics |
ascarpino@9788 | 323 | if (has_vis3() && (UseVIS > 2)) { |
ascarpino@9788 | 324 | if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) { |
ascarpino@9788 | 325 | UseGHASHIntrinsics = true; |
ascarpino@9788 | 326 | } |
ascarpino@9788 | 327 | } else if (UseGHASHIntrinsics) { |
ascarpino@9788 | 328 | if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics)) |
ascarpino@9788 | 329 | warning("GHASH intrinsics require VIS3 insructions support. Intriniscs will be disabled"); |
ascarpino@9788 | 330 | FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); |
ascarpino@9788 | 331 | } |
ascarpino@9788 | 332 | |
kvn@7027 | 333 | // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times |
kvn@7027 | 334 | if (has_sha1() || has_sha256() || has_sha512()) { |
kvn@7027 | 335 | if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions |
kvn@7027 | 336 | if (FLAG_IS_DEFAULT(UseSHA)) { |
kvn@7027 | 337 | FLAG_SET_DEFAULT(UseSHA, true); |
kvn@7027 | 338 | } |
kvn@7027 | 339 | } else { |
kvn@7027 | 340 | if (UseSHA) { |
kvn@7027 | 341 | warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled."); |
kvn@7027 | 342 | FLAG_SET_DEFAULT(UseSHA, false); |
kvn@7027 | 343 | } |
kvn@7027 | 344 | } |
kvn@7027 | 345 | } else if (UseSHA) { |
kvn@7027 | 346 | warning("SHA instructions are not available on this CPU"); |
kvn@7027 | 347 | FLAG_SET_DEFAULT(UseSHA, false); |
kvn@7027 | 348 | } |
kvn@7027 | 349 | |
kvn@7027 | 350 | if (!UseSHA) { |
kvn@7027 | 351 | FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); |
kvn@7027 | 352 | FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); |
kvn@7027 | 353 | FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); |
kvn@7027 | 354 | } else { |
kvn@7027 | 355 | if (has_sha1()) { |
kvn@7027 | 356 | if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { |
kvn@7027 | 357 | FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); |
kvn@7027 | 358 | } |
kvn@7027 | 359 | } else if (UseSHA1Intrinsics) { |
kvn@7027 | 360 | warning("SHA1 instruction is not available on this CPU."); |
kvn@7027 | 361 | FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); |
kvn@7027 | 362 | } |
kvn@7027 | 363 | if (has_sha256()) { |
kvn@7027 | 364 | if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { |
kvn@7027 | 365 | FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); |
kvn@7027 | 366 | } |
kvn@7027 | 367 | } else if (UseSHA256Intrinsics) { |
kvn@7027 | 368 | warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU."); |
kvn@7027 | 369 | FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); |
kvn@7027 | 370 | } |
kvn@7027 | 371 | |
kvn@7027 | 372 | if (has_sha512()) { |
kvn@7027 | 373 | if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { |
kvn@7027 | 374 | FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); |
kvn@7027 | 375 | } |
kvn@7027 | 376 | } else if (UseSHA512Intrinsics) { |
kvn@7027 | 377 | warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU."); |
kvn@7027 | 378 | FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); |
kvn@7027 | 379 | } |
kvn@7027 | 380 | if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { |
kvn@7027 | 381 | FLAG_SET_DEFAULT(UseSHA, false); |
kvn@7027 | 382 | } |
kvn@7027 | 383 | } |
kvn@7027 | 384 | |
jwilhelm@4430 | 385 | if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
jwilhelm@4430 | 386 | (cache_line_size > ContendedPaddingWidth)) |
jwilhelm@4430 | 387 | ContendedPaddingWidth = cache_line_size; |
jwilhelm@4430 | 388 | |
duke@435 | 389 | #ifndef PRODUCT |
duke@435 | 390 | if (PrintMiscellaneous && Verbose) { |
kevinw@8966 | 391 | tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size()); |
iveresov@7767 | 392 | tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size()); |
kvn@3052 | 393 | tty->print("Allocation"); |
duke@435 | 394 | if (AllocatePrefetchStyle <= 0) { |
kvn@3052 | 395 | tty->print_cr(": no prefetching"); |
duke@435 | 396 | } else { |
kvn@3052 | 397 | tty->print(" prefetching: "); |
kvn@3052 | 398 | if (AllocatePrefetchInstr == 0) { |
kvn@3052 | 399 | tty->print("PREFETCH"); |
kvn@3052 | 400 | } else if (AllocatePrefetchInstr == 1) { |
kvn@3052 | 401 | tty->print("BIS"); |
kvn@3052 | 402 | } |
duke@435 | 403 | if (AllocatePrefetchLines > 1) { |
drchase@6680 | 404 | tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); |
duke@435 | 405 | } else { |
drchase@6680 | 406 | tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); |
duke@435 | 407 | } |
duke@435 | 408 | } |
duke@435 | 409 | if (PrefetchCopyIntervalInBytes > 0) { |
drchase@6680 | 410 | tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); |
duke@435 | 411 | } |
duke@435 | 412 | if (PrefetchScanIntervalInBytes > 0) { |
drchase@6680 | 413 | tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); |
duke@435 | 414 | } |
duke@435 | 415 | if (PrefetchFieldsAhead > 0) { |
drchase@6680 | 416 | tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); |
duke@435 | 417 | } |
jwilhelm@4430 | 418 | if (ContendedPaddingWidth > 0) { |
drchase@6680 | 419 | tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); |
jwilhelm@4430 | 420 | } |
duke@435 | 421 | } |
duke@435 | 422 | #endif // PRODUCT |
duke@435 | 423 | } |
duke@435 | 424 | |
duke@435 | 425 | void VM_Version::print_features() { |
duke@435 | 426 | tty->print_cr("Version:%s", cpu_features()); |
duke@435 | 427 | } |
duke@435 | 428 | |
duke@435 | 429 | int VM_Version::determine_features() { |
duke@435 | 430 | if (UseV8InstrsOnly) { |
duke@435 | 431 | NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");) |
duke@435 | 432 | return generic_v8_m; |
duke@435 | 433 | } |
duke@435 | 434 | |
duke@435 | 435 | int features = platform_features(unknown_m); // platform_features() is os_arch specific |
duke@435 | 436 | |
duke@435 | 437 | if (features == unknown_m) { |
duke@435 | 438 | features = generic_v9_m; |
duke@435 | 439 | warning("Cannot recognize SPARC version. Default to V9"); |
duke@435 | 440 | } |
duke@435 | 441 | |
kvn@2403 | 442 | assert(is_T_family(features) == is_niagara(features), "Niagara should be T series"); |
kvn@2403 | 443 | if (UseNiagaraInstrs) { // Force code generation for Niagara |
kvn@2403 | 444 | if (is_T_family(features)) { |
duke@435 | 445 | // Happy to accomodate... |
duke@435 | 446 | } else { |
duke@435 | 447 | NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");) |
kvn@2403 | 448 | features |= T_family_m; |
duke@435 | 449 | } |
duke@435 | 450 | } else { |
kvn@2403 | 451 | if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) { |
duke@435 | 452 | NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");) |
kvn@2403 | 453 | features &= ~(T_family_m | T1_model_m); |
duke@435 | 454 | } else { |
duke@435 | 455 | // Happy to accomodate... |
duke@435 | 456 | } |
duke@435 | 457 | } |
duke@435 | 458 | |
duke@435 | 459 | return features; |
duke@435 | 460 | } |
duke@435 | 461 | |
duke@435 | 462 | static int saved_features = 0; |
duke@435 | 463 | |
duke@435 | 464 | void VM_Version::allow_all() { |
duke@435 | 465 | saved_features = _features; |
duke@435 | 466 | _features = all_features_m; |
duke@435 | 467 | } |
duke@435 | 468 | |
duke@435 | 469 | void VM_Version::revert() { |
duke@435 | 470 | _features = saved_features; |
duke@435 | 471 | } |
jmasa@445 | 472 | |
jmasa@445 | 473 | unsigned int VM_Version::calc_parallel_worker_threads() { |
jmasa@445 | 474 | unsigned int result; |
kevinw@8971 | 475 | if (is_M_series() || is_S_series()) { |
kevinw@8971 | 476 | // for now, use same gc thread calculation for M-series and S-series as for |
kevinw@8971 | 477 | // niagara-plus. In future, we may want to tweak parameters for |
kevinw@8971 | 478 | // nof_parallel_worker_thread |
twisti@4108 | 479 | result = nof_parallel_worker_threads(5, 16, 8); |
twisti@4108 | 480 | } else if (is_niagara_plus()) { |
jmasa@445 | 481 | result = nof_parallel_worker_threads(5, 16, 8); |
jmasa@445 | 482 | } else { |
jmasa@445 | 483 | result = nof_parallel_worker_threads(5, 8, 8); |
jmasa@445 | 484 | } |
jmasa@445 | 485 | return result; |
jmasa@445 | 486 | } |
kevinw@8968 | 487 | |
kevinw@8968 | 488 | |
kevinw@8968 | 489 | int VM_Version::parse_features(const char* implementation) { |
kevinw@8968 | 490 | int features = unknown_m; |
kevinw@8968 | 491 | // Convert to UPPER case before compare. |
kevinw@8968 | 492 | char* impl = os::strdup(implementation); |
kevinw@8968 | 493 | |
kevinw@8968 | 494 | for (int i = 0; impl[i] != 0; i++) |
kevinw@8968 | 495 | impl[i] = (char)toupper((uint)impl[i]); |
kevinw@8968 | 496 | |
kevinw@8968 | 497 | if (strstr(impl, "SPARC64") != NULL) { |
kevinw@8968 | 498 | features |= sparc64_family_m; |
kevinw@8968 | 499 | } else if (strstr(impl, "SPARC-M") != NULL) { |
kevinw@8968 | 500 | // M-series SPARC is based on T-series. |
kevinw@8968 | 501 | features |= (M_family_m | T_family_m); |
kevinw@8971 | 502 | } else if (strstr(impl, "SPARC-S") != NULL) { |
kevinw@8971 | 503 | // S-series SPARC is based on T-series. |
kevinw@8971 | 504 | features |= (S_family_m | T_family_m); |
kevinw@8968 | 505 | } else if (strstr(impl, "SPARC-T") != NULL) { |
kevinw@8968 | 506 | features |= T_family_m; |
kevinw@8968 | 507 | if (strstr(impl, "SPARC-T1") != NULL) { |
kevinw@8968 | 508 | features |= T1_model_m; |
kevinw@8968 | 509 | } |
kevinw@8969 | 510 | } else if (strstr(impl, "SUN4V-CPU") != NULL) { |
kevinw@8969 | 511 | // Generic or migration class LDOM |
kevinw@8969 | 512 | features |= T_family_m; |
kevinw@8968 | 513 | } else { |
kevinw@8968 | 514 | #ifndef PRODUCT |
kevinw@8969 | 515 | warning("Failed to parse CPU implementation = '%s'", impl); |
kevinw@8968 | 516 | #endif |
kevinw@8968 | 517 | } |
kevinw@8968 | 518 | os::free((void*)impl); |
kevinw@8968 | 519 | return features; |
kevinw@8968 | 520 | } |