1.1 --- a/src/cpu/sparc/vm/vm_version_sparc.cpp Tue Feb 04 17:38:01 2020 +0800
1.2 +++ b/src/cpu/sparc/vm/vm_version_sparc.cpp Tue Feb 04 18:13:14 2020 +0800
1.3 @@ -286,39 +286,50 @@
1.4
1.5 // SPARC T4 and above should have support for AES instructions
1.6 if (has_aes()) {
1.7 - if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3
1.8 - if (FLAG_IS_DEFAULT(UseAES)) {
1.9 - FLAG_SET_DEFAULT(UseAES, true);
1.10 + if (FLAG_IS_DEFAULT(UseAES)) {
1.11 + FLAG_SET_DEFAULT(UseAES, true);
1.12 + }
1.13 + if (!UseAES) {
1.14 + if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1.15 + warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
1.16 }
1.17 - if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1.18 - FLAG_SET_DEFAULT(UseAESIntrinsics, true);
1.19 - }
1.20 - // we disable both the AES flags if either of them is disabled on the command line
1.21 - if (!UseAES || !UseAESIntrinsics) {
1.22 - FLAG_SET_DEFAULT(UseAES, false);
1.23 + FLAG_SET_DEFAULT(UseAESIntrinsics, false);
1.24 + } else {
1.25 + // The AES intrinsic stubs require AES instruction support (of course)
1.26 + // but also require VIS3 mode or higher for instructions it use.
1.27 + if (UseVIS > 2) {
1.28 + if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1.29 + FLAG_SET_DEFAULT(UseAESIntrinsics, true);
1.30 + }
1.31 + } else {
1.32 + if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1.33 + warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
1.34 + }
1.35 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
1.36 }
1.37 - } else {
1.38 - if (UseAES || UseAESIntrinsics) {
1.39 - warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
1.40 - if (UseAES) {
1.41 - FLAG_SET_DEFAULT(UseAES, false);
1.42 - }
1.43 - if (UseAESIntrinsics) {
1.44 - FLAG_SET_DEFAULT(UseAESIntrinsics, false);
1.45 - }
1.46 - }
1.47 }
1.48 } else if (UseAES || UseAESIntrinsics) {
1.49 - warning("AES instructions are not available on this CPU");
1.50 - if (UseAES) {
1.51 + if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
1.52 + warning("AES instructions are not available on this CPU");
1.53 FLAG_SET_DEFAULT(UseAES, false);
1.54 }
1.55 - if (UseAESIntrinsics) {
1.56 + if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1.57 + warning("AES intrinsics are not available on this CPU");
1.58 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
1.59 }
1.60 }
1.61
1.62 + // GHASH/GCM intrinsics
1.63 + if (has_vis3() && (UseVIS > 2)) {
1.64 + if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
1.65 + UseGHASHIntrinsics = true;
1.66 + }
1.67 + } else if (UseGHASHIntrinsics) {
1.68 + if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
1.69 + warning("GHASH intrinsics require VIS3 insructions support. Intriniscs will be disabled");
1.70 + FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
1.71 + }
1.72 +
1.73 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
1.74 if (has_sha1() || has_sha256() || has_sha512()) {
1.75 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
