Fri, 29 Apr 2016 00:06:10 +0800
Added MIPS 64-bit port.
aoqi@1 | 1 | /* |
aoqi@1 | 2 | * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. |
aoqi@1 | 3 | * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. |
aoqi@1 | 4 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
aoqi@1 | 5 | * |
aoqi@1 | 6 | * This code is free software; you can redistribute it and/or modify it |
aoqi@1 | 7 | * under the terms of the GNU General Public License version 2 only, as |
aoqi@1 | 8 | * published by the Free Software Foundation. |
aoqi@1 | 9 | * |
aoqi@1 | 10 | * This code is distributed in the hope that it will be useful, but WITHOUT |
aoqi@1 | 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
aoqi@1 | 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
aoqi@1 | 13 | * version 2 for more details (a copy is included in the LICENSE file that |
aoqi@1 | 14 | * accompanied this code). |
aoqi@1 | 15 | * |
aoqi@1 | 16 | * You should have received a copy of the GNU General Public License version |
aoqi@1 | 17 | * 2 along with this work; if not, write to the Free Software Foundation, |
aoqi@1 | 18 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
aoqi@1 | 19 | * |
aoqi@1 | 20 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
aoqi@1 | 21 | * or visit www.oracle.com if you need additional information or have any |
aoqi@1 | 22 | * questions. |
aoqi@1 | 23 | * |
aoqi@1 | 24 | */ |
aoqi@1 | 25 | |
aoqi@1 | 26 | #ifndef CPU_MIPS_VM_C1_FRAMEMAP_MIPS_HPP |
aoqi@1 | 27 | #define CPU_MIPS_VM_C1_FRAMEMAP_MIPS_HPP |
aoqi@1 | 28 | |
aoqi@1 | 29 | // On i486/gs2 the frame looks as follows: |
aoqi@1 | 30 | // |
aoqi@1 | 31 | // +----------------+---------+----------------------------+----------------+----------- |
aoqi@1 | 32 | // | size_arguments | 2 words | size_locals-size_arguments | _size_monitors | spilling . |
aoqi@1 | 33 | // +----------------+---------+----------------------------+----------------+----------- |
aoqi@1 | 34 | // |
aoqi@1 | 35 | //12/21, 06, jerome |
aoqi@1 | 36 | private: |
aoqi@1 | 37 | |
aoqi@1 | 38 | //static FloatRegister _fpu_regs [nof_fpu_regs]; |
aoqi@1 | 39 | static FloatRegister _fpu_regs [32]; |
aoqi@1 | 40 | |
aoqi@1 | 41 | WordSize fp_offset_for_slot (int slot) const; |
aoqi@1 | 42 | int local_to_slot (int local_name, bool is_two_word) const; |
aoqi@1 | 43 | // NOTE : name consist of argument, local, spill, they are not continuous |
aoqi@1 | 44 | WordSize fp_offset_for_name (int name, bool is_two_word, bool for_hi_word) const; |
aoqi@1 | 45 | WordSize fp_offset_for_monitor_lock (int monitor_index) const; |
aoqi@1 | 46 | WordSize fp_offset_for_monitor_object(int monitor_index) const; |
aoqi@1 | 47 | bool location_for_fp_offset (WordSize word_offset_from_fp, |
aoqi@1 | 48 | Location::Type loc_type, |
aoqi@1 | 49 | Location* loc) const; |
aoqi@1 | 50 | WordSize fp2sp_offset (WordSize fp_offset) const; |
aoqi@1 | 51 | |
aoqi@1 | 52 | |
aoqi@1 | 53 | public: |
aoqi@1 | 54 | static const int pd_c_runtime_reserved_arg_size; |
aoqi@1 | 55 | enum { |
aoqi@1 | 56 | nof_reg_args = 5, // registers t0,a0-a3 are available for parameter passing |
aoqi@1 | 57 | first_available_sp_in_frame = 0, |
aoqi@1 | 58 | //frame_pad_in_bytes = 8 |
aoqi@1 | 59 | frame_pad_in_bytes = 2 * sizeof(intptr_t) |
aoqi@1 | 60 | }; |
aoqi@1 | 61 | |
aoqi@1 | 62 | static LIR_Opr _zero_opr; |
aoqi@1 | 63 | static LIR_Opr _at_opr; |
aoqi@1 | 64 | static LIR_Opr _v0_opr; |
aoqi@1 | 65 | static LIR_Opr _v1_opr; |
aoqi@1 | 66 | static LIR_Opr _a0_opr; |
aoqi@1 | 67 | static LIR_Opr _a1_opr; |
aoqi@1 | 68 | static LIR_Opr _a2_opr; |
aoqi@1 | 69 | static LIR_Opr _a3_opr; |
aoqi@1 | 70 | static LIR_Opr _t0_opr; |
aoqi@1 | 71 | static LIR_Opr _t1_opr; |
aoqi@1 | 72 | static LIR_Opr _t2_opr; |
aoqi@1 | 73 | static LIR_Opr _t3_opr; |
aoqi@1 | 74 | #ifndef _LP64 |
aoqi@1 | 75 | static LIR_Opr _t4_opr; |
aoqi@1 | 76 | static LIR_Opr _t5_opr; |
aoqi@1 | 77 | static LIR_Opr _t6_opr; |
aoqi@1 | 78 | static LIR_Opr _t7_opr; |
aoqi@1 | 79 | #else |
aoqi@1 | 80 | static LIR_Opr _a4_opr; |
aoqi@1 | 81 | static LIR_Opr _a5_opr; |
aoqi@1 | 82 | static LIR_Opr _a6_opr; |
aoqi@1 | 83 | static LIR_Opr _a7_opr; |
aoqi@1 | 84 | #endif |
aoqi@1 | 85 | static LIR_Opr _t8_opr; |
aoqi@1 | 86 | static LIR_Opr _t9_opr; |
aoqi@1 | 87 | static LIR_Opr _s0_opr; |
aoqi@1 | 88 | static LIR_Opr _s1_opr; |
aoqi@1 | 89 | static LIR_Opr _s2_opr; |
aoqi@1 | 90 | static LIR_Opr _s3_opr; |
aoqi@1 | 91 | static LIR_Opr _s4_opr; |
aoqi@1 | 92 | static LIR_Opr _s5_opr; |
aoqi@1 | 93 | static LIR_Opr _s6_opr; |
aoqi@1 | 94 | static LIR_Opr _s7_opr; |
aoqi@1 | 95 | static LIR_Opr _gp_opr; |
aoqi@1 | 96 | static LIR_Opr _fp_opr; |
aoqi@1 | 97 | static LIR_Opr _sp_opr; |
aoqi@1 | 98 | static LIR_Opr _ra_opr; |
aoqi@1 | 99 | static LIR_Opr _k0_opr; |
aoqi@1 | 100 | static LIR_Opr _k1_opr; |
aoqi@1 | 101 | |
aoqi@1 | 102 | static LIR_Opr _f0_opr; |
aoqi@1 | 103 | static LIR_Opr _f12_opr; |
aoqi@1 | 104 | static LIR_Opr _f14_opr; |
aoqi@1 | 105 | static LIR_Opr _d0_opr; |
aoqi@1 | 106 | static LIR_Opr _d12_opr; |
aoqi@1 | 107 | static LIR_Opr _d14_opr; |
aoqi@1 | 108 | |
aoqi@1 | 109 | static LIR_Opr _a0_a1_opr; |
aoqi@1 | 110 | static LIR_Opr _a2_a3_opr; |
aoqi@1 | 111 | static LIR_Opr _v0_v1_opr; |
aoqi@1 | 112 | |
aoqi@1 | 113 | |
aoqi@1 | 114 | static LIR_Opr receiver_opr; |
aoqi@1 | 115 | static LIR_Opr _zero_oop_opr; |
aoqi@1 | 116 | static LIR_Opr _at_oop_opr; |
aoqi@1 | 117 | static LIR_Opr _v0_oop_opr; |
aoqi@1 | 118 | static LIR_Opr _v1_oop_opr; |
aoqi@1 | 119 | static LIR_Opr _a0_oop_opr; |
aoqi@1 | 120 | static LIR_Opr _a1_oop_opr; |
aoqi@1 | 121 | static LIR_Opr _a2_oop_opr; |
aoqi@1 | 122 | static LIR_Opr _a3_oop_opr; |
aoqi@1 | 123 | static LIR_Opr _t0_oop_opr; |
aoqi@1 | 124 | static LIR_Opr _t1_oop_opr; |
aoqi@1 | 125 | static LIR_Opr _t2_oop_opr; |
aoqi@1 | 126 | static LIR_Opr _t3_oop_opr; |
aoqi@1 | 127 | #ifndef _LP64 |
aoqi@1 | 128 | static LIR_Opr _t4_oop_opr; |
aoqi@1 | 129 | static LIR_Opr _t5_oop_opr; |
aoqi@1 | 130 | static LIR_Opr _t6_oop_opr; |
aoqi@1 | 131 | static LIR_Opr _t7_oop_opr; |
aoqi@1 | 132 | #else |
aoqi@1 | 133 | static LIR_Opr _a4_oop_opr; |
aoqi@1 | 134 | static LIR_Opr _a5_oop_opr; |
aoqi@1 | 135 | static LIR_Opr _a6_oop_opr; |
aoqi@1 | 136 | static LIR_Opr _a7_oop_opr; |
aoqi@1 | 137 | #endif |
aoqi@1 | 138 | static LIR_Opr _t8_oop_opr; |
aoqi@1 | 139 | static LIR_Opr _t9_oop_opr; |
aoqi@1 | 140 | static LIR_Opr _s0_oop_opr; |
aoqi@1 | 141 | static LIR_Opr _s1_oop_opr; |
aoqi@1 | 142 | static LIR_Opr _s2_oop_opr; |
aoqi@1 | 143 | static LIR_Opr _s3_oop_opr; |
aoqi@1 | 144 | static LIR_Opr _s4_oop_opr; |
aoqi@1 | 145 | static LIR_Opr _s5_oop_opr; |
aoqi@1 | 146 | static LIR_Opr _s6_oop_opr; |
aoqi@1 | 147 | static LIR_Opr _s7_oop_opr; |
aoqi@1 | 148 | static LIR_Opr _gp_oop_opr; |
aoqi@1 | 149 | static LIR_Opr _fp_oop_opr; |
aoqi@1 | 150 | static LIR_Opr _sp_oop_opr; |
aoqi@1 | 151 | static LIR_Opr _ra_oop_opr; |
aoqi@1 | 152 | static LIR_Opr _k0_oop_opr; |
aoqi@1 | 153 | static LIR_Opr _k1_oop_opr; |
aoqi@1 | 154 | |
aoqi@1 | 155 | static LIR_Opr _f0_oop_opr; |
aoqi@1 | 156 | static LIR_Opr _f12_oop_opr; |
aoqi@1 | 157 | static LIR_Opr _f14_oop_opr; |
aoqi@1 | 158 | static LIR_Opr _d0_oop_opr; |
aoqi@1 | 159 | static LIR_Opr _d12_oop_opr; |
aoqi@1 | 160 | static LIR_Opr _d14_oop_opr; |
aoqi@1 | 161 | |
aoqi@1 | 162 | static LIR_Opr _a0_a1_oop_opr; |
aoqi@1 | 163 | static LIR_Opr _a2_a3_oop_opr; |
aoqi@1 | 164 | static LIR_Opr _v0_v1_oop_opr; |
aoqi@1 | 165 | |
aoqi@1 | 166 | //FIXME, needed under 64-bit? by aoqi |
aoqi@1 | 167 | static LIR_Opr _a0_a1_long_opr; |
aoqi@1 | 168 | static LIR_Opr _a2_a3_long_opr; |
aoqi@1 | 169 | static LIR_Opr _v0_v1_long_opr; |
aoqi@1 | 170 | static LIR_Opr _f0_float_opr; |
aoqi@1 | 171 | static LIR_Opr _f12_float_opr; |
aoqi@1 | 172 | static LIR_Opr _f14_float_opr; |
aoqi@1 | 173 | static LIR_Opr _d0_double_opr; |
aoqi@1 | 174 | static LIR_Opr _d12_double_opr; |
aoqi@1 | 175 | static LIR_Opr _d14_double_opr; |
aoqi@1 | 176 | |
aoqi@1 | 177 | |
aoqi@1 | 178 | static LIR_Opr as_long_opr(Register r, Register r2){ |
aoqi@1 | 179 | return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2)); |
aoqi@1 | 180 | } |
aoqi@1 | 181 | |
aoqi@1 | 182 | static LIR_Opr as_float_opr(FloatRegister r) { |
aoqi@1 | 183 | return LIR_OprFact::single_fpu(r->encoding()); |
aoqi@1 | 184 | } |
aoqi@1 | 185 | |
aoqi@1 | 186 | |
aoqi@1 | 187 | static bool is_caller_save_register (LIR_Opr opr); |
aoqi@1 | 188 | static bool is_caller_save_register (Register r); |
aoqi@1 | 189 | |
aoqi@1 | 190 | |
aoqi@1 | 191 | // OptoReg name for spilled virtual FPU register n |
aoqi@1 | 192 | //OptoReg::Name fpu_regname (int n); |
aoqi@1 | 193 | |
aoqi@1 | 194 | static VMReg fpu_regname (int n); |
aoqi@1 | 195 | static Register first_register(); |
aoqi@1 | 196 | static FloatRegister nr2floatreg (int rnr); |
aoqi@1 | 197 | static int adjust_reg_range(int range) { |
aoqi@1 | 198 | // Reduce the number of available regs (to free r12) in case of compressed oops |
aoqi@1 | 199 | if (UseCompressedOops || UseCompressedClassPointers) return range - 1; |
aoqi@1 | 200 | return range; |
aoqi@1 | 201 | } |
aoqi@1 | 202 | |
aoqi@1 | 203 | static int nof_caller_save_cpu_regs() { return adjust_reg_range(pd_nof_caller_save_cpu_regs_frame_map); } |
aoqi@1 | 204 | static int last_cpu_reg() { return adjust_reg_range(pd_last_cpu_reg); } |
aoqi@1 | 205 | //static int last_byte_reg() { return adjust_reg_range(pd_last_byte_reg); } |
aoqi@1 | 206 | |
aoqi@1 | 207 | #endif // CPU_MIPS_VM_C1_FRAMEMAP_MIPS_HPP |
aoqi@1 | 208 |