# HG changeset patch
# User fujie
# Date 1469417847 -28800
# Node ID 440521e9c7138af29a032422adb01f04e391704b
# Parent  e32766b589240e385c6e8187b0a127c320de3404
Add move conditional instructions (movz and movn) in MIPS assembler.

diff -r e32766b58924 -r 440521e9c713 src/cpu/mips/vm/assembler_mips.hpp
--- a/src/cpu/mips/vm/assembler_mips.hpp	Fri Jul 15 10:54:18 2016 +0800
+++ b/src/cpu/mips/vm/assembler_mips.hpp	Mon Jul 25 11:37:27 2016 +0800
@@ -434,6 +434,8 @@
 		srav_op 		= 0x07,
 		jr_op				= 0x08,
 		jalr_op			= 0x09,
+		movz_op			= 0x0a,
+		movn_op			= 0x0b,
 		syscall_op	= 0x0c,
 		break_op		= 0x0d,
 		sync_op			= 0x0f,
@@ -853,6 +855,10 @@
 	void daddu (Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), daddu_op)); }
 	void ddiv  (Register rs, Register rt)              { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, ddiv_op));	}
 	void ddivu (Register rs, Register rt)              { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, ddivu_op)); }
+
+	void movz  (Register rd, Register rs,   Register rt) { emit_long(insn_RRRO((int)rs->encoding(),  (int)rt->encoding(),   (int)rd->encoding(), movz_op)); }	
+	void movn  (Register rd, Register rs,   Register rt) { emit_long(insn_RRRO((int)rs->encoding(),  (int)rt->encoding(),   (int)rd->encoding(), movn_op)); }	
+
 // Do mult and div need both 32-bit and 64-bit version? FIXME aoqi
 //#ifndef _LP64
 #if 1