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src/cpu/mips/vm/vm_version_mips.hpp@3089aa0aa0ee
src/cpu/mips/vm/vm_version_mips.hpp
Thu, 05 Sep 2019 13:07:31 +0800
- author
- aoqi
- date
- Thu, 05 Sep 2019 13:07:31 +0800
- changeset 9644
- 3089aa0aa0ee
- parent 9578
- 191e90d9878f
- permissions
- -rw-r--r--
#9372 Refactor VM_Version, removed UseLoongsonISA and Use3A3000, added UseLEXT1, UseLEXT2, UseLEXT3.
Summary: used cpucfg to detect cpu features
Reviewed-by: wanghaomin
1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #ifndef CPU_MIPS_VM_VM_VERSION_MIPS_HPP
27 #define CPU_MIPS_VM_VM_VERSION_MIPS_HPP
29 #include "runtime/globals_extension.hpp"
30 #include "runtime/vm_version.hpp"
33 class VM_Version: public Abstract_VM_Version {
34 public:
36 union Loongson_Cpucfg_Id1 {
37 uint32_t value;
38 struct {
39 uint32_t FP : 1,
40 FPREV : 3,
41 MMI : 1,
42 MSA1 : 1,
43 MSA2 : 1,
44 CGP : 1,
45 WRP : 1,
46 LSX1 : 1,
47 LSX2 : 1,
48 LASX : 1,
49 R6FXP : 1,
50 R6CRCP : 1,
51 R6FPP : 1,
52 CNT64 : 1,
53 LSLDR0 : 1,
54 LSPREF : 1,
55 LSPREFX : 1,
56 LSSYNCI : 1,
57 LSUCA : 1,
58 LLSYNC : 1,
59 TGTSYNC : 1,
60 LLEXC : 1,
61 SCRAND : 1,
62 MUALP : 1,
63 KMUALEn : 1,
64 ITLBT : 1,
65 LSUPERF : 1,
66 SFBP : 1,
67 CDMAP : 1,
68 : 1;
69 } bits;
70 };
72 union Loongson_Cpucfg_Id2 {
73 uint32_t value;
74 struct {
75 uint32_t LEXT1 : 1,
76 LEXT2 : 1,
77 LEXT3 : 1,
78 LSPW : 1,
79 LBT1 : 1,
80 LBT2 : 1,
81 LBT3 : 1,
82 LBTMMU : 1,
83 LPMP : 1,
84 LPMRev : 3,
85 LAMO : 1,
86 LPIXU : 1,
87 LPIXNU : 1,
88 LVZP : 1,
89 LVZRev : 3,
90 LGFTP : 1,
91 LGFTRev : 3,
92 LLFTP : 1,
93 LLFTRev : 3,
94 LCSRP : 1,
95 DISBLKLY : 1,
96 : 3;
97 } bits;
98 };
100 protected:
102 enum {
103 CPU_LOONGSON = (1 << 1),
104 CPU_LOONGSON_GS464 = (1 << 2),
105 CPU_LOONGSON_GS464E = (1 << 3),
106 CPU_LOONGSON_GS264 = (1 << 4),
107 CPU_MMI = (1 << 11),
108 CPU_MSA1_0 = (1 << 12),
109 CPU_MSA2_0 = (1 << 13),
110 CPU_CGP = (1 << 14),
111 CPU_LSX1 = (1 << 15),
112 CPU_LSX2 = (1 << 16),
113 CPU_LASX = (1 << 17),
114 CPU_LEXT1 = (1 << 18),
115 CPU_LEXT2 = (1 << 19),
116 CPU_LEXT3 = (1 << 20),
117 CPU_LAMO = (1 << 21),
118 CPU_LPIXU = (1 << 22),
119 CPU_LLSYNC = (1 << 23),
120 CPU_TGTSYNC = (1 << 24),
121 CPU_ULSYNC = (1 << 25),
122 CPU_MUALP = (1 << 26),
124 //////////////////////add some other feature here//////////////////
125 } cpuFeatureFlags;
127 enum Loongson_Family {
128 L_3A1000 = 0,
129 L_3B1500 = 1,
130 L_3A2000 = 2,
131 L_3B2000 = 3,
132 L_3A3000 = 4,
133 L_3B3000 = 5,
134 L_2K1000 = 6,
135 L_UNKNOWN = 7
136 };
138 struct Loongson_Cpuinfo {
139 Loongson_Family id;
140 const char* const match_str;
141 };
143 static int _cpuFeatures;
144 static const char* _features_str;
145 static volatile bool _is_determine_cpucfg_supported_running;
146 static bool _is_cpucfg_instruction_supported;
147 static bool _cpu_info_is_initialized;
149 struct CpuidInfo {
150 uint32_t cpucfg_info_id0;
151 Loongson_Cpucfg_Id1 cpucfg_info_id1;
152 Loongson_Cpucfg_Id2 cpucfg_info_id2;
153 uint32_t cpucfg_info_id3;
154 uint32_t cpucfg_info_id4;
155 uint32_t cpucfg_info_id5;
156 uint32_t cpucfg_info_id6;
157 uint32_t cpucfg_info_id8;
158 };
160 // The actual cpuid info block
161 static CpuidInfo _cpuid_info;
163 static uint32_t get_feature_flags_by_cpucfg();
164 static int get_feature_flags_by_cpuinfo(int features);
165 static void get_processor_features();
167 public:
168 // Offsets for cpuid asm stub
169 static ByteSize Loongson_Cpucfg_id0_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id0); }
170 static ByteSize Loongson_Cpucfg_id1_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id1); }
171 static ByteSize Loongson_Cpucfg_id2_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id2); }
172 static ByteSize Loongson_Cpucfg_id3_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id3); }
173 static ByteSize Loongson_Cpucfg_id4_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id4); }
174 static ByteSize Loongson_Cpucfg_id5_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id5); }
175 static ByteSize Loongson_Cpucfg_id6_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id6); }
176 static ByteSize Loongson_Cpucfg_id8_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id8); }
178 static bool is_determine_features_test_running() { return _is_determine_cpucfg_supported_running; }
180 static void clean_cpuFeatures() { _cpuFeatures = 0; }
182 // Initialization
183 static void initialize();
185 static bool cpu_info_is_initialized() { return _cpu_info_is_initialized; }
187 static bool supports_cpucfg() { return _is_cpucfg_instruction_supported; }
188 static bool set_supports_cpucfg(bool value) { return _is_cpucfg_instruction_supported = value; }
190 static bool is_loongson() { return _cpuFeatures & CPU_LOONGSON; }
191 static bool is_gs264() { return _cpuFeatures & CPU_LOONGSON_GS264; }
192 static bool is_gs464() { return _cpuFeatures & CPU_LOONGSON_GS464; }
193 static bool is_gs464e() { return _cpuFeatures & CPU_LOONGSON_GS464E; }
194 static bool supports_dsp() { return 0; /*not supported yet*/}
195 static bool supports_ps() { return 0; /*not supported yet*/}
196 static bool supports_3d() { return 0; /*not supported yet*/}
197 static bool supports_msa1_0() { return _cpuFeatures & CPU_MSA1_0; }
198 static bool supports_msa2_0() { return _cpuFeatures & CPU_MSA2_0; }
199 static bool supports_cgp() { return _cpuFeatures & CPU_CGP; }
200 static bool supports_mmi() { return _cpuFeatures & CPU_MMI; }
201 static bool supports_lsx1() { return _cpuFeatures & CPU_LSX1; }
202 static bool supports_lsx2() { return _cpuFeatures & CPU_LSX2; }
203 static bool supports_lasx() { return _cpuFeatures & CPU_LASX; }
204 static bool supports_lext1() { return _cpuFeatures & CPU_LEXT1; }
205 static bool supports_lext2() { return _cpuFeatures & CPU_LEXT2; }
206 static bool supports_lext3() { return _cpuFeatures & CPU_LEXT3; }
207 static bool supports_lamo() { return _cpuFeatures & CPU_LAMO; }
208 static bool supports_lpixu() { return _cpuFeatures & CPU_LPIXU; }
209 static bool needs_llsync() { return _cpuFeatures & CPU_LLSYNC; }
210 static bool needs_tgtsync() { return _cpuFeatures & CPU_TGTSYNC; }
211 static bool needs_ulsync() { return _cpuFeatures & CPU_ULSYNC; }
212 static bool supports_mualp() { return _cpuFeatures & CPU_MUALP; }
214 //mips has no such instructions, use ll/sc instead
215 static bool supports_compare_and_exchange() { return false; }
217 static const char* cpu_features() { return _features_str; }
219 };
221 #endif // CPU_MIPS_VM_VM_VERSION_MIPS_HPP
