Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/sparc/vm/macroAssembler_sparc.cpp	Thu Sep 22 02:04:40 2016 -0700
     1.2 +++ b/src/cpu/sparc/vm/macroAssembler_sparc.cpp	Fri Oct 21 20:34:04 2016 +0300
     1.3 @@ -4261,6 +4261,7 @@
     1.4    assert(UseBlockZeroing && VM_Version::has_block_zeroing(), "only works with BIS zeroing");
     1.5    Register end = count;
     1.6    int cache_line_size = VM_Version::prefetch_data_size();
     1.7 +  assert(cache_line_size > 0, "cache line size should be known for this code");
     1.8    // Minimum count when BIS zeroing can be used since
     1.9    // it needs membar which is expensive.
    1.10    int block_zero_size  = MAX2(cache_line_size*3, (int)BlockZeroingLowLimit);

     2.1 --- a/src/cpu/sparc/vm/vm_version_sparc.cpp	Thu Sep 22 02:04:40 2016 -0700
     2.2 +++ b/src/cpu/sparc/vm/vm_version_sparc.cpp	Fri Oct 21 20:34:04 2016 +0300
     2.3 @@ -74,7 +74,7 @@
     2.4      AllocatePrefetchDistance = AllocatePrefetchStepSize;
     2.5    }
     2.6  
     2.7 -  if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
     2.8 +  if (AllocatePrefetchStyle == 3 && (!has_blk_init() || cache_line_size <= 0)) {
     2.9      warning("BIS instructions are not available on this CPU");
    2.10      FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
    2.11    }
    2.12 @@ -138,7 +138,7 @@
    2.13        FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
    2.14      }
    2.15      if (is_niagara_plus()) {
    2.16 -      if (has_blk_init() && UseTLAB &&
    2.17 +      if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
    2.18            FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
    2.19          // Use BIS instruction for TLAB allocation prefetch.
    2.20          FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);