src/cpu/sparc/vm/vm_version_sparc.cpp

changeset 8924
26b1fe7cd851
parent 8645
a9bd2ebd8bcc
child 8729
402618d5afc9
child 8940
eb9e617d6f64
     1.1 --- a/src/cpu/sparc/vm/vm_version_sparc.cpp	Thu Sep 22 02:04:40 2016 -0700
     1.2 +++ b/src/cpu/sparc/vm/vm_version_sparc.cpp	Fri Oct 21 20:34:04 2016 +0300
     1.3 @@ -74,7 +74,7 @@
     1.4      AllocatePrefetchDistance = AllocatePrefetchStepSize;
     1.5    }
     1.6  
     1.7 -  if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
     1.8 +  if (AllocatePrefetchStyle == 3 && (!has_blk_init() || cache_line_size <= 0)) {
     1.9      warning("BIS instructions are not available on this CPU");
    1.10      FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
    1.11    }
    1.12 @@ -138,7 +138,7 @@
    1.13        FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
    1.14      }
    1.15      if (is_niagara_plus()) {
    1.16 -      if (has_blk_init() && UseTLAB &&
    1.17 +      if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
    1.18            FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
    1.19          // Use BIS instruction for TLAB allocation prefetch.
    1.20          FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);

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