# HG changeset patch
# User vkempik
# Date 1477071244 -10800
# Node ID 26b1fe7cd85126318429932180d767148f4b6ad0
# Parent  82f3ae5b4190583c203b7233908fec86d292584d
8157184: java/lang/invoke/LFCaching/LFMultiThreadCachingTest.java failed with a fatal error
Summary: Add missing cache_line_size > 0 checks.
Reviewed-by: kvn

diff -r 82f3ae5b4190 -r 26b1fe7cd851 src/cpu/sparc/vm/macroAssembler_sparc.cpp
--- a/src/cpu/sparc/vm/macroAssembler_sparc.cpp	Thu Sep 22 02:04:40 2016 -0700
+++ b/src/cpu/sparc/vm/macroAssembler_sparc.cpp	Fri Oct 21 20:34:04 2016 +0300
@@ -4261,6 +4261,7 @@
   assert(UseBlockZeroing && VM_Version::has_block_zeroing(), "only works with BIS zeroing");
   Register end = count;
   int cache_line_size = VM_Version::prefetch_data_size();
+  assert(cache_line_size > 0, "cache line size should be known for this code");
   // Minimum count when BIS zeroing can be used since
   // it needs membar which is expensive.
   int block_zero_size  = MAX2(cache_line_size*3, (int)BlockZeroingLowLimit);
diff -r 82f3ae5b4190 -r 26b1fe7cd851 src/cpu/sparc/vm/vm_version_sparc.cpp
--- a/src/cpu/sparc/vm/vm_version_sparc.cpp	Thu Sep 22 02:04:40 2016 -0700
+++ b/src/cpu/sparc/vm/vm_version_sparc.cpp	Fri Oct 21 20:34:04 2016 +0300
@@ -74,7 +74,7 @@
     AllocatePrefetchDistance = AllocatePrefetchStepSize;
   }
 
-  if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
+  if (AllocatePrefetchStyle == 3 && (!has_blk_init() || cache_line_size <= 0)) {
     warning("BIS instructions are not available on this CPU");
     FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
   }
@@ -138,7 +138,7 @@
       FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
     }
     if (is_niagara_plus()) {
-      if (has_blk_init() && UseTLAB &&
+      if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
           FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
         // Use BIS instruction for TLAB allocation prefetch.
         FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);