Wed, 03 Feb 2010 15:56:37 -0800
6921969: optimize 64 long multiply for case with high bits zero
Reviewed-by: never, twisti, kvn, rasbold
Contributed-by: Hiroshi Yamauchi <yamauchi@google.com>
1 //
2 // Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
25 // X86 Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source_hpp %{
239 // Must be visible to the DFA in dfa_x86_32.cpp
240 extern bool is_operand_hi32_zero(Node* n);
241 %}
243 source %{
244 #define RELOC_IMM32 Assembler::imm_operand
245 #define RELOC_DISP32 Assembler::disp32_operand
247 #define __ _masm.
249 // How to find the high register of a Long pair, given the low register
250 #define HIGH_FROM_LOW(x) ((x)+2)
252 // These masks are used to provide 128-bit aligned bitmasks to the XMM
253 // instructions, to allow sign-masking or sign-bit flipping. They allow
254 // fast versions of NegF/NegD and AbsF/AbsD.
256 // Note: 'double' and 'long long' have 32-bits alignment on x86.
257 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
258 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
259 // of 128-bits operands for SSE instructions.
260 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
261 // Store the value to a 128-bits operand.
262 operand[0] = lo;
263 operand[1] = hi;
264 return operand;
265 }
267 // Buffer for 128-bits masks used by SSE instructions.
268 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
270 // Static initialization during VM startup.
271 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
272 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
273 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
274 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
276 // Offset hacking within calls.
277 static int pre_call_FPU_size() {
278 if (Compile::current()->in_24_bit_fp_mode())
279 return 6; // fldcw
280 return 0;
281 }
283 static int preserve_SP_size() {
284 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg)
285 }
287 // !!!!! Special hack to get all type of calls to specify the byte offset
288 // from the start of the call to the point where the return address
289 // will point.
290 int MachCallStaticJavaNode::ret_addr_offset() {
291 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
292 if (_method_handle_invoke)
293 offset += preserve_SP_size();
294 return offset;
295 }
297 int MachCallDynamicJavaNode::ret_addr_offset() {
298 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
299 }
301 static int sizeof_FFree_Float_Stack_All = -1;
303 int MachCallRuntimeNode::ret_addr_offset() {
304 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
305 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
306 }
308 // Indicate if the safepoint node needs the polling page as an input.
309 // Since x86 does have absolute addressing, it doesn't.
310 bool SafePointNode::needs_polling_address_input() {
311 return false;
312 }
314 //
315 // Compute padding required for nodes which need alignment
316 //
318 // The address of the call instruction needs to be 4-byte aligned to
319 // ensure that it does not span a cache line so that it can be patched.
320 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
321 current_offset += pre_call_FPU_size(); // skip fldcw, if any
322 current_offset += 1; // skip call opcode byte
323 return round_to(current_offset, alignment_required()) - current_offset;
324 }
326 // The address of the call instruction needs to be 4-byte aligned to
327 // ensure that it does not span a cache line so that it can be patched.
328 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
329 current_offset += pre_call_FPU_size(); // skip fldcw, if any
330 current_offset += preserve_SP_size(); // skip mov rbp, rsp
331 current_offset += 1; // skip call opcode byte
332 return round_to(current_offset, alignment_required()) - current_offset;
333 }
335 // The address of the call instruction needs to be 4-byte aligned to
336 // ensure that it does not span a cache line so that it can be patched.
337 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
338 current_offset += pre_call_FPU_size(); // skip fldcw, if any
339 current_offset += 5; // skip MOV instruction
340 current_offset += 1; // skip call opcode byte
341 return round_to(current_offset, alignment_required()) - current_offset;
342 }
344 #ifndef PRODUCT
345 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
346 st->print("INT3");
347 }
348 #endif
350 // EMIT_RM()
351 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
352 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
353 *(cbuf.code_end()) = c;
354 cbuf.set_code_end(cbuf.code_end() + 1);
355 }
357 // EMIT_CC()
358 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
359 unsigned char c = (unsigned char)( f1 | f2 );
360 *(cbuf.code_end()) = c;
361 cbuf.set_code_end(cbuf.code_end() + 1);
362 }
364 // EMIT_OPCODE()
365 void emit_opcode(CodeBuffer &cbuf, int code) {
366 *(cbuf.code_end()) = (unsigned char)code;
367 cbuf.set_code_end(cbuf.code_end() + 1);
368 }
370 // EMIT_OPCODE() w/ relocation information
371 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
372 cbuf.relocate(cbuf.inst_mark() + offset, reloc);
373 emit_opcode(cbuf, code);
374 }
376 // EMIT_D8()
377 void emit_d8(CodeBuffer &cbuf, int d8) {
378 *(cbuf.code_end()) = (unsigned char)d8;
379 cbuf.set_code_end(cbuf.code_end() + 1);
380 }
382 // EMIT_D16()
383 void emit_d16(CodeBuffer &cbuf, int d16) {
384 *((short *)(cbuf.code_end())) = d16;
385 cbuf.set_code_end(cbuf.code_end() + 2);
386 }
388 // EMIT_D32()
389 void emit_d32(CodeBuffer &cbuf, int d32) {
390 *((int *)(cbuf.code_end())) = d32;
391 cbuf.set_code_end(cbuf.code_end() + 4);
392 }
394 // emit 32 bit value and construct relocation entry from relocInfo::relocType
395 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
396 int format) {
397 cbuf.relocate(cbuf.inst_mark(), reloc, format);
399 *((int *)(cbuf.code_end())) = d32;
400 cbuf.set_code_end(cbuf.code_end() + 4);
401 }
403 // emit 32 bit value and construct relocation entry from RelocationHolder
404 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
405 int format) {
406 #ifdef ASSERT
407 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
408 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
409 }
410 #endif
411 cbuf.relocate(cbuf.inst_mark(), rspec, format);
413 *((int *)(cbuf.code_end())) = d32;
414 cbuf.set_code_end(cbuf.code_end() + 4);
415 }
417 // Access stack slot for load or store
418 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
419 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
420 if( -128 <= disp && disp <= 127 ) {
421 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
422 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
423 emit_d8 (cbuf, disp); // Displacement // R/M byte
424 } else {
425 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
426 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
427 emit_d32(cbuf, disp); // Displacement // R/M byte
428 }
429 }
431 // eRegI ereg, memory mem) %{ // emit_reg_mem
432 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
433 // There is no index & no scale, use form without SIB byte
434 if ((index == 0x4) &&
435 (scale == 0) && (base != ESP_enc)) {
436 // If no displacement, mode is 0x0; unless base is [EBP]
437 if ( (displace == 0) && (base != EBP_enc) ) {
438 emit_rm(cbuf, 0x0, reg_encoding, base);
439 }
440 else { // If 8-bit displacement, mode 0x1
441 if ((displace >= -128) && (displace <= 127)
442 && !(displace_is_oop) ) {
443 emit_rm(cbuf, 0x1, reg_encoding, base);
444 emit_d8(cbuf, displace);
445 }
446 else { // If 32-bit displacement
447 if (base == -1) { // Special flag for absolute address
448 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
449 // (manual lies; no SIB needed here)
450 if ( displace_is_oop ) {
451 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
452 } else {
453 emit_d32 (cbuf, displace);
454 }
455 }
456 else { // Normal base + offset
457 emit_rm(cbuf, 0x2, reg_encoding, base);
458 if ( displace_is_oop ) {
459 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
460 } else {
461 emit_d32 (cbuf, displace);
462 }
463 }
464 }
465 }
466 }
467 else { // Else, encode with the SIB byte
468 // If no displacement, mode is 0x0; unless base is [EBP]
469 if (displace == 0 && (base != EBP_enc)) { // If no displacement
470 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
471 emit_rm(cbuf, scale, index, base);
472 }
473 else { // If 8-bit displacement, mode 0x1
474 if ((displace >= -128) && (displace <= 127)
475 && !(displace_is_oop) ) {
476 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
477 emit_rm(cbuf, scale, index, base);
478 emit_d8(cbuf, displace);
479 }
480 else { // If 32-bit displacement
481 if (base == 0x04 ) {
482 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
483 emit_rm(cbuf, scale, index, 0x04);
484 } else {
485 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
486 emit_rm(cbuf, scale, index, base);
487 }
488 if ( displace_is_oop ) {
489 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
490 } else {
491 emit_d32 (cbuf, displace);
492 }
493 }
494 }
495 }
496 }
499 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
500 if( dst_encoding == src_encoding ) {
501 // reg-reg copy, use an empty encoding
502 } else {
503 emit_opcode( cbuf, 0x8B );
504 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
505 }
506 }
508 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
509 if( dst_encoding == src_encoding ) {
510 // reg-reg copy, use an empty encoding
511 } else {
512 MacroAssembler _masm(&cbuf);
514 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
515 }
516 }
519 //=============================================================================
520 #ifndef PRODUCT
521 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
522 Compile* C = ra_->C;
523 if( C->in_24_bit_fp_mode() ) {
524 st->print("FLDCW 24 bit fpu control word");
525 st->print_cr(""); st->print("\t");
526 }
528 int framesize = C->frame_slots() << LogBytesPerInt;
529 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
530 // Remove two words for return addr and rbp,
531 framesize -= 2*wordSize;
533 // Calls to C2R adapters often do not accept exceptional returns.
534 // We require that their callers must bang for them. But be careful, because
535 // some VM calls (such as call site linkage) can use several kilobytes of
536 // stack. But the stack safety zone should account for that.
537 // See bugs 4446381, 4468289, 4497237.
538 if (C->need_stack_bang(framesize)) {
539 st->print_cr("# stack bang"); st->print("\t");
540 }
541 st->print_cr("PUSHL EBP"); st->print("\t");
543 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
544 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
545 st->print_cr(""); st->print("\t");
546 framesize -= wordSize;
547 }
549 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
550 if (framesize) {
551 st->print("SUB ESP,%d\t# Create frame",framesize);
552 }
553 } else {
554 st->print("SUB ESP,%d\t# Create frame",framesize);
555 }
556 }
557 #endif
560 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
561 Compile* C = ra_->C;
563 if (UseSSE >= 2 && VerifyFPU) {
564 MacroAssembler masm(&cbuf);
565 masm.verify_FPU(0, "FPU stack must be clean on entry");
566 }
568 // WARNING: Initial instruction MUST be 5 bytes or longer so that
569 // NativeJump::patch_verified_entry will be able to patch out the entry
570 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
571 // depth is ok at 5 bytes, the frame allocation can be either 3 or
572 // 6 bytes. So if we don't do the fldcw or the push then we must
573 // use the 6 byte frame allocation even if we have no frame. :-(
574 // If method sets FPU control word do it now
575 if( C->in_24_bit_fp_mode() ) {
576 MacroAssembler masm(&cbuf);
577 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
578 }
580 int framesize = C->frame_slots() << LogBytesPerInt;
581 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
582 // Remove two words for return addr and rbp,
583 framesize -= 2*wordSize;
585 // Calls to C2R adapters often do not accept exceptional returns.
586 // We require that their callers must bang for them. But be careful, because
587 // some VM calls (such as call site linkage) can use several kilobytes of
588 // stack. But the stack safety zone should account for that.
589 // See bugs 4446381, 4468289, 4497237.
590 if (C->need_stack_bang(framesize)) {
591 MacroAssembler masm(&cbuf);
592 masm.generate_stack_overflow_check(framesize);
593 }
595 // We always push rbp, so that on return to interpreter rbp, will be
596 // restored correctly and we can correct the stack.
597 emit_opcode(cbuf, 0x50 | EBP_enc);
599 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
600 emit_opcode(cbuf, 0x68); // push 0xbadb100d
601 emit_d32(cbuf, 0xbadb100d);
602 framesize -= wordSize;
603 }
605 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
606 if (framesize) {
607 emit_opcode(cbuf, 0x83); // sub SP,#framesize
608 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
609 emit_d8(cbuf, framesize);
610 }
611 } else {
612 emit_opcode(cbuf, 0x81); // sub SP,#framesize
613 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
614 emit_d32(cbuf, framesize);
615 }
616 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
618 #ifdef ASSERT
619 if (VerifyStackAtCalls) {
620 Label L;
621 MacroAssembler masm(&cbuf);
622 masm.push(rax);
623 masm.mov(rax, rsp);
624 masm.andptr(rax, StackAlignmentInBytes-1);
625 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
626 masm.pop(rax);
627 masm.jcc(Assembler::equal, L);
628 masm.stop("Stack is not properly aligned!");
629 masm.bind(L);
630 }
631 #endif
633 }
635 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
636 return MachNode::size(ra_); // too many variables; just compute it the hard way
637 }
639 int MachPrologNode::reloc() const {
640 return 0; // a large enough number
641 }
643 //=============================================================================
644 #ifndef PRODUCT
645 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
646 Compile *C = ra_->C;
647 int framesize = C->frame_slots() << LogBytesPerInt;
648 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
649 // Remove two words for return addr and rbp,
650 framesize -= 2*wordSize;
652 if( C->in_24_bit_fp_mode() ) {
653 st->print("FLDCW standard control word");
654 st->cr(); st->print("\t");
655 }
656 if( framesize ) {
657 st->print("ADD ESP,%d\t# Destroy frame",framesize);
658 st->cr(); st->print("\t");
659 }
660 st->print_cr("POPL EBP"); st->print("\t");
661 if( do_polling() && C->is_method_compilation() ) {
662 st->print("TEST PollPage,EAX\t! Poll Safepoint");
663 st->cr(); st->print("\t");
664 }
665 }
666 #endif
668 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
669 Compile *C = ra_->C;
671 // If method set FPU control word, restore to standard control word
672 if( C->in_24_bit_fp_mode() ) {
673 MacroAssembler masm(&cbuf);
674 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
675 }
677 int framesize = C->frame_slots() << LogBytesPerInt;
678 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
679 // Remove two words for return addr and rbp,
680 framesize -= 2*wordSize;
682 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
684 if( framesize >= 128 ) {
685 emit_opcode(cbuf, 0x81); // add SP, #framesize
686 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
687 emit_d32(cbuf, framesize);
688 }
689 else if( framesize ) {
690 emit_opcode(cbuf, 0x83); // add SP, #framesize
691 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
692 emit_d8(cbuf, framesize);
693 }
695 emit_opcode(cbuf, 0x58 | EBP_enc);
697 if( do_polling() && C->is_method_compilation() ) {
698 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0);
699 emit_opcode(cbuf,0x85);
700 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
701 emit_d32(cbuf, (intptr_t)os::get_polling_page());
702 }
703 }
705 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
706 Compile *C = ra_->C;
707 // If method set FPU control word, restore to standard control word
708 int size = C->in_24_bit_fp_mode() ? 6 : 0;
709 if( do_polling() && C->is_method_compilation() ) size += 6;
711 int framesize = C->frame_slots() << LogBytesPerInt;
712 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
713 // Remove two words for return addr and rbp,
714 framesize -= 2*wordSize;
716 size++; // popl rbp,
718 if( framesize >= 128 ) {
719 size += 6;
720 } else {
721 size += framesize ? 3 : 0;
722 }
723 return size;
724 }
726 int MachEpilogNode::reloc() const {
727 return 0; // a large enough number
728 }
730 const Pipeline * MachEpilogNode::pipeline() const {
731 return MachNode::pipeline_class();
732 }
734 int MachEpilogNode::safepoint_offset() const { return 0; }
736 //=============================================================================
738 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
739 static enum RC rc_class( OptoReg::Name reg ) {
741 if( !OptoReg::is_valid(reg) ) return rc_bad;
742 if (OptoReg::is_stack(reg)) return rc_stack;
744 VMReg r = OptoReg::as_VMReg(reg);
745 if (r->is_Register()) return rc_int;
746 if (r->is_FloatRegister()) {
747 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
748 return rc_float;
749 }
750 assert(r->is_XMMRegister(), "must be");
751 return rc_xmm;
752 }
754 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
755 int opcode, const char *op_str, int size, outputStream* st ) {
756 if( cbuf ) {
757 emit_opcode (*cbuf, opcode );
758 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
759 #ifndef PRODUCT
760 } else if( !do_size ) {
761 if( size != 0 ) st->print("\n\t");
762 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
763 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
764 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
765 } else { // FLD, FST, PUSH, POP
766 st->print("%s [ESP + #%d]",op_str,offset);
767 }
768 #endif
769 }
770 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
771 return size+3+offset_size;
772 }
774 // Helper for XMM registers. Extra opcode bits, limited syntax.
775 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
776 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
777 if( cbuf ) {
778 if( reg_lo+1 == reg_hi ) { // double move?
779 if( is_load && !UseXmmLoadAndClearUpper )
780 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load
781 else
782 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise
783 } else {
784 emit_opcode(*cbuf, 0xF3 );
785 }
786 emit_opcode(*cbuf, 0x0F );
787 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper )
788 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load
789 else
790 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 );
791 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false);
792 #ifndef PRODUCT
793 } else if( !do_size ) {
794 if( size != 0 ) st->print("\n\t");
795 if( reg_lo+1 == reg_hi ) { // double move?
796 if( is_load ) st->print("%s %s,[ESP + #%d]",
797 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
798 Matcher::regName[reg_lo], offset);
799 else st->print("MOVSD [ESP + #%d],%s",
800 offset, Matcher::regName[reg_lo]);
801 } else {
802 if( is_load ) st->print("MOVSS %s,[ESP + #%d]",
803 Matcher::regName[reg_lo], offset);
804 else st->print("MOVSS [ESP + #%d],%s",
805 offset, Matcher::regName[reg_lo]);
806 }
807 #endif
808 }
809 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
810 return size+5+offset_size;
811 }
814 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
815 int src_hi, int dst_hi, int size, outputStream* st ) {
816 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers
817 if( cbuf ) {
818 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) {
819 emit_opcode(*cbuf, 0x66 );
820 }
821 emit_opcode(*cbuf, 0x0F );
822 emit_opcode(*cbuf, 0x28 );
823 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
824 #ifndef PRODUCT
825 } else if( !do_size ) {
826 if( size != 0 ) st->print("\n\t");
827 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
828 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
829 } else {
830 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
831 }
832 #endif
833 }
834 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3);
835 } else {
836 if( cbuf ) {
837 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 );
838 emit_opcode(*cbuf, 0x0F );
839 emit_opcode(*cbuf, 0x10 );
840 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
841 #ifndef PRODUCT
842 } else if( !do_size ) {
843 if( size != 0 ) st->print("\n\t");
844 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
845 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
846 } else {
847 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
848 }
849 #endif
850 }
851 return size+4;
852 }
853 }
855 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
856 if( cbuf ) {
857 emit_opcode(*cbuf, 0x8B );
858 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
859 #ifndef PRODUCT
860 } else if( !do_size ) {
861 if( size != 0 ) st->print("\n\t");
862 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
863 #endif
864 }
865 return size+2;
866 }
868 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
869 int offset, int size, outputStream* st ) {
870 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
871 if( cbuf ) {
872 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
873 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
874 #ifndef PRODUCT
875 } else if( !do_size ) {
876 if( size != 0 ) st->print("\n\t");
877 st->print("FLD %s",Matcher::regName[src_lo]);
878 #endif
879 }
880 size += 2;
881 }
883 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
884 const char *op_str;
885 int op;
886 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
887 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
888 op = 0xDD;
889 } else { // 32-bit store
890 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
891 op = 0xD9;
892 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
893 }
895 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
896 }
898 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
899 // Get registers to move
900 OptoReg::Name src_second = ra_->get_reg_second(in(1));
901 OptoReg::Name src_first = ra_->get_reg_first(in(1));
902 OptoReg::Name dst_second = ra_->get_reg_second(this );
903 OptoReg::Name dst_first = ra_->get_reg_first(this );
905 enum RC src_second_rc = rc_class(src_second);
906 enum RC src_first_rc = rc_class(src_first);
907 enum RC dst_second_rc = rc_class(dst_second);
908 enum RC dst_first_rc = rc_class(dst_first);
910 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
912 // Generate spill code!
913 int size = 0;
915 if( src_first == dst_first && src_second == dst_second )
916 return size; // Self copy, no move
918 // --------------------------------------
919 // Check for mem-mem move. push/pop to move.
920 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
921 if( src_second == dst_first ) { // overlapping stack copy ranges
922 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
923 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
924 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
925 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
926 }
927 // move low bits
928 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
929 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
930 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
931 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
932 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
933 }
934 return size;
935 }
937 // --------------------------------------
938 // Check for integer reg-reg copy
939 if( src_first_rc == rc_int && dst_first_rc == rc_int )
940 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
942 // Check for integer store
943 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
944 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
946 // Check for integer load
947 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
948 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
950 // --------------------------------------
951 // Check for float reg-reg copy
952 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
953 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
954 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
955 if( cbuf ) {
957 // Note the mucking with the register encode to compensate for the 0/1
958 // indexing issue mentioned in a comment in the reg_def sections
959 // for FPR registers many lines above here.
961 if( src_first != FPR1L_num ) {
962 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
963 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
964 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
965 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
966 } else {
967 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
968 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
969 }
970 #ifndef PRODUCT
971 } else if( !do_size ) {
972 if( size != 0 ) st->print("\n\t");
973 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
974 else st->print( "FST %s", Matcher::regName[dst_first]);
975 #endif
976 }
977 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
978 }
980 // Check for float store
981 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
982 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
983 }
985 // Check for float load
986 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
987 int offset = ra_->reg2offset(src_first);
988 const char *op_str;
989 int op;
990 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
991 op_str = "FLD_D";
992 op = 0xDD;
993 } else { // 32-bit load
994 op_str = "FLD_S";
995 op = 0xD9;
996 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
997 }
998 if( cbuf ) {
999 emit_opcode (*cbuf, op );
1000 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
1001 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1002 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1003 #ifndef PRODUCT
1004 } else if( !do_size ) {
1005 if( size != 0 ) st->print("\n\t");
1006 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1007 #endif
1008 }
1009 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1010 return size + 3+offset_size+2;
1011 }
1013 // Check for xmm reg-reg copy
1014 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1015 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1016 (src_first+1 == src_second && dst_first+1 == dst_second),
1017 "no non-adjacent float-moves" );
1018 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1019 }
1021 // Check for xmm store
1022 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1023 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1024 }
1026 // Check for float xmm load
1027 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1028 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1029 }
1031 // Copy from float reg to xmm reg
1032 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1033 // copy to the top of stack from floating point reg
1034 // and use LEA to preserve flags
1035 if( cbuf ) {
1036 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1037 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1038 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1039 emit_d8(*cbuf,0xF8);
1040 #ifndef PRODUCT
1041 } else if( !do_size ) {
1042 if( size != 0 ) st->print("\n\t");
1043 st->print("LEA ESP,[ESP-8]");
1044 #endif
1045 }
1046 size += 4;
1048 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1050 // Copy from the temp memory to the xmm reg.
1051 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1053 if( cbuf ) {
1054 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1055 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1056 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1057 emit_d8(*cbuf,0x08);
1058 #ifndef PRODUCT
1059 } else if( !do_size ) {
1060 if( size != 0 ) st->print("\n\t");
1061 st->print("LEA ESP,[ESP+8]");
1062 #endif
1063 }
1064 size += 4;
1065 return size;
1066 }
1068 assert( size > 0, "missed a case" );
1070 // --------------------------------------------------------------------
1071 // Check for second bits still needing moving.
1072 if( src_second == dst_second )
1073 return size; // Self copy; no move
1074 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1076 // Check for second word int-int move
1077 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1078 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1080 // Check for second word integer store
1081 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1082 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1084 // Check for second word integer load
1085 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1086 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1089 Unimplemented();
1090 }
1092 #ifndef PRODUCT
1093 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1094 implementation( NULL, ra_, false, st );
1095 }
1096 #endif
1098 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1099 implementation( &cbuf, ra_, false, NULL );
1100 }
1102 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1103 return implementation( NULL, ra_, true, NULL );
1104 }
1106 //=============================================================================
1107 #ifndef PRODUCT
1108 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1109 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1110 }
1111 #endif
1113 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1114 MacroAssembler _masm(&cbuf);
1115 __ nop(_count);
1116 }
1118 uint MachNopNode::size(PhaseRegAlloc *) const {
1119 return _count;
1120 }
1123 //=============================================================================
1124 #ifndef PRODUCT
1125 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1126 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1127 int reg = ra_->get_reg_first(this);
1128 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1129 }
1130 #endif
1132 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1133 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1134 int reg = ra_->get_encode(this);
1135 if( offset >= 128 ) {
1136 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1137 emit_rm(cbuf, 0x2, reg, 0x04);
1138 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1139 emit_d32(cbuf, offset);
1140 }
1141 else {
1142 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1143 emit_rm(cbuf, 0x1, reg, 0x04);
1144 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1145 emit_d8(cbuf, offset);
1146 }
1147 }
1149 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1150 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1151 if( offset >= 128 ) {
1152 return 7;
1153 }
1154 else {
1155 return 4;
1156 }
1157 }
1159 //=============================================================================
1161 // emit call stub, compiled java to interpreter
1162 void emit_java_to_interp(CodeBuffer &cbuf ) {
1163 // Stub is fixed up when the corresponding call is converted from calling
1164 // compiled code to calling interpreted code.
1165 // mov rbx,0
1166 // jmp -1
1168 address mark = cbuf.inst_mark(); // get mark within main instrs section
1170 // Note that the code buffer's inst_mark is always relative to insts.
1171 // That's why we must use the macroassembler to generate a stub.
1172 MacroAssembler _masm(&cbuf);
1174 address base =
1175 __ start_a_stub(Compile::MAX_stubs_size);
1176 if (base == NULL) return; // CodeBuffer::expand failed
1177 // static stub relocation stores the instruction address of the call
1178 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1179 // static stub relocation also tags the methodOop in the code-stream.
1180 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1181 // This is recognized as unresolved by relocs/nativeInst/ic code
1182 __ jump(RuntimeAddress(__ pc()));
1184 __ end_a_stub();
1185 // Update current stubs pointer and restore code_end.
1186 }
1187 // size of call stub, compiled java to interpretor
1188 uint size_java_to_interp() {
1189 return 10; // movl; jmp
1190 }
1191 // relocation entries for call stub, compiled java to interpretor
1192 uint reloc_java_to_interp() {
1193 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1194 }
1196 //=============================================================================
1197 #ifndef PRODUCT
1198 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1199 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1200 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1201 st->print_cr("\tNOP");
1202 st->print_cr("\tNOP");
1203 if( !OptoBreakpoint )
1204 st->print_cr("\tNOP");
1205 }
1206 #endif
1208 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1209 MacroAssembler masm(&cbuf);
1210 #ifdef ASSERT
1211 uint code_size = cbuf.code_size();
1212 #endif
1213 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1214 masm.jump_cc(Assembler::notEqual,
1215 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1216 /* WARNING these NOPs are critical so that verified entry point is properly
1217 aligned for patching by NativeJump::patch_verified_entry() */
1218 int nops_cnt = 2;
1219 if( !OptoBreakpoint ) // Leave space for int3
1220 nops_cnt += 1;
1221 masm.nop(nops_cnt);
1223 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node");
1224 }
1226 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1227 return OptoBreakpoint ? 11 : 12;
1228 }
1231 //=============================================================================
1232 uint size_exception_handler() {
1233 // NativeCall instruction size is the same as NativeJump.
1234 // exception handler starts out as jump and can be patched to
1235 // a call be deoptimization. (4932387)
1236 // Note that this value is also credited (in output.cpp) to
1237 // the size of the code section.
1238 return NativeJump::instruction_size;
1239 }
1241 // Emit exception handler code. Stuff framesize into a register
1242 // and call a VM stub routine.
1243 int emit_exception_handler(CodeBuffer& cbuf) {
1245 // Note that the code buffer's inst_mark is always relative to insts.
1246 // That's why we must use the macroassembler to generate a handler.
1247 MacroAssembler _masm(&cbuf);
1248 address base =
1249 __ start_a_stub(size_exception_handler());
1250 if (base == NULL) return 0; // CodeBuffer::expand failed
1251 int offset = __ offset();
1252 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1253 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1254 __ end_a_stub();
1255 return offset;
1256 }
1258 uint size_deopt_handler() {
1259 // NativeCall instruction size is the same as NativeJump.
1260 // exception handler starts out as jump and can be patched to
1261 // a call be deoptimization. (4932387)
1262 // Note that this value is also credited (in output.cpp) to
1263 // the size of the code section.
1264 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1265 }
1267 // Emit deopt handler code.
1268 int emit_deopt_handler(CodeBuffer& cbuf) {
1270 // Note that the code buffer's inst_mark is always relative to insts.
1271 // That's why we must use the macroassembler to generate a handler.
1272 MacroAssembler _masm(&cbuf);
1273 address base =
1274 __ start_a_stub(size_exception_handler());
1275 if (base == NULL) return 0; // CodeBuffer::expand failed
1276 int offset = __ offset();
1277 InternalAddress here(__ pc());
1278 __ pushptr(here.addr());
1280 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1281 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1282 __ end_a_stub();
1283 return offset;
1284 }
1287 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1288 int mark = cbuf.insts()->mark_off();
1289 MacroAssembler _masm(&cbuf);
1290 address double_address = __ double_constant(x);
1291 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1292 emit_d32_reloc(cbuf,
1293 (int)double_address,
1294 internal_word_Relocation::spec(double_address),
1295 RELOC_DISP32);
1296 }
1298 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1299 int mark = cbuf.insts()->mark_off();
1300 MacroAssembler _masm(&cbuf);
1301 address float_address = __ float_constant(x);
1302 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1303 emit_d32_reloc(cbuf,
1304 (int)float_address,
1305 internal_word_Relocation::spec(float_address),
1306 RELOC_DISP32);
1307 }
1310 const bool Matcher::match_rule_supported(int opcode) {
1311 if (!has_match_rule(opcode))
1312 return false;
1314 return true; // Per default match rules are supported.
1315 }
1317 int Matcher::regnum_to_fpu_offset(int regnum) {
1318 return regnum - 32; // The FP registers are in the second chunk
1319 }
1321 bool is_positive_zero_float(jfloat f) {
1322 return jint_cast(f) == jint_cast(0.0F);
1323 }
1325 bool is_positive_one_float(jfloat f) {
1326 return jint_cast(f) == jint_cast(1.0F);
1327 }
1329 bool is_positive_zero_double(jdouble d) {
1330 return jlong_cast(d) == jlong_cast(0.0);
1331 }
1333 bool is_positive_one_double(jdouble d) {
1334 return jlong_cast(d) == jlong_cast(1.0);
1335 }
1337 // This is UltraSparc specific, true just means we have fast l2f conversion
1338 const bool Matcher::convL2FSupported(void) {
1339 return true;
1340 }
1342 // Vector width in bytes
1343 const uint Matcher::vector_width_in_bytes(void) {
1344 return UseSSE >= 2 ? 8 : 0;
1345 }
1347 // Vector ideal reg
1348 const uint Matcher::vector_ideal_reg(void) {
1349 return Op_RegD;
1350 }
1352 // Is this branch offset short enough that a short branch can be used?
1353 //
1354 // NOTE: If the platform does not provide any short branch variants, then
1355 // this method should return false for offset 0.
1356 bool Matcher::is_short_branch_offset(int rule, int offset) {
1357 // the short version of jmpConUCF2 contains multiple branches,
1358 // making the reach slightly less
1359 if (rule == jmpConUCF2_rule)
1360 return (-126 <= offset && offset <= 125);
1361 return (-128 <= offset && offset <= 127);
1362 }
1364 const bool Matcher::isSimpleConstant64(jlong value) {
1365 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1366 return false;
1367 }
1369 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1370 const bool Matcher::init_array_count_is_in_bytes = false;
1372 // Threshold size for cleararray.
1373 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1375 // Should the Matcher clone shifts on addressing modes, expecting them to
1376 // be subsumed into complex addressing expressions or compute them into
1377 // registers? True for Intel but false for most RISCs
1378 const bool Matcher::clone_shift_expressions = true;
1380 // Is it better to copy float constants, or load them directly from memory?
1381 // Intel can load a float constant from a direct address, requiring no
1382 // extra registers. Most RISCs will have to materialize an address into a
1383 // register first, so they would do better to copy the constant from stack.
1384 const bool Matcher::rematerialize_float_constants = true;
1386 // If CPU can load and store mis-aligned doubles directly then no fixup is
1387 // needed. Else we split the double into 2 integer pieces and move it
1388 // piece-by-piece. Only happens when passing doubles into C code as the
1389 // Java calling convention forces doubles to be aligned.
1390 const bool Matcher::misaligned_doubles_ok = true;
1393 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1394 // Get the memory operand from the node
1395 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1396 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1397 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1398 uint opcnt = 1; // First operand
1399 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1400 while( idx >= skipped+num_edges ) {
1401 skipped += num_edges;
1402 opcnt++; // Bump operand count
1403 assert( opcnt < numopnds, "Accessing non-existent operand" );
1404 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1405 }
1407 MachOper *memory = node->_opnds[opcnt];
1408 MachOper *new_memory = NULL;
1409 switch (memory->opcode()) {
1410 case DIRECT:
1411 case INDOFFSET32X:
1412 // No transformation necessary.
1413 return;
1414 case INDIRECT:
1415 new_memory = new (C) indirect_win95_safeOper( );
1416 break;
1417 case INDOFFSET8:
1418 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1419 break;
1420 case INDOFFSET32:
1421 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1422 break;
1423 case INDINDEXOFFSET:
1424 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1425 break;
1426 case INDINDEXSCALE:
1427 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1428 break;
1429 case INDINDEXSCALEOFFSET:
1430 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1431 break;
1432 case LOAD_LONG_INDIRECT:
1433 case LOAD_LONG_INDOFFSET32:
1434 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1435 return;
1436 default:
1437 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1438 return;
1439 }
1440 node->_opnds[opcnt] = new_memory;
1441 }
1443 // Advertise here if the CPU requires explicit rounding operations
1444 // to implement the UseStrictFP mode.
1445 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1447 // Do floats take an entire double register or just half?
1448 const bool Matcher::float_in_double = true;
1449 // Do ints take an entire long register or just half?
1450 const bool Matcher::int_in_long = false;
1452 // Return whether or not this register is ever used as an argument. This
1453 // function is used on startup to build the trampoline stubs in generateOptoStub.
1454 // Registers not mentioned will be killed by the VM call in the trampoline, and
1455 // arguments in those registers not be available to the callee.
1456 bool Matcher::can_be_java_arg( int reg ) {
1457 if( reg == ECX_num || reg == EDX_num ) return true;
1458 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1459 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1460 return false;
1461 }
1463 bool Matcher::is_spillable_arg( int reg ) {
1464 return can_be_java_arg(reg);
1465 }
1467 // Register for DIVI projection of divmodI
1468 RegMask Matcher::divI_proj_mask() {
1469 return EAX_REG_mask;
1470 }
1472 // Register for MODI projection of divmodI
1473 RegMask Matcher::modI_proj_mask() {
1474 return EDX_REG_mask;
1475 }
1477 // Register for DIVL projection of divmodL
1478 RegMask Matcher::divL_proj_mask() {
1479 ShouldNotReachHere();
1480 return RegMask();
1481 }
1483 // Register for MODL projection of divmodL
1484 RegMask Matcher::modL_proj_mask() {
1485 ShouldNotReachHere();
1486 return RegMask();
1487 }
1489 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1490 return EBP_REG_mask;
1491 }
1493 // Returns true if the high 32 bits of the value is known to be zero.
1494 bool is_operand_hi32_zero(Node* n) {
1495 int opc = n->Opcode();
1496 if (opc == Op_LoadUI2L) {
1497 return true;
1498 }
1499 if (opc == Op_AndL) {
1500 Node* o2 = n->in(2);
1501 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1502 return true;
1503 }
1504 }
1505 return false;
1506 }
1508 %}
1510 //----------ENCODING BLOCK-----------------------------------------------------
1511 // This block specifies the encoding classes used by the compiler to output
1512 // byte streams. Encoding classes generate functions which are called by
1513 // Machine Instruction Nodes in order to generate the bit encoding of the
1514 // instruction. Operands specify their base encoding interface with the
1515 // interface keyword. There are currently supported four interfaces,
1516 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1517 // operand to generate a function which returns its register number when
1518 // queried. CONST_INTER causes an operand to generate a function which
1519 // returns the value of the constant when queried. MEMORY_INTER causes an
1520 // operand to generate four functions which return the Base Register, the
1521 // Index Register, the Scale Value, and the Offset Value of the operand when
1522 // queried. COND_INTER causes an operand to generate six functions which
1523 // return the encoding code (ie - encoding bits for the instruction)
1524 // associated with each basic boolean condition for a conditional instruction.
1525 // Instructions specify two basic values for encoding. They use the
1526 // ins_encode keyword to specify their encoding class (which must be one of
1527 // the class names specified in the encoding block), and they use the
1528 // opcode keyword to specify, in order, their primary, secondary, and
1529 // tertiary opcode. Only the opcode sections which a particular instruction
1530 // needs for encoding need to be specified.
1531 encode %{
1532 // Build emit functions for each basic byte or larger field in the intel
1533 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1534 // code in the enc_class source block. Emit functions will live in the
1535 // main source block for now. In future, we can generalize this by
1536 // adding a syntax that specifies the sizes of fields in an order,
1537 // so that the adlc can build the emit functions automagically
1539 // Emit primary opcode
1540 enc_class OpcP %{
1541 emit_opcode(cbuf, $primary);
1542 %}
1544 // Emit secondary opcode
1545 enc_class OpcS %{
1546 emit_opcode(cbuf, $secondary);
1547 %}
1549 // Emit opcode directly
1550 enc_class Opcode(immI d8) %{
1551 emit_opcode(cbuf, $d8$$constant);
1552 %}
1554 enc_class SizePrefix %{
1555 emit_opcode(cbuf,0x66);
1556 %}
1558 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1559 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1560 %}
1562 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1563 emit_opcode(cbuf,$opcode$$constant);
1564 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1565 %}
1567 enc_class mov_r32_imm0( eRegI dst ) %{
1568 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1569 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1570 %}
1572 enc_class cdq_enc %{
1573 // Full implementation of Java idiv and irem; checks for
1574 // special case as described in JVM spec., p.243 & p.271.
1575 //
1576 // normal case special case
1577 //
1578 // input : rax,: dividend min_int
1579 // reg: divisor -1
1580 //
1581 // output: rax,: quotient (= rax, idiv reg) min_int
1582 // rdx: remainder (= rax, irem reg) 0
1583 //
1584 // Code sequnce:
1585 //
1586 // 81 F8 00 00 00 80 cmp rax,80000000h
1587 // 0F 85 0B 00 00 00 jne normal_case
1588 // 33 D2 xor rdx,edx
1589 // 83 F9 FF cmp rcx,0FFh
1590 // 0F 84 03 00 00 00 je done
1591 // normal_case:
1592 // 99 cdq
1593 // F7 F9 idiv rax,ecx
1594 // done:
1595 //
1596 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1597 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1598 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1599 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1600 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1601 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1602 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1603 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1604 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1605 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1606 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1607 // normal_case:
1608 emit_opcode(cbuf,0x99); // cdq
1609 // idiv (note: must be emitted by the user of this rule)
1610 // normal:
1611 %}
1613 // Dense encoding for older common ops
1614 enc_class Opc_plus(immI opcode, eRegI reg) %{
1615 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1616 %}
1619 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1620 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1621 // Check for 8-bit immediate, and set sign extend bit in opcode
1622 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1623 emit_opcode(cbuf, $primary | 0x02);
1624 }
1625 else { // If 32-bit immediate
1626 emit_opcode(cbuf, $primary);
1627 }
1628 %}
1630 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1631 // Emit primary opcode and set sign-extend bit
1632 // Check for 8-bit immediate, and set sign extend bit in opcode
1633 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1634 emit_opcode(cbuf, $primary | 0x02); }
1635 else { // If 32-bit immediate
1636 emit_opcode(cbuf, $primary);
1637 }
1638 // Emit r/m byte with secondary opcode, after primary opcode.
1639 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1640 %}
1642 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1643 // Check for 8-bit immediate, and set sign extend bit in opcode
1644 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1645 $$$emit8$imm$$constant;
1646 }
1647 else { // If 32-bit immediate
1648 // Output immediate
1649 $$$emit32$imm$$constant;
1650 }
1651 %}
1653 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1654 // Emit primary opcode and set sign-extend bit
1655 // Check for 8-bit immediate, and set sign extend bit in opcode
1656 int con = (int)$imm$$constant; // Throw away top bits
1657 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1658 // Emit r/m byte with secondary opcode, after primary opcode.
1659 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1660 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1661 else emit_d32(cbuf,con);
1662 %}
1664 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1665 // Emit primary opcode and set sign-extend bit
1666 // Check for 8-bit immediate, and set sign extend bit in opcode
1667 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1668 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1669 // Emit r/m byte with tertiary opcode, after primary opcode.
1670 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1671 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1672 else emit_d32(cbuf,con);
1673 %}
1675 enc_class Lbl (label labl) %{ // JMP, CALL
1676 Label *l = $labl$$label;
1677 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1678 %}
1680 enc_class LblShort (label labl) %{ // JMP, CALL
1681 Label *l = $labl$$label;
1682 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1683 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1684 emit_d8(cbuf, disp);
1685 %}
1687 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1688 emit_cc(cbuf, $secondary, $dst$$reg );
1689 %}
1691 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1692 int destlo = $dst$$reg;
1693 int desthi = HIGH_FROM_LOW(destlo);
1694 // bswap lo
1695 emit_opcode(cbuf, 0x0F);
1696 emit_cc(cbuf, 0xC8, destlo);
1697 // bswap hi
1698 emit_opcode(cbuf, 0x0F);
1699 emit_cc(cbuf, 0xC8, desthi);
1700 // xchg lo and hi
1701 emit_opcode(cbuf, 0x87);
1702 emit_rm(cbuf, 0x3, destlo, desthi);
1703 %}
1705 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1706 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1707 %}
1709 enc_class Jcc (cmpOp cop, label labl) %{ // JCC
1710 Label *l = $labl$$label;
1711 $$$emit8$primary;
1712 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1713 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1714 %}
1716 enc_class JccShort (cmpOp cop, label labl) %{ // JCC
1717 Label *l = $labl$$label;
1718 emit_cc(cbuf, $primary, $cop$$cmpcode);
1719 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1720 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1721 emit_d8(cbuf, disp);
1722 %}
1724 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1725 $$$emit8$primary;
1726 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1727 %}
1729 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1730 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1731 emit_d8(cbuf, op >> 8 );
1732 emit_d8(cbuf, op & 255);
1733 %}
1735 // emulate a CMOV with a conditional branch around a MOV
1736 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1737 // Invert sense of branch from sense of CMOV
1738 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1739 emit_d8( cbuf, $brOffs$$constant );
1740 %}
1742 enc_class enc_PartialSubtypeCheck( ) %{
1743 Register Redi = as_Register(EDI_enc); // result register
1744 Register Reax = as_Register(EAX_enc); // super class
1745 Register Recx = as_Register(ECX_enc); // killed
1746 Register Resi = as_Register(ESI_enc); // sub class
1747 Label miss;
1749 MacroAssembler _masm(&cbuf);
1750 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1751 NULL, &miss,
1752 /*set_cond_codes:*/ true);
1753 if ($primary) {
1754 __ xorptr(Redi, Redi);
1755 }
1756 __ bind(miss);
1757 %}
1759 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1760 MacroAssembler masm(&cbuf);
1761 int start = masm.offset();
1762 if (UseSSE >= 2) {
1763 if (VerifyFPU) {
1764 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1765 }
1766 } else {
1767 // External c_calling_convention expects the FPU stack to be 'clean'.
1768 // Compiled code leaves it dirty. Do cleanup now.
1769 masm.empty_FPU_stack();
1770 }
1771 if (sizeof_FFree_Float_Stack_All == -1) {
1772 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1773 } else {
1774 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1775 }
1776 %}
1778 enc_class Verify_FPU_For_Leaf %{
1779 if( VerifyFPU ) {
1780 MacroAssembler masm(&cbuf);
1781 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1782 }
1783 %}
1785 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1786 // This is the instruction starting address for relocation info.
1787 cbuf.set_inst_mark();
1788 $$$emit8$primary;
1789 // CALL directly to the runtime
1790 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1791 runtime_call_Relocation::spec(), RELOC_IMM32 );
1793 if (UseSSE >= 2) {
1794 MacroAssembler _masm(&cbuf);
1795 BasicType rt = tf()->return_type();
1797 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1798 // A C runtime call where the return value is unused. In SSE2+
1799 // mode the result needs to be removed from the FPU stack. It's
1800 // likely that this function call could be removed by the
1801 // optimizer if the C function is a pure function.
1802 __ ffree(0);
1803 } else if (rt == T_FLOAT) {
1804 __ lea(rsp, Address(rsp, -4));
1805 __ fstp_s(Address(rsp, 0));
1806 __ movflt(xmm0, Address(rsp, 0));
1807 __ lea(rsp, Address(rsp, 4));
1808 } else if (rt == T_DOUBLE) {
1809 __ lea(rsp, Address(rsp, -8));
1810 __ fstp_d(Address(rsp, 0));
1811 __ movdbl(xmm0, Address(rsp, 0));
1812 __ lea(rsp, Address(rsp, 8));
1813 }
1814 }
1815 %}
1818 enc_class pre_call_FPU %{
1819 // If method sets FPU control word restore it here
1820 debug_only(int off0 = cbuf.code_size());
1821 if( Compile::current()->in_24_bit_fp_mode() ) {
1822 MacroAssembler masm(&cbuf);
1823 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1824 }
1825 debug_only(int off1 = cbuf.code_size());
1826 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1827 %}
1829 enc_class post_call_FPU %{
1830 // If method sets FPU control word do it here also
1831 if( Compile::current()->in_24_bit_fp_mode() ) {
1832 MacroAssembler masm(&cbuf);
1833 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1834 }
1835 %}
1837 enc_class preserve_SP %{
1838 debug_only(int off0 = cbuf.code_size());
1839 MacroAssembler _masm(&cbuf);
1840 // RBP is preserved across all calls, even compiled calls.
1841 // Use it to preserve RSP in places where the callee might change the SP.
1842 __ movptr(rbp, rsp);
1843 debug_only(int off1 = cbuf.code_size());
1844 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
1845 %}
1847 enc_class restore_SP %{
1848 MacroAssembler _masm(&cbuf);
1849 __ movptr(rsp, rbp);
1850 %}
1852 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1853 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1854 // who we intended to call.
1855 cbuf.set_inst_mark();
1856 $$$emit8$primary;
1857 if ( !_method ) {
1858 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1859 runtime_call_Relocation::spec(), RELOC_IMM32 );
1860 } else if(_optimized_virtual) {
1861 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1862 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1863 } else {
1864 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1865 static_call_Relocation::spec(), RELOC_IMM32 );
1866 }
1867 if( _method ) { // Emit stub for static call
1868 emit_java_to_interp(cbuf);
1869 }
1870 %}
1872 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1873 // !!!!!
1874 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1875 // emit_call_dynamic_prologue( cbuf );
1876 cbuf.set_inst_mark();
1877 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1878 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1879 address virtual_call_oop_addr = cbuf.inst_mark();
1880 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1881 // who we intended to call.
1882 cbuf.set_inst_mark();
1883 $$$emit8$primary;
1884 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1885 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1886 %}
1888 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1889 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1890 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1892 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1893 cbuf.set_inst_mark();
1894 $$$emit8$primary;
1895 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1896 emit_d8(cbuf, disp); // Displacement
1898 %}
1900 enc_class Xor_Reg (eRegI dst) %{
1901 emit_opcode(cbuf, 0x33);
1902 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
1903 %}
1905 // Following encoding is no longer used, but may be restored if calling
1906 // convention changes significantly.
1907 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1908 //
1909 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1910 // // int ic_reg = Matcher::inline_cache_reg();
1911 // // int ic_encode = Matcher::_regEncode[ic_reg];
1912 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1913 // // int imo_encode = Matcher::_regEncode[imo_reg];
1914 //
1915 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1916 // // // so we load it immediately before the call
1917 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1918 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1919 //
1920 // // xor rbp,ebp
1921 // emit_opcode(cbuf, 0x33);
1922 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1923 //
1924 // // CALL to interpreter.
1925 // cbuf.set_inst_mark();
1926 // $$$emit8$primary;
1927 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4),
1928 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1929 // %}
1931 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1932 $$$emit8$primary;
1933 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1934 $$$emit8$shift$$constant;
1935 %}
1937 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1938 // Load immediate does not have a zero or sign extended version
1939 // for 8-bit immediates
1940 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1941 $$$emit32$src$$constant;
1942 %}
1944 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1945 // Load immediate does not have a zero or sign extended version
1946 // for 8-bit immediates
1947 emit_opcode(cbuf, $primary + $dst$$reg);
1948 $$$emit32$src$$constant;
1949 %}
1951 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1952 // Load immediate does not have a zero or sign extended version
1953 // for 8-bit immediates
1954 int dst_enc = $dst$$reg;
1955 int src_con = $src$$constant & 0x0FFFFFFFFL;
1956 if (src_con == 0) {
1957 // xor dst, dst
1958 emit_opcode(cbuf, 0x33);
1959 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1960 } else {
1961 emit_opcode(cbuf, $primary + dst_enc);
1962 emit_d32(cbuf, src_con);
1963 }
1964 %}
1966 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1967 // Load immediate does not have a zero or sign extended version
1968 // for 8-bit immediates
1969 int dst_enc = $dst$$reg + 2;
1970 int src_con = ((julong)($src$$constant)) >> 32;
1971 if (src_con == 0) {
1972 // xor dst, dst
1973 emit_opcode(cbuf, 0x33);
1974 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1975 } else {
1976 emit_opcode(cbuf, $primary + dst_enc);
1977 emit_d32(cbuf, src_con);
1978 }
1979 %}
1982 enc_class LdImmD (immD src) %{ // Load Immediate
1983 if( is_positive_zero_double($src$$constant)) {
1984 // FLDZ
1985 emit_opcode(cbuf,0xD9);
1986 emit_opcode(cbuf,0xEE);
1987 } else if( is_positive_one_double($src$$constant)) {
1988 // FLD1
1989 emit_opcode(cbuf,0xD9);
1990 emit_opcode(cbuf,0xE8);
1991 } else {
1992 emit_opcode(cbuf,0xDD);
1993 emit_rm(cbuf, 0x0, 0x0, 0x5);
1994 emit_double_constant(cbuf, $src$$constant);
1995 }
1996 %}
1999 enc_class LdImmF (immF src) %{ // Load Immediate
2000 if( is_positive_zero_float($src$$constant)) {
2001 emit_opcode(cbuf,0xD9);
2002 emit_opcode(cbuf,0xEE);
2003 } else if( is_positive_one_float($src$$constant)) {
2004 emit_opcode(cbuf,0xD9);
2005 emit_opcode(cbuf,0xE8);
2006 } else {
2007 $$$emit8$primary;
2008 // Load immediate does not have a zero or sign extended version
2009 // for 8-bit immediates
2010 // First load to TOS, then move to dst
2011 emit_rm(cbuf, 0x0, 0x0, 0x5);
2012 emit_float_constant(cbuf, $src$$constant);
2013 }
2014 %}
2016 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate
2017 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
2018 emit_float_constant(cbuf, $con$$constant);
2019 %}
2021 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate
2022 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
2023 emit_double_constant(cbuf, $con$$constant);
2024 %}
2026 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant
2027 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
2028 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2029 emit_opcode(cbuf, 0x0F);
2030 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2031 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
2032 emit_double_constant(cbuf, $con$$constant);
2033 %}
2035 enc_class Opc_MemImm_F(immF src) %{
2036 cbuf.set_inst_mark();
2037 $$$emit8$primary;
2038 emit_rm(cbuf, 0x0, $secondary, 0x5);
2039 emit_float_constant(cbuf, $src$$constant);
2040 %}
2043 enc_class MovI2X_reg(regX dst, eRegI src) %{
2044 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
2045 emit_opcode(cbuf, 0x0F );
2046 emit_opcode(cbuf, 0x6E );
2047 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2048 %}
2050 enc_class MovX2I_reg(eRegI dst, regX src) %{
2051 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
2052 emit_opcode(cbuf, 0x0F );
2053 emit_opcode(cbuf, 0x7E );
2054 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2055 %}
2057 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{
2058 { // MOVD $dst,$src.lo
2059 emit_opcode(cbuf,0x66);
2060 emit_opcode(cbuf,0x0F);
2061 emit_opcode(cbuf,0x6E);
2062 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2063 }
2064 { // MOVD $tmp,$src.hi
2065 emit_opcode(cbuf,0x66);
2066 emit_opcode(cbuf,0x0F);
2067 emit_opcode(cbuf,0x6E);
2068 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2069 }
2070 { // PUNPCKLDQ $dst,$tmp
2071 emit_opcode(cbuf,0x66);
2072 emit_opcode(cbuf,0x0F);
2073 emit_opcode(cbuf,0x62);
2074 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg);
2075 }
2076 %}
2078 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{
2079 { // MOVD $dst.lo,$src
2080 emit_opcode(cbuf,0x66);
2081 emit_opcode(cbuf,0x0F);
2082 emit_opcode(cbuf,0x7E);
2083 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2084 }
2085 { // PSHUFLW $tmp,$src,0x4E (01001110b)
2086 emit_opcode(cbuf,0xF2);
2087 emit_opcode(cbuf,0x0F);
2088 emit_opcode(cbuf,0x70);
2089 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2090 emit_d8(cbuf, 0x4E);
2091 }
2092 { // MOVD $dst.hi,$tmp
2093 emit_opcode(cbuf,0x66);
2094 emit_opcode(cbuf,0x0F);
2095 emit_opcode(cbuf,0x7E);
2096 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
2097 }
2098 %}
2101 // Encode a reg-reg copy. If it is useless, then empty encoding.
2102 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2103 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2104 %}
2106 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2107 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2108 %}
2110 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2111 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{
2112 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2113 %}
2115 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2116 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2117 %}
2119 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2120 $$$emit8$primary;
2121 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2122 %}
2124 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2125 $$$emit8$secondary;
2126 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2127 %}
2129 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2130 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2131 %}
2133 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2134 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2135 %}
2137 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2138 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2139 %}
2141 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2142 // Output immediate
2143 $$$emit32$src$$constant;
2144 %}
2146 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2147 // Output Float immediate bits
2148 jfloat jf = $src$$constant;
2149 int jf_as_bits = jint_cast( jf );
2150 emit_d32(cbuf, jf_as_bits);
2151 %}
2153 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2154 // Output Float immediate bits
2155 jfloat jf = $src$$constant;
2156 int jf_as_bits = jint_cast( jf );
2157 emit_d32(cbuf, jf_as_bits);
2158 %}
2160 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2161 // Output immediate
2162 $$$emit16$src$$constant;
2163 %}
2165 enc_class Con_d32(immI src) %{
2166 emit_d32(cbuf,$src$$constant);
2167 %}
2169 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2170 // Output immediate memory reference
2171 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2172 emit_d32(cbuf, 0x00);
2173 %}
2175 enc_class lock_prefix( ) %{
2176 if( os::is_MP() )
2177 emit_opcode(cbuf,0xF0); // [Lock]
2178 %}
2180 // Cmp-xchg long value.
2181 // Note: we need to swap rbx, and rcx before and after the
2182 // cmpxchg8 instruction because the instruction uses
2183 // rcx as the high order word of the new value to store but
2184 // our register encoding uses rbx,.
2185 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2187 // XCHG rbx,ecx
2188 emit_opcode(cbuf,0x87);
2189 emit_opcode(cbuf,0xD9);
2190 // [Lock]
2191 if( os::is_MP() )
2192 emit_opcode(cbuf,0xF0);
2193 // CMPXCHG8 [Eptr]
2194 emit_opcode(cbuf,0x0F);
2195 emit_opcode(cbuf,0xC7);
2196 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2197 // XCHG rbx,ecx
2198 emit_opcode(cbuf,0x87);
2199 emit_opcode(cbuf,0xD9);
2200 %}
2202 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2203 // [Lock]
2204 if( os::is_MP() )
2205 emit_opcode(cbuf,0xF0);
2207 // CMPXCHG [Eptr]
2208 emit_opcode(cbuf,0x0F);
2209 emit_opcode(cbuf,0xB1);
2210 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2211 %}
2213 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2214 int res_encoding = $res$$reg;
2216 // MOV res,0
2217 emit_opcode( cbuf, 0xB8 + res_encoding);
2218 emit_d32( cbuf, 0 );
2219 // JNE,s fail
2220 emit_opcode(cbuf,0x75);
2221 emit_d8(cbuf, 5 );
2222 // MOV res,1
2223 emit_opcode( cbuf, 0xB8 + res_encoding);
2224 emit_d32( cbuf, 1 );
2225 // fail:
2226 %}
2228 enc_class set_instruction_start( ) %{
2229 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2230 %}
2232 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2233 int reg_encoding = $ereg$$reg;
2234 int base = $mem$$base;
2235 int index = $mem$$index;
2236 int scale = $mem$$scale;
2237 int displace = $mem$$disp;
2238 bool disp_is_oop = $mem->disp_is_oop();
2239 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2240 %}
2242 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2243 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2244 int base = $mem$$base;
2245 int index = $mem$$index;
2246 int scale = $mem$$scale;
2247 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2248 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2249 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2250 %}
2252 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2253 int r1, r2;
2254 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2255 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2256 emit_opcode(cbuf,0x0F);
2257 emit_opcode(cbuf,$tertiary);
2258 emit_rm(cbuf, 0x3, r1, r2);
2259 emit_d8(cbuf,$cnt$$constant);
2260 emit_d8(cbuf,$primary);
2261 emit_rm(cbuf, 0x3, $secondary, r1);
2262 emit_d8(cbuf,$cnt$$constant);
2263 %}
2265 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2266 emit_opcode( cbuf, 0x8B ); // Move
2267 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2268 emit_d8(cbuf,$primary);
2269 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2270 emit_d8(cbuf,$cnt$$constant-32);
2271 emit_d8(cbuf,$primary);
2272 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2273 emit_d8(cbuf,31);
2274 %}
2276 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2277 int r1, r2;
2278 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2279 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2281 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2282 emit_rm(cbuf, 0x3, r1, r2);
2283 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2284 emit_opcode(cbuf,$primary);
2285 emit_rm(cbuf, 0x3, $secondary, r1);
2286 emit_d8(cbuf,$cnt$$constant-32);
2287 }
2288 emit_opcode(cbuf,0x33); // XOR r2,r2
2289 emit_rm(cbuf, 0x3, r2, r2);
2290 %}
2292 // Clone of RegMem but accepts an extra parameter to access each
2293 // half of a double in memory; it never needs relocation info.
2294 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2295 emit_opcode(cbuf,$opcode$$constant);
2296 int reg_encoding = $rm_reg$$reg;
2297 int base = $mem$$base;
2298 int index = $mem$$index;
2299 int scale = $mem$$scale;
2300 int displace = $mem$$disp + $disp_for_half$$constant;
2301 bool disp_is_oop = false;
2302 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2303 %}
2305 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2306 //
2307 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2308 // and it never needs relocation information.
2309 // Frequently used to move data between FPU's Stack Top and memory.
2310 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2311 int rm_byte_opcode = $rm_opcode$$constant;
2312 int base = $mem$$base;
2313 int index = $mem$$index;
2314 int scale = $mem$$scale;
2315 int displace = $mem$$disp;
2316 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2317 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2318 %}
2320 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2321 int rm_byte_opcode = $rm_opcode$$constant;
2322 int base = $mem$$base;
2323 int index = $mem$$index;
2324 int scale = $mem$$scale;
2325 int displace = $mem$$disp;
2326 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2327 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2328 %}
2330 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2331 int reg_encoding = $dst$$reg;
2332 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2333 int index = 0x04; // 0x04 indicates no index
2334 int scale = 0x00; // 0x00 indicates no scale
2335 int displace = $src1$$constant; // 0x00 indicates no displacement
2336 bool disp_is_oop = false;
2337 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2338 %}
2340 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2341 // Compare dst,src
2342 emit_opcode(cbuf,0x3B);
2343 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2344 // jmp dst < src around move
2345 emit_opcode(cbuf,0x7C);
2346 emit_d8(cbuf,2);
2347 // move dst,src
2348 emit_opcode(cbuf,0x8B);
2349 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2350 %}
2352 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2353 // Compare dst,src
2354 emit_opcode(cbuf,0x3B);
2355 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2356 // jmp dst > src around move
2357 emit_opcode(cbuf,0x7F);
2358 emit_d8(cbuf,2);
2359 // move dst,src
2360 emit_opcode(cbuf,0x8B);
2361 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2362 %}
2364 enc_class enc_FP_store(memory mem, regD src) %{
2365 // If src is FPR1, we can just FST to store it.
2366 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2367 int reg_encoding = 0x2; // Just store
2368 int base = $mem$$base;
2369 int index = $mem$$index;
2370 int scale = $mem$$scale;
2371 int displace = $mem$$disp;
2372 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2373 if( $src$$reg != FPR1L_enc ) {
2374 reg_encoding = 0x3; // Store & pop
2375 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2376 emit_d8( cbuf, 0xC0-1+$src$$reg );
2377 }
2378 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2379 emit_opcode(cbuf,$primary);
2380 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2381 %}
2383 enc_class neg_reg(eRegI dst) %{
2384 // NEG $dst
2385 emit_opcode(cbuf,0xF7);
2386 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2387 %}
2389 enc_class setLT_reg(eCXRegI dst) %{
2390 // SETLT $dst
2391 emit_opcode(cbuf,0x0F);
2392 emit_opcode(cbuf,0x9C);
2393 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2394 %}
2396 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2397 int tmpReg = $tmp$$reg;
2399 // SUB $p,$q
2400 emit_opcode(cbuf,0x2B);
2401 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2402 // SBB $tmp,$tmp
2403 emit_opcode(cbuf,0x1B);
2404 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2405 // AND $tmp,$y
2406 emit_opcode(cbuf,0x23);
2407 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2408 // ADD $p,$tmp
2409 emit_opcode(cbuf,0x03);
2410 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2411 %}
2413 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2414 int tmpReg = $tmp$$reg;
2416 // SUB $p,$q
2417 emit_opcode(cbuf,0x2B);
2418 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2419 // SBB $tmp,$tmp
2420 emit_opcode(cbuf,0x1B);
2421 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2422 // AND $tmp,$y
2423 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2424 emit_opcode(cbuf,0x23);
2425 int reg_encoding = tmpReg;
2426 int base = $mem$$base;
2427 int index = $mem$$index;
2428 int scale = $mem$$scale;
2429 int displace = $mem$$disp;
2430 bool disp_is_oop = $mem->disp_is_oop();
2431 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2432 // ADD $p,$tmp
2433 emit_opcode(cbuf,0x03);
2434 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2435 %}
2437 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2438 // TEST shift,32
2439 emit_opcode(cbuf,0xF7);
2440 emit_rm(cbuf, 0x3, 0, ECX_enc);
2441 emit_d32(cbuf,0x20);
2442 // JEQ,s small
2443 emit_opcode(cbuf, 0x74);
2444 emit_d8(cbuf, 0x04);
2445 // MOV $dst.hi,$dst.lo
2446 emit_opcode( cbuf, 0x8B );
2447 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2448 // CLR $dst.lo
2449 emit_opcode(cbuf, 0x33);
2450 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2451 // small:
2452 // SHLD $dst.hi,$dst.lo,$shift
2453 emit_opcode(cbuf,0x0F);
2454 emit_opcode(cbuf,0xA5);
2455 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2456 // SHL $dst.lo,$shift"
2457 emit_opcode(cbuf,0xD3);
2458 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2459 %}
2461 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2462 // TEST shift,32
2463 emit_opcode(cbuf,0xF7);
2464 emit_rm(cbuf, 0x3, 0, ECX_enc);
2465 emit_d32(cbuf,0x20);
2466 // JEQ,s small
2467 emit_opcode(cbuf, 0x74);
2468 emit_d8(cbuf, 0x04);
2469 // MOV $dst.lo,$dst.hi
2470 emit_opcode( cbuf, 0x8B );
2471 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2472 // CLR $dst.hi
2473 emit_opcode(cbuf, 0x33);
2474 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2475 // small:
2476 // SHRD $dst.lo,$dst.hi,$shift
2477 emit_opcode(cbuf,0x0F);
2478 emit_opcode(cbuf,0xAD);
2479 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2480 // SHR $dst.hi,$shift"
2481 emit_opcode(cbuf,0xD3);
2482 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2483 %}
2485 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2486 // TEST shift,32
2487 emit_opcode(cbuf,0xF7);
2488 emit_rm(cbuf, 0x3, 0, ECX_enc);
2489 emit_d32(cbuf,0x20);
2490 // JEQ,s small
2491 emit_opcode(cbuf, 0x74);
2492 emit_d8(cbuf, 0x05);
2493 // MOV $dst.lo,$dst.hi
2494 emit_opcode( cbuf, 0x8B );
2495 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2496 // SAR $dst.hi,31
2497 emit_opcode(cbuf, 0xC1);
2498 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2499 emit_d8(cbuf, 0x1F );
2500 // small:
2501 // SHRD $dst.lo,$dst.hi,$shift
2502 emit_opcode(cbuf,0x0F);
2503 emit_opcode(cbuf,0xAD);
2504 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2505 // SAR $dst.hi,$shift"
2506 emit_opcode(cbuf,0xD3);
2507 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2508 %}
2511 // ----------------- Encodings for floating point unit -----------------
2512 // May leave result in FPU-TOS or FPU reg depending on opcodes
2513 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2514 $$$emit8$primary;
2515 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2516 %}
2518 // Pop argument in FPR0 with FSTP ST(0)
2519 enc_class PopFPU() %{
2520 emit_opcode( cbuf, 0xDD );
2521 emit_d8( cbuf, 0xD8 );
2522 %}
2524 // !!!!! equivalent to Pop_Reg_F
2525 enc_class Pop_Reg_D( regD dst ) %{
2526 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2527 emit_d8( cbuf, 0xD8+$dst$$reg );
2528 %}
2530 enc_class Push_Reg_D( regD dst ) %{
2531 emit_opcode( cbuf, 0xD9 );
2532 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2533 %}
2535 enc_class strictfp_bias1( regD dst ) %{
2536 emit_opcode( cbuf, 0xDB ); // FLD m80real
2537 emit_opcode( cbuf, 0x2D );
2538 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2539 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2540 emit_opcode( cbuf, 0xC8+$dst$$reg );
2541 %}
2543 enc_class strictfp_bias2( regD dst ) %{
2544 emit_opcode( cbuf, 0xDB ); // FLD m80real
2545 emit_opcode( cbuf, 0x2D );
2546 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2547 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2548 emit_opcode( cbuf, 0xC8+$dst$$reg );
2549 %}
2551 // Special case for moving an integer register to a stack slot.
2552 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2553 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2554 %}
2556 // Special case for moving a register to a stack slot.
2557 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2558 // Opcode already emitted
2559 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2560 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2561 emit_d32(cbuf, $dst$$disp); // Displacement
2562 %}
2564 // Push the integer in stackSlot 'src' onto FP-stack
2565 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2566 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2567 %}
2569 // Push the float in stackSlot 'src' onto FP-stack
2570 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2571 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2572 %}
2574 // Push the double in stackSlot 'src' onto FP-stack
2575 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2576 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2577 %}
2579 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2580 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2581 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2582 %}
2584 // Same as Pop_Mem_F except for opcode
2585 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2586 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2587 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2588 %}
2590 enc_class Pop_Reg_F( regF dst ) %{
2591 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2592 emit_d8( cbuf, 0xD8+$dst$$reg );
2593 %}
2595 enc_class Push_Reg_F( regF dst ) %{
2596 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2597 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2598 %}
2600 // Push FPU's float to a stack-slot, and pop FPU-stack
2601 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2602 int pop = 0x02;
2603 if ($src$$reg != FPR1L_enc) {
2604 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2605 emit_d8( cbuf, 0xC0-1+$src$$reg );
2606 pop = 0x03;
2607 }
2608 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2609 %}
2611 // Push FPU's double to a stack-slot, and pop FPU-stack
2612 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2613 int pop = 0x02;
2614 if ($src$$reg != FPR1L_enc) {
2615 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2616 emit_d8( cbuf, 0xC0-1+$src$$reg );
2617 pop = 0x03;
2618 }
2619 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2620 %}
2622 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2623 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2624 int pop = 0xD0 - 1; // -1 since we skip FLD
2625 if ($src$$reg != FPR1L_enc) {
2626 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2627 emit_d8( cbuf, 0xC0-1+$src$$reg );
2628 pop = 0xD8;
2629 }
2630 emit_opcode( cbuf, 0xDD );
2631 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2632 %}
2635 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2636 MacroAssembler masm(&cbuf);
2637 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2638 masm.fmul( $src2$$reg+0); // value at TOS
2639 masm.fadd( $src$$reg+0); // value at TOS
2640 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2641 %}
2644 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2645 // load dst in FPR0
2646 emit_opcode( cbuf, 0xD9 );
2647 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2648 if ($src$$reg != FPR1L_enc) {
2649 // fincstp
2650 emit_opcode (cbuf, 0xD9);
2651 emit_opcode (cbuf, 0xF7);
2652 // swap src with FPR1:
2653 // FXCH FPR1 with src
2654 emit_opcode(cbuf, 0xD9);
2655 emit_d8(cbuf, 0xC8-1+$src$$reg );
2656 // fdecstp
2657 emit_opcode (cbuf, 0xD9);
2658 emit_opcode (cbuf, 0xF6);
2659 }
2660 %}
2662 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{
2663 // Allocate a word
2664 emit_opcode(cbuf,0x83); // SUB ESP,8
2665 emit_opcode(cbuf,0xEC);
2666 emit_d8(cbuf,0x08);
2668 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1
2669 emit_opcode (cbuf, 0x0F );
2670 emit_opcode (cbuf, 0x11 );
2671 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2673 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2674 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2676 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0
2677 emit_opcode (cbuf, 0x0F );
2678 emit_opcode (cbuf, 0x11 );
2679 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2681 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2682 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2684 %}
2686 enc_class Push_ModX_encoding( regX src0, regX src1) %{
2687 // Allocate a word
2688 emit_opcode(cbuf,0x83); // SUB ESP,4
2689 emit_opcode(cbuf,0xEC);
2690 emit_d8(cbuf,0x04);
2692 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1
2693 emit_opcode (cbuf, 0x0F );
2694 emit_opcode (cbuf, 0x11 );
2695 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2697 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2698 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2700 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0
2701 emit_opcode (cbuf, 0x0F );
2702 emit_opcode (cbuf, 0x11 );
2703 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2705 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2706 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2708 %}
2710 enc_class Push_ResultXD(regXD dst) %{
2711 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP]
2713 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp]
2714 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2715 emit_opcode (cbuf, 0x0F );
2716 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2717 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2719 emit_opcode(cbuf,0x83); // ADD ESP,8
2720 emit_opcode(cbuf,0xC4);
2721 emit_d8(cbuf,0x08);
2722 %}
2724 enc_class Push_ResultX(regX dst, immI d8) %{
2725 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP]
2727 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
2728 emit_opcode (cbuf, 0x0F );
2729 emit_opcode (cbuf, 0x10 );
2730 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2732 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8)
2733 emit_opcode(cbuf,0xC4);
2734 emit_d8(cbuf,$d8$$constant);
2735 %}
2737 enc_class Push_SrcXD(regXD src) %{
2738 // Allocate a word
2739 emit_opcode(cbuf,0x83); // SUB ESP,8
2740 emit_opcode(cbuf,0xEC);
2741 emit_d8(cbuf,0x08);
2743 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
2744 emit_opcode (cbuf, 0x0F );
2745 emit_opcode (cbuf, 0x11 );
2746 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
2748 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2749 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2750 %}
2752 enc_class push_stack_temp_qword() %{
2753 emit_opcode(cbuf,0x83); // SUB ESP,8
2754 emit_opcode(cbuf,0xEC);
2755 emit_d8 (cbuf,0x08);
2756 %}
2758 enc_class pop_stack_temp_qword() %{
2759 emit_opcode(cbuf,0x83); // ADD ESP,8
2760 emit_opcode(cbuf,0xC4);
2761 emit_d8 (cbuf,0x08);
2762 %}
2764 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{
2765 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src
2766 emit_opcode (cbuf, 0x0F );
2767 emit_opcode (cbuf, 0x11 );
2768 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false);
2770 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2771 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2772 %}
2774 // Compute X^Y using Intel's fast hardware instructions, if possible.
2775 // Otherwise return a NaN.
2776 enc_class pow_exp_core_encoding %{
2777 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2778 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2779 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2780 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2781 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2782 emit_opcode(cbuf,0x1C);
2783 emit_d8(cbuf,0x24);
2784 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2785 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2786 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2787 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2788 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2789 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2790 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2791 emit_d32(cbuf,0xFFFFF800);
2792 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2793 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2794 emit_d32(cbuf,1023);
2795 emit_opcode(cbuf,0x8B); // mov rbx,eax
2796 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2797 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2798 emit_rm(cbuf,0x3,0x4,EAX_enc);
2799 emit_d8(cbuf,20);
2800 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2801 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2802 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2803 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2804 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2805 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2806 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2807 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2808 emit_d32(cbuf,0);
2809 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2810 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2811 %}
2813 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2814 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2816 enc_class Push_Result_Mod_D( regD src) %{
2817 if ($src$$reg != FPR1L_enc) {
2818 // fincstp
2819 emit_opcode (cbuf, 0xD9);
2820 emit_opcode (cbuf, 0xF7);
2821 // FXCH FPR1 with src
2822 emit_opcode(cbuf, 0xD9);
2823 emit_d8(cbuf, 0xC8-1+$src$$reg );
2824 // fdecstp
2825 emit_opcode (cbuf, 0xD9);
2826 emit_opcode (cbuf, 0xF6);
2827 }
2828 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2829 // // FSTP FPR$dst$$reg
2830 // emit_opcode( cbuf, 0xDD );
2831 // emit_d8( cbuf, 0xD8+$dst$$reg );
2832 %}
2834 enc_class fnstsw_sahf_skip_parity() %{
2835 // fnstsw ax
2836 emit_opcode( cbuf, 0xDF );
2837 emit_opcode( cbuf, 0xE0 );
2838 // sahf
2839 emit_opcode( cbuf, 0x9E );
2840 // jnp ::skip
2841 emit_opcode( cbuf, 0x7B );
2842 emit_opcode( cbuf, 0x05 );
2843 %}
2845 enc_class emitModD() %{
2846 // fprem must be iterative
2847 // :: loop
2848 // fprem
2849 emit_opcode( cbuf, 0xD9 );
2850 emit_opcode( cbuf, 0xF8 );
2851 // wait
2852 emit_opcode( cbuf, 0x9b );
2853 // fnstsw ax
2854 emit_opcode( cbuf, 0xDF );
2855 emit_opcode( cbuf, 0xE0 );
2856 // sahf
2857 emit_opcode( cbuf, 0x9E );
2858 // jp ::loop
2859 emit_opcode( cbuf, 0x0F );
2860 emit_opcode( cbuf, 0x8A );
2861 emit_opcode( cbuf, 0xF4 );
2862 emit_opcode( cbuf, 0xFF );
2863 emit_opcode( cbuf, 0xFF );
2864 emit_opcode( cbuf, 0xFF );
2865 %}
2867 enc_class fpu_flags() %{
2868 // fnstsw_ax
2869 emit_opcode( cbuf, 0xDF);
2870 emit_opcode( cbuf, 0xE0);
2871 // test ax,0x0400
2872 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2873 emit_opcode( cbuf, 0xA9 );
2874 emit_d16 ( cbuf, 0x0400 );
2875 // // // This sequence works, but stalls for 12-16 cycles on PPro
2876 // // test rax,0x0400
2877 // emit_opcode( cbuf, 0xA9 );
2878 // emit_d32 ( cbuf, 0x00000400 );
2879 //
2880 // jz exit (no unordered comparison)
2881 emit_opcode( cbuf, 0x74 );
2882 emit_d8 ( cbuf, 0x02 );
2883 // mov ah,1 - treat as LT case (set carry flag)
2884 emit_opcode( cbuf, 0xB4 );
2885 emit_d8 ( cbuf, 0x01 );
2886 // sahf
2887 emit_opcode( cbuf, 0x9E);
2888 %}
2890 enc_class cmpF_P6_fixup() %{
2891 // Fixup the integer flags in case comparison involved a NaN
2892 //
2893 // JNP exit (no unordered comparison, P-flag is set by NaN)
2894 emit_opcode( cbuf, 0x7B );
2895 emit_d8 ( cbuf, 0x03 );
2896 // MOV AH,1 - treat as LT case (set carry flag)
2897 emit_opcode( cbuf, 0xB4 );
2898 emit_d8 ( cbuf, 0x01 );
2899 // SAHF
2900 emit_opcode( cbuf, 0x9E);
2901 // NOP // target for branch to avoid branch to branch
2902 emit_opcode( cbuf, 0x90);
2903 %}
2905 // fnstsw_ax();
2906 // sahf();
2907 // movl(dst, nan_result);
2908 // jcc(Assembler::parity, exit);
2909 // movl(dst, less_result);
2910 // jcc(Assembler::below, exit);
2911 // movl(dst, equal_result);
2912 // jcc(Assembler::equal, exit);
2913 // movl(dst, greater_result);
2915 // less_result = 1;
2916 // greater_result = -1;
2917 // equal_result = 0;
2918 // nan_result = -1;
2920 enc_class CmpF_Result(eRegI dst) %{
2921 // fnstsw_ax();
2922 emit_opcode( cbuf, 0xDF);
2923 emit_opcode( cbuf, 0xE0);
2924 // sahf
2925 emit_opcode( cbuf, 0x9E);
2926 // movl(dst, nan_result);
2927 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2928 emit_d32( cbuf, -1 );
2929 // jcc(Assembler::parity, exit);
2930 emit_opcode( cbuf, 0x7A );
2931 emit_d8 ( cbuf, 0x13 );
2932 // movl(dst, less_result);
2933 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2934 emit_d32( cbuf, -1 );
2935 // jcc(Assembler::below, exit);
2936 emit_opcode( cbuf, 0x72 );
2937 emit_d8 ( cbuf, 0x0C );
2938 // movl(dst, equal_result);
2939 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2940 emit_d32( cbuf, 0 );
2941 // jcc(Assembler::equal, exit);
2942 emit_opcode( cbuf, 0x74 );
2943 emit_d8 ( cbuf, 0x05 );
2944 // movl(dst, greater_result);
2945 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2946 emit_d32( cbuf, 1 );
2947 %}
2950 // XMM version of CmpF_Result. Because the XMM compare
2951 // instructions set the EFLAGS directly. It becomes simpler than
2952 // the float version above.
2953 enc_class CmpX_Result(eRegI dst) %{
2954 MacroAssembler _masm(&cbuf);
2955 Label nan, inc, done;
2957 __ jccb(Assembler::parity, nan);
2958 __ jccb(Assembler::equal, done);
2959 __ jccb(Assembler::above, inc);
2960 __ bind(nan);
2961 __ decrement(as_Register($dst$$reg)); // NO L qqq
2962 __ jmpb(done);
2963 __ bind(inc);
2964 __ increment(as_Register($dst$$reg)); // NO L qqq
2965 __ bind(done);
2966 %}
2968 // Compare the longs and set flags
2969 // BROKEN! Do Not use as-is
2970 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2971 // CMP $src1.hi,$src2.hi
2972 emit_opcode( cbuf, 0x3B );
2973 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2974 // JNE,s done
2975 emit_opcode(cbuf,0x75);
2976 emit_d8(cbuf, 2 );
2977 // CMP $src1.lo,$src2.lo
2978 emit_opcode( cbuf, 0x3B );
2979 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2980 // done:
2981 %}
2983 enc_class convert_int_long( regL dst, eRegI src ) %{
2984 // mov $dst.lo,$src
2985 int dst_encoding = $dst$$reg;
2986 int src_encoding = $src$$reg;
2987 encode_Copy( cbuf, dst_encoding , src_encoding );
2988 // mov $dst.hi,$src
2989 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2990 // sar $dst.hi,31
2991 emit_opcode( cbuf, 0xC1 );
2992 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2993 emit_d8(cbuf, 0x1F );
2994 %}
2996 enc_class convert_long_double( eRegL src ) %{
2997 // push $src.hi
2998 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2999 // push $src.lo
3000 emit_opcode(cbuf, 0x50+$src$$reg );
3001 // fild 64-bits at [SP]
3002 emit_opcode(cbuf,0xdf);
3003 emit_d8(cbuf, 0x6C);
3004 emit_d8(cbuf, 0x24);
3005 emit_d8(cbuf, 0x00);
3006 // pop stack
3007 emit_opcode(cbuf, 0x83); // add SP, #8
3008 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3009 emit_d8(cbuf, 0x8);
3010 %}
3012 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
3013 // IMUL EDX:EAX,$src1
3014 emit_opcode( cbuf, 0xF7 );
3015 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
3016 // SAR EDX,$cnt-32
3017 int shift_count = ((int)$cnt$$constant) - 32;
3018 if (shift_count > 0) {
3019 emit_opcode(cbuf, 0xC1);
3020 emit_rm(cbuf, 0x3, 7, $dst$$reg );
3021 emit_d8(cbuf, shift_count);
3022 }
3023 %}
3025 // this version doesn't have add sp, 8
3026 enc_class convert_long_double2( eRegL src ) %{
3027 // push $src.hi
3028 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
3029 // push $src.lo
3030 emit_opcode(cbuf, 0x50+$src$$reg );
3031 // fild 64-bits at [SP]
3032 emit_opcode(cbuf,0xdf);
3033 emit_d8(cbuf, 0x6C);
3034 emit_d8(cbuf, 0x24);
3035 emit_d8(cbuf, 0x00);
3036 %}
3038 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
3039 // Basic idea: long = (long)int * (long)int
3040 // IMUL EDX:EAX, src
3041 emit_opcode( cbuf, 0xF7 );
3042 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
3043 %}
3045 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
3046 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
3047 // MUL EDX:EAX, src
3048 emit_opcode( cbuf, 0xF7 );
3049 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
3050 %}
3052 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
3053 // Basic idea: lo(result) = lo(x_lo * y_lo)
3054 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
3055 // MOV $tmp,$src.lo
3056 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
3057 // IMUL $tmp,EDX
3058 emit_opcode( cbuf, 0x0F );
3059 emit_opcode( cbuf, 0xAF );
3060 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3061 // MOV EDX,$src.hi
3062 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
3063 // IMUL EDX,EAX
3064 emit_opcode( cbuf, 0x0F );
3065 emit_opcode( cbuf, 0xAF );
3066 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
3067 // ADD $tmp,EDX
3068 emit_opcode( cbuf, 0x03 );
3069 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3070 // MUL EDX:EAX,$src.lo
3071 emit_opcode( cbuf, 0xF7 );
3072 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
3073 // ADD EDX,ESI
3074 emit_opcode( cbuf, 0x03 );
3075 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
3076 %}
3078 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
3079 // Basic idea: lo(result) = lo(src * y_lo)
3080 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
3081 // IMUL $tmp,EDX,$src
3082 emit_opcode( cbuf, 0x6B );
3083 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3084 emit_d8( cbuf, (int)$src$$constant );
3085 // MOV EDX,$src
3086 emit_opcode(cbuf, 0xB8 + EDX_enc);
3087 emit_d32( cbuf, (int)$src$$constant );
3088 // MUL EDX:EAX,EDX
3089 emit_opcode( cbuf, 0xF7 );
3090 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
3091 // ADD EDX,ESI
3092 emit_opcode( cbuf, 0x03 );
3093 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
3094 %}
3096 enc_class long_div( eRegL src1, eRegL src2 ) %{
3097 // PUSH src1.hi
3098 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3099 // PUSH src1.lo
3100 emit_opcode(cbuf, 0x50+$src1$$reg );
3101 // PUSH src2.hi
3102 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3103 // PUSH src2.lo
3104 emit_opcode(cbuf, 0x50+$src2$$reg );
3105 // CALL directly to the runtime
3106 cbuf.set_inst_mark();
3107 emit_opcode(cbuf,0xE8); // Call into runtime
3108 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3109 // Restore stack
3110 emit_opcode(cbuf, 0x83); // add SP, #framesize
3111 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3112 emit_d8(cbuf, 4*4);
3113 %}
3115 enc_class long_mod( eRegL src1, eRegL src2 ) %{
3116 // PUSH src1.hi
3117 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3118 // PUSH src1.lo
3119 emit_opcode(cbuf, 0x50+$src1$$reg );
3120 // PUSH src2.hi
3121 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3122 // PUSH src2.lo
3123 emit_opcode(cbuf, 0x50+$src2$$reg );
3124 // CALL directly to the runtime
3125 cbuf.set_inst_mark();
3126 emit_opcode(cbuf,0xE8); // Call into runtime
3127 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3128 // Restore stack
3129 emit_opcode(cbuf, 0x83); // add SP, #framesize
3130 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3131 emit_d8(cbuf, 4*4);
3132 %}
3134 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
3135 // MOV $tmp,$src.lo
3136 emit_opcode(cbuf, 0x8B);
3137 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
3138 // OR $tmp,$src.hi
3139 emit_opcode(cbuf, 0x0B);
3140 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
3141 %}
3143 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
3144 // CMP $src1.lo,$src2.lo
3145 emit_opcode( cbuf, 0x3B );
3146 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3147 // JNE,s skip
3148 emit_cc(cbuf, 0x70, 0x5);
3149 emit_d8(cbuf,2);
3150 // CMP $src1.hi,$src2.hi
3151 emit_opcode( cbuf, 0x3B );
3152 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3153 %}
3155 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3156 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3157 emit_opcode( cbuf, 0x3B );
3158 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3159 // MOV $tmp,$src1.hi
3160 emit_opcode( cbuf, 0x8B );
3161 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3162 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3163 emit_opcode( cbuf, 0x1B );
3164 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3165 %}
3167 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3168 // XOR $tmp,$tmp
3169 emit_opcode(cbuf,0x33); // XOR
3170 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3171 // CMP $tmp,$src.lo
3172 emit_opcode( cbuf, 0x3B );
3173 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3174 // SBB $tmp,$src.hi
3175 emit_opcode( cbuf, 0x1B );
3176 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3177 %}
3179 // Sniff, sniff... smells like Gnu Superoptimizer
3180 enc_class neg_long( eRegL dst ) %{
3181 emit_opcode(cbuf,0xF7); // NEG hi
3182 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3183 emit_opcode(cbuf,0xF7); // NEG lo
3184 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3185 emit_opcode(cbuf,0x83); // SBB hi,0
3186 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3187 emit_d8 (cbuf,0 );
3188 %}
3190 enc_class movq_ld(regXD dst, memory mem) %{
3191 MacroAssembler _masm(&cbuf);
3192 __ movq($dst$$XMMRegister, $mem$$Address);
3193 %}
3195 enc_class movq_st(memory mem, regXD src) %{
3196 MacroAssembler _masm(&cbuf);
3197 __ movq($mem$$Address, $src$$XMMRegister);
3198 %}
3200 enc_class pshufd_8x8(regX dst, regX src) %{
3201 MacroAssembler _masm(&cbuf);
3203 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3204 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3205 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3206 %}
3208 enc_class pshufd_4x16(regX dst, regX src) %{
3209 MacroAssembler _masm(&cbuf);
3211 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3212 %}
3214 enc_class pshufd(regXD dst, regXD src, int mode) %{
3215 MacroAssembler _masm(&cbuf);
3217 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3218 %}
3220 enc_class pxor(regXD dst, regXD src) %{
3221 MacroAssembler _masm(&cbuf);
3223 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3224 %}
3226 enc_class mov_i2x(regXD dst, eRegI src) %{
3227 MacroAssembler _masm(&cbuf);
3229 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3230 %}
3233 // Because the transitions from emitted code to the runtime
3234 // monitorenter/exit helper stubs are so slow it's critical that
3235 // we inline both the stack-locking fast-path and the inflated fast path.
3236 //
3237 // See also: cmpFastLock and cmpFastUnlock.
3238 //
3239 // What follows is a specialized inline transliteration of the code
3240 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3241 // another option would be to emit TrySlowEnter and TrySlowExit methods
3242 // at startup-time. These methods would accept arguments as
3243 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3244 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3245 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3246 // In practice, however, the # of lock sites is bounded and is usually small.
3247 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3248 // if the processor uses simple bimodal branch predictors keyed by EIP
3249 // Since the helper routines would be called from multiple synchronization
3250 // sites.
3251 //
3252 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3253 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3254 // to those specialized methods. That'd give us a mostly platform-independent
3255 // implementation that the JITs could optimize and inline at their pleasure.
3256 // Done correctly, the only time we'd need to cross to native could would be
3257 // to park() or unpark() threads. We'd also need a few more unsafe operators
3258 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3259 // (b) explicit barriers or fence operations.
3260 //
3261 // TODO:
3262 //
3263 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3264 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3265 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3266 // the lock operators would typically be faster than reifying Self.
3267 //
3268 // * Ideally I'd define the primitives as:
3269 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3270 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3271 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3272 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3273 // Furthermore the register assignments are overconstrained, possibly resulting in
3274 // sub-optimal code near the synchronization site.
3275 //
3276 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3277 // Alternately, use a better sp-proximity test.
3278 //
3279 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3280 // Either one is sufficient to uniquely identify a thread.
3281 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3282 //
3283 // * Intrinsify notify() and notifyAll() for the common cases where the
3284 // object is locked by the calling thread but the waitlist is empty.
3285 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3286 //
3287 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3288 // But beware of excessive branch density on AMD Opterons.
3289 //
3290 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3291 // or failure of the fast-path. If the fast-path fails then we pass
3292 // control to the slow-path, typically in C. In Fast_Lock and
3293 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3294 // will emit a conditional branch immediately after the node.
3295 // So we have branches to branches and lots of ICC.ZF games.
3296 // Instead, it might be better to have C2 pass a "FailureLabel"
3297 // into Fast_Lock and Fast_Unlock. In the case of success, control
3298 // will drop through the node. ICC.ZF is undefined at exit.
3299 // In the case of failure, the node will branch directly to the
3300 // FailureLabel
3303 // obj: object to lock
3304 // box: on-stack box address (displaced header location) - KILLED
3305 // rax,: tmp -- KILLED
3306 // scr: tmp -- KILLED
3307 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3309 Register objReg = as_Register($obj$$reg);
3310 Register boxReg = as_Register($box$$reg);
3311 Register tmpReg = as_Register($tmp$$reg);
3312 Register scrReg = as_Register($scr$$reg);
3314 // Ensure the register assignents are disjoint
3315 guarantee (objReg != boxReg, "") ;
3316 guarantee (objReg != tmpReg, "") ;
3317 guarantee (objReg != scrReg, "") ;
3318 guarantee (boxReg != tmpReg, "") ;
3319 guarantee (boxReg != scrReg, "") ;
3320 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3322 MacroAssembler masm(&cbuf);
3324 if (_counters != NULL) {
3325 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3326 }
3327 if (EmitSync & 1) {
3328 // set box->dhw = unused_mark (3)
3329 // Force all sync thru slow-path: slow_enter() and slow_exit()
3330 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3331 masm.cmpptr (rsp, (int32_t)0) ;
3332 } else
3333 if (EmitSync & 2) {
3334 Label DONE_LABEL ;
3335 if (UseBiasedLocking) {
3336 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3337 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3338 }
3340 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3341 masm.orptr (tmpReg, 0x1);
3342 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3343 if (os::is_MP()) { masm.lock(); }
3344 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3345 masm.jcc(Assembler::equal, DONE_LABEL);
3346 // Recursive locking
3347 masm.subptr(tmpReg, rsp);
3348 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3349 masm.movptr(Address(boxReg, 0), tmpReg);
3350 masm.bind(DONE_LABEL) ;
3351 } else {
3352 // Possible cases that we'll encounter in fast_lock
3353 // ------------------------------------------------
3354 // * Inflated
3355 // -- unlocked
3356 // -- Locked
3357 // = by self
3358 // = by other
3359 // * biased
3360 // -- by Self
3361 // -- by other
3362 // * neutral
3363 // * stack-locked
3364 // -- by self
3365 // = sp-proximity test hits
3366 // = sp-proximity test generates false-negative
3367 // -- by other
3368 //
3370 Label IsInflated, DONE_LABEL, PopDone ;
3372 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3373 // order to reduce the number of conditional branches in the most common cases.
3374 // Beware -- there's a subtle invariant that fetch of the markword
3375 // at [FETCH], below, will never observe a biased encoding (*101b).
3376 // If this invariant is not held we risk exclusion (safety) failure.
3377 if (UseBiasedLocking && !UseOptoBiasInlining) {
3378 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3379 }
3381 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3382 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3383 masm.jccb (Assembler::notZero, IsInflated) ;
3385 // Attempt stack-locking ...
3386 masm.orptr (tmpReg, 0x1);
3387 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3388 if (os::is_MP()) { masm.lock(); }
3389 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3390 if (_counters != NULL) {
3391 masm.cond_inc32(Assembler::equal,
3392 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3393 }
3394 masm.jccb (Assembler::equal, DONE_LABEL);
3396 // Recursive locking
3397 masm.subptr(tmpReg, rsp);
3398 masm.andptr(tmpReg, 0xFFFFF003 );
3399 masm.movptr(Address(boxReg, 0), tmpReg);
3400 if (_counters != NULL) {
3401 masm.cond_inc32(Assembler::equal,
3402 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3403 }
3404 masm.jmp (DONE_LABEL) ;
3406 masm.bind (IsInflated) ;
3408 // The object is inflated.
3409 //
3410 // TODO-FIXME: eliminate the ugly use of manifest constants:
3411 // Use markOopDesc::monitor_value instead of "2".
3412 // use markOop::unused_mark() instead of "3".
3413 // The tmpReg value is an objectMonitor reference ORed with
3414 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3415 // objectmonitor pointer by masking off the "2" bit or we can just
3416 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3417 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3418 //
3419 // I use the latter as it avoids AGI stalls.
3420 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3421 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3422 //
3423 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3425 // boxReg refers to the on-stack BasicLock in the current frame.
3426 // We'd like to write:
3427 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3428 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3429 // additional latency as we have another ST in the store buffer that must drain.
3431 if (EmitSync & 8192) {
3432 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3433 masm.get_thread (scrReg) ;
3434 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3435 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3436 if (os::is_MP()) { masm.lock(); }
3437 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3438 } else
3439 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3440 masm.movptr(scrReg, boxReg) ;
3441 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3443 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3444 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3445 // prefetchw [eax + Offset(_owner)-2]
3446 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3447 }
3449 if ((EmitSync & 64) == 0) {
3450 // Optimistic form: consider XORL tmpReg,tmpReg
3451 masm.movptr(tmpReg, NULL_WORD) ;
3452 } else {
3453 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3454 // Test-And-CAS instead of CAS
3455 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3456 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3457 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3458 }
3460 // Appears unlocked - try to swing _owner from null to non-null.
3461 // Ideally, I'd manifest "Self" with get_thread and then attempt
3462 // to CAS the register containing Self into m->Owner.
3463 // But we don't have enough registers, so instead we can either try to CAS
3464 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3465 // we later store "Self" into m->Owner. Transiently storing a stack address
3466 // (rsp or the address of the box) into m->owner is harmless.
3467 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3468 if (os::is_MP()) { masm.lock(); }
3469 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3470 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3471 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3472 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3473 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3474 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3476 // If the CAS fails we can either retry or pass control to the slow-path.
3477 // We use the latter tactic.
3478 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3479 // If the CAS was successful ...
3480 // Self has acquired the lock
3481 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3482 // Intentional fall-through into DONE_LABEL ...
3483 } else {
3484 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3485 masm.movptr(boxReg, tmpReg) ;
3487 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3488 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3489 // prefetchw [eax + Offset(_owner)-2]
3490 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3491 }
3493 if ((EmitSync & 64) == 0) {
3494 // Optimistic form
3495 masm.xorptr (tmpReg, tmpReg) ;
3496 } else {
3497 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3498 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3499 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3500 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3501 }
3503 // Appears unlocked - try to swing _owner from null to non-null.
3504 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3505 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3506 masm.get_thread (scrReg) ;
3507 if (os::is_MP()) { masm.lock(); }
3508 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3510 // If the CAS fails we can either retry or pass control to the slow-path.
3511 // We use the latter tactic.
3512 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3513 // If the CAS was successful ...
3514 // Self has acquired the lock
3515 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3516 // Intentional fall-through into DONE_LABEL ...
3517 }
3519 // DONE_LABEL is a hot target - we'd really like to place it at the
3520 // start of cache line by padding with NOPs.
3521 // See the AMD and Intel software optimization manuals for the
3522 // most efficient "long" NOP encodings.
3523 // Unfortunately none of our alignment mechanisms suffice.
3524 masm.bind(DONE_LABEL);
3526 // Avoid branch-to-branch on AMD processors
3527 // This appears to be superstition.
3528 if (EmitSync & 32) masm.nop() ;
3531 // At DONE_LABEL the icc ZFlag is set as follows ...
3532 // Fast_Unlock uses the same protocol.
3533 // ZFlag == 1 -> Success
3534 // ZFlag == 0 -> Failure - force control through the slow-path
3535 }
3536 %}
3538 // obj: object to unlock
3539 // box: box address (displaced header location), killed. Must be EAX.
3540 // rbx,: killed tmp; cannot be obj nor box.
3541 //
3542 // Some commentary on balanced locking:
3543 //
3544 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3545 // Methods that don't have provably balanced locking are forced to run in the
3546 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3547 // The interpreter provides two properties:
3548 // I1: At return-time the interpreter automatically and quietly unlocks any
3549 // objects acquired the current activation (frame). Recall that the
3550 // interpreter maintains an on-stack list of locks currently held by
3551 // a frame.
3552 // I2: If a method attempts to unlock an object that is not held by the
3553 // the frame the interpreter throws IMSX.
3554 //
3555 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3556 // B() doesn't have provably balanced locking so it runs in the interpreter.
3557 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3558 // is still locked by A().
3559 //
3560 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3561 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3562 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3563 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3565 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3567 Register objReg = as_Register($obj$$reg);
3568 Register boxReg = as_Register($box$$reg);
3569 Register tmpReg = as_Register($tmp$$reg);
3571 guarantee (objReg != boxReg, "") ;
3572 guarantee (objReg != tmpReg, "") ;
3573 guarantee (boxReg != tmpReg, "") ;
3574 guarantee (boxReg == as_Register(EAX_enc), "") ;
3575 MacroAssembler masm(&cbuf);
3577 if (EmitSync & 4) {
3578 // Disable - inhibit all inlining. Force control through the slow-path
3579 masm.cmpptr (rsp, 0) ;
3580 } else
3581 if (EmitSync & 8) {
3582 Label DONE_LABEL ;
3583 if (UseBiasedLocking) {
3584 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3585 }
3586 // classic stack-locking code ...
3587 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3588 masm.testptr(tmpReg, tmpReg) ;
3589 masm.jcc (Assembler::zero, DONE_LABEL) ;
3590 if (os::is_MP()) { masm.lock(); }
3591 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3592 masm.bind(DONE_LABEL);
3593 } else {
3594 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3596 // Critically, the biased locking test must have precedence over
3597 // and appear before the (box->dhw == 0) recursive stack-lock test.
3598 if (UseBiasedLocking && !UseOptoBiasInlining) {
3599 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3600 }
3602 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3603 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3604 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3606 masm.testptr(tmpReg, 0x02) ; // Inflated?
3607 masm.jccb (Assembler::zero, Stacked) ;
3609 masm.bind (Inflated) ;
3610 // It's inflated.
3611 // Despite our balanced locking property we still check that m->_owner == Self
3612 // as java routines or native JNI code called by this thread might
3613 // have released the lock.
3614 // Refer to the comments in synchronizer.cpp for how we might encode extra
3615 // state in _succ so we can avoid fetching EntryList|cxq.
3616 //
3617 // I'd like to add more cases in fast_lock() and fast_unlock() --
3618 // such as recursive enter and exit -- but we have to be wary of
3619 // I$ bloat, T$ effects and BP$ effects.
3620 //
3621 // If there's no contention try a 1-0 exit. That is, exit without
3622 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3623 // we detect and recover from the race that the 1-0 exit admits.
3624 //
3625 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3626 // before it STs null into _owner, releasing the lock. Updates
3627 // to data protected by the critical section must be visible before
3628 // we drop the lock (and thus before any other thread could acquire
3629 // the lock and observe the fields protected by the lock).
3630 // IA32's memory-model is SPO, so STs are ordered with respect to
3631 // each other and there's no need for an explicit barrier (fence).
3632 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3634 masm.get_thread (boxReg) ;
3635 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) {
3636 // prefetchw [ebx + Offset(_owner)-2]
3637 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3638 }
3640 // Note that we could employ various encoding schemes to reduce
3641 // the number of loads below (currently 4) to just 2 or 3.
3642 // Refer to the comments in synchronizer.cpp.
3643 // In practice the chain of fetches doesn't seem to impact performance, however.
3644 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3645 // Attempt to reduce branch density - AMD's branch predictor.
3646 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3647 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3648 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3649 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3650 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3651 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3652 masm.jmpb (DONE_LABEL) ;
3653 } else {
3654 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3655 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3656 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3657 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3658 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3659 masm.jccb (Assembler::notZero, CheckSucc) ;
3660 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3661 masm.jmpb (DONE_LABEL) ;
3662 }
3664 // The Following code fragment (EmitSync & 65536) improves the performance of
3665 // contended applications and contended synchronization microbenchmarks.
3666 // Unfortunately the emission of the code - even though not executed - causes regressions
3667 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3668 // with an equal number of never-executed NOPs results in the same regression.
3669 // We leave it off by default.
3671 if ((EmitSync & 65536) != 0) {
3672 Label LSuccess, LGoSlowPath ;
3674 masm.bind (CheckSucc) ;
3676 // Optional pre-test ... it's safe to elide this
3677 if ((EmitSync & 16) == 0) {
3678 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3679 masm.jccb (Assembler::zero, LGoSlowPath) ;
3680 }
3682 // We have a classic Dekker-style idiom:
3683 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3684 // There are a number of ways to implement the barrier:
3685 // (1) lock:andl &m->_owner, 0
3686 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3687 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3688 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3689 // (2) If supported, an explicit MFENCE is appealing.
3690 // In older IA32 processors MFENCE is slower than lock:add or xchg
3691 // particularly if the write-buffer is full as might be the case if
3692 // if stores closely precede the fence or fence-equivalent instruction.
3693 // In more modern implementations MFENCE appears faster, however.
3694 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3695 // The $lines underlying the top-of-stack should be in M-state.
3696 // The locked add instruction is serializing, of course.
3697 // (4) Use xchg, which is serializing
3698 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3699 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3700 // The integer condition codes will tell us if succ was 0.
3701 // Since _succ and _owner should reside in the same $line and
3702 // we just stored into _owner, it's likely that the $line
3703 // remains in M-state for the lock:orl.
3704 //
3705 // We currently use (3), although it's likely that switching to (2)
3706 // is correct for the future.
3708 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3709 if (os::is_MP()) {
3710 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3711 masm.mfence();
3712 } else {
3713 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3714 }
3715 }
3716 // Ratify _succ remains non-null
3717 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3718 masm.jccb (Assembler::notZero, LSuccess) ;
3720 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3721 if (os::is_MP()) { masm.lock(); }
3722 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3723 masm.jccb (Assembler::notEqual, LSuccess) ;
3724 // Since we're low on registers we installed rsp as a placeholding in _owner.
3725 // Now install Self over rsp. This is safe as we're transitioning from
3726 // non-null to non=null
3727 masm.get_thread (boxReg) ;
3728 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3729 // Intentional fall-through into LGoSlowPath ...
3731 masm.bind (LGoSlowPath) ;
3732 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3733 masm.jmpb (DONE_LABEL) ;
3735 masm.bind (LSuccess) ;
3736 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3737 masm.jmpb (DONE_LABEL) ;
3738 }
3740 masm.bind (Stacked) ;
3741 // It's not inflated and it's not recursively stack-locked and it's not biased.
3742 // It must be stack-locked.
3743 // Try to reset the header to displaced header.
3744 // The "box" value on the stack is stable, so we can reload
3745 // and be assured we observe the same value as above.
3746 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3747 if (os::is_MP()) { masm.lock(); }
3748 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3749 // Intention fall-thru into DONE_LABEL
3752 // DONE_LABEL is a hot target - we'd really like to place it at the
3753 // start of cache line by padding with NOPs.
3754 // See the AMD and Intel software optimization manuals for the
3755 // most efficient "long" NOP encodings.
3756 // Unfortunately none of our alignment mechanisms suffice.
3757 if ((EmitSync & 65536) == 0) {
3758 masm.bind (CheckSucc) ;
3759 }
3760 masm.bind(DONE_LABEL);
3762 // Avoid branch to branch on AMD processors
3763 if (EmitSync & 32768) { masm.nop() ; }
3764 }
3765 %}
3768 enc_class enc_pop_rdx() %{
3769 emit_opcode(cbuf,0x5A);
3770 %}
3772 enc_class enc_rethrow() %{
3773 cbuf.set_inst_mark();
3774 emit_opcode(cbuf, 0xE9); // jmp entry
3775 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4,
3776 runtime_call_Relocation::spec(), RELOC_IMM32 );
3777 %}
3780 // Convert a double to an int. Java semantics require we do complex
3781 // manglelations in the corner cases. So we set the rounding mode to
3782 // 'zero', store the darned double down as an int, and reset the
3783 // rounding mode to 'nearest'. The hardware throws an exception which
3784 // patches up the correct value directly to the stack.
3785 enc_class D2I_encoding( regD src ) %{
3786 // Flip to round-to-zero mode. We attempted to allow invalid-op
3787 // exceptions here, so that a NAN or other corner-case value will
3788 // thrown an exception (but normal values get converted at full speed).
3789 // However, I2C adapters and other float-stack manglers leave pending
3790 // invalid-op exceptions hanging. We would have to clear them before
3791 // enabling them and that is more expensive than just testing for the
3792 // invalid value Intel stores down in the corner cases.
3793 emit_opcode(cbuf,0xD9); // FLDCW trunc
3794 emit_opcode(cbuf,0x2D);
3795 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3796 // Allocate a word
3797 emit_opcode(cbuf,0x83); // SUB ESP,4
3798 emit_opcode(cbuf,0xEC);
3799 emit_d8(cbuf,0x04);
3800 // Encoding assumes a double has been pushed into FPR0.
3801 // Store down the double as an int, popping the FPU stack
3802 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3803 emit_opcode(cbuf,0x1C);
3804 emit_d8(cbuf,0x24);
3805 // Restore the rounding mode; mask the exception
3806 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3807 emit_opcode(cbuf,0x2D);
3808 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3809 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3810 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3812 // Load the converted int; adjust CPU stack
3813 emit_opcode(cbuf,0x58); // POP EAX
3814 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3815 emit_d32 (cbuf,0x80000000); // 0x80000000
3816 emit_opcode(cbuf,0x75); // JNE around_slow_call
3817 emit_d8 (cbuf,0x07); // Size of slow_call
3818 // Push src onto stack slow-path
3819 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3820 emit_d8 (cbuf,0xC0-1+$src$$reg );
3821 // CALL directly to the runtime
3822 cbuf.set_inst_mark();
3823 emit_opcode(cbuf,0xE8); // Call into runtime
3824 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3825 // Carry on here...
3826 %}
3828 enc_class D2L_encoding( regD src ) %{
3829 emit_opcode(cbuf,0xD9); // FLDCW trunc
3830 emit_opcode(cbuf,0x2D);
3831 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3832 // Allocate a word
3833 emit_opcode(cbuf,0x83); // SUB ESP,8
3834 emit_opcode(cbuf,0xEC);
3835 emit_d8(cbuf,0x08);
3836 // Encoding assumes a double has been pushed into FPR0.
3837 // Store down the double as a long, popping the FPU stack
3838 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3839 emit_opcode(cbuf,0x3C);
3840 emit_d8(cbuf,0x24);
3841 // Restore the rounding mode; mask the exception
3842 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3843 emit_opcode(cbuf,0x2D);
3844 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3845 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3846 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3848 // Load the converted int; adjust CPU stack
3849 emit_opcode(cbuf,0x58); // POP EAX
3850 emit_opcode(cbuf,0x5A); // POP EDX
3851 emit_opcode(cbuf,0x81); // CMP EDX,imm
3852 emit_d8 (cbuf,0xFA); // rdx
3853 emit_d32 (cbuf,0x80000000); // 0x80000000
3854 emit_opcode(cbuf,0x75); // JNE around_slow_call
3855 emit_d8 (cbuf,0x07+4); // Size of slow_call
3856 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3857 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3858 emit_opcode(cbuf,0x75); // JNE around_slow_call
3859 emit_d8 (cbuf,0x07); // Size of slow_call
3860 // Push src onto stack slow-path
3861 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3862 emit_d8 (cbuf,0xC0-1+$src$$reg );
3863 // CALL directly to the runtime
3864 cbuf.set_inst_mark();
3865 emit_opcode(cbuf,0xE8); // Call into runtime
3866 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3867 // Carry on here...
3868 %}
3870 enc_class X2L_encoding( regX src ) %{
3871 // Allocate a word
3872 emit_opcode(cbuf,0x83); // SUB ESP,8
3873 emit_opcode(cbuf,0xEC);
3874 emit_d8(cbuf,0x08);
3876 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3877 emit_opcode (cbuf, 0x0F );
3878 emit_opcode (cbuf, 0x11 );
3879 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3881 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3882 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3884 emit_opcode(cbuf,0xD9); // FLDCW trunc
3885 emit_opcode(cbuf,0x2D);
3886 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3888 // Encoding assumes a double has been pushed into FPR0.
3889 // Store down the double as a long, popping the FPU stack
3890 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3891 emit_opcode(cbuf,0x3C);
3892 emit_d8(cbuf,0x24);
3894 // Restore the rounding mode; mask the exception
3895 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3896 emit_opcode(cbuf,0x2D);
3897 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3898 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3899 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3901 // Load the converted int; adjust CPU stack
3902 emit_opcode(cbuf,0x58); // POP EAX
3904 emit_opcode(cbuf,0x5A); // POP EDX
3906 emit_opcode(cbuf,0x81); // CMP EDX,imm
3907 emit_d8 (cbuf,0xFA); // rdx
3908 emit_d32 (cbuf,0x80000000);// 0x80000000
3910 emit_opcode(cbuf,0x75); // JNE around_slow_call
3911 emit_d8 (cbuf,0x13+4); // Size of slow_call
3913 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3914 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3916 emit_opcode(cbuf,0x75); // JNE around_slow_call
3917 emit_d8 (cbuf,0x13); // Size of slow_call
3919 // Allocate a word
3920 emit_opcode(cbuf,0x83); // SUB ESP,4
3921 emit_opcode(cbuf,0xEC);
3922 emit_d8(cbuf,0x04);
3924 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3925 emit_opcode (cbuf, 0x0F );
3926 emit_opcode (cbuf, 0x11 );
3927 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3929 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3930 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3932 emit_opcode(cbuf,0x83); // ADD ESP,4
3933 emit_opcode(cbuf,0xC4);
3934 emit_d8(cbuf,0x04);
3936 // CALL directly to the runtime
3937 cbuf.set_inst_mark();
3938 emit_opcode(cbuf,0xE8); // Call into runtime
3939 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3940 // Carry on here...
3941 %}
3943 enc_class XD2L_encoding( regXD src ) %{
3944 // Allocate a word
3945 emit_opcode(cbuf,0x83); // SUB ESP,8
3946 emit_opcode(cbuf,0xEC);
3947 emit_d8(cbuf,0x08);
3949 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
3950 emit_opcode (cbuf, 0x0F );
3951 emit_opcode (cbuf, 0x11 );
3952 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3954 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
3955 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3957 emit_opcode(cbuf,0xD9); // FLDCW trunc
3958 emit_opcode(cbuf,0x2D);
3959 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3961 // Encoding assumes a double has been pushed into FPR0.
3962 // Store down the double as a long, popping the FPU stack
3963 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3964 emit_opcode(cbuf,0x3C);
3965 emit_d8(cbuf,0x24);
3967 // Restore the rounding mode; mask the exception
3968 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3969 emit_opcode(cbuf,0x2D);
3970 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3971 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3972 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3974 // Load the converted int; adjust CPU stack
3975 emit_opcode(cbuf,0x58); // POP EAX
3977 emit_opcode(cbuf,0x5A); // POP EDX
3979 emit_opcode(cbuf,0x81); // CMP EDX,imm
3980 emit_d8 (cbuf,0xFA); // rdx
3981 emit_d32 (cbuf,0x80000000); // 0x80000000
3983 emit_opcode(cbuf,0x75); // JNE around_slow_call
3984 emit_d8 (cbuf,0x13+4); // Size of slow_call
3986 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3987 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3989 emit_opcode(cbuf,0x75); // JNE around_slow_call
3990 emit_d8 (cbuf,0x13); // Size of slow_call
3992 // Push src onto stack slow-path
3993 // Allocate a word
3994 emit_opcode(cbuf,0x83); // SUB ESP,8
3995 emit_opcode(cbuf,0xEC);
3996 emit_d8(cbuf,0x08);
3998 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
3999 emit_opcode (cbuf, 0x0F );
4000 emit_opcode (cbuf, 0x11 );
4001 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4003 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4004 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4006 emit_opcode(cbuf,0x83); // ADD ESP,8
4007 emit_opcode(cbuf,0xC4);
4008 emit_d8(cbuf,0x08);
4010 // CALL directly to the runtime
4011 cbuf.set_inst_mark();
4012 emit_opcode(cbuf,0xE8); // Call into runtime
4013 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4014 // Carry on here...
4015 %}
4017 enc_class D2X_encoding( regX dst, regD src ) %{
4018 // Allocate a word
4019 emit_opcode(cbuf,0x83); // SUB ESP,4
4020 emit_opcode(cbuf,0xEC);
4021 emit_d8(cbuf,0x04);
4022 int pop = 0x02;
4023 if ($src$$reg != FPR1L_enc) {
4024 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
4025 emit_d8( cbuf, 0xC0-1+$src$$reg );
4026 pop = 0x03;
4027 }
4028 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP]
4030 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
4031 emit_opcode (cbuf, 0x0F );
4032 emit_opcode (cbuf, 0x10 );
4033 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
4035 emit_opcode(cbuf,0x83); // ADD ESP,4
4036 emit_opcode(cbuf,0xC4);
4037 emit_d8(cbuf,0x04);
4038 // Carry on here...
4039 %}
4041 enc_class FX2I_encoding( regX src, eRegI dst ) %{
4042 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
4044 // Compare the result to see if we need to go to the slow path
4045 emit_opcode(cbuf,0x81); // CMP dst,imm
4046 emit_rm (cbuf,0x3,0x7,$dst$$reg);
4047 emit_d32 (cbuf,0x80000000); // 0x80000000
4049 emit_opcode(cbuf,0x75); // JNE around_slow_call
4050 emit_d8 (cbuf,0x13); // Size of slow_call
4051 // Store xmm to a temp memory
4052 // location and push it onto stack.
4054 emit_opcode(cbuf,0x83); // SUB ESP,4
4055 emit_opcode(cbuf,0xEC);
4056 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4058 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm
4059 emit_opcode (cbuf, 0x0F );
4060 emit_opcode (cbuf, 0x11 );
4061 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4063 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP]
4064 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4066 emit_opcode(cbuf,0x83); // ADD ESP,4
4067 emit_opcode(cbuf,0xC4);
4068 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4070 // CALL directly to the runtime
4071 cbuf.set_inst_mark();
4072 emit_opcode(cbuf,0xE8); // Call into runtime
4073 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4075 // Carry on here...
4076 %}
4078 enc_class X2D_encoding( regD dst, regX src ) %{
4079 // Allocate a word
4080 emit_opcode(cbuf,0x83); // SUB ESP,4
4081 emit_opcode(cbuf,0xEC);
4082 emit_d8(cbuf,0x04);
4084 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm
4085 emit_opcode (cbuf, 0x0F );
4086 emit_opcode (cbuf, 0x11 );
4087 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4089 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4090 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4092 emit_opcode(cbuf,0x83); // ADD ESP,4
4093 emit_opcode(cbuf,0xC4);
4094 emit_d8(cbuf,0x04);
4096 // Carry on here...
4097 %}
4099 enc_class AbsXF_encoding(regX dst) %{
4100 address signmask_address=(address)float_signmask_pool;
4101 // andpd:\tANDPS $dst,[signconst]
4102 emit_opcode(cbuf, 0x0F);
4103 emit_opcode(cbuf, 0x54);
4104 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4105 emit_d32(cbuf, (int)signmask_address);
4106 %}
4108 enc_class AbsXD_encoding(regXD dst) %{
4109 address signmask_address=(address)double_signmask_pool;
4110 // andpd:\tANDPD $dst,[signconst]
4111 emit_opcode(cbuf, 0x66);
4112 emit_opcode(cbuf, 0x0F);
4113 emit_opcode(cbuf, 0x54);
4114 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4115 emit_d32(cbuf, (int)signmask_address);
4116 %}
4118 enc_class NegXF_encoding(regX dst) %{
4119 address signmask_address=(address)float_signflip_pool;
4120 // andpd:\tXORPS $dst,[signconst]
4121 emit_opcode(cbuf, 0x0F);
4122 emit_opcode(cbuf, 0x57);
4123 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4124 emit_d32(cbuf, (int)signmask_address);
4125 %}
4127 enc_class NegXD_encoding(regXD dst) %{
4128 address signmask_address=(address)double_signflip_pool;
4129 // andpd:\tXORPD $dst,[signconst]
4130 emit_opcode(cbuf, 0x66);
4131 emit_opcode(cbuf, 0x0F);
4132 emit_opcode(cbuf, 0x57);
4133 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4134 emit_d32(cbuf, (int)signmask_address);
4135 %}
4137 enc_class FMul_ST_reg( eRegF src1 ) %{
4138 // Operand was loaded from memory into fp ST (stack top)
4139 // FMUL ST,$src /* D8 C8+i */
4140 emit_opcode(cbuf, 0xD8);
4141 emit_opcode(cbuf, 0xC8 + $src1$$reg);
4142 %}
4144 enc_class FAdd_ST_reg( eRegF src2 ) %{
4145 // FADDP ST,src2 /* D8 C0+i */
4146 emit_opcode(cbuf, 0xD8);
4147 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4148 //could use FADDP src2,fpST /* DE C0+i */
4149 %}
4151 enc_class FAddP_reg_ST( eRegF src2 ) %{
4152 // FADDP src2,ST /* DE C0+i */
4153 emit_opcode(cbuf, 0xDE);
4154 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4155 %}
4157 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
4158 // Operand has been loaded into fp ST (stack top)
4159 // FSUB ST,$src1
4160 emit_opcode(cbuf, 0xD8);
4161 emit_opcode(cbuf, 0xE0 + $src1$$reg);
4163 // FDIV
4164 emit_opcode(cbuf, 0xD8);
4165 emit_opcode(cbuf, 0xF0 + $src2$$reg);
4166 %}
4168 enc_class MulFAddF (eRegF src1, eRegF src2) %{
4169 // Operand was loaded from memory into fp ST (stack top)
4170 // FADD ST,$src /* D8 C0+i */
4171 emit_opcode(cbuf, 0xD8);
4172 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4174 // FMUL ST,src2 /* D8 C*+i */
4175 emit_opcode(cbuf, 0xD8);
4176 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4177 %}
4180 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
4181 // Operand was loaded from memory into fp ST (stack top)
4182 // FADD ST,$src /* D8 C0+i */
4183 emit_opcode(cbuf, 0xD8);
4184 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4186 // FMULP src2,ST /* DE C8+i */
4187 emit_opcode(cbuf, 0xDE);
4188 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4189 %}
4191 // Atomically load the volatile long
4192 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
4193 emit_opcode(cbuf,0xDF);
4194 int rm_byte_opcode = 0x05;
4195 int base = $mem$$base;
4196 int index = $mem$$index;
4197 int scale = $mem$$scale;
4198 int displace = $mem$$disp;
4199 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4200 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4201 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
4202 %}
4204 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{
4205 { // Atomic long load
4206 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4207 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4208 emit_opcode(cbuf,0x0F);
4209 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4210 int base = $mem$$base;
4211 int index = $mem$$index;
4212 int scale = $mem$$scale;
4213 int displace = $mem$$disp;
4214 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4215 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4216 }
4217 { // MOVSD $dst,$tmp ! atomic long store
4218 emit_opcode(cbuf,0xF2);
4219 emit_opcode(cbuf,0x0F);
4220 emit_opcode(cbuf,0x11);
4221 int base = $dst$$base;
4222 int index = $dst$$index;
4223 int scale = $dst$$scale;
4224 int displace = $dst$$disp;
4225 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals
4226 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4227 }
4228 %}
4230 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{
4231 { // Atomic long load
4232 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4233 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4234 emit_opcode(cbuf,0x0F);
4235 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4236 int base = $mem$$base;
4237 int index = $mem$$index;
4238 int scale = $mem$$scale;
4239 int displace = $mem$$disp;
4240 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4241 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4242 }
4243 { // MOVD $dst.lo,$tmp
4244 emit_opcode(cbuf,0x66);
4245 emit_opcode(cbuf,0x0F);
4246 emit_opcode(cbuf,0x7E);
4247 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg);
4248 }
4249 { // PSRLQ $tmp,32
4250 emit_opcode(cbuf,0x66);
4251 emit_opcode(cbuf,0x0F);
4252 emit_opcode(cbuf,0x73);
4253 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg);
4254 emit_d8(cbuf, 0x20);
4255 }
4256 { // MOVD $dst.hi,$tmp
4257 emit_opcode(cbuf,0x66);
4258 emit_opcode(cbuf,0x0F);
4259 emit_opcode(cbuf,0x7E);
4260 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
4261 }
4262 %}
4264 // Volatile Store Long. Must be atomic, so move it into
4265 // the FP TOS and then do a 64-bit FIST. Has to probe the
4266 // target address before the store (for null-ptr checks)
4267 // so the memory operand is used twice in the encoding.
4268 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
4269 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
4270 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop
4271 emit_opcode(cbuf,0xDF);
4272 int rm_byte_opcode = 0x07;
4273 int base = $mem$$base;
4274 int index = $mem$$index;
4275 int scale = $mem$$scale;
4276 int displace = $mem$$disp;
4277 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4278 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4279 %}
4281 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{
4282 { // Atomic long load
4283 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src]
4284 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4285 emit_opcode(cbuf,0x0F);
4286 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4287 int base = $src$$base;
4288 int index = $src$$index;
4289 int scale = $src$$scale;
4290 int displace = $src$$disp;
4291 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals
4292 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4293 }
4294 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4295 { // MOVSD $mem,$tmp ! atomic long store
4296 emit_opcode(cbuf,0xF2);
4297 emit_opcode(cbuf,0x0F);
4298 emit_opcode(cbuf,0x11);
4299 int base = $mem$$base;
4300 int index = $mem$$index;
4301 int scale = $mem$$scale;
4302 int displace = $mem$$disp;
4303 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4304 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4305 }
4306 %}
4308 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{
4309 { // MOVD $tmp,$src.lo
4310 emit_opcode(cbuf,0x66);
4311 emit_opcode(cbuf,0x0F);
4312 emit_opcode(cbuf,0x6E);
4313 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
4314 }
4315 { // MOVD $tmp2,$src.hi
4316 emit_opcode(cbuf,0x66);
4317 emit_opcode(cbuf,0x0F);
4318 emit_opcode(cbuf,0x6E);
4319 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg));
4320 }
4321 { // PUNPCKLDQ $tmp,$tmp2
4322 emit_opcode(cbuf,0x66);
4323 emit_opcode(cbuf,0x0F);
4324 emit_opcode(cbuf,0x62);
4325 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg);
4326 }
4327 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4328 { // MOVSD $mem,$tmp ! atomic long store
4329 emit_opcode(cbuf,0xF2);
4330 emit_opcode(cbuf,0x0F);
4331 emit_opcode(cbuf,0x11);
4332 int base = $mem$$base;
4333 int index = $mem$$index;
4334 int scale = $mem$$scale;
4335 int displace = $mem$$disp;
4336 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4337 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4338 }
4339 %}
4341 // Safepoint Poll. This polls the safepoint page, and causes an
4342 // exception if it is not readable. Unfortunately, it kills the condition code
4343 // in the process
4344 // We current use TESTL [spp],EDI
4345 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
4347 enc_class Safepoint_Poll() %{
4348 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0);
4349 emit_opcode(cbuf,0x85);
4350 emit_rm (cbuf, 0x0, 0x7, 0x5);
4351 emit_d32(cbuf, (intptr_t)os::get_polling_page());
4352 %}
4353 %}
4356 //----------FRAME--------------------------------------------------------------
4357 // Definition of frame structure and management information.
4358 //
4359 // S T A C K L A Y O U T Allocators stack-slot number
4360 // | (to get allocators register number
4361 // G Owned by | | v add OptoReg::stack0())
4362 // r CALLER | |
4363 // o | +--------+ pad to even-align allocators stack-slot
4364 // w V | pad0 | numbers; owned by CALLER
4365 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4366 // h ^ | in | 5
4367 // | | args | 4 Holes in incoming args owned by SELF
4368 // | | | | 3
4369 // | | +--------+
4370 // V | | old out| Empty on Intel, window on Sparc
4371 // | old |preserve| Must be even aligned.
4372 // | SP-+--------+----> Matcher::_old_SP, even aligned
4373 // | | in | 3 area for Intel ret address
4374 // Owned by |preserve| Empty on Sparc.
4375 // SELF +--------+
4376 // | | pad2 | 2 pad to align old SP
4377 // | +--------+ 1
4378 // | | locks | 0
4379 // | +--------+----> OptoReg::stack0(), even aligned
4380 // | | pad1 | 11 pad to align new SP
4381 // | +--------+
4382 // | | | 10
4383 // | | spills | 9 spills
4384 // V | | 8 (pad0 slot for callee)
4385 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4386 // ^ | out | 7
4387 // | | args | 6 Holes in outgoing args owned by CALLEE
4388 // Owned by +--------+
4389 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4390 // | new |preserve| Must be even-aligned.
4391 // | SP-+--------+----> Matcher::_new_SP, even aligned
4392 // | | |
4393 //
4394 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4395 // known from SELF's arguments and the Java calling convention.
4396 // Region 6-7 is determined per call site.
4397 // Note 2: If the calling convention leaves holes in the incoming argument
4398 // area, those holes are owned by SELF. Holes in the outgoing area
4399 // are owned by the CALLEE. Holes should not be nessecary in the
4400 // incoming area, as the Java calling convention is completely under
4401 // the control of the AD file. Doubles can be sorted and packed to
4402 // avoid holes. Holes in the outgoing arguments may be nessecary for
4403 // varargs C calling conventions.
4404 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4405 // even aligned with pad0 as needed.
4406 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4407 // region 6-11 is even aligned; it may be padded out more so that
4408 // the region from SP to FP meets the minimum stack alignment.
4410 frame %{
4411 // What direction does stack grow in (assumed to be same for C & Java)
4412 stack_direction(TOWARDS_LOW);
4414 // These three registers define part of the calling convention
4415 // between compiled code and the interpreter.
4416 inline_cache_reg(EAX); // Inline Cache Register
4417 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
4419 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
4420 cisc_spilling_operand_name(indOffset32);
4422 // Number of stack slots consumed by locking an object
4423 sync_stack_slots(1);
4425 // Compiled code's Frame Pointer
4426 frame_pointer(ESP);
4427 // Interpreter stores its frame pointer in a register which is
4428 // stored to the stack by I2CAdaptors.
4429 // I2CAdaptors convert from interpreted java to compiled java.
4430 interpreter_frame_pointer(EBP);
4432 // Stack alignment requirement
4433 // Alignment size in bytes (128-bit -> 16 bytes)
4434 stack_alignment(StackAlignmentInBytes);
4436 // Number of stack slots between incoming argument block and the start of
4437 // a new frame. The PROLOG must add this many slots to the stack. The
4438 // EPILOG must remove this many slots. Intel needs one slot for
4439 // return address and one for rbp, (must save rbp)
4440 in_preserve_stack_slots(2+VerifyStackAtCalls);
4442 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4443 // for calls to C. Supports the var-args backing area for register parms.
4444 varargs_C_out_slots_killed(0);
4446 // The after-PROLOG location of the return address. Location of
4447 // return address specifies a type (REG or STACK) and a number
4448 // representing the register number (i.e. - use a register name) or
4449 // stack slot.
4450 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4451 // Otherwise, it is above the locks and verification slot and alignment word
4452 return_addr(STACK - 1 +
4453 round_to(1+VerifyStackAtCalls+
4454 Compile::current()->fixed_slots(),
4455 (StackAlignmentInBytes/wordSize)));
4457 // Body of function which returns an integer array locating
4458 // arguments either in registers or in stack slots. Passed an array
4459 // of ideal registers called "sig" and a "length" count. Stack-slot
4460 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4461 // arguments for a CALLEE. Incoming stack arguments are
4462 // automatically biased by the preserve_stack_slots field above.
4463 calling_convention %{
4464 // No difference between ingoing/outgoing just pass false
4465 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4466 %}
4469 // Body of function which returns an integer array locating
4470 // arguments either in registers or in stack slots. Passed an array
4471 // of ideal registers called "sig" and a "length" count. Stack-slot
4472 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4473 // arguments for a CALLEE. Incoming stack arguments are
4474 // automatically biased by the preserve_stack_slots field above.
4475 c_calling_convention %{
4476 // This is obviously always outgoing
4477 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4478 %}
4480 // Location of C & interpreter return values
4481 c_return_value %{
4482 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4483 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4484 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4486 // in SSE2+ mode we want to keep the FPU stack clean so pretend
4487 // that C functions return float and double results in XMM0.
4488 if( ideal_reg == Op_RegD && UseSSE>=2 )
4489 return OptoRegPair(XMM0b_num,XMM0a_num);
4490 if( ideal_reg == Op_RegF && UseSSE>=2 )
4491 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4493 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4494 %}
4496 // Location of return values
4497 return_value %{
4498 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4499 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4500 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4501 if( ideal_reg == Op_RegD && UseSSE>=2 )
4502 return OptoRegPair(XMM0b_num,XMM0a_num);
4503 if( ideal_reg == Op_RegF && UseSSE>=1 )
4504 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4505 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4506 %}
4508 %}
4510 //----------ATTRIBUTES---------------------------------------------------------
4511 //----------Operand Attributes-------------------------------------------------
4512 op_attrib op_cost(0); // Required cost attribute
4514 //----------Instruction Attributes---------------------------------------------
4515 ins_attrib ins_cost(100); // Required cost attribute
4516 ins_attrib ins_size(8); // Required size attribute (in bits)
4517 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4518 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
4519 // non-matching short branch variant of some
4520 // long branch?
4521 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
4522 // specifies the alignment that some part of the instruction (not
4523 // necessarily the start) requires. If > 1, a compute_padding()
4524 // function must be provided for the instruction
4526 //----------OPERANDS-----------------------------------------------------------
4527 // Operand definitions must precede instruction definitions for correct parsing
4528 // in the ADLC because operands constitute user defined types which are used in
4529 // instruction definitions.
4531 //----------Simple Operands----------------------------------------------------
4532 // Immediate Operands
4533 // Integer Immediate
4534 operand immI() %{
4535 match(ConI);
4537 op_cost(10);
4538 format %{ %}
4539 interface(CONST_INTER);
4540 %}
4542 // Constant for test vs zero
4543 operand immI0() %{
4544 predicate(n->get_int() == 0);
4545 match(ConI);
4547 op_cost(0);
4548 format %{ %}
4549 interface(CONST_INTER);
4550 %}
4552 // Constant for increment
4553 operand immI1() %{
4554 predicate(n->get_int() == 1);
4555 match(ConI);
4557 op_cost(0);
4558 format %{ %}
4559 interface(CONST_INTER);
4560 %}
4562 // Constant for decrement
4563 operand immI_M1() %{
4564 predicate(n->get_int() == -1);
4565 match(ConI);
4567 op_cost(0);
4568 format %{ %}
4569 interface(CONST_INTER);
4570 %}
4572 // Valid scale values for addressing modes
4573 operand immI2() %{
4574 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4575 match(ConI);
4577 format %{ %}
4578 interface(CONST_INTER);
4579 %}
4581 operand immI8() %{
4582 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4583 match(ConI);
4585 op_cost(5);
4586 format %{ %}
4587 interface(CONST_INTER);
4588 %}
4590 operand immI16() %{
4591 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4592 match(ConI);
4594 op_cost(10);
4595 format %{ %}
4596 interface(CONST_INTER);
4597 %}
4599 // Constant for long shifts
4600 operand immI_32() %{
4601 predicate( n->get_int() == 32 );
4602 match(ConI);
4604 op_cost(0);
4605 format %{ %}
4606 interface(CONST_INTER);
4607 %}
4609 operand immI_1_31() %{
4610 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
4611 match(ConI);
4613 op_cost(0);
4614 format %{ %}
4615 interface(CONST_INTER);
4616 %}
4618 operand immI_32_63() %{
4619 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
4620 match(ConI);
4621 op_cost(0);
4623 format %{ %}
4624 interface(CONST_INTER);
4625 %}
4627 operand immI_1() %{
4628 predicate( n->get_int() == 1 );
4629 match(ConI);
4631 op_cost(0);
4632 format %{ %}
4633 interface(CONST_INTER);
4634 %}
4636 operand immI_2() %{
4637 predicate( n->get_int() == 2 );
4638 match(ConI);
4640 op_cost(0);
4641 format %{ %}
4642 interface(CONST_INTER);
4643 %}
4645 operand immI_3() %{
4646 predicate( n->get_int() == 3 );
4647 match(ConI);
4649 op_cost(0);
4650 format %{ %}
4651 interface(CONST_INTER);
4652 %}
4654 // Pointer Immediate
4655 operand immP() %{
4656 match(ConP);
4658 op_cost(10);
4659 format %{ %}
4660 interface(CONST_INTER);
4661 %}
4663 // NULL Pointer Immediate
4664 operand immP0() %{
4665 predicate( n->get_ptr() == 0 );
4666 match(ConP);
4667 op_cost(0);
4669 format %{ %}
4670 interface(CONST_INTER);
4671 %}
4673 // Long Immediate
4674 operand immL() %{
4675 match(ConL);
4677 op_cost(20);
4678 format %{ %}
4679 interface(CONST_INTER);
4680 %}
4682 // Long Immediate zero
4683 operand immL0() %{
4684 predicate( n->get_long() == 0L );
4685 match(ConL);
4686 op_cost(0);
4688 format %{ %}
4689 interface(CONST_INTER);
4690 %}
4692 // Long Immediate zero
4693 operand immL_M1() %{
4694 predicate( n->get_long() == -1L );
4695 match(ConL);
4696 op_cost(0);
4698 format %{ %}
4699 interface(CONST_INTER);
4700 %}
4702 // Long immediate from 0 to 127.
4703 // Used for a shorter form of long mul by 10.
4704 operand immL_127() %{
4705 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4706 match(ConL);
4707 op_cost(0);
4709 format %{ %}
4710 interface(CONST_INTER);
4711 %}
4713 // Long Immediate: low 32-bit mask
4714 operand immL_32bits() %{
4715 predicate(n->get_long() == 0xFFFFFFFFL);
4716 match(ConL);
4717 op_cost(0);
4719 format %{ %}
4720 interface(CONST_INTER);
4721 %}
4723 // Long Immediate: low 32-bit mask
4724 operand immL32() %{
4725 predicate(n->get_long() == (int)(n->get_long()));
4726 match(ConL);
4727 op_cost(20);
4729 format %{ %}
4730 interface(CONST_INTER);
4731 %}
4733 //Double Immediate zero
4734 operand immD0() %{
4735 // Do additional (and counter-intuitive) test against NaN to work around VC++
4736 // bug that generates code such that NaNs compare equal to 0.0
4737 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4738 match(ConD);
4740 op_cost(5);
4741 format %{ %}
4742 interface(CONST_INTER);
4743 %}
4745 // Double Immediate
4746 operand immD1() %{
4747 predicate( UseSSE<=1 && n->getd() == 1.0 );
4748 match(ConD);
4750 op_cost(5);
4751 format %{ %}
4752 interface(CONST_INTER);
4753 %}
4755 // Double Immediate
4756 operand immD() %{
4757 predicate(UseSSE<=1);
4758 match(ConD);
4760 op_cost(5);
4761 format %{ %}
4762 interface(CONST_INTER);
4763 %}
4765 operand immXD() %{
4766 predicate(UseSSE>=2);
4767 match(ConD);
4769 op_cost(5);
4770 format %{ %}
4771 interface(CONST_INTER);
4772 %}
4774 // Double Immediate zero
4775 operand immXD0() %{
4776 // Do additional (and counter-intuitive) test against NaN to work around VC++
4777 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4778 // compare equal to -0.0.
4779 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4780 match(ConD);
4782 format %{ %}
4783 interface(CONST_INTER);
4784 %}
4786 // Float Immediate zero
4787 operand immF0() %{
4788 predicate( UseSSE == 0 && n->getf() == 0.0 );
4789 match(ConF);
4791 op_cost(5);
4792 format %{ %}
4793 interface(CONST_INTER);
4794 %}
4796 // Float Immediate
4797 operand immF() %{
4798 predicate( UseSSE == 0 );
4799 match(ConF);
4801 op_cost(5);
4802 format %{ %}
4803 interface(CONST_INTER);
4804 %}
4806 // Float Immediate
4807 operand immXF() %{
4808 predicate(UseSSE >= 1);
4809 match(ConF);
4811 op_cost(5);
4812 format %{ %}
4813 interface(CONST_INTER);
4814 %}
4816 // Float Immediate zero. Zero and not -0.0
4817 operand immXF0() %{
4818 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4819 match(ConF);
4821 op_cost(5);
4822 format %{ %}
4823 interface(CONST_INTER);
4824 %}
4826 // Immediates for special shifts (sign extend)
4828 // Constants for increment
4829 operand immI_16() %{
4830 predicate( n->get_int() == 16 );
4831 match(ConI);
4833 format %{ %}
4834 interface(CONST_INTER);
4835 %}
4837 operand immI_24() %{
4838 predicate( n->get_int() == 24 );
4839 match(ConI);
4841 format %{ %}
4842 interface(CONST_INTER);
4843 %}
4845 // Constant for byte-wide masking
4846 operand immI_255() %{
4847 predicate( n->get_int() == 255 );
4848 match(ConI);
4850 format %{ %}
4851 interface(CONST_INTER);
4852 %}
4854 // Constant for short-wide masking
4855 operand immI_65535() %{
4856 predicate(n->get_int() == 65535);
4857 match(ConI);
4859 format %{ %}
4860 interface(CONST_INTER);
4861 %}
4863 // Register Operands
4864 // Integer Register
4865 operand eRegI() %{
4866 constraint(ALLOC_IN_RC(e_reg));
4867 match(RegI);
4868 match(xRegI);
4869 match(eAXRegI);
4870 match(eBXRegI);
4871 match(eCXRegI);
4872 match(eDXRegI);
4873 match(eDIRegI);
4874 match(eSIRegI);
4876 format %{ %}
4877 interface(REG_INTER);
4878 %}
4880 // Subset of Integer Register
4881 operand xRegI(eRegI reg) %{
4882 constraint(ALLOC_IN_RC(x_reg));
4883 match(reg);
4884 match(eAXRegI);
4885 match(eBXRegI);
4886 match(eCXRegI);
4887 match(eDXRegI);
4889 format %{ %}
4890 interface(REG_INTER);
4891 %}
4893 // Special Registers
4894 operand eAXRegI(xRegI reg) %{
4895 constraint(ALLOC_IN_RC(eax_reg));
4896 match(reg);
4897 match(eRegI);
4899 format %{ "EAX" %}
4900 interface(REG_INTER);
4901 %}
4903 // Special Registers
4904 operand eBXRegI(xRegI reg) %{
4905 constraint(ALLOC_IN_RC(ebx_reg));
4906 match(reg);
4907 match(eRegI);
4909 format %{ "EBX" %}
4910 interface(REG_INTER);
4911 %}
4913 operand eCXRegI(xRegI reg) %{
4914 constraint(ALLOC_IN_RC(ecx_reg));
4915 match(reg);
4916 match(eRegI);
4918 format %{ "ECX" %}
4919 interface(REG_INTER);
4920 %}
4922 operand eDXRegI(xRegI reg) %{
4923 constraint(ALLOC_IN_RC(edx_reg));
4924 match(reg);
4925 match(eRegI);
4927 format %{ "EDX" %}
4928 interface(REG_INTER);
4929 %}
4931 operand eDIRegI(xRegI reg) %{
4932 constraint(ALLOC_IN_RC(edi_reg));
4933 match(reg);
4934 match(eRegI);
4936 format %{ "EDI" %}
4937 interface(REG_INTER);
4938 %}
4940 operand naxRegI() %{
4941 constraint(ALLOC_IN_RC(nax_reg));
4942 match(RegI);
4943 match(eCXRegI);
4944 match(eDXRegI);
4945 match(eSIRegI);
4946 match(eDIRegI);
4948 format %{ %}
4949 interface(REG_INTER);
4950 %}
4952 operand nadxRegI() %{
4953 constraint(ALLOC_IN_RC(nadx_reg));
4954 match(RegI);
4955 match(eBXRegI);
4956 match(eCXRegI);
4957 match(eSIRegI);
4958 match(eDIRegI);
4960 format %{ %}
4961 interface(REG_INTER);
4962 %}
4964 operand ncxRegI() %{
4965 constraint(ALLOC_IN_RC(ncx_reg));
4966 match(RegI);
4967 match(eAXRegI);
4968 match(eDXRegI);
4969 match(eSIRegI);
4970 match(eDIRegI);
4972 format %{ %}
4973 interface(REG_INTER);
4974 %}
4976 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4977 // //
4978 operand eSIRegI(xRegI reg) %{
4979 constraint(ALLOC_IN_RC(esi_reg));
4980 match(reg);
4981 match(eRegI);
4983 format %{ "ESI" %}
4984 interface(REG_INTER);
4985 %}
4987 // Pointer Register
4988 operand anyRegP() %{
4989 constraint(ALLOC_IN_RC(any_reg));
4990 match(RegP);
4991 match(eAXRegP);
4992 match(eBXRegP);
4993 match(eCXRegP);
4994 match(eDIRegP);
4995 match(eRegP);
4997 format %{ %}
4998 interface(REG_INTER);
4999 %}
5001 operand eRegP() %{
5002 constraint(ALLOC_IN_RC(e_reg));
5003 match(RegP);
5004 match(eAXRegP);
5005 match(eBXRegP);
5006 match(eCXRegP);
5007 match(eDIRegP);
5009 format %{ %}
5010 interface(REG_INTER);
5011 %}
5013 // On windows95, EBP is not safe to use for implicit null tests.
5014 operand eRegP_no_EBP() %{
5015 constraint(ALLOC_IN_RC(e_reg_no_rbp));
5016 match(RegP);
5017 match(eAXRegP);
5018 match(eBXRegP);
5019 match(eCXRegP);
5020 match(eDIRegP);
5022 op_cost(100);
5023 format %{ %}
5024 interface(REG_INTER);
5025 %}
5027 operand naxRegP() %{
5028 constraint(ALLOC_IN_RC(nax_reg));
5029 match(RegP);
5030 match(eBXRegP);
5031 match(eDXRegP);
5032 match(eCXRegP);
5033 match(eSIRegP);
5034 match(eDIRegP);
5036 format %{ %}
5037 interface(REG_INTER);
5038 %}
5040 operand nabxRegP() %{
5041 constraint(ALLOC_IN_RC(nabx_reg));
5042 match(RegP);
5043 match(eCXRegP);
5044 match(eDXRegP);
5045 match(eSIRegP);
5046 match(eDIRegP);
5048 format %{ %}
5049 interface(REG_INTER);
5050 %}
5052 operand pRegP() %{
5053 constraint(ALLOC_IN_RC(p_reg));
5054 match(RegP);
5055 match(eBXRegP);
5056 match(eDXRegP);
5057 match(eSIRegP);
5058 match(eDIRegP);
5060 format %{ %}
5061 interface(REG_INTER);
5062 %}
5064 // Special Registers
5065 // Return a pointer value
5066 operand eAXRegP(eRegP reg) %{
5067 constraint(ALLOC_IN_RC(eax_reg));
5068 match(reg);
5069 format %{ "EAX" %}
5070 interface(REG_INTER);
5071 %}
5073 // Used in AtomicAdd
5074 operand eBXRegP(eRegP reg) %{
5075 constraint(ALLOC_IN_RC(ebx_reg));
5076 match(reg);
5077 format %{ "EBX" %}
5078 interface(REG_INTER);
5079 %}
5081 // Tail-call (interprocedural jump) to interpreter
5082 operand eCXRegP(eRegP reg) %{
5083 constraint(ALLOC_IN_RC(ecx_reg));
5084 match(reg);
5085 format %{ "ECX" %}
5086 interface(REG_INTER);
5087 %}
5089 operand eSIRegP(eRegP reg) %{
5090 constraint(ALLOC_IN_RC(esi_reg));
5091 match(reg);
5092 format %{ "ESI" %}
5093 interface(REG_INTER);
5094 %}
5096 // Used in rep stosw
5097 operand eDIRegP(eRegP reg) %{
5098 constraint(ALLOC_IN_RC(edi_reg));
5099 match(reg);
5100 format %{ "EDI" %}
5101 interface(REG_INTER);
5102 %}
5104 operand eBPRegP() %{
5105 constraint(ALLOC_IN_RC(ebp_reg));
5106 match(RegP);
5107 format %{ "EBP" %}
5108 interface(REG_INTER);
5109 %}
5111 operand eRegL() %{
5112 constraint(ALLOC_IN_RC(long_reg));
5113 match(RegL);
5114 match(eADXRegL);
5116 format %{ %}
5117 interface(REG_INTER);
5118 %}
5120 operand eADXRegL( eRegL reg ) %{
5121 constraint(ALLOC_IN_RC(eadx_reg));
5122 match(reg);
5124 format %{ "EDX:EAX" %}
5125 interface(REG_INTER);
5126 %}
5128 operand eBCXRegL( eRegL reg ) %{
5129 constraint(ALLOC_IN_RC(ebcx_reg));
5130 match(reg);
5132 format %{ "EBX:ECX" %}
5133 interface(REG_INTER);
5134 %}
5136 // Special case for integer high multiply
5137 operand eADXRegL_low_only() %{
5138 constraint(ALLOC_IN_RC(eadx_reg));
5139 match(RegL);
5141 format %{ "EAX" %}
5142 interface(REG_INTER);
5143 %}
5145 // Flags register, used as output of compare instructions
5146 operand eFlagsReg() %{
5147 constraint(ALLOC_IN_RC(int_flags));
5148 match(RegFlags);
5150 format %{ "EFLAGS" %}
5151 interface(REG_INTER);
5152 %}
5154 // Flags register, used as output of FLOATING POINT compare instructions
5155 operand eFlagsRegU() %{
5156 constraint(ALLOC_IN_RC(int_flags));
5157 match(RegFlags);
5159 format %{ "EFLAGS_U" %}
5160 interface(REG_INTER);
5161 %}
5163 operand eFlagsRegUCF() %{
5164 constraint(ALLOC_IN_RC(int_flags));
5165 match(RegFlags);
5166 predicate(false);
5168 format %{ "EFLAGS_U_CF" %}
5169 interface(REG_INTER);
5170 %}
5172 // Condition Code Register used by long compare
5173 operand flagsReg_long_LTGE() %{
5174 constraint(ALLOC_IN_RC(int_flags));
5175 match(RegFlags);
5176 format %{ "FLAGS_LTGE" %}
5177 interface(REG_INTER);
5178 %}
5179 operand flagsReg_long_EQNE() %{
5180 constraint(ALLOC_IN_RC(int_flags));
5181 match(RegFlags);
5182 format %{ "FLAGS_EQNE" %}
5183 interface(REG_INTER);
5184 %}
5185 operand flagsReg_long_LEGT() %{
5186 constraint(ALLOC_IN_RC(int_flags));
5187 match(RegFlags);
5188 format %{ "FLAGS_LEGT" %}
5189 interface(REG_INTER);
5190 %}
5192 // Float register operands
5193 operand regD() %{
5194 predicate( UseSSE < 2 );
5195 constraint(ALLOC_IN_RC(dbl_reg));
5196 match(RegD);
5197 match(regDPR1);
5198 match(regDPR2);
5199 format %{ %}
5200 interface(REG_INTER);
5201 %}
5203 operand regDPR1(regD reg) %{
5204 predicate( UseSSE < 2 );
5205 constraint(ALLOC_IN_RC(dbl_reg0));
5206 match(reg);
5207 format %{ "FPR1" %}
5208 interface(REG_INTER);
5209 %}
5211 operand regDPR2(regD reg) %{
5212 predicate( UseSSE < 2 );
5213 constraint(ALLOC_IN_RC(dbl_reg1));
5214 match(reg);
5215 format %{ "FPR2" %}
5216 interface(REG_INTER);
5217 %}
5219 operand regnotDPR1(regD reg) %{
5220 predicate( UseSSE < 2 );
5221 constraint(ALLOC_IN_RC(dbl_notreg0));
5222 match(reg);
5223 format %{ %}
5224 interface(REG_INTER);
5225 %}
5227 // XMM Double register operands
5228 operand regXD() %{
5229 predicate( UseSSE>=2 );
5230 constraint(ALLOC_IN_RC(xdb_reg));
5231 match(RegD);
5232 match(regXD6);
5233 match(regXD7);
5234 format %{ %}
5235 interface(REG_INTER);
5236 %}
5238 // XMM6 double register operands
5239 operand regXD6(regXD reg) %{
5240 predicate( UseSSE>=2 );
5241 constraint(ALLOC_IN_RC(xdb_reg6));
5242 match(reg);
5243 format %{ "XMM6" %}
5244 interface(REG_INTER);
5245 %}
5247 // XMM7 double register operands
5248 operand regXD7(regXD reg) %{
5249 predicate( UseSSE>=2 );
5250 constraint(ALLOC_IN_RC(xdb_reg7));
5251 match(reg);
5252 format %{ "XMM7" %}
5253 interface(REG_INTER);
5254 %}
5256 // Float register operands
5257 operand regF() %{
5258 predicate( UseSSE < 2 );
5259 constraint(ALLOC_IN_RC(flt_reg));
5260 match(RegF);
5261 match(regFPR1);
5262 format %{ %}
5263 interface(REG_INTER);
5264 %}
5266 // Float register operands
5267 operand regFPR1(regF reg) %{
5268 predicate( UseSSE < 2 );
5269 constraint(ALLOC_IN_RC(flt_reg0));
5270 match(reg);
5271 format %{ "FPR1" %}
5272 interface(REG_INTER);
5273 %}
5275 // XMM register operands
5276 operand regX() %{
5277 predicate( UseSSE>=1 );
5278 constraint(ALLOC_IN_RC(xmm_reg));
5279 match(RegF);
5280 format %{ %}
5281 interface(REG_INTER);
5282 %}
5285 //----------Memory Operands----------------------------------------------------
5286 // Direct Memory Operand
5287 operand direct(immP addr) %{
5288 match(addr);
5290 format %{ "[$addr]" %}
5291 interface(MEMORY_INTER) %{
5292 base(0xFFFFFFFF);
5293 index(0x4);
5294 scale(0x0);
5295 disp($addr);
5296 %}
5297 %}
5299 // Indirect Memory Operand
5300 operand indirect(eRegP reg) %{
5301 constraint(ALLOC_IN_RC(e_reg));
5302 match(reg);
5304 format %{ "[$reg]" %}
5305 interface(MEMORY_INTER) %{
5306 base($reg);
5307 index(0x4);
5308 scale(0x0);
5309 disp(0x0);
5310 %}
5311 %}
5313 // Indirect Memory Plus Short Offset Operand
5314 operand indOffset8(eRegP reg, immI8 off) %{
5315 match(AddP reg off);
5317 format %{ "[$reg + $off]" %}
5318 interface(MEMORY_INTER) %{
5319 base($reg);
5320 index(0x4);
5321 scale(0x0);
5322 disp($off);
5323 %}
5324 %}
5326 // Indirect Memory Plus Long Offset Operand
5327 operand indOffset32(eRegP reg, immI off) %{
5328 match(AddP reg off);
5330 format %{ "[$reg + $off]" %}
5331 interface(MEMORY_INTER) %{
5332 base($reg);
5333 index(0x4);
5334 scale(0x0);
5335 disp($off);
5336 %}
5337 %}
5339 // Indirect Memory Plus Long Offset Operand
5340 operand indOffset32X(eRegI reg, immP off) %{
5341 match(AddP off reg);
5343 format %{ "[$reg + $off]" %}
5344 interface(MEMORY_INTER) %{
5345 base($reg);
5346 index(0x4);
5347 scale(0x0);
5348 disp($off);
5349 %}
5350 %}
5352 // Indirect Memory Plus Index Register Plus Offset Operand
5353 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
5354 match(AddP (AddP reg ireg) off);
5356 op_cost(10);
5357 format %{"[$reg + $off + $ireg]" %}
5358 interface(MEMORY_INTER) %{
5359 base($reg);
5360 index($ireg);
5361 scale(0x0);
5362 disp($off);
5363 %}
5364 %}
5366 // Indirect Memory Plus Index Register Plus Offset Operand
5367 operand indIndex(eRegP reg, eRegI ireg) %{
5368 match(AddP reg ireg);
5370 op_cost(10);
5371 format %{"[$reg + $ireg]" %}
5372 interface(MEMORY_INTER) %{
5373 base($reg);
5374 index($ireg);
5375 scale(0x0);
5376 disp(0x0);
5377 %}
5378 %}
5380 // // -------------------------------------------------------------------------
5381 // // 486 architecture doesn't support "scale * index + offset" with out a base
5382 // // -------------------------------------------------------------------------
5383 // // Scaled Memory Operands
5384 // // Indirect Memory Times Scale Plus Offset Operand
5385 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
5386 // match(AddP off (LShiftI ireg scale));
5387 //
5388 // op_cost(10);
5389 // format %{"[$off + $ireg << $scale]" %}
5390 // interface(MEMORY_INTER) %{
5391 // base(0x4);
5392 // index($ireg);
5393 // scale($scale);
5394 // disp($off);
5395 // %}
5396 // %}
5398 // Indirect Memory Times Scale Plus Index Register
5399 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
5400 match(AddP reg (LShiftI ireg scale));
5402 op_cost(10);
5403 format %{"[$reg + $ireg << $scale]" %}
5404 interface(MEMORY_INTER) %{
5405 base($reg);
5406 index($ireg);
5407 scale($scale);
5408 disp(0x0);
5409 %}
5410 %}
5412 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5413 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
5414 match(AddP (AddP reg (LShiftI ireg scale)) off);
5416 op_cost(10);
5417 format %{"[$reg + $off + $ireg << $scale]" %}
5418 interface(MEMORY_INTER) %{
5419 base($reg);
5420 index($ireg);
5421 scale($scale);
5422 disp($off);
5423 %}
5424 %}
5426 //----------Load Long Memory Operands------------------------------------------
5427 // The load-long idiom will use it's address expression again after loading
5428 // the first word of the long. If the load-long destination overlaps with
5429 // registers used in the addressing expression, the 2nd half will be loaded
5430 // from a clobbered address. Fix this by requiring that load-long use
5431 // address registers that do not overlap with the load-long target.
5433 // load-long support
5434 operand load_long_RegP() %{
5435 constraint(ALLOC_IN_RC(esi_reg));
5436 match(RegP);
5437 match(eSIRegP);
5438 op_cost(100);
5439 format %{ %}
5440 interface(REG_INTER);
5441 %}
5443 // Indirect Memory Operand Long
5444 operand load_long_indirect(load_long_RegP reg) %{
5445 constraint(ALLOC_IN_RC(esi_reg));
5446 match(reg);
5448 format %{ "[$reg]" %}
5449 interface(MEMORY_INTER) %{
5450 base($reg);
5451 index(0x4);
5452 scale(0x0);
5453 disp(0x0);
5454 %}
5455 %}
5457 // Indirect Memory Plus Long Offset Operand
5458 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
5459 match(AddP reg off);
5461 format %{ "[$reg + $off]" %}
5462 interface(MEMORY_INTER) %{
5463 base($reg);
5464 index(0x4);
5465 scale(0x0);
5466 disp($off);
5467 %}
5468 %}
5470 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
5473 //----------Special Memory Operands--------------------------------------------
5474 // Stack Slot Operand - This operand is used for loading and storing temporary
5475 // values on the stack where a match requires a value to
5476 // flow through memory.
5477 operand stackSlotP(sRegP reg) %{
5478 constraint(ALLOC_IN_RC(stack_slots));
5479 // No match rule because this operand is only generated in matching
5480 format %{ "[$reg]" %}
5481 interface(MEMORY_INTER) %{
5482 base(0x4); // ESP
5483 index(0x4); // No Index
5484 scale(0x0); // No Scale
5485 disp($reg); // Stack Offset
5486 %}
5487 %}
5489 operand stackSlotI(sRegI reg) %{
5490 constraint(ALLOC_IN_RC(stack_slots));
5491 // No match rule because this operand is only generated in matching
5492 format %{ "[$reg]" %}
5493 interface(MEMORY_INTER) %{
5494 base(0x4); // ESP
5495 index(0x4); // No Index
5496 scale(0x0); // No Scale
5497 disp($reg); // Stack Offset
5498 %}
5499 %}
5501 operand stackSlotF(sRegF reg) %{
5502 constraint(ALLOC_IN_RC(stack_slots));
5503 // No match rule because this operand is only generated in matching
5504 format %{ "[$reg]" %}
5505 interface(MEMORY_INTER) %{
5506 base(0x4); // ESP
5507 index(0x4); // No Index
5508 scale(0x0); // No Scale
5509 disp($reg); // Stack Offset
5510 %}
5511 %}
5513 operand stackSlotD(sRegD reg) %{
5514 constraint(ALLOC_IN_RC(stack_slots));
5515 // No match rule because this operand is only generated in matching
5516 format %{ "[$reg]" %}
5517 interface(MEMORY_INTER) %{
5518 base(0x4); // ESP
5519 index(0x4); // No Index
5520 scale(0x0); // No Scale
5521 disp($reg); // Stack Offset
5522 %}
5523 %}
5525 operand stackSlotL(sRegL reg) %{
5526 constraint(ALLOC_IN_RC(stack_slots));
5527 // No match rule because this operand is only generated in matching
5528 format %{ "[$reg]" %}
5529 interface(MEMORY_INTER) %{
5530 base(0x4); // ESP
5531 index(0x4); // No Index
5532 scale(0x0); // No Scale
5533 disp($reg); // Stack Offset
5534 %}
5535 %}
5537 //----------Memory Operands - Win95 Implicit Null Variants----------------
5538 // Indirect Memory Operand
5539 operand indirect_win95_safe(eRegP_no_EBP reg)
5540 %{
5541 constraint(ALLOC_IN_RC(e_reg));
5542 match(reg);
5544 op_cost(100);
5545 format %{ "[$reg]" %}
5546 interface(MEMORY_INTER) %{
5547 base($reg);
5548 index(0x4);
5549 scale(0x0);
5550 disp(0x0);
5551 %}
5552 %}
5554 // Indirect Memory Plus Short Offset Operand
5555 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
5556 %{
5557 match(AddP reg off);
5559 op_cost(100);
5560 format %{ "[$reg + $off]" %}
5561 interface(MEMORY_INTER) %{
5562 base($reg);
5563 index(0x4);
5564 scale(0x0);
5565 disp($off);
5566 %}
5567 %}
5569 // Indirect Memory Plus Long Offset Operand
5570 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
5571 %{
5572 match(AddP reg off);
5574 op_cost(100);
5575 format %{ "[$reg + $off]" %}
5576 interface(MEMORY_INTER) %{
5577 base($reg);
5578 index(0x4);
5579 scale(0x0);
5580 disp($off);
5581 %}
5582 %}
5584 // Indirect Memory Plus Index Register Plus Offset Operand
5585 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5586 %{
5587 match(AddP (AddP reg ireg) off);
5589 op_cost(100);
5590 format %{"[$reg + $off + $ireg]" %}
5591 interface(MEMORY_INTER) %{
5592 base($reg);
5593 index($ireg);
5594 scale(0x0);
5595 disp($off);
5596 %}
5597 %}
5599 // Indirect Memory Times Scale Plus Index Register
5600 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5601 %{
5602 match(AddP reg (LShiftI ireg scale));
5604 op_cost(100);
5605 format %{"[$reg + $ireg << $scale]" %}
5606 interface(MEMORY_INTER) %{
5607 base($reg);
5608 index($ireg);
5609 scale($scale);
5610 disp(0x0);
5611 %}
5612 %}
5614 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5615 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
5616 %{
5617 match(AddP (AddP reg (LShiftI ireg scale)) off);
5619 op_cost(100);
5620 format %{"[$reg + $off + $ireg << $scale]" %}
5621 interface(MEMORY_INTER) %{
5622 base($reg);
5623 index($ireg);
5624 scale($scale);
5625 disp($off);
5626 %}
5627 %}
5629 //----------Conditional Branch Operands----------------------------------------
5630 // Comparison Op - This is the operation of the comparison, and is limited to
5631 // the following set of codes:
5632 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5633 //
5634 // Other attributes of the comparison, such as unsignedness, are specified
5635 // by the comparison instruction that sets a condition code flags register.
5636 // That result is represented by a flags operand whose subtype is appropriate
5637 // to the unsignedness (etc.) of the comparison.
5638 //
5639 // Later, the instruction which matches both the Comparison Op (a Bool) and
5640 // the flags (produced by the Cmp) specifies the coding of the comparison op
5641 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5643 // Comparision Code
5644 operand cmpOp() %{
5645 match(Bool);
5647 format %{ "" %}
5648 interface(COND_INTER) %{
5649 equal(0x4, "e");
5650 not_equal(0x5, "ne");
5651 less(0xC, "l");
5652 greater_equal(0xD, "ge");
5653 less_equal(0xE, "le");
5654 greater(0xF, "g");
5655 %}
5656 %}
5658 // Comparison Code, unsigned compare. Used by FP also, with
5659 // C2 (unordered) turned into GT or LT already. The other bits
5660 // C0 and C3 are turned into Carry & Zero flags.
5661 operand cmpOpU() %{
5662 match(Bool);
5664 format %{ "" %}
5665 interface(COND_INTER) %{
5666 equal(0x4, "e");
5667 not_equal(0x5, "ne");
5668 less(0x2, "b");
5669 greater_equal(0x3, "nb");
5670 less_equal(0x6, "be");
5671 greater(0x7, "nbe");
5672 %}
5673 %}
5675 // Floating comparisons that don't require any fixup for the unordered case
5676 operand cmpOpUCF() %{
5677 match(Bool);
5678 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5679 n->as_Bool()->_test._test == BoolTest::ge ||
5680 n->as_Bool()->_test._test == BoolTest::le ||
5681 n->as_Bool()->_test._test == BoolTest::gt);
5682 format %{ "" %}
5683 interface(COND_INTER) %{
5684 equal(0x4, "e");
5685 not_equal(0x5, "ne");
5686 less(0x2, "b");
5687 greater_equal(0x3, "nb");
5688 less_equal(0x6, "be");
5689 greater(0x7, "nbe");
5690 %}
5691 %}
5694 // Floating comparisons that can be fixed up with extra conditional jumps
5695 operand cmpOpUCF2() %{
5696 match(Bool);
5697 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5698 n->as_Bool()->_test._test == BoolTest::eq);
5699 format %{ "" %}
5700 interface(COND_INTER) %{
5701 equal(0x4, "e");
5702 not_equal(0x5, "ne");
5703 less(0x2, "b");
5704 greater_equal(0x3, "nb");
5705 less_equal(0x6, "be");
5706 greater(0x7, "nbe");
5707 %}
5708 %}
5710 // Comparison Code for FP conditional move
5711 operand cmpOp_fcmov() %{
5712 match(Bool);
5714 format %{ "" %}
5715 interface(COND_INTER) %{
5716 equal (0x0C8);
5717 not_equal (0x1C8);
5718 less (0x0C0);
5719 greater_equal(0x1C0);
5720 less_equal (0x0D0);
5721 greater (0x1D0);
5722 %}
5723 %}
5725 // Comparision Code used in long compares
5726 operand cmpOp_commute() %{
5727 match(Bool);
5729 format %{ "" %}
5730 interface(COND_INTER) %{
5731 equal(0x4, "e");
5732 not_equal(0x5, "ne");
5733 less(0xF, "g");
5734 greater_equal(0xE, "le");
5735 less_equal(0xD, "ge");
5736 greater(0xC, "l");
5737 %}
5738 %}
5740 //----------OPERAND CLASSES----------------------------------------------------
5741 // Operand Classes are groups of operands that are used as to simplify
5742 // instruction definitions by not requiring the AD writer to specify separate
5743 // instructions for every form of operand when the instruction accepts
5744 // multiple operand types with the same basic encoding and format. The classic
5745 // case of this is memory operands.
5747 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5748 indIndex, indIndexScale, indIndexScaleOffset);
5750 // Long memory operations are encoded in 2 instructions and a +4 offset.
5751 // This means some kind of offset is always required and you cannot use
5752 // an oop as the offset (done when working on static globals).
5753 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5754 indIndex, indIndexScale, indIndexScaleOffset);
5757 //----------PIPELINE-----------------------------------------------------------
5758 // Rules which define the behavior of the target architectures pipeline.
5759 pipeline %{
5761 //----------ATTRIBUTES---------------------------------------------------------
5762 attributes %{
5763 variable_size_instructions; // Fixed size instructions
5764 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5765 instruction_unit_size = 1; // An instruction is 1 bytes long
5766 instruction_fetch_unit_size = 16; // The processor fetches one line
5767 instruction_fetch_units = 1; // of 16 bytes
5769 // List of nop instructions
5770 nops( MachNop );
5771 %}
5773 //----------RESOURCES----------------------------------------------------------
5774 // Resources are the functional units available to the machine
5776 // Generic P2/P3 pipeline
5777 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5778 // 3 instructions decoded per cycle.
5779 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5780 // 2 ALU op, only ALU0 handles mul/div instructions.
5781 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5782 MS0, MS1, MEM = MS0 | MS1,
5783 BR, FPU,
5784 ALU0, ALU1, ALU = ALU0 | ALU1 );
5786 //----------PIPELINE DESCRIPTION-----------------------------------------------
5787 // Pipeline Description specifies the stages in the machine's pipeline
5789 // Generic P2/P3 pipeline
5790 pipe_desc(S0, S1, S2, S3, S4, S5);
5792 //----------PIPELINE CLASSES---------------------------------------------------
5793 // Pipeline Classes describe the stages in which input and output are
5794 // referenced by the hardware pipeline.
5796 // Naming convention: ialu or fpu
5797 // Then: _reg
5798 // Then: _reg if there is a 2nd register
5799 // Then: _long if it's a pair of instructions implementing a long
5800 // Then: _fat if it requires the big decoder
5801 // Or: _mem if it requires the big decoder and a memory unit.
5803 // Integer ALU reg operation
5804 pipe_class ialu_reg(eRegI dst) %{
5805 single_instruction;
5806 dst : S4(write);
5807 dst : S3(read);
5808 DECODE : S0; // any decoder
5809 ALU : S3; // any alu
5810 %}
5812 // Long ALU reg operation
5813 pipe_class ialu_reg_long(eRegL dst) %{
5814 instruction_count(2);
5815 dst : S4(write);
5816 dst : S3(read);
5817 DECODE : S0(2); // any 2 decoders
5818 ALU : S3(2); // both alus
5819 %}
5821 // Integer ALU reg operation using big decoder
5822 pipe_class ialu_reg_fat(eRegI dst) %{
5823 single_instruction;
5824 dst : S4(write);
5825 dst : S3(read);
5826 D0 : S0; // big decoder only
5827 ALU : S3; // any alu
5828 %}
5830 // Long ALU reg operation using big decoder
5831 pipe_class ialu_reg_long_fat(eRegL dst) %{
5832 instruction_count(2);
5833 dst : S4(write);
5834 dst : S3(read);
5835 D0 : S0(2); // big decoder only; twice
5836 ALU : S3(2); // any 2 alus
5837 %}
5839 // Integer ALU reg-reg operation
5840 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
5841 single_instruction;
5842 dst : S4(write);
5843 src : S3(read);
5844 DECODE : S0; // any decoder
5845 ALU : S3; // any alu
5846 %}
5848 // Long ALU reg-reg operation
5849 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5850 instruction_count(2);
5851 dst : S4(write);
5852 src : S3(read);
5853 DECODE : S0(2); // any 2 decoders
5854 ALU : S3(2); // both alus
5855 %}
5857 // Integer ALU reg-reg operation
5858 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
5859 single_instruction;
5860 dst : S4(write);
5861 src : S3(read);
5862 D0 : S0; // big decoder only
5863 ALU : S3; // any alu
5864 %}
5866 // Long ALU reg-reg operation
5867 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5868 instruction_count(2);
5869 dst : S4(write);
5870 src : S3(read);
5871 D0 : S0(2); // big decoder only; twice
5872 ALU : S3(2); // both alus
5873 %}
5875 // Integer ALU reg-mem operation
5876 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
5877 single_instruction;
5878 dst : S5(write);
5879 mem : S3(read);
5880 D0 : S0; // big decoder only
5881 ALU : S4; // any alu
5882 MEM : S3; // any mem
5883 %}
5885 // Long ALU reg-mem operation
5886 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5887 instruction_count(2);
5888 dst : S5(write);
5889 mem : S3(read);
5890 D0 : S0(2); // big decoder only; twice
5891 ALU : S4(2); // any 2 alus
5892 MEM : S3(2); // both mems
5893 %}
5895 // Integer mem operation (prefetch)
5896 pipe_class ialu_mem(memory mem)
5897 %{
5898 single_instruction;
5899 mem : S3(read);
5900 D0 : S0; // big decoder only
5901 MEM : S3; // any mem
5902 %}
5904 // Integer Store to Memory
5905 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
5906 single_instruction;
5907 mem : S3(read);
5908 src : S5(read);
5909 D0 : S0; // big decoder only
5910 ALU : S4; // any alu
5911 MEM : S3;
5912 %}
5914 // Long Store to Memory
5915 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5916 instruction_count(2);
5917 mem : S3(read);
5918 src : S5(read);
5919 D0 : S0(2); // big decoder only; twice
5920 ALU : S4(2); // any 2 alus
5921 MEM : S3(2); // Both mems
5922 %}
5924 // Integer Store to Memory
5925 pipe_class ialu_mem_imm(memory mem) %{
5926 single_instruction;
5927 mem : S3(read);
5928 D0 : S0; // big decoder only
5929 ALU : S4; // any alu
5930 MEM : S3;
5931 %}
5933 // Integer ALU0 reg-reg operation
5934 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
5935 single_instruction;
5936 dst : S4(write);
5937 src : S3(read);
5938 D0 : S0; // Big decoder only
5939 ALU0 : S3; // only alu0
5940 %}
5942 // Integer ALU0 reg-mem operation
5943 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
5944 single_instruction;
5945 dst : S5(write);
5946 mem : S3(read);
5947 D0 : S0; // big decoder only
5948 ALU0 : S4; // ALU0 only
5949 MEM : S3; // any mem
5950 %}
5952 // Integer ALU reg-reg operation
5953 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
5954 single_instruction;
5955 cr : S4(write);
5956 src1 : S3(read);
5957 src2 : S3(read);
5958 DECODE : S0; // any decoder
5959 ALU : S3; // any alu
5960 %}
5962 // Integer ALU reg-imm operation
5963 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
5964 single_instruction;
5965 cr : S4(write);
5966 src1 : S3(read);
5967 DECODE : S0; // any decoder
5968 ALU : S3; // any alu
5969 %}
5971 // Integer ALU reg-mem operation
5972 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
5973 single_instruction;
5974 cr : S4(write);
5975 src1 : S3(read);
5976 src2 : S3(read);
5977 D0 : S0; // big decoder only
5978 ALU : S4; // any alu
5979 MEM : S3;
5980 %}
5982 // Conditional move reg-reg
5983 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
5984 instruction_count(4);
5985 y : S4(read);
5986 q : S3(read);
5987 p : S3(read);
5988 DECODE : S0(4); // any decoder
5989 %}
5991 // Conditional move reg-reg
5992 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
5993 single_instruction;
5994 dst : S4(write);
5995 src : S3(read);
5996 cr : S3(read);
5997 DECODE : S0; // any decoder
5998 %}
6000 // Conditional move reg-mem
6001 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
6002 single_instruction;
6003 dst : S4(write);
6004 src : S3(read);
6005 cr : S3(read);
6006 DECODE : S0; // any decoder
6007 MEM : S3;
6008 %}
6010 // Conditional move reg-reg long
6011 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
6012 single_instruction;
6013 dst : S4(write);
6014 src : S3(read);
6015 cr : S3(read);
6016 DECODE : S0(2); // any 2 decoders
6017 %}
6019 // Conditional move double reg-reg
6020 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
6021 single_instruction;
6022 dst : S4(write);
6023 src : S3(read);
6024 cr : S3(read);
6025 DECODE : S0; // any decoder
6026 %}
6028 // Float reg-reg operation
6029 pipe_class fpu_reg(regD dst) %{
6030 instruction_count(2);
6031 dst : S3(read);
6032 DECODE : S0(2); // any 2 decoders
6033 FPU : S3;
6034 %}
6036 // Float reg-reg operation
6037 pipe_class fpu_reg_reg(regD dst, regD src) %{
6038 instruction_count(2);
6039 dst : S4(write);
6040 src : S3(read);
6041 DECODE : S0(2); // any 2 decoders
6042 FPU : S3;
6043 %}
6045 // Float reg-reg operation
6046 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
6047 instruction_count(3);
6048 dst : S4(write);
6049 src1 : S3(read);
6050 src2 : S3(read);
6051 DECODE : S0(3); // any 3 decoders
6052 FPU : S3(2);
6053 %}
6055 // Float reg-reg operation
6056 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
6057 instruction_count(4);
6058 dst : S4(write);
6059 src1 : S3(read);
6060 src2 : S3(read);
6061 src3 : S3(read);
6062 DECODE : S0(4); // any 3 decoders
6063 FPU : S3(2);
6064 %}
6066 // Float reg-reg operation
6067 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
6068 instruction_count(4);
6069 dst : S4(write);
6070 src1 : S3(read);
6071 src2 : S3(read);
6072 src3 : S3(read);
6073 DECODE : S1(3); // any 3 decoders
6074 D0 : S0; // Big decoder only
6075 FPU : S3(2);
6076 MEM : S3;
6077 %}
6079 // Float reg-mem operation
6080 pipe_class fpu_reg_mem(regD dst, memory mem) %{
6081 instruction_count(2);
6082 dst : S5(write);
6083 mem : S3(read);
6084 D0 : S0; // big decoder only
6085 DECODE : S1; // any decoder for FPU POP
6086 FPU : S4;
6087 MEM : S3; // any mem
6088 %}
6090 // Float reg-mem operation
6091 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
6092 instruction_count(3);
6093 dst : S5(write);
6094 src1 : S3(read);
6095 mem : S3(read);
6096 D0 : S0; // big decoder only
6097 DECODE : S1(2); // any decoder for FPU POP
6098 FPU : S4;
6099 MEM : S3; // any mem
6100 %}
6102 // Float mem-reg operation
6103 pipe_class fpu_mem_reg(memory mem, regD src) %{
6104 instruction_count(2);
6105 src : S5(read);
6106 mem : S3(read);
6107 DECODE : S0; // any decoder for FPU PUSH
6108 D0 : S1; // big decoder only
6109 FPU : S4;
6110 MEM : S3; // any mem
6111 %}
6113 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
6114 instruction_count(3);
6115 src1 : S3(read);
6116 src2 : S3(read);
6117 mem : S3(read);
6118 DECODE : S0(2); // any decoder for FPU PUSH
6119 D0 : S1; // big decoder only
6120 FPU : S4;
6121 MEM : S3; // any mem
6122 %}
6124 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
6125 instruction_count(3);
6126 src1 : S3(read);
6127 src2 : S3(read);
6128 mem : S4(read);
6129 DECODE : S0; // any decoder for FPU PUSH
6130 D0 : S0(2); // big decoder only
6131 FPU : S4;
6132 MEM : S3(2); // any mem
6133 %}
6135 pipe_class fpu_mem_mem(memory dst, memory src1) %{
6136 instruction_count(2);
6137 src1 : S3(read);
6138 dst : S4(read);
6139 D0 : S0(2); // big decoder only
6140 MEM : S3(2); // any mem
6141 %}
6143 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
6144 instruction_count(3);
6145 src1 : S3(read);
6146 src2 : S3(read);
6147 dst : S4(read);
6148 D0 : S0(3); // big decoder only
6149 FPU : S4;
6150 MEM : S3(3); // any mem
6151 %}
6153 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
6154 instruction_count(3);
6155 src1 : S4(read);
6156 mem : S4(read);
6157 DECODE : S0; // any decoder for FPU PUSH
6158 D0 : S0(2); // big decoder only
6159 FPU : S4;
6160 MEM : S3(2); // any mem
6161 %}
6163 // Float load constant
6164 pipe_class fpu_reg_con(regD dst) %{
6165 instruction_count(2);
6166 dst : S5(write);
6167 D0 : S0; // big decoder only for the load
6168 DECODE : S1; // any decoder for FPU POP
6169 FPU : S4;
6170 MEM : S3; // any mem
6171 %}
6173 // Float load constant
6174 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
6175 instruction_count(3);
6176 dst : S5(write);
6177 src : S3(read);
6178 D0 : S0; // big decoder only for the load
6179 DECODE : S1(2); // any decoder for FPU POP
6180 FPU : S4;
6181 MEM : S3; // any mem
6182 %}
6184 // UnConditional branch
6185 pipe_class pipe_jmp( label labl ) %{
6186 single_instruction;
6187 BR : S3;
6188 %}
6190 // Conditional branch
6191 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
6192 single_instruction;
6193 cr : S1(read);
6194 BR : S3;
6195 %}
6197 // Allocation idiom
6198 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
6199 instruction_count(1); force_serialization;
6200 fixed_latency(6);
6201 heap_ptr : S3(read);
6202 DECODE : S0(3);
6203 D0 : S2;
6204 MEM : S3;
6205 ALU : S3(2);
6206 dst : S5(write);
6207 BR : S5;
6208 %}
6210 // Generic big/slow expanded idiom
6211 pipe_class pipe_slow( ) %{
6212 instruction_count(10); multiple_bundles; force_serialization;
6213 fixed_latency(100);
6214 D0 : S0(2);
6215 MEM : S3(2);
6216 %}
6218 // The real do-nothing guy
6219 pipe_class empty( ) %{
6220 instruction_count(0);
6221 %}
6223 // Define the class for the Nop node
6224 define %{
6225 MachNop = empty;
6226 %}
6228 %}
6230 //----------INSTRUCTIONS-------------------------------------------------------
6231 //
6232 // match -- States which machine-independent subtree may be replaced
6233 // by this instruction.
6234 // ins_cost -- The estimated cost of this instruction is used by instruction
6235 // selection to identify a minimum cost tree of machine
6236 // instructions that matches a tree of machine-independent
6237 // instructions.
6238 // format -- A string providing the disassembly for this instruction.
6239 // The value of an instruction's operand may be inserted
6240 // by referring to it with a '$' prefix.
6241 // opcode -- Three instruction opcodes may be provided. These are referred
6242 // to within an encode class as $primary, $secondary, and $tertiary
6243 // respectively. The primary opcode is commonly used to
6244 // indicate the type of machine instruction, while secondary
6245 // and tertiary are often used for prefix options or addressing
6246 // modes.
6247 // ins_encode -- A list of encode classes with parameters. The encode class
6248 // name must have been defined in an 'enc_class' specification
6249 // in the encode section of the architecture description.
6251 //----------BSWAP-Instruction--------------------------------------------------
6252 instruct bytes_reverse_int(eRegI dst) %{
6253 match(Set dst (ReverseBytesI dst));
6255 format %{ "BSWAP $dst" %}
6256 opcode(0x0F, 0xC8);
6257 ins_encode( OpcP, OpcSReg(dst) );
6258 ins_pipe( ialu_reg );
6259 %}
6261 instruct bytes_reverse_long(eRegL dst) %{
6262 match(Set dst (ReverseBytesL dst));
6264 format %{ "BSWAP $dst.lo\n\t"
6265 "BSWAP $dst.hi\n\t"
6266 "XCHG $dst.lo $dst.hi" %}
6268 ins_cost(125);
6269 ins_encode( bswap_long_bytes(dst) );
6270 ins_pipe( ialu_reg_reg);
6271 %}
6274 //---------- Zeros Count Instructions ------------------------------------------
6276 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6277 predicate(UseCountLeadingZerosInstruction);
6278 match(Set dst (CountLeadingZerosI src));
6279 effect(KILL cr);
6281 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
6282 ins_encode %{
6283 __ lzcntl($dst$$Register, $src$$Register);
6284 %}
6285 ins_pipe(ialu_reg);
6286 %}
6288 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
6289 predicate(!UseCountLeadingZerosInstruction);
6290 match(Set dst (CountLeadingZerosI src));
6291 effect(KILL cr);
6293 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
6294 "JNZ skip\n\t"
6295 "MOV $dst, -1\n"
6296 "skip:\n\t"
6297 "NEG $dst\n\t"
6298 "ADD $dst, 31" %}
6299 ins_encode %{
6300 Register Rdst = $dst$$Register;
6301 Register Rsrc = $src$$Register;
6302 Label skip;
6303 __ bsrl(Rdst, Rsrc);
6304 __ jccb(Assembler::notZero, skip);
6305 __ movl(Rdst, -1);
6306 __ bind(skip);
6307 __ negl(Rdst);
6308 __ addl(Rdst, BitsPerInt - 1);
6309 %}
6310 ins_pipe(ialu_reg);
6311 %}
6313 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6314 predicate(UseCountLeadingZerosInstruction);
6315 match(Set dst (CountLeadingZerosL src));
6316 effect(TEMP dst, KILL cr);
6318 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
6319 "JNC done\n\t"
6320 "LZCNT $dst, $src.lo\n\t"
6321 "ADD $dst, 32\n"
6322 "done:" %}
6323 ins_encode %{
6324 Register Rdst = $dst$$Register;
6325 Register Rsrc = $src$$Register;
6326 Label done;
6327 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
6328 __ jccb(Assembler::carryClear, done);
6329 __ lzcntl(Rdst, Rsrc);
6330 __ addl(Rdst, BitsPerInt);
6331 __ bind(done);
6332 %}
6333 ins_pipe(ialu_reg);
6334 %}
6336 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
6337 predicate(!UseCountLeadingZerosInstruction);
6338 match(Set dst (CountLeadingZerosL src));
6339 effect(TEMP dst, KILL cr);
6341 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
6342 "JZ msw_is_zero\n\t"
6343 "ADD $dst, 32\n\t"
6344 "JMP not_zero\n"
6345 "msw_is_zero:\n\t"
6346 "BSR $dst, $src.lo\n\t"
6347 "JNZ not_zero\n\t"
6348 "MOV $dst, -1\n"
6349 "not_zero:\n\t"
6350 "NEG $dst\n\t"
6351 "ADD $dst, 63\n" %}
6352 ins_encode %{
6353 Register Rdst = $dst$$Register;
6354 Register Rsrc = $src$$Register;
6355 Label msw_is_zero;
6356 Label not_zero;
6357 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
6358 __ jccb(Assembler::zero, msw_is_zero);
6359 __ addl(Rdst, BitsPerInt);
6360 __ jmpb(not_zero);
6361 __ bind(msw_is_zero);
6362 __ bsrl(Rdst, Rsrc);
6363 __ jccb(Assembler::notZero, not_zero);
6364 __ movl(Rdst, -1);
6365 __ bind(not_zero);
6366 __ negl(Rdst);
6367 __ addl(Rdst, BitsPerLong - 1);
6368 %}
6369 ins_pipe(ialu_reg);
6370 %}
6372 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6373 match(Set dst (CountTrailingZerosI src));
6374 effect(KILL cr);
6376 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
6377 "JNZ done\n\t"
6378 "MOV $dst, 32\n"
6379 "done:" %}
6380 ins_encode %{
6381 Register Rdst = $dst$$Register;
6382 Label done;
6383 __ bsfl(Rdst, $src$$Register);
6384 __ jccb(Assembler::notZero, done);
6385 __ movl(Rdst, BitsPerInt);
6386 __ bind(done);
6387 %}
6388 ins_pipe(ialu_reg);
6389 %}
6391 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6392 match(Set dst (CountTrailingZerosL src));
6393 effect(TEMP dst, KILL cr);
6395 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
6396 "JNZ done\n\t"
6397 "BSF $dst, $src.hi\n\t"
6398 "JNZ msw_not_zero\n\t"
6399 "MOV $dst, 32\n"
6400 "msw_not_zero:\n\t"
6401 "ADD $dst, 32\n"
6402 "done:" %}
6403 ins_encode %{
6404 Register Rdst = $dst$$Register;
6405 Register Rsrc = $src$$Register;
6406 Label msw_not_zero;
6407 Label done;
6408 __ bsfl(Rdst, Rsrc);
6409 __ jccb(Assembler::notZero, done);
6410 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
6411 __ jccb(Assembler::notZero, msw_not_zero);
6412 __ movl(Rdst, BitsPerInt);
6413 __ bind(msw_not_zero);
6414 __ addl(Rdst, BitsPerInt);
6415 __ bind(done);
6416 %}
6417 ins_pipe(ialu_reg);
6418 %}
6421 //---------- Population Count Instructions -------------------------------------
6423 instruct popCountI(eRegI dst, eRegI src) %{
6424 predicate(UsePopCountInstruction);
6425 match(Set dst (PopCountI src));
6427 format %{ "POPCNT $dst, $src" %}
6428 ins_encode %{
6429 __ popcntl($dst$$Register, $src$$Register);
6430 %}
6431 ins_pipe(ialu_reg);
6432 %}
6434 instruct popCountI_mem(eRegI dst, memory mem) %{
6435 predicate(UsePopCountInstruction);
6436 match(Set dst (PopCountI (LoadI mem)));
6438 format %{ "POPCNT $dst, $mem" %}
6439 ins_encode %{
6440 __ popcntl($dst$$Register, $mem$$Address);
6441 %}
6442 ins_pipe(ialu_reg);
6443 %}
6445 // Note: Long.bitCount(long) returns an int.
6446 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
6447 predicate(UsePopCountInstruction);
6448 match(Set dst (PopCountL src));
6449 effect(KILL cr, TEMP tmp, TEMP dst);
6451 format %{ "POPCNT $dst, $src.lo\n\t"
6452 "POPCNT $tmp, $src.hi\n\t"
6453 "ADD $dst, $tmp" %}
6454 ins_encode %{
6455 __ popcntl($dst$$Register, $src$$Register);
6456 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
6457 __ addl($dst$$Register, $tmp$$Register);
6458 %}
6459 ins_pipe(ialu_reg);
6460 %}
6462 // Note: Long.bitCount(long) returns an int.
6463 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
6464 predicate(UsePopCountInstruction);
6465 match(Set dst (PopCountL (LoadL mem)));
6466 effect(KILL cr, TEMP tmp, TEMP dst);
6468 format %{ "POPCNT $dst, $mem\n\t"
6469 "POPCNT $tmp, $mem+4\n\t"
6470 "ADD $dst, $tmp" %}
6471 ins_encode %{
6472 //__ popcntl($dst$$Register, $mem$$Address$$first);
6473 //__ popcntl($tmp$$Register, $mem$$Address$$second);
6474 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
6475 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
6476 __ addl($dst$$Register, $tmp$$Register);
6477 %}
6478 ins_pipe(ialu_reg);
6479 %}
6482 //----------Load/Store/Move Instructions---------------------------------------
6483 //----------Load Instructions--------------------------------------------------
6484 // Load Byte (8bit signed)
6485 instruct loadB(xRegI dst, memory mem) %{
6486 match(Set dst (LoadB mem));
6488 ins_cost(125);
6489 format %{ "MOVSX8 $dst,$mem\t# byte" %}
6491 ins_encode %{
6492 __ movsbl($dst$$Register, $mem$$Address);
6493 %}
6495 ins_pipe(ialu_reg_mem);
6496 %}
6498 // Load Byte (8bit signed) into Long Register
6499 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6500 match(Set dst (ConvI2L (LoadB mem)));
6501 effect(KILL cr);
6503 ins_cost(375);
6504 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
6505 "MOV $dst.hi,$dst.lo\n\t"
6506 "SAR $dst.hi,7" %}
6508 ins_encode %{
6509 __ movsbl($dst$$Register, $mem$$Address);
6510 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6511 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
6512 %}
6514 ins_pipe(ialu_reg_mem);
6515 %}
6517 // Load Unsigned Byte (8bit UNsigned)
6518 instruct loadUB(xRegI dst, memory mem) %{
6519 match(Set dst (LoadUB mem));
6521 ins_cost(125);
6522 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
6524 ins_encode %{
6525 __ movzbl($dst$$Register, $mem$$Address);
6526 %}
6528 ins_pipe(ialu_reg_mem);
6529 %}
6531 // Load Unsigned Byte (8 bit UNsigned) into Long Register
6532 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6533 match(Set dst (ConvI2L (LoadUB mem)));
6534 effect(KILL cr);
6536 ins_cost(250);
6537 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
6538 "XOR $dst.hi,$dst.hi" %}
6540 ins_encode %{
6541 Register Rdst = $dst$$Register;
6542 __ movzbl(Rdst, $mem$$Address);
6543 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6544 %}
6546 ins_pipe(ialu_reg_mem);
6547 %}
6549 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
6550 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
6551 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
6552 effect(KILL cr);
6554 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
6555 "XOR $dst.hi,$dst.hi\n\t"
6556 "AND $dst.lo,$mask" %}
6557 ins_encode %{
6558 Register Rdst = $dst$$Register;
6559 __ movzbl(Rdst, $mem$$Address);
6560 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6561 __ andl(Rdst, $mask$$constant);
6562 %}
6563 ins_pipe(ialu_reg_mem);
6564 %}
6566 // Load Short (16bit signed)
6567 instruct loadS(eRegI dst, memory mem) %{
6568 match(Set dst (LoadS mem));
6570 ins_cost(125);
6571 format %{ "MOVSX $dst,$mem\t# short" %}
6573 ins_encode %{
6574 __ movswl($dst$$Register, $mem$$Address);
6575 %}
6577 ins_pipe(ialu_reg_mem);
6578 %}
6580 // Load Short (16 bit signed) to Byte (8 bit signed)
6581 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6582 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
6584 ins_cost(125);
6585 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
6586 ins_encode %{
6587 __ movsbl($dst$$Register, $mem$$Address);
6588 %}
6589 ins_pipe(ialu_reg_mem);
6590 %}
6592 // Load Short (16bit signed) into Long Register
6593 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6594 match(Set dst (ConvI2L (LoadS mem)));
6595 effect(KILL cr);
6597 ins_cost(375);
6598 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
6599 "MOV $dst.hi,$dst.lo\n\t"
6600 "SAR $dst.hi,15" %}
6602 ins_encode %{
6603 __ movswl($dst$$Register, $mem$$Address);
6604 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6605 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
6606 %}
6608 ins_pipe(ialu_reg_mem);
6609 %}
6611 // Load Unsigned Short/Char (16bit unsigned)
6612 instruct loadUS(eRegI dst, memory mem) %{
6613 match(Set dst (LoadUS mem));
6615 ins_cost(125);
6616 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
6618 ins_encode %{
6619 __ movzwl($dst$$Register, $mem$$Address);
6620 %}
6622 ins_pipe(ialu_reg_mem);
6623 %}
6625 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
6626 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6627 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
6629 ins_cost(125);
6630 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
6631 ins_encode %{
6632 __ movsbl($dst$$Register, $mem$$Address);
6633 %}
6634 ins_pipe(ialu_reg_mem);
6635 %}
6637 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6638 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6639 match(Set dst (ConvI2L (LoadUS mem)));
6640 effect(KILL cr);
6642 ins_cost(250);
6643 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6644 "XOR $dst.hi,$dst.hi" %}
6646 ins_encode %{
6647 __ movzwl($dst$$Register, $mem$$Address);
6648 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6649 %}
6651 ins_pipe(ialu_reg_mem);
6652 %}
6654 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
6655 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6656 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6657 effect(KILL cr);
6659 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6660 "XOR $dst.hi,$dst.hi" %}
6661 ins_encode %{
6662 Register Rdst = $dst$$Register;
6663 __ movzbl(Rdst, $mem$$Address);
6664 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6665 %}
6666 ins_pipe(ialu_reg_mem);
6667 %}
6669 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6670 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6671 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6672 effect(KILL cr);
6674 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6675 "XOR $dst.hi,$dst.hi\n\t"
6676 "AND $dst.lo,$mask" %}
6677 ins_encode %{
6678 Register Rdst = $dst$$Register;
6679 __ movzwl(Rdst, $mem$$Address);
6680 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6681 __ andl(Rdst, $mask$$constant);
6682 %}
6683 ins_pipe(ialu_reg_mem);
6684 %}
6686 // Load Integer
6687 instruct loadI(eRegI dst, memory mem) %{
6688 match(Set dst (LoadI mem));
6690 ins_cost(125);
6691 format %{ "MOV $dst,$mem\t# int" %}
6693 ins_encode %{
6694 __ movl($dst$$Register, $mem$$Address);
6695 %}
6697 ins_pipe(ialu_reg_mem);
6698 %}
6700 // Load Integer (32 bit signed) to Byte (8 bit signed)
6701 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6702 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6704 ins_cost(125);
6705 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6706 ins_encode %{
6707 __ movsbl($dst$$Register, $mem$$Address);
6708 %}
6709 ins_pipe(ialu_reg_mem);
6710 %}
6712 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6713 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{
6714 match(Set dst (AndI (LoadI mem) mask));
6716 ins_cost(125);
6717 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6718 ins_encode %{
6719 __ movzbl($dst$$Register, $mem$$Address);
6720 %}
6721 ins_pipe(ialu_reg_mem);
6722 %}
6724 // Load Integer (32 bit signed) to Short (16 bit signed)
6725 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{
6726 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6728 ins_cost(125);
6729 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6730 ins_encode %{
6731 __ movswl($dst$$Register, $mem$$Address);
6732 %}
6733 ins_pipe(ialu_reg_mem);
6734 %}
6736 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6737 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{
6738 match(Set dst (AndI (LoadI mem) mask));
6740 ins_cost(125);
6741 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6742 ins_encode %{
6743 __ movzwl($dst$$Register, $mem$$Address);
6744 %}
6745 ins_pipe(ialu_reg_mem);
6746 %}
6748 // Load Integer into Long Register
6749 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6750 match(Set dst (ConvI2L (LoadI mem)));
6751 effect(KILL cr);
6753 ins_cost(375);
6754 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6755 "MOV $dst.hi,$dst.lo\n\t"
6756 "SAR $dst.hi,31" %}
6758 ins_encode %{
6759 __ movl($dst$$Register, $mem$$Address);
6760 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6761 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6762 %}
6764 ins_pipe(ialu_reg_mem);
6765 %}
6767 // Load Integer with mask 0xFF into Long Register
6768 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6769 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6770 effect(KILL cr);
6772 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6773 "XOR $dst.hi,$dst.hi" %}
6774 ins_encode %{
6775 Register Rdst = $dst$$Register;
6776 __ movzbl(Rdst, $mem$$Address);
6777 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6778 %}
6779 ins_pipe(ialu_reg_mem);
6780 %}
6782 // Load Integer with mask 0xFFFF into Long Register
6783 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6784 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6785 effect(KILL cr);
6787 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6788 "XOR $dst.hi,$dst.hi" %}
6789 ins_encode %{
6790 Register Rdst = $dst$$Register;
6791 __ movzwl(Rdst, $mem$$Address);
6792 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6793 %}
6794 ins_pipe(ialu_reg_mem);
6795 %}
6797 // Load Integer with 32-bit mask into Long Register
6798 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6799 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6800 effect(KILL cr);
6802 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6803 "XOR $dst.hi,$dst.hi\n\t"
6804 "AND $dst.lo,$mask" %}
6805 ins_encode %{
6806 Register Rdst = $dst$$Register;
6807 __ movl(Rdst, $mem$$Address);
6808 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6809 __ andl(Rdst, $mask$$constant);
6810 %}
6811 ins_pipe(ialu_reg_mem);
6812 %}
6814 // Load Unsigned Integer into Long Register
6815 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6816 match(Set dst (LoadUI2L mem));
6817 effect(KILL cr);
6819 ins_cost(250);
6820 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6821 "XOR $dst.hi,$dst.hi" %}
6823 ins_encode %{
6824 __ movl($dst$$Register, $mem$$Address);
6825 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6826 %}
6828 ins_pipe(ialu_reg_mem);
6829 %}
6831 // Load Long. Cannot clobber address while loading, so restrict address
6832 // register to ESI
6833 instruct loadL(eRegL dst, load_long_memory mem) %{
6834 predicate(!((LoadLNode*)n)->require_atomic_access());
6835 match(Set dst (LoadL mem));
6837 ins_cost(250);
6838 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6839 "MOV $dst.hi,$mem+4" %}
6841 ins_encode %{
6842 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6843 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6844 __ movl($dst$$Register, Amemlo);
6845 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6846 %}
6848 ins_pipe(ialu_reg_long_mem);
6849 %}
6851 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6852 // then store it down to the stack and reload on the int
6853 // side.
6854 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6855 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6856 match(Set dst (LoadL mem));
6858 ins_cost(200);
6859 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6860 "FISTp $dst" %}
6861 ins_encode(enc_loadL_volatile(mem,dst));
6862 ins_pipe( fpu_reg_mem );
6863 %}
6865 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
6866 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6867 match(Set dst (LoadL mem));
6868 effect(TEMP tmp);
6869 ins_cost(180);
6870 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6871 "MOVSD $dst,$tmp" %}
6872 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
6873 ins_pipe( pipe_slow );
6874 %}
6876 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
6877 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6878 match(Set dst (LoadL mem));
6879 effect(TEMP tmp);
6880 ins_cost(160);
6881 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6882 "MOVD $dst.lo,$tmp\n\t"
6883 "PSRLQ $tmp,32\n\t"
6884 "MOVD $dst.hi,$tmp" %}
6885 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
6886 ins_pipe( pipe_slow );
6887 %}
6889 // Load Range
6890 instruct loadRange(eRegI dst, memory mem) %{
6891 match(Set dst (LoadRange mem));
6893 ins_cost(125);
6894 format %{ "MOV $dst,$mem" %}
6895 opcode(0x8B);
6896 ins_encode( OpcP, RegMem(dst,mem));
6897 ins_pipe( ialu_reg_mem );
6898 %}
6901 // Load Pointer
6902 instruct loadP(eRegP dst, memory mem) %{
6903 match(Set dst (LoadP mem));
6905 ins_cost(125);
6906 format %{ "MOV $dst,$mem" %}
6907 opcode(0x8B);
6908 ins_encode( OpcP, RegMem(dst,mem));
6909 ins_pipe( ialu_reg_mem );
6910 %}
6912 // Load Klass Pointer
6913 instruct loadKlass(eRegP dst, memory mem) %{
6914 match(Set dst (LoadKlass mem));
6916 ins_cost(125);
6917 format %{ "MOV $dst,$mem" %}
6918 opcode(0x8B);
6919 ins_encode( OpcP, RegMem(dst,mem));
6920 ins_pipe( ialu_reg_mem );
6921 %}
6923 // Load Double
6924 instruct loadD(regD dst, memory mem) %{
6925 predicate(UseSSE<=1);
6926 match(Set dst (LoadD mem));
6928 ins_cost(150);
6929 format %{ "FLD_D ST,$mem\n\t"
6930 "FSTP $dst" %}
6931 opcode(0xDD); /* DD /0 */
6932 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6933 Pop_Reg_D(dst) );
6934 ins_pipe( fpu_reg_mem );
6935 %}
6937 // Load Double to XMM
6938 instruct loadXD(regXD dst, memory mem) %{
6939 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6940 match(Set dst (LoadD mem));
6941 ins_cost(145);
6942 format %{ "MOVSD $dst,$mem" %}
6943 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6944 ins_pipe( pipe_slow );
6945 %}
6947 instruct loadXD_partial(regXD dst, memory mem) %{
6948 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6949 match(Set dst (LoadD mem));
6950 ins_cost(145);
6951 format %{ "MOVLPD $dst,$mem" %}
6952 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem));
6953 ins_pipe( pipe_slow );
6954 %}
6956 // Load to XMM register (single-precision floating point)
6957 // MOVSS instruction
6958 instruct loadX(regX dst, memory mem) %{
6959 predicate(UseSSE>=1);
6960 match(Set dst (LoadF mem));
6961 ins_cost(145);
6962 format %{ "MOVSS $dst,$mem" %}
6963 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6964 ins_pipe( pipe_slow );
6965 %}
6967 // Load Float
6968 instruct loadF(regF dst, memory mem) %{
6969 predicate(UseSSE==0);
6970 match(Set dst (LoadF mem));
6972 ins_cost(150);
6973 format %{ "FLD_S ST,$mem\n\t"
6974 "FSTP $dst" %}
6975 opcode(0xD9); /* D9 /0 */
6976 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6977 Pop_Reg_F(dst) );
6978 ins_pipe( fpu_reg_mem );
6979 %}
6981 // Load Aligned Packed Byte to XMM register
6982 instruct loadA8B(regXD dst, memory mem) %{
6983 predicate(UseSSE>=1);
6984 match(Set dst (Load8B mem));
6985 ins_cost(125);
6986 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6987 ins_encode( movq_ld(dst, mem));
6988 ins_pipe( pipe_slow );
6989 %}
6991 // Load Aligned Packed Short to XMM register
6992 instruct loadA4S(regXD dst, memory mem) %{
6993 predicate(UseSSE>=1);
6994 match(Set dst (Load4S mem));
6995 ins_cost(125);
6996 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6997 ins_encode( movq_ld(dst, mem));
6998 ins_pipe( pipe_slow );
6999 %}
7001 // Load Aligned Packed Char to XMM register
7002 instruct loadA4C(regXD dst, memory mem) %{
7003 predicate(UseSSE>=1);
7004 match(Set dst (Load4C mem));
7005 ins_cost(125);
7006 format %{ "MOVQ $dst,$mem\t! packed4C" %}
7007 ins_encode( movq_ld(dst, mem));
7008 ins_pipe( pipe_slow );
7009 %}
7011 // Load Aligned Packed Integer to XMM register
7012 instruct load2IU(regXD dst, memory mem) %{
7013 predicate(UseSSE>=1);
7014 match(Set dst (Load2I mem));
7015 ins_cost(125);
7016 format %{ "MOVQ $dst,$mem\t! packed2I" %}
7017 ins_encode( movq_ld(dst, mem));
7018 ins_pipe( pipe_slow );
7019 %}
7021 // Load Aligned Packed Single to XMM
7022 instruct loadA2F(regXD dst, memory mem) %{
7023 predicate(UseSSE>=1);
7024 match(Set dst (Load2F mem));
7025 ins_cost(145);
7026 format %{ "MOVQ $dst,$mem\t! packed2F" %}
7027 ins_encode( movq_ld(dst, mem));
7028 ins_pipe( pipe_slow );
7029 %}
7031 // Load Effective Address
7032 instruct leaP8(eRegP dst, indOffset8 mem) %{
7033 match(Set dst mem);
7035 ins_cost(110);
7036 format %{ "LEA $dst,$mem" %}
7037 opcode(0x8D);
7038 ins_encode( OpcP, RegMem(dst,mem));
7039 ins_pipe( ialu_reg_reg_fat );
7040 %}
7042 instruct leaP32(eRegP dst, indOffset32 mem) %{
7043 match(Set dst mem);
7045 ins_cost(110);
7046 format %{ "LEA $dst,$mem" %}
7047 opcode(0x8D);
7048 ins_encode( OpcP, RegMem(dst,mem));
7049 ins_pipe( ialu_reg_reg_fat );
7050 %}
7052 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
7053 match(Set dst mem);
7055 ins_cost(110);
7056 format %{ "LEA $dst,$mem" %}
7057 opcode(0x8D);
7058 ins_encode( OpcP, RegMem(dst,mem));
7059 ins_pipe( ialu_reg_reg_fat );
7060 %}
7062 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
7063 match(Set dst mem);
7065 ins_cost(110);
7066 format %{ "LEA $dst,$mem" %}
7067 opcode(0x8D);
7068 ins_encode( OpcP, RegMem(dst,mem));
7069 ins_pipe( ialu_reg_reg_fat );
7070 %}
7072 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
7073 match(Set dst mem);
7075 ins_cost(110);
7076 format %{ "LEA $dst,$mem" %}
7077 opcode(0x8D);
7078 ins_encode( OpcP, RegMem(dst,mem));
7079 ins_pipe( ialu_reg_reg_fat );
7080 %}
7082 // Load Constant
7083 instruct loadConI(eRegI dst, immI src) %{
7084 match(Set dst src);
7086 format %{ "MOV $dst,$src" %}
7087 ins_encode( LdImmI(dst, src) );
7088 ins_pipe( ialu_reg_fat );
7089 %}
7091 // Load Constant zero
7092 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
7093 match(Set dst src);
7094 effect(KILL cr);
7096 ins_cost(50);
7097 format %{ "XOR $dst,$dst" %}
7098 opcode(0x33); /* + rd */
7099 ins_encode( OpcP, RegReg( dst, dst ) );
7100 ins_pipe( ialu_reg );
7101 %}
7103 instruct loadConP(eRegP dst, immP src) %{
7104 match(Set dst src);
7106 format %{ "MOV $dst,$src" %}
7107 opcode(0xB8); /* + rd */
7108 ins_encode( LdImmP(dst, src) );
7109 ins_pipe( ialu_reg_fat );
7110 %}
7112 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
7113 match(Set dst src);
7114 effect(KILL cr);
7115 ins_cost(200);
7116 format %{ "MOV $dst.lo,$src.lo\n\t"
7117 "MOV $dst.hi,$src.hi" %}
7118 opcode(0xB8);
7119 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
7120 ins_pipe( ialu_reg_long_fat );
7121 %}
7123 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
7124 match(Set dst src);
7125 effect(KILL cr);
7126 ins_cost(150);
7127 format %{ "XOR $dst.lo,$dst.lo\n\t"
7128 "XOR $dst.hi,$dst.hi" %}
7129 opcode(0x33,0x33);
7130 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
7131 ins_pipe( ialu_reg_long );
7132 %}
7134 // The instruction usage is guarded by predicate in operand immF().
7135 instruct loadConF(regF dst, immF src) %{
7136 match(Set dst src);
7137 ins_cost(125);
7139 format %{ "FLD_S ST,$src\n\t"
7140 "FSTP $dst" %}
7141 opcode(0xD9, 0x00); /* D9 /0 */
7142 ins_encode(LdImmF(src), Pop_Reg_F(dst) );
7143 ins_pipe( fpu_reg_con );
7144 %}
7146 // The instruction usage is guarded by predicate in operand immXF().
7147 instruct loadConX(regX dst, immXF con) %{
7148 match(Set dst con);
7149 ins_cost(125);
7150 format %{ "MOVSS $dst,[$con]" %}
7151 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con));
7152 ins_pipe( pipe_slow );
7153 %}
7155 // The instruction usage is guarded by predicate in operand immXF0().
7156 instruct loadConX0(regX dst, immXF0 src) %{
7157 match(Set dst src);
7158 ins_cost(100);
7159 format %{ "XORPS $dst,$dst\t# float 0.0" %}
7160 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7161 ins_pipe( pipe_slow );
7162 %}
7164 // The instruction usage is guarded by predicate in operand immD().
7165 instruct loadConD(regD dst, immD src) %{
7166 match(Set dst src);
7167 ins_cost(125);
7169 format %{ "FLD_D ST,$src\n\t"
7170 "FSTP $dst" %}
7171 ins_encode(LdImmD(src), Pop_Reg_D(dst) );
7172 ins_pipe( fpu_reg_con );
7173 %}
7175 // The instruction usage is guarded by predicate in operand immXD().
7176 instruct loadConXD(regXD dst, immXD con) %{
7177 match(Set dst con);
7178 ins_cost(125);
7179 format %{ "MOVSD $dst,[$con]" %}
7180 ins_encode(load_conXD(dst, con));
7181 ins_pipe( pipe_slow );
7182 %}
7184 // The instruction usage is guarded by predicate in operand immXD0().
7185 instruct loadConXD0(regXD dst, immXD0 src) %{
7186 match(Set dst src);
7187 ins_cost(100);
7188 format %{ "XORPD $dst,$dst\t# double 0.0" %}
7189 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7190 ins_pipe( pipe_slow );
7191 %}
7193 // Load Stack Slot
7194 instruct loadSSI(eRegI dst, stackSlotI src) %{
7195 match(Set dst src);
7196 ins_cost(125);
7198 format %{ "MOV $dst,$src" %}
7199 opcode(0x8B);
7200 ins_encode( OpcP, RegMem(dst,src));
7201 ins_pipe( ialu_reg_mem );
7202 %}
7204 instruct loadSSL(eRegL dst, stackSlotL src) %{
7205 match(Set dst src);
7207 ins_cost(200);
7208 format %{ "MOV $dst,$src.lo\n\t"
7209 "MOV $dst+4,$src.hi" %}
7210 opcode(0x8B, 0x8B);
7211 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
7212 ins_pipe( ialu_mem_long_reg );
7213 %}
7215 // Load Stack Slot
7216 instruct loadSSP(eRegP dst, stackSlotP src) %{
7217 match(Set dst src);
7218 ins_cost(125);
7220 format %{ "MOV $dst,$src" %}
7221 opcode(0x8B);
7222 ins_encode( OpcP, RegMem(dst,src));
7223 ins_pipe( ialu_reg_mem );
7224 %}
7226 // Load Stack Slot
7227 instruct loadSSF(regF dst, stackSlotF src) %{
7228 match(Set dst src);
7229 ins_cost(125);
7231 format %{ "FLD_S $src\n\t"
7232 "FSTP $dst" %}
7233 opcode(0xD9); /* D9 /0, FLD m32real */
7234 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7235 Pop_Reg_F(dst) );
7236 ins_pipe( fpu_reg_mem );
7237 %}
7239 // Load Stack Slot
7240 instruct loadSSD(regD dst, stackSlotD src) %{
7241 match(Set dst src);
7242 ins_cost(125);
7244 format %{ "FLD_D $src\n\t"
7245 "FSTP $dst" %}
7246 opcode(0xDD); /* DD /0, FLD m64real */
7247 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7248 Pop_Reg_D(dst) );
7249 ins_pipe( fpu_reg_mem );
7250 %}
7252 // Prefetch instructions.
7253 // Must be safe to execute with invalid address (cannot fault).
7255 instruct prefetchr0( memory mem ) %{
7256 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7257 match(PrefetchRead mem);
7258 ins_cost(0);
7259 size(0);
7260 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
7261 ins_encode();
7262 ins_pipe(empty);
7263 %}
7265 instruct prefetchr( memory mem ) %{
7266 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3);
7267 match(PrefetchRead mem);
7268 ins_cost(100);
7270 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7271 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
7272 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7273 ins_pipe(ialu_mem);
7274 %}
7276 instruct prefetchrNTA( memory mem ) %{
7277 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
7278 match(PrefetchRead mem);
7279 ins_cost(100);
7281 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
7282 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7283 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7284 ins_pipe(ialu_mem);
7285 %}
7287 instruct prefetchrT0( memory mem ) %{
7288 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
7289 match(PrefetchRead mem);
7290 ins_cost(100);
7292 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
7293 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7294 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7295 ins_pipe(ialu_mem);
7296 %}
7298 instruct prefetchrT2( memory mem ) %{
7299 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
7300 match(PrefetchRead mem);
7301 ins_cost(100);
7303 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
7304 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7305 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7306 ins_pipe(ialu_mem);
7307 %}
7309 instruct prefetchw0( memory mem ) %{
7310 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7311 match(PrefetchWrite mem);
7312 ins_cost(0);
7313 size(0);
7314 format %{ "Prefetch (non-SSE is empty encoding)" %}
7315 ins_encode();
7316 ins_pipe(empty);
7317 %}
7319 instruct prefetchw( memory mem ) %{
7320 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3);
7321 match( PrefetchWrite mem );
7322 ins_cost(100);
7324 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7325 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
7326 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7327 ins_pipe(ialu_mem);
7328 %}
7330 instruct prefetchwNTA( memory mem ) %{
7331 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
7332 match(PrefetchWrite mem);
7333 ins_cost(100);
7335 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
7336 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7337 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7338 ins_pipe(ialu_mem);
7339 %}
7341 instruct prefetchwT0( memory mem ) %{
7342 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
7343 match(PrefetchWrite mem);
7344 ins_cost(100);
7346 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %}
7347 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7348 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7349 ins_pipe(ialu_mem);
7350 %}
7352 instruct prefetchwT2( memory mem ) %{
7353 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
7354 match(PrefetchWrite mem);
7355 ins_cost(100);
7357 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %}
7358 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7359 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7360 ins_pipe(ialu_mem);
7361 %}
7363 //----------Store Instructions-------------------------------------------------
7365 // Store Byte
7366 instruct storeB(memory mem, xRegI src) %{
7367 match(Set mem (StoreB mem src));
7369 ins_cost(125);
7370 format %{ "MOV8 $mem,$src" %}
7371 opcode(0x88);
7372 ins_encode( OpcP, RegMem( src, mem ) );
7373 ins_pipe( ialu_mem_reg );
7374 %}
7376 // Store Char/Short
7377 instruct storeC(memory mem, eRegI src) %{
7378 match(Set mem (StoreC mem src));
7380 ins_cost(125);
7381 format %{ "MOV16 $mem,$src" %}
7382 opcode(0x89, 0x66);
7383 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
7384 ins_pipe( ialu_mem_reg );
7385 %}
7387 // Store Integer
7388 instruct storeI(memory mem, eRegI src) %{
7389 match(Set mem (StoreI mem src));
7391 ins_cost(125);
7392 format %{ "MOV $mem,$src" %}
7393 opcode(0x89);
7394 ins_encode( OpcP, RegMem( src, mem ) );
7395 ins_pipe( ialu_mem_reg );
7396 %}
7398 // Store Long
7399 instruct storeL(long_memory mem, eRegL src) %{
7400 predicate(!((StoreLNode*)n)->require_atomic_access());
7401 match(Set mem (StoreL mem src));
7403 ins_cost(200);
7404 format %{ "MOV $mem,$src.lo\n\t"
7405 "MOV $mem+4,$src.hi" %}
7406 opcode(0x89, 0x89);
7407 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
7408 ins_pipe( ialu_mem_long_reg );
7409 %}
7411 // Store Long to Integer
7412 instruct storeL2I(memory mem, eRegL src) %{
7413 match(Set mem (StoreI mem (ConvL2I src)));
7415 format %{ "MOV $mem,$src.lo\t# long -> int" %}
7416 ins_encode %{
7417 __ movl($mem$$Address, $src$$Register);
7418 %}
7419 ins_pipe(ialu_mem_reg);
7420 %}
7422 // Volatile Store Long. Must be atomic, so move it into
7423 // the FP TOS and then do a 64-bit FIST. Has to probe the
7424 // target address before the store (for null-ptr checks)
7425 // so the memory operand is used twice in the encoding.
7426 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
7427 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
7428 match(Set mem (StoreL mem src));
7429 effect( KILL cr );
7430 ins_cost(400);
7431 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7432 "FILD $src\n\t"
7433 "FISTp $mem\t # 64-bit atomic volatile long store" %}
7434 opcode(0x3B);
7435 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
7436 ins_pipe( fpu_reg_mem );
7437 %}
7439 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
7440 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7441 match(Set mem (StoreL mem src));
7442 effect( TEMP tmp, KILL cr );
7443 ins_cost(380);
7444 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7445 "MOVSD $tmp,$src\n\t"
7446 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7447 opcode(0x3B);
7448 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp));
7449 ins_pipe( pipe_slow );
7450 %}
7452 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
7453 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7454 match(Set mem (StoreL mem src));
7455 effect( TEMP tmp2 , TEMP tmp, KILL cr );
7456 ins_cost(360);
7457 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7458 "MOVD $tmp,$src.lo\n\t"
7459 "MOVD $tmp2,$src.hi\n\t"
7460 "PUNPCKLDQ $tmp,$tmp2\n\t"
7461 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7462 opcode(0x3B);
7463 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2));
7464 ins_pipe( pipe_slow );
7465 %}
7467 // Store Pointer; for storing unknown oops and raw pointers
7468 instruct storeP(memory mem, anyRegP src) %{
7469 match(Set mem (StoreP mem src));
7471 ins_cost(125);
7472 format %{ "MOV $mem,$src" %}
7473 opcode(0x89);
7474 ins_encode( OpcP, RegMem( src, mem ) );
7475 ins_pipe( ialu_mem_reg );
7476 %}
7478 // Store Integer Immediate
7479 instruct storeImmI(memory mem, immI src) %{
7480 match(Set mem (StoreI mem src));
7482 ins_cost(150);
7483 format %{ "MOV $mem,$src" %}
7484 opcode(0xC7); /* C7 /0 */
7485 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7486 ins_pipe( ialu_mem_imm );
7487 %}
7489 // Store Short/Char Immediate
7490 instruct storeImmI16(memory mem, immI16 src) %{
7491 predicate(UseStoreImmI16);
7492 match(Set mem (StoreC mem src));
7494 ins_cost(150);
7495 format %{ "MOV16 $mem,$src" %}
7496 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7497 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7498 ins_pipe( ialu_mem_imm );
7499 %}
7501 // Store Pointer Immediate; null pointers or constant oops that do not
7502 // need card-mark barriers.
7503 instruct storeImmP(memory mem, immP src) %{
7504 match(Set mem (StoreP mem src));
7506 ins_cost(150);
7507 format %{ "MOV $mem,$src" %}
7508 opcode(0xC7); /* C7 /0 */
7509 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7510 ins_pipe( ialu_mem_imm );
7511 %}
7513 // Store Byte Immediate
7514 instruct storeImmB(memory mem, immI8 src) %{
7515 match(Set mem (StoreB mem src));
7517 ins_cost(150);
7518 format %{ "MOV8 $mem,$src" %}
7519 opcode(0xC6); /* C6 /0 */
7520 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7521 ins_pipe( ialu_mem_imm );
7522 %}
7524 // Store Aligned Packed Byte XMM register to memory
7525 instruct storeA8B(memory mem, regXD src) %{
7526 predicate(UseSSE>=1);
7527 match(Set mem (Store8B mem src));
7528 ins_cost(145);
7529 format %{ "MOVQ $mem,$src\t! packed8B" %}
7530 ins_encode( movq_st(mem, src));
7531 ins_pipe( pipe_slow );
7532 %}
7534 // Store Aligned Packed Char/Short XMM register to memory
7535 instruct storeA4C(memory mem, regXD src) %{
7536 predicate(UseSSE>=1);
7537 match(Set mem (Store4C mem src));
7538 ins_cost(145);
7539 format %{ "MOVQ $mem,$src\t! packed4C" %}
7540 ins_encode( movq_st(mem, src));
7541 ins_pipe( pipe_slow );
7542 %}
7544 // Store Aligned Packed Integer XMM register to memory
7545 instruct storeA2I(memory mem, regXD src) %{
7546 predicate(UseSSE>=1);
7547 match(Set mem (Store2I mem src));
7548 ins_cost(145);
7549 format %{ "MOVQ $mem,$src\t! packed2I" %}
7550 ins_encode( movq_st(mem, src));
7551 ins_pipe( pipe_slow );
7552 %}
7554 // Store CMS card-mark Immediate
7555 instruct storeImmCM(memory mem, immI8 src) %{
7556 match(Set mem (StoreCM mem src));
7558 ins_cost(150);
7559 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7560 opcode(0xC6); /* C6 /0 */
7561 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7562 ins_pipe( ialu_mem_imm );
7563 %}
7565 // Store Double
7566 instruct storeD( memory mem, regDPR1 src) %{
7567 predicate(UseSSE<=1);
7568 match(Set mem (StoreD mem src));
7570 ins_cost(100);
7571 format %{ "FST_D $mem,$src" %}
7572 opcode(0xDD); /* DD /2 */
7573 ins_encode( enc_FP_store(mem,src) );
7574 ins_pipe( fpu_mem_reg );
7575 %}
7577 // Store double does rounding on x86
7578 instruct storeD_rounded( memory mem, regDPR1 src) %{
7579 predicate(UseSSE<=1);
7580 match(Set mem (StoreD mem (RoundDouble src)));
7582 ins_cost(100);
7583 format %{ "FST_D $mem,$src\t# round" %}
7584 opcode(0xDD); /* DD /2 */
7585 ins_encode( enc_FP_store(mem,src) );
7586 ins_pipe( fpu_mem_reg );
7587 %}
7589 // Store XMM register to memory (double-precision floating points)
7590 // MOVSD instruction
7591 instruct storeXD(memory mem, regXD src) %{
7592 predicate(UseSSE>=2);
7593 match(Set mem (StoreD mem src));
7594 ins_cost(95);
7595 format %{ "MOVSD $mem,$src" %}
7596 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7597 ins_pipe( pipe_slow );
7598 %}
7600 // Store XMM register to memory (single-precision floating point)
7601 // MOVSS instruction
7602 instruct storeX(memory mem, regX src) %{
7603 predicate(UseSSE>=1);
7604 match(Set mem (StoreF mem src));
7605 ins_cost(95);
7606 format %{ "MOVSS $mem,$src" %}
7607 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7608 ins_pipe( pipe_slow );
7609 %}
7611 // Store Aligned Packed Single Float XMM register to memory
7612 instruct storeA2F(memory mem, regXD src) %{
7613 predicate(UseSSE>=1);
7614 match(Set mem (Store2F mem src));
7615 ins_cost(145);
7616 format %{ "MOVQ $mem,$src\t! packed2F" %}
7617 ins_encode( movq_st(mem, src));
7618 ins_pipe( pipe_slow );
7619 %}
7621 // Store Float
7622 instruct storeF( memory mem, regFPR1 src) %{
7623 predicate(UseSSE==0);
7624 match(Set mem (StoreF mem src));
7626 ins_cost(100);
7627 format %{ "FST_S $mem,$src" %}
7628 opcode(0xD9); /* D9 /2 */
7629 ins_encode( enc_FP_store(mem,src) );
7630 ins_pipe( fpu_mem_reg );
7631 %}
7633 // Store Float does rounding on x86
7634 instruct storeF_rounded( memory mem, regFPR1 src) %{
7635 predicate(UseSSE==0);
7636 match(Set mem (StoreF mem (RoundFloat src)));
7638 ins_cost(100);
7639 format %{ "FST_S $mem,$src\t# round" %}
7640 opcode(0xD9); /* D9 /2 */
7641 ins_encode( enc_FP_store(mem,src) );
7642 ins_pipe( fpu_mem_reg );
7643 %}
7645 // Store Float does rounding on x86
7646 instruct storeF_Drounded( memory mem, regDPR1 src) %{
7647 predicate(UseSSE<=1);
7648 match(Set mem (StoreF mem (ConvD2F src)));
7650 ins_cost(100);
7651 format %{ "FST_S $mem,$src\t# D-round" %}
7652 opcode(0xD9); /* D9 /2 */
7653 ins_encode( enc_FP_store(mem,src) );
7654 ins_pipe( fpu_mem_reg );
7655 %}
7657 // Store immediate Float value (it is faster than store from FPU register)
7658 // The instruction usage is guarded by predicate in operand immF().
7659 instruct storeF_imm( memory mem, immF src) %{
7660 match(Set mem (StoreF mem src));
7662 ins_cost(50);
7663 format %{ "MOV $mem,$src\t# store float" %}
7664 opcode(0xC7); /* C7 /0 */
7665 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7666 ins_pipe( ialu_mem_imm );
7667 %}
7669 // Store immediate Float value (it is faster than store from XMM register)
7670 // The instruction usage is guarded by predicate in operand immXF().
7671 instruct storeX_imm( memory mem, immXF src) %{
7672 match(Set mem (StoreF mem src));
7674 ins_cost(50);
7675 format %{ "MOV $mem,$src\t# store float" %}
7676 opcode(0xC7); /* C7 /0 */
7677 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
7678 ins_pipe( ialu_mem_imm );
7679 %}
7681 // Store Integer to stack slot
7682 instruct storeSSI(stackSlotI dst, eRegI src) %{
7683 match(Set dst src);
7685 ins_cost(100);
7686 format %{ "MOV $dst,$src" %}
7687 opcode(0x89);
7688 ins_encode( OpcPRegSS( dst, src ) );
7689 ins_pipe( ialu_mem_reg );
7690 %}
7692 // Store Integer to stack slot
7693 instruct storeSSP(stackSlotP dst, eRegP src) %{
7694 match(Set dst src);
7696 ins_cost(100);
7697 format %{ "MOV $dst,$src" %}
7698 opcode(0x89);
7699 ins_encode( OpcPRegSS( dst, src ) );
7700 ins_pipe( ialu_mem_reg );
7701 %}
7703 // Store Long to stack slot
7704 instruct storeSSL(stackSlotL dst, eRegL src) %{
7705 match(Set dst src);
7707 ins_cost(200);
7708 format %{ "MOV $dst,$src.lo\n\t"
7709 "MOV $dst+4,$src.hi" %}
7710 opcode(0x89, 0x89);
7711 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7712 ins_pipe( ialu_mem_long_reg );
7713 %}
7715 //----------MemBar Instructions-----------------------------------------------
7716 // Memory barrier flavors
7718 instruct membar_acquire() %{
7719 match(MemBarAcquire);
7720 ins_cost(400);
7722 size(0);
7723 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7724 ins_encode();
7725 ins_pipe(empty);
7726 %}
7728 instruct membar_acquire_lock() %{
7729 match(MemBarAcquire);
7730 predicate(Matcher::prior_fast_lock(n));
7731 ins_cost(0);
7733 size(0);
7734 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7735 ins_encode( );
7736 ins_pipe(empty);
7737 %}
7739 instruct membar_release() %{
7740 match(MemBarRelease);
7741 ins_cost(400);
7743 size(0);
7744 format %{ "MEMBAR-release ! (empty encoding)" %}
7745 ins_encode( );
7746 ins_pipe(empty);
7747 %}
7749 instruct membar_release_lock() %{
7750 match(MemBarRelease);
7751 predicate(Matcher::post_fast_unlock(n));
7752 ins_cost(0);
7754 size(0);
7755 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7756 ins_encode( );
7757 ins_pipe(empty);
7758 %}
7760 instruct membar_volatile(eFlagsReg cr) %{
7761 match(MemBarVolatile);
7762 effect(KILL cr);
7763 ins_cost(400);
7765 format %{
7766 $$template
7767 if (os::is_MP()) {
7768 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7769 } else {
7770 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7771 }
7772 %}
7773 ins_encode %{
7774 __ membar(Assembler::StoreLoad);
7775 %}
7776 ins_pipe(pipe_slow);
7777 %}
7779 instruct unnecessary_membar_volatile() %{
7780 match(MemBarVolatile);
7781 predicate(Matcher::post_store_load_barrier(n));
7782 ins_cost(0);
7784 size(0);
7785 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7786 ins_encode( );
7787 ins_pipe(empty);
7788 %}
7790 //----------Move Instructions--------------------------------------------------
7791 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7792 match(Set dst (CastX2P src));
7793 format %{ "# X2P $dst, $src" %}
7794 ins_encode( /*empty encoding*/ );
7795 ins_cost(0);
7796 ins_pipe(empty);
7797 %}
7799 instruct castP2X(eRegI dst, eRegP src ) %{
7800 match(Set dst (CastP2X src));
7801 ins_cost(50);
7802 format %{ "MOV $dst, $src\t# CastP2X" %}
7803 ins_encode( enc_Copy( dst, src) );
7804 ins_pipe( ialu_reg_reg );
7805 %}
7807 //----------Conditional Move---------------------------------------------------
7808 // Conditional move
7809 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7810 predicate(VM_Version::supports_cmov() );
7811 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7812 ins_cost(200);
7813 format %{ "CMOV$cop $dst,$src" %}
7814 opcode(0x0F,0x40);
7815 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7816 ins_pipe( pipe_cmov_reg );
7817 %}
7819 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
7820 predicate(VM_Version::supports_cmov() );
7821 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7822 ins_cost(200);
7823 format %{ "CMOV$cop $dst,$src" %}
7824 opcode(0x0F,0x40);
7825 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7826 ins_pipe( pipe_cmov_reg );
7827 %}
7829 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
7830 predicate(VM_Version::supports_cmov() );
7831 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7832 ins_cost(200);
7833 expand %{
7834 cmovI_regU(cop, cr, dst, src);
7835 %}
7836 %}
7838 // Conditional move
7839 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7840 predicate(VM_Version::supports_cmov() );
7841 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7842 ins_cost(250);
7843 format %{ "CMOV$cop $dst,$src" %}
7844 opcode(0x0F,0x40);
7845 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7846 ins_pipe( pipe_cmov_mem );
7847 %}
7849 // Conditional move
7850 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7851 predicate(VM_Version::supports_cmov() );
7852 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7853 ins_cost(250);
7854 format %{ "CMOV$cop $dst,$src" %}
7855 opcode(0x0F,0x40);
7856 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7857 ins_pipe( pipe_cmov_mem );
7858 %}
7860 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
7861 predicate(VM_Version::supports_cmov() );
7862 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7863 ins_cost(250);
7864 expand %{
7865 cmovI_memU(cop, cr, dst, src);
7866 %}
7867 %}
7869 // Conditional move
7870 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7871 predicate(VM_Version::supports_cmov() );
7872 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7873 ins_cost(200);
7874 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7875 opcode(0x0F,0x40);
7876 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7877 ins_pipe( pipe_cmov_reg );
7878 %}
7880 // Conditional move (non-P6 version)
7881 // Note: a CMoveP is generated for stubs and native wrappers
7882 // regardless of whether we are on a P6, so we
7883 // emulate a cmov here
7884 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7885 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7886 ins_cost(300);
7887 format %{ "Jn$cop skip\n\t"
7888 "MOV $dst,$src\t# pointer\n"
7889 "skip:" %}
7890 opcode(0x8b);
7891 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7892 ins_pipe( pipe_cmov_reg );
7893 %}
7895 // Conditional move
7896 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7897 predicate(VM_Version::supports_cmov() );
7898 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7899 ins_cost(200);
7900 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7901 opcode(0x0F,0x40);
7902 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7903 ins_pipe( pipe_cmov_reg );
7904 %}
7906 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7907 predicate(VM_Version::supports_cmov() );
7908 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7909 ins_cost(200);
7910 expand %{
7911 cmovP_regU(cop, cr, dst, src);
7912 %}
7913 %}
7915 // DISABLED: Requires the ADLC to emit a bottom_type call that
7916 // correctly meets the two pointer arguments; one is an incoming
7917 // register but the other is a memory operand. ALSO appears to
7918 // be buggy with implicit null checks.
7919 //
7920 //// Conditional move
7921 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7922 // predicate(VM_Version::supports_cmov() );
7923 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7924 // ins_cost(250);
7925 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7926 // opcode(0x0F,0x40);
7927 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7928 // ins_pipe( pipe_cmov_mem );
7929 //%}
7930 //
7931 //// Conditional move
7932 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7933 // predicate(VM_Version::supports_cmov() );
7934 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7935 // ins_cost(250);
7936 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7937 // opcode(0x0F,0x40);
7938 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7939 // ins_pipe( pipe_cmov_mem );
7940 //%}
7942 // Conditional move
7943 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
7944 predicate(UseSSE<=1);
7945 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7946 ins_cost(200);
7947 format %{ "FCMOV$cop $dst,$src\t# double" %}
7948 opcode(0xDA);
7949 ins_encode( enc_cmov_d(cop,src) );
7950 ins_pipe( pipe_cmovD_reg );
7951 %}
7953 // Conditional move
7954 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
7955 predicate(UseSSE==0);
7956 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7957 ins_cost(200);
7958 format %{ "FCMOV$cop $dst,$src\t# float" %}
7959 opcode(0xDA);
7960 ins_encode( enc_cmov_d(cop,src) );
7961 ins_pipe( pipe_cmovD_reg );
7962 %}
7964 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7965 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7966 predicate(UseSSE<=1);
7967 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7968 ins_cost(200);
7969 format %{ "Jn$cop skip\n\t"
7970 "MOV $dst,$src\t# double\n"
7971 "skip:" %}
7972 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7973 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
7974 ins_pipe( pipe_cmovD_reg );
7975 %}
7977 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7978 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7979 predicate(UseSSE==0);
7980 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7981 ins_cost(200);
7982 format %{ "Jn$cop skip\n\t"
7983 "MOV $dst,$src\t# float\n"
7984 "skip:" %}
7985 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7986 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
7987 ins_pipe( pipe_cmovD_reg );
7988 %}
7990 // No CMOVE with SSE/SSE2
7991 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
7992 predicate (UseSSE>=1);
7993 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7994 ins_cost(200);
7995 format %{ "Jn$cop skip\n\t"
7996 "MOVSS $dst,$src\t# float\n"
7997 "skip:" %}
7998 ins_encode %{
7999 Label skip;
8000 // Invert sense of branch from sense of CMOV
8001 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8002 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8003 __ bind(skip);
8004 %}
8005 ins_pipe( pipe_slow );
8006 %}
8008 // No CMOVE with SSE/SSE2
8009 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
8010 predicate (UseSSE>=2);
8011 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8012 ins_cost(200);
8013 format %{ "Jn$cop skip\n\t"
8014 "MOVSD $dst,$src\t# float\n"
8015 "skip:" %}
8016 ins_encode %{
8017 Label skip;
8018 // Invert sense of branch from sense of CMOV
8019 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8020 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8021 __ bind(skip);
8022 %}
8023 ins_pipe( pipe_slow );
8024 %}
8026 // unsigned version
8027 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
8028 predicate (UseSSE>=1);
8029 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8030 ins_cost(200);
8031 format %{ "Jn$cop skip\n\t"
8032 "MOVSS $dst,$src\t# float\n"
8033 "skip:" %}
8034 ins_encode %{
8035 Label skip;
8036 // Invert sense of branch from sense of CMOV
8037 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8038 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8039 __ bind(skip);
8040 %}
8041 ins_pipe( pipe_slow );
8042 %}
8044 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{
8045 predicate (UseSSE>=1);
8046 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8047 ins_cost(200);
8048 expand %{
8049 fcmovX_regU(cop, cr, dst, src);
8050 %}
8051 %}
8053 // unsigned version
8054 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
8055 predicate (UseSSE>=2);
8056 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8057 ins_cost(200);
8058 format %{ "Jn$cop skip\n\t"
8059 "MOVSD $dst,$src\t# float\n"
8060 "skip:" %}
8061 ins_encode %{
8062 Label skip;
8063 // Invert sense of branch from sense of CMOV
8064 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8065 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8066 __ bind(skip);
8067 %}
8068 ins_pipe( pipe_slow );
8069 %}
8071 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{
8072 predicate (UseSSE>=2);
8073 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8074 ins_cost(200);
8075 expand %{
8076 fcmovXD_regU(cop, cr, dst, src);
8077 %}
8078 %}
8080 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
8081 predicate(VM_Version::supports_cmov() );
8082 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8083 ins_cost(200);
8084 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8085 "CMOV$cop $dst.hi,$src.hi" %}
8086 opcode(0x0F,0x40);
8087 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8088 ins_pipe( pipe_cmov_reg_long );
8089 %}
8091 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
8092 predicate(VM_Version::supports_cmov() );
8093 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8094 ins_cost(200);
8095 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8096 "CMOV$cop $dst.hi,$src.hi" %}
8097 opcode(0x0F,0x40);
8098 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8099 ins_pipe( pipe_cmov_reg_long );
8100 %}
8102 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
8103 predicate(VM_Version::supports_cmov() );
8104 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8105 ins_cost(200);
8106 expand %{
8107 cmovL_regU(cop, cr, dst, src);
8108 %}
8109 %}
8111 //----------Arithmetic Instructions--------------------------------------------
8112 //----------Addition Instructions----------------------------------------------
8113 // Integer Addition Instructions
8114 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8115 match(Set dst (AddI dst src));
8116 effect(KILL cr);
8118 size(2);
8119 format %{ "ADD $dst,$src" %}
8120 opcode(0x03);
8121 ins_encode( OpcP, RegReg( dst, src) );
8122 ins_pipe( ialu_reg_reg );
8123 %}
8125 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8126 match(Set dst (AddI dst src));
8127 effect(KILL cr);
8129 format %{ "ADD $dst,$src" %}
8130 opcode(0x81, 0x00); /* /0 id */
8131 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8132 ins_pipe( ialu_reg );
8133 %}
8135 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
8136 predicate(UseIncDec);
8137 match(Set dst (AddI dst src));
8138 effect(KILL cr);
8140 size(1);
8141 format %{ "INC $dst" %}
8142 opcode(0x40); /* */
8143 ins_encode( Opc_plus( primary, dst ) );
8144 ins_pipe( ialu_reg );
8145 %}
8147 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
8148 match(Set dst (AddI src0 src1));
8149 ins_cost(110);
8151 format %{ "LEA $dst,[$src0 + $src1]" %}
8152 opcode(0x8D); /* 0x8D /r */
8153 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8154 ins_pipe( ialu_reg_reg );
8155 %}
8157 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
8158 match(Set dst (AddP src0 src1));
8159 ins_cost(110);
8161 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
8162 opcode(0x8D); /* 0x8D /r */
8163 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8164 ins_pipe( ialu_reg_reg );
8165 %}
8167 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
8168 predicate(UseIncDec);
8169 match(Set dst (AddI dst src));
8170 effect(KILL cr);
8172 size(1);
8173 format %{ "DEC $dst" %}
8174 opcode(0x48); /* */
8175 ins_encode( Opc_plus( primary, dst ) );
8176 ins_pipe( ialu_reg );
8177 %}
8179 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
8180 match(Set dst (AddP dst src));
8181 effect(KILL cr);
8183 size(2);
8184 format %{ "ADD $dst,$src" %}
8185 opcode(0x03);
8186 ins_encode( OpcP, RegReg( dst, src) );
8187 ins_pipe( ialu_reg_reg );
8188 %}
8190 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
8191 match(Set dst (AddP dst src));
8192 effect(KILL cr);
8194 format %{ "ADD $dst,$src" %}
8195 opcode(0x81,0x00); /* Opcode 81 /0 id */
8196 // ins_encode( RegImm( dst, src) );
8197 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8198 ins_pipe( ialu_reg );
8199 %}
8201 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8202 match(Set dst (AddI dst (LoadI src)));
8203 effect(KILL cr);
8205 ins_cost(125);
8206 format %{ "ADD $dst,$src" %}
8207 opcode(0x03);
8208 ins_encode( OpcP, RegMem( dst, src) );
8209 ins_pipe( ialu_reg_mem );
8210 %}
8212 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8213 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8214 effect(KILL cr);
8216 ins_cost(150);
8217 format %{ "ADD $dst,$src" %}
8218 opcode(0x01); /* Opcode 01 /r */
8219 ins_encode( OpcP, RegMem( src, dst ) );
8220 ins_pipe( ialu_mem_reg );
8221 %}
8223 // Add Memory with Immediate
8224 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8225 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8226 effect(KILL cr);
8228 ins_cost(125);
8229 format %{ "ADD $dst,$src" %}
8230 opcode(0x81); /* Opcode 81 /0 id */
8231 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
8232 ins_pipe( ialu_mem_imm );
8233 %}
8235 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
8236 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8237 effect(KILL cr);
8239 ins_cost(125);
8240 format %{ "INC $dst" %}
8241 opcode(0xFF); /* Opcode FF /0 */
8242 ins_encode( OpcP, RMopc_Mem(0x00,dst));
8243 ins_pipe( ialu_mem_imm );
8244 %}
8246 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
8247 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8248 effect(KILL cr);
8250 ins_cost(125);
8251 format %{ "DEC $dst" %}
8252 opcode(0xFF); /* Opcode FF /1 */
8253 ins_encode( OpcP, RMopc_Mem(0x01,dst));
8254 ins_pipe( ialu_mem_imm );
8255 %}
8258 instruct checkCastPP( eRegP dst ) %{
8259 match(Set dst (CheckCastPP dst));
8261 size(0);
8262 format %{ "#checkcastPP of $dst" %}
8263 ins_encode( /*empty encoding*/ );
8264 ins_pipe( empty );
8265 %}
8267 instruct castPP( eRegP dst ) %{
8268 match(Set dst (CastPP dst));
8269 format %{ "#castPP of $dst" %}
8270 ins_encode( /*empty encoding*/ );
8271 ins_pipe( empty );
8272 %}
8274 instruct castII( eRegI dst ) %{
8275 match(Set dst (CastII dst));
8276 format %{ "#castII of $dst" %}
8277 ins_encode( /*empty encoding*/ );
8278 ins_cost(0);
8279 ins_pipe( empty );
8280 %}
8283 // Load-locked - same as a regular pointer load when used with compare-swap
8284 instruct loadPLocked(eRegP dst, memory mem) %{
8285 match(Set dst (LoadPLocked mem));
8287 ins_cost(125);
8288 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
8289 opcode(0x8B);
8290 ins_encode( OpcP, RegMem(dst,mem));
8291 ins_pipe( ialu_reg_mem );
8292 %}
8294 // LoadLong-locked - same as a volatile long load when used with compare-swap
8295 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{
8296 predicate(UseSSE<=1);
8297 match(Set dst (LoadLLocked mem));
8299 ins_cost(200);
8300 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
8301 "FISTp $dst" %}
8302 ins_encode(enc_loadL_volatile(mem,dst));
8303 ins_pipe( fpu_reg_mem );
8304 %}
8306 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{
8307 predicate(UseSSE>=2);
8308 match(Set dst (LoadLLocked mem));
8309 effect(TEMP tmp);
8310 ins_cost(180);
8311 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8312 "MOVSD $dst,$tmp" %}
8313 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
8314 ins_pipe( pipe_slow );
8315 %}
8317 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{
8318 predicate(UseSSE>=2);
8319 match(Set dst (LoadLLocked mem));
8320 effect(TEMP tmp);
8321 ins_cost(160);
8322 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8323 "MOVD $dst.lo,$tmp\n\t"
8324 "PSRLQ $tmp,32\n\t"
8325 "MOVD $dst.hi,$tmp" %}
8326 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
8327 ins_pipe( pipe_slow );
8328 %}
8330 // Conditional-store of the updated heap-top.
8331 // Used during allocation of the shared heap.
8332 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
8333 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
8334 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
8335 // EAX is killed if there is contention, but then it's also unused.
8336 // In the common case of no contention, EAX holds the new oop address.
8337 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
8338 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
8339 ins_pipe( pipe_cmpxchg );
8340 %}
8342 // Conditional-store of an int value.
8343 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
8344 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
8345 match(Set cr (StoreIConditional mem (Binary oldval newval)));
8346 effect(KILL oldval);
8347 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
8348 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
8349 ins_pipe( pipe_cmpxchg );
8350 %}
8352 // Conditional-store of a long value.
8353 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
8354 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8355 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8356 effect(KILL oldval);
8357 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
8358 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
8359 "XCHG EBX,ECX"
8360 %}
8361 ins_encode %{
8362 // Note: we need to swap rbx, and rcx before and after the
8363 // cmpxchg8 instruction because the instruction uses
8364 // rcx as the high order word of the new value to store but
8365 // our register encoding uses rbx.
8366 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8367 if( os::is_MP() )
8368 __ lock();
8369 __ cmpxchg8($mem$$Address);
8370 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8371 %}
8372 ins_pipe( pipe_cmpxchg );
8373 %}
8375 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8377 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8378 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8379 effect(KILL cr, KILL oldval);
8380 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8381 "MOV $res,0\n\t"
8382 "JNE,s fail\n\t"
8383 "MOV $res,1\n"
8384 "fail:" %}
8385 ins_encode( enc_cmpxchg8(mem_ptr),
8386 enc_flags_ne_to_boolean(res) );
8387 ins_pipe( pipe_cmpxchg );
8388 %}
8390 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
8391 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8392 effect(KILL cr, KILL oldval);
8393 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8394 "MOV $res,0\n\t"
8395 "JNE,s fail\n\t"
8396 "MOV $res,1\n"
8397 "fail:" %}
8398 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8399 ins_pipe( pipe_cmpxchg );
8400 %}
8402 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
8403 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8404 effect(KILL cr, KILL oldval);
8405 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8406 "MOV $res,0\n\t"
8407 "JNE,s fail\n\t"
8408 "MOV $res,1\n"
8409 "fail:" %}
8410 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8411 ins_pipe( pipe_cmpxchg );
8412 %}
8414 //----------Subtraction Instructions-------------------------------------------
8415 // Integer Subtraction Instructions
8416 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8417 match(Set dst (SubI dst src));
8418 effect(KILL cr);
8420 size(2);
8421 format %{ "SUB $dst,$src" %}
8422 opcode(0x2B);
8423 ins_encode( OpcP, RegReg( dst, src) );
8424 ins_pipe( ialu_reg_reg );
8425 %}
8427 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8428 match(Set dst (SubI dst src));
8429 effect(KILL cr);
8431 format %{ "SUB $dst,$src" %}
8432 opcode(0x81,0x05); /* Opcode 81 /5 */
8433 // ins_encode( RegImm( dst, src) );
8434 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8435 ins_pipe( ialu_reg );
8436 %}
8438 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8439 match(Set dst (SubI dst (LoadI src)));
8440 effect(KILL cr);
8442 ins_cost(125);
8443 format %{ "SUB $dst,$src" %}
8444 opcode(0x2B);
8445 ins_encode( OpcP, RegMem( dst, src) );
8446 ins_pipe( ialu_reg_mem );
8447 %}
8449 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8450 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8451 effect(KILL cr);
8453 ins_cost(150);
8454 format %{ "SUB $dst,$src" %}
8455 opcode(0x29); /* Opcode 29 /r */
8456 ins_encode( OpcP, RegMem( src, dst ) );
8457 ins_pipe( ialu_mem_reg );
8458 %}
8460 // Subtract from a pointer
8461 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
8462 match(Set dst (AddP dst (SubI zero src)));
8463 effect(KILL cr);
8465 size(2);
8466 format %{ "SUB $dst,$src" %}
8467 opcode(0x2B);
8468 ins_encode( OpcP, RegReg( dst, src) );
8469 ins_pipe( ialu_reg_reg );
8470 %}
8472 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
8473 match(Set dst (SubI zero dst));
8474 effect(KILL cr);
8476 size(2);
8477 format %{ "NEG $dst" %}
8478 opcode(0xF7,0x03); // Opcode F7 /3
8479 ins_encode( OpcP, RegOpc( dst ) );
8480 ins_pipe( ialu_reg );
8481 %}
8484 //----------Multiplication/Division Instructions-------------------------------
8485 // Integer Multiplication Instructions
8486 // Multiply Register
8487 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8488 match(Set dst (MulI dst src));
8489 effect(KILL cr);
8491 size(3);
8492 ins_cost(300);
8493 format %{ "IMUL $dst,$src" %}
8494 opcode(0xAF, 0x0F);
8495 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8496 ins_pipe( ialu_reg_reg_alu0 );
8497 %}
8499 // Multiply 32-bit Immediate
8500 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8501 match(Set dst (MulI src imm));
8502 effect(KILL cr);
8504 ins_cost(300);
8505 format %{ "IMUL $dst,$src,$imm" %}
8506 opcode(0x69); /* 69 /r id */
8507 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8508 ins_pipe( ialu_reg_reg_alu0 );
8509 %}
8511 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8512 match(Set dst src);
8513 effect(KILL cr);
8515 // Note that this is artificially increased to make it more expensive than loadConL
8516 ins_cost(250);
8517 format %{ "MOV EAX,$src\t// low word only" %}
8518 opcode(0xB8);
8519 ins_encode( LdImmL_Lo(dst, src) );
8520 ins_pipe( ialu_reg_fat );
8521 %}
8523 // Multiply by 32-bit Immediate, taking the shifted high order results
8524 // (special case for shift by 32)
8525 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8526 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8527 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8528 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8529 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8530 effect(USE src1, KILL cr);
8532 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8533 ins_cost(0*100 + 1*400 - 150);
8534 format %{ "IMUL EDX:EAX,$src1" %}
8535 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8536 ins_pipe( pipe_slow );
8537 %}
8539 // Multiply by 32-bit Immediate, taking the shifted high order results
8540 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8541 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8542 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8543 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8544 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8545 effect(USE src1, KILL cr);
8547 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8548 ins_cost(1*100 + 1*400 - 150);
8549 format %{ "IMUL EDX:EAX,$src1\n\t"
8550 "SAR EDX,$cnt-32" %}
8551 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8552 ins_pipe( pipe_slow );
8553 %}
8555 // Multiply Memory 32-bit Immediate
8556 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8557 match(Set dst (MulI (LoadI src) imm));
8558 effect(KILL cr);
8560 ins_cost(300);
8561 format %{ "IMUL $dst,$src,$imm" %}
8562 opcode(0x69); /* 69 /r id */
8563 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8564 ins_pipe( ialu_reg_mem_alu0 );
8565 %}
8567 // Multiply Memory
8568 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8569 match(Set dst (MulI dst (LoadI src)));
8570 effect(KILL cr);
8572 ins_cost(350);
8573 format %{ "IMUL $dst,$src" %}
8574 opcode(0xAF, 0x0F);
8575 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8576 ins_pipe( ialu_reg_mem_alu0 );
8577 %}
8579 // Multiply Register Int to Long
8580 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8581 // Basic Idea: long = (long)int * (long)int
8582 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8583 effect(DEF dst, USE src, USE src1, KILL flags);
8585 ins_cost(300);
8586 format %{ "IMUL $dst,$src1" %}
8588 ins_encode( long_int_multiply( dst, src1 ) );
8589 ins_pipe( ialu_reg_reg_alu0 );
8590 %}
8592 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8593 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8594 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8595 effect(KILL flags);
8597 ins_cost(300);
8598 format %{ "MUL $dst,$src1" %}
8600 ins_encode( long_uint_multiply(dst, src1) );
8601 ins_pipe( ialu_reg_reg_alu0 );
8602 %}
8604 // Multiply Register Long
8605 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8606 match(Set dst (MulL dst src));
8607 effect(KILL cr, TEMP tmp);
8608 ins_cost(4*100+3*400);
8609 // Basic idea: lo(result) = lo(x_lo * y_lo)
8610 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8611 format %{ "MOV $tmp,$src.lo\n\t"
8612 "IMUL $tmp,EDX\n\t"
8613 "MOV EDX,$src.hi\n\t"
8614 "IMUL EDX,EAX\n\t"
8615 "ADD $tmp,EDX\n\t"
8616 "MUL EDX:EAX,$src.lo\n\t"
8617 "ADD EDX,$tmp" %}
8618 ins_encode( long_multiply( dst, src, tmp ) );
8619 ins_pipe( pipe_slow );
8620 %}
8622 // Multiply Register Long where the left operand's high 32 bits are zero
8623 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8624 predicate(is_operand_hi32_zero(n->in(1)));
8625 match(Set dst (MulL dst src));
8626 effect(KILL cr, TEMP tmp);
8627 ins_cost(2*100+2*400);
8628 // Basic idea: lo(result) = lo(x_lo * y_lo)
8629 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8630 format %{ "MOV $tmp,$src.hi\n\t"
8631 "IMUL $tmp,EAX\n\t"
8632 "MUL EDX:EAX,$src.lo\n\t"
8633 "ADD EDX,$tmp" %}
8634 ins_encode %{
8635 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8636 __ imull($tmp$$Register, rax);
8637 __ mull($src$$Register);
8638 __ addl(rdx, $tmp$$Register);
8639 %}
8640 ins_pipe( pipe_slow );
8641 %}
8643 // Multiply Register Long where the right operand's high 32 bits are zero
8644 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8645 predicate(is_operand_hi32_zero(n->in(2)));
8646 match(Set dst (MulL dst src));
8647 effect(KILL cr, TEMP tmp);
8648 ins_cost(2*100+2*400);
8649 // Basic idea: lo(result) = lo(x_lo * y_lo)
8650 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8651 format %{ "MOV $tmp,$src.lo\n\t"
8652 "IMUL $tmp,EDX\n\t"
8653 "MUL EDX:EAX,$src.lo\n\t"
8654 "ADD EDX,$tmp" %}
8655 ins_encode %{
8656 __ movl($tmp$$Register, $src$$Register);
8657 __ imull($tmp$$Register, rdx);
8658 __ mull($src$$Register);
8659 __ addl(rdx, $tmp$$Register);
8660 %}
8661 ins_pipe( pipe_slow );
8662 %}
8664 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8665 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8666 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8667 match(Set dst (MulL dst src));
8668 effect(KILL cr);
8669 ins_cost(1*400);
8670 // Basic idea: lo(result) = lo(x_lo * y_lo)
8671 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8672 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8673 ins_encode %{
8674 __ mull($src$$Register);
8675 %}
8676 ins_pipe( pipe_slow );
8677 %}
8679 // Multiply Register Long by small constant
8680 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8681 match(Set dst (MulL dst src));
8682 effect(KILL cr, TEMP tmp);
8683 ins_cost(2*100+2*400);
8684 size(12);
8685 // Basic idea: lo(result) = lo(src * EAX)
8686 // hi(result) = hi(src * EAX) + lo(src * EDX)
8687 format %{ "IMUL $tmp,EDX,$src\n\t"
8688 "MOV EDX,$src\n\t"
8689 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8690 "ADD EDX,$tmp" %}
8691 ins_encode( long_multiply_con( dst, src, tmp ) );
8692 ins_pipe( pipe_slow );
8693 %}
8695 // Integer DIV with Register
8696 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8697 match(Set rax (DivI rax div));
8698 effect(KILL rdx, KILL cr);
8699 size(26);
8700 ins_cost(30*100+10*100);
8701 format %{ "CMP EAX,0x80000000\n\t"
8702 "JNE,s normal\n\t"
8703 "XOR EDX,EDX\n\t"
8704 "CMP ECX,-1\n\t"
8705 "JE,s done\n"
8706 "normal: CDQ\n\t"
8707 "IDIV $div\n\t"
8708 "done:" %}
8709 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8710 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8711 ins_pipe( ialu_reg_reg_alu0 );
8712 %}
8714 // Divide Register Long
8715 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8716 match(Set dst (DivL src1 src2));
8717 effect( KILL cr, KILL cx, KILL bx );
8718 ins_cost(10000);
8719 format %{ "PUSH $src1.hi\n\t"
8720 "PUSH $src1.lo\n\t"
8721 "PUSH $src2.hi\n\t"
8722 "PUSH $src2.lo\n\t"
8723 "CALL SharedRuntime::ldiv\n\t"
8724 "ADD ESP,16" %}
8725 ins_encode( long_div(src1,src2) );
8726 ins_pipe( pipe_slow );
8727 %}
8729 // Integer DIVMOD with Register, both quotient and mod results
8730 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8731 match(DivModI rax div);
8732 effect(KILL cr);
8733 size(26);
8734 ins_cost(30*100+10*100);
8735 format %{ "CMP EAX,0x80000000\n\t"
8736 "JNE,s normal\n\t"
8737 "XOR EDX,EDX\n\t"
8738 "CMP ECX,-1\n\t"
8739 "JE,s done\n"
8740 "normal: CDQ\n\t"
8741 "IDIV $div\n\t"
8742 "done:" %}
8743 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8744 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8745 ins_pipe( pipe_slow );
8746 %}
8748 // Integer MOD with Register
8749 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8750 match(Set rdx (ModI rax div));
8751 effect(KILL rax, KILL cr);
8753 size(26);
8754 ins_cost(300);
8755 format %{ "CDQ\n\t"
8756 "IDIV $div" %}
8757 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8758 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8759 ins_pipe( ialu_reg_reg_alu0 );
8760 %}
8762 // Remainder Register Long
8763 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8764 match(Set dst (ModL src1 src2));
8765 effect( KILL cr, KILL cx, KILL bx );
8766 ins_cost(10000);
8767 format %{ "PUSH $src1.hi\n\t"
8768 "PUSH $src1.lo\n\t"
8769 "PUSH $src2.hi\n\t"
8770 "PUSH $src2.lo\n\t"
8771 "CALL SharedRuntime::lrem\n\t"
8772 "ADD ESP,16" %}
8773 ins_encode( long_mod(src1,src2) );
8774 ins_pipe( pipe_slow );
8775 %}
8777 // Integer Shift Instructions
8778 // Shift Left by one
8779 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8780 match(Set dst (LShiftI dst shift));
8781 effect(KILL cr);
8783 size(2);
8784 format %{ "SHL $dst,$shift" %}
8785 opcode(0xD1, 0x4); /* D1 /4 */
8786 ins_encode( OpcP, RegOpc( dst ) );
8787 ins_pipe( ialu_reg );
8788 %}
8790 // Shift Left by 8-bit immediate
8791 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8792 match(Set dst (LShiftI dst shift));
8793 effect(KILL cr);
8795 size(3);
8796 format %{ "SHL $dst,$shift" %}
8797 opcode(0xC1, 0x4); /* C1 /4 ib */
8798 ins_encode( RegOpcImm( dst, shift) );
8799 ins_pipe( ialu_reg );
8800 %}
8802 // Shift Left by variable
8803 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8804 match(Set dst (LShiftI dst shift));
8805 effect(KILL cr);
8807 size(2);
8808 format %{ "SHL $dst,$shift" %}
8809 opcode(0xD3, 0x4); /* D3 /4 */
8810 ins_encode( OpcP, RegOpc( dst ) );
8811 ins_pipe( ialu_reg_reg );
8812 %}
8814 // Arithmetic shift right by one
8815 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8816 match(Set dst (RShiftI dst shift));
8817 effect(KILL cr);
8819 size(2);
8820 format %{ "SAR $dst,$shift" %}
8821 opcode(0xD1, 0x7); /* D1 /7 */
8822 ins_encode( OpcP, RegOpc( dst ) );
8823 ins_pipe( ialu_reg );
8824 %}
8826 // Arithmetic shift right by one
8827 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8828 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8829 effect(KILL cr);
8830 format %{ "SAR $dst,$shift" %}
8831 opcode(0xD1, 0x7); /* D1 /7 */
8832 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8833 ins_pipe( ialu_mem_imm );
8834 %}
8836 // Arithmetic Shift Right by 8-bit immediate
8837 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8838 match(Set dst (RShiftI dst shift));
8839 effect(KILL cr);
8841 size(3);
8842 format %{ "SAR $dst,$shift" %}
8843 opcode(0xC1, 0x7); /* C1 /7 ib */
8844 ins_encode( RegOpcImm( dst, shift ) );
8845 ins_pipe( ialu_mem_imm );
8846 %}
8848 // Arithmetic Shift Right by 8-bit immediate
8849 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8850 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8851 effect(KILL cr);
8853 format %{ "SAR $dst,$shift" %}
8854 opcode(0xC1, 0x7); /* C1 /7 ib */
8855 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8856 ins_pipe( ialu_mem_imm );
8857 %}
8859 // Arithmetic Shift Right by variable
8860 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8861 match(Set dst (RShiftI dst shift));
8862 effect(KILL cr);
8864 size(2);
8865 format %{ "SAR $dst,$shift" %}
8866 opcode(0xD3, 0x7); /* D3 /7 */
8867 ins_encode( OpcP, RegOpc( dst ) );
8868 ins_pipe( ialu_reg_reg );
8869 %}
8871 // Logical shift right by one
8872 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8873 match(Set dst (URShiftI dst shift));
8874 effect(KILL cr);
8876 size(2);
8877 format %{ "SHR $dst,$shift" %}
8878 opcode(0xD1, 0x5); /* D1 /5 */
8879 ins_encode( OpcP, RegOpc( dst ) );
8880 ins_pipe( ialu_reg );
8881 %}
8883 // Logical Shift Right by 8-bit immediate
8884 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8885 match(Set dst (URShiftI dst shift));
8886 effect(KILL cr);
8888 size(3);
8889 format %{ "SHR $dst,$shift" %}
8890 opcode(0xC1, 0x5); /* C1 /5 ib */
8891 ins_encode( RegOpcImm( dst, shift) );
8892 ins_pipe( ialu_reg );
8893 %}
8896 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8897 // This idiom is used by the compiler for the i2b bytecode.
8898 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{
8899 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8901 size(3);
8902 format %{ "MOVSX $dst,$src :8" %}
8903 ins_encode %{
8904 __ movsbl($dst$$Register, $src$$Register);
8905 %}
8906 ins_pipe(ialu_reg_reg);
8907 %}
8909 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8910 // This idiom is used by the compiler the i2s bytecode.
8911 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{
8912 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8914 size(3);
8915 format %{ "MOVSX $dst,$src :16" %}
8916 ins_encode %{
8917 __ movswl($dst$$Register, $src$$Register);
8918 %}
8919 ins_pipe(ialu_reg_reg);
8920 %}
8923 // Logical Shift Right by variable
8924 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8925 match(Set dst (URShiftI dst shift));
8926 effect(KILL cr);
8928 size(2);
8929 format %{ "SHR $dst,$shift" %}
8930 opcode(0xD3, 0x5); /* D3 /5 */
8931 ins_encode( OpcP, RegOpc( dst ) );
8932 ins_pipe( ialu_reg_reg );
8933 %}
8936 //----------Logical Instructions-----------------------------------------------
8937 //----------Integer Logical Instructions---------------------------------------
8938 // And Instructions
8939 // And Register with Register
8940 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8941 match(Set dst (AndI dst src));
8942 effect(KILL cr);
8944 size(2);
8945 format %{ "AND $dst,$src" %}
8946 opcode(0x23);
8947 ins_encode( OpcP, RegReg( dst, src) );
8948 ins_pipe( ialu_reg_reg );
8949 %}
8951 // And Register with Immediate
8952 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8953 match(Set dst (AndI dst src));
8954 effect(KILL cr);
8956 format %{ "AND $dst,$src" %}
8957 opcode(0x81,0x04); /* Opcode 81 /4 */
8958 // ins_encode( RegImm( dst, src) );
8959 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8960 ins_pipe( ialu_reg );
8961 %}
8963 // And Register with Memory
8964 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8965 match(Set dst (AndI dst (LoadI src)));
8966 effect(KILL cr);
8968 ins_cost(125);
8969 format %{ "AND $dst,$src" %}
8970 opcode(0x23);
8971 ins_encode( OpcP, RegMem( dst, src) );
8972 ins_pipe( ialu_reg_mem );
8973 %}
8975 // And Memory with Register
8976 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8977 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8978 effect(KILL cr);
8980 ins_cost(150);
8981 format %{ "AND $dst,$src" %}
8982 opcode(0x21); /* Opcode 21 /r */
8983 ins_encode( OpcP, RegMem( src, dst ) );
8984 ins_pipe( ialu_mem_reg );
8985 %}
8987 // And Memory with Immediate
8988 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8989 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8990 effect(KILL cr);
8992 ins_cost(125);
8993 format %{ "AND $dst,$src" %}
8994 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8995 // ins_encode( MemImm( dst, src) );
8996 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8997 ins_pipe( ialu_mem_imm );
8998 %}
9000 // Or Instructions
9001 // Or Register with Register
9002 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9003 match(Set dst (OrI dst src));
9004 effect(KILL cr);
9006 size(2);
9007 format %{ "OR $dst,$src" %}
9008 opcode(0x0B);
9009 ins_encode( OpcP, RegReg( dst, src) );
9010 ins_pipe( ialu_reg_reg );
9011 %}
9013 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
9014 match(Set dst (OrI dst (CastP2X src)));
9015 effect(KILL cr);
9017 size(2);
9018 format %{ "OR $dst,$src" %}
9019 opcode(0x0B);
9020 ins_encode( OpcP, RegReg( dst, src) );
9021 ins_pipe( ialu_reg_reg );
9022 %}
9025 // Or Register with Immediate
9026 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9027 match(Set dst (OrI dst src));
9028 effect(KILL cr);
9030 format %{ "OR $dst,$src" %}
9031 opcode(0x81,0x01); /* Opcode 81 /1 id */
9032 // ins_encode( RegImm( dst, src) );
9033 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9034 ins_pipe( ialu_reg );
9035 %}
9037 // Or Register with Memory
9038 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9039 match(Set dst (OrI dst (LoadI src)));
9040 effect(KILL cr);
9042 ins_cost(125);
9043 format %{ "OR $dst,$src" %}
9044 opcode(0x0B);
9045 ins_encode( OpcP, RegMem( dst, src) );
9046 ins_pipe( ialu_reg_mem );
9047 %}
9049 // Or Memory with Register
9050 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9051 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9052 effect(KILL cr);
9054 ins_cost(150);
9055 format %{ "OR $dst,$src" %}
9056 opcode(0x09); /* Opcode 09 /r */
9057 ins_encode( OpcP, RegMem( src, dst ) );
9058 ins_pipe( ialu_mem_reg );
9059 %}
9061 // Or Memory with Immediate
9062 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9063 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9064 effect(KILL cr);
9066 ins_cost(125);
9067 format %{ "OR $dst,$src" %}
9068 opcode(0x81,0x1); /* Opcode 81 /1 id */
9069 // ins_encode( MemImm( dst, src) );
9070 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9071 ins_pipe( ialu_mem_imm );
9072 %}
9074 // ROL/ROR
9075 // ROL expand
9076 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9077 effect(USE_DEF dst, USE shift, KILL cr);
9079 format %{ "ROL $dst, $shift" %}
9080 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9081 ins_encode( OpcP, RegOpc( dst ));
9082 ins_pipe( ialu_reg );
9083 %}
9085 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9086 effect(USE_DEF dst, USE shift, KILL cr);
9088 format %{ "ROL $dst, $shift" %}
9089 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
9090 ins_encode( RegOpcImm(dst, shift) );
9091 ins_pipe(ialu_reg);
9092 %}
9094 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
9095 effect(USE_DEF dst, USE shift, KILL cr);
9097 format %{ "ROL $dst, $shift" %}
9098 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9099 ins_encode(OpcP, RegOpc(dst));
9100 ins_pipe( ialu_reg_reg );
9101 %}
9102 // end of ROL expand
9104 // ROL 32bit by one once
9105 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
9106 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9108 expand %{
9109 rolI_eReg_imm1(dst, lshift, cr);
9110 %}
9111 %}
9113 // ROL 32bit var by imm8 once
9114 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
9115 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9116 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9118 expand %{
9119 rolI_eReg_imm8(dst, lshift, cr);
9120 %}
9121 %}
9123 // ROL 32bit var by var once
9124 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9125 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9127 expand %{
9128 rolI_eReg_CL(dst, shift, cr);
9129 %}
9130 %}
9132 // ROL 32bit var by var once
9133 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9134 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9136 expand %{
9137 rolI_eReg_CL(dst, shift, cr);
9138 %}
9139 %}
9141 // ROR expand
9142 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9143 effect(USE_DEF dst, USE shift, KILL cr);
9145 format %{ "ROR $dst, $shift" %}
9146 opcode(0xD1,0x1); /* Opcode D1 /1 */
9147 ins_encode( OpcP, RegOpc( dst ) );
9148 ins_pipe( ialu_reg );
9149 %}
9151 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9152 effect (USE_DEF dst, USE shift, KILL cr);
9154 format %{ "ROR $dst, $shift" %}
9155 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
9156 ins_encode( RegOpcImm(dst, shift) );
9157 ins_pipe( ialu_reg );
9158 %}
9160 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
9161 effect(USE_DEF dst, USE shift, KILL cr);
9163 format %{ "ROR $dst, $shift" %}
9164 opcode(0xD3, 0x1); /* Opcode D3 /1 */
9165 ins_encode(OpcP, RegOpc(dst));
9166 ins_pipe( ialu_reg_reg );
9167 %}
9168 // end of ROR expand
9170 // ROR right once
9171 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
9172 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9174 expand %{
9175 rorI_eReg_imm1(dst, rshift, cr);
9176 %}
9177 %}
9179 // ROR 32bit by immI8 once
9180 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
9181 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9182 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9184 expand %{
9185 rorI_eReg_imm8(dst, rshift, cr);
9186 %}
9187 %}
9189 // ROR 32bit var by var once
9190 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9191 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9193 expand %{
9194 rorI_eReg_CL(dst, shift, cr);
9195 %}
9196 %}
9198 // ROR 32bit var by var once
9199 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9200 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9202 expand %{
9203 rorI_eReg_CL(dst, shift, cr);
9204 %}
9205 %}
9207 // Xor Instructions
9208 // Xor Register with Register
9209 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9210 match(Set dst (XorI dst src));
9211 effect(KILL cr);
9213 size(2);
9214 format %{ "XOR $dst,$src" %}
9215 opcode(0x33);
9216 ins_encode( OpcP, RegReg( dst, src) );
9217 ins_pipe( ialu_reg_reg );
9218 %}
9220 // Xor Register with Immediate -1
9221 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
9222 match(Set dst (XorI dst imm));
9224 size(2);
9225 format %{ "NOT $dst" %}
9226 ins_encode %{
9227 __ notl($dst$$Register);
9228 %}
9229 ins_pipe( ialu_reg );
9230 %}
9232 // Xor Register with Immediate
9233 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9234 match(Set dst (XorI dst src));
9235 effect(KILL cr);
9237 format %{ "XOR $dst,$src" %}
9238 opcode(0x81,0x06); /* Opcode 81 /6 id */
9239 // ins_encode( RegImm( dst, src) );
9240 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9241 ins_pipe( ialu_reg );
9242 %}
9244 // Xor Register with Memory
9245 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9246 match(Set dst (XorI dst (LoadI src)));
9247 effect(KILL cr);
9249 ins_cost(125);
9250 format %{ "XOR $dst,$src" %}
9251 opcode(0x33);
9252 ins_encode( OpcP, RegMem(dst, src) );
9253 ins_pipe( ialu_reg_mem );
9254 %}
9256 // Xor Memory with Register
9257 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9258 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9259 effect(KILL cr);
9261 ins_cost(150);
9262 format %{ "XOR $dst,$src" %}
9263 opcode(0x31); /* Opcode 31 /r */
9264 ins_encode( OpcP, RegMem( src, dst ) );
9265 ins_pipe( ialu_mem_reg );
9266 %}
9268 // Xor Memory with Immediate
9269 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9270 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9271 effect(KILL cr);
9273 ins_cost(125);
9274 format %{ "XOR $dst,$src" %}
9275 opcode(0x81,0x6); /* Opcode 81 /6 id */
9276 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9277 ins_pipe( ialu_mem_imm );
9278 %}
9280 //----------Convert Int to Boolean---------------------------------------------
9282 instruct movI_nocopy(eRegI dst, eRegI src) %{
9283 effect( DEF dst, USE src );
9284 format %{ "MOV $dst,$src" %}
9285 ins_encode( enc_Copy( dst, src) );
9286 ins_pipe( ialu_reg_reg );
9287 %}
9289 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
9290 effect( USE_DEF dst, USE src, KILL cr );
9292 size(4);
9293 format %{ "NEG $dst\n\t"
9294 "ADC $dst,$src" %}
9295 ins_encode( neg_reg(dst),
9296 OpcRegReg(0x13,dst,src) );
9297 ins_pipe( ialu_reg_reg_long );
9298 %}
9300 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
9301 match(Set dst (Conv2B src));
9303 expand %{
9304 movI_nocopy(dst,src);
9305 ci2b(dst,src,cr);
9306 %}
9307 %}
9309 instruct movP_nocopy(eRegI dst, eRegP src) %{
9310 effect( DEF dst, USE src );
9311 format %{ "MOV $dst,$src" %}
9312 ins_encode( enc_Copy( dst, src) );
9313 ins_pipe( ialu_reg_reg );
9314 %}
9316 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
9317 effect( USE_DEF dst, USE src, KILL cr );
9318 format %{ "NEG $dst\n\t"
9319 "ADC $dst,$src" %}
9320 ins_encode( neg_reg(dst),
9321 OpcRegReg(0x13,dst,src) );
9322 ins_pipe( ialu_reg_reg_long );
9323 %}
9325 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
9326 match(Set dst (Conv2B src));
9328 expand %{
9329 movP_nocopy(dst,src);
9330 cp2b(dst,src,cr);
9331 %}
9332 %}
9334 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
9335 match(Set dst (CmpLTMask p q));
9336 effect( KILL cr );
9337 ins_cost(400);
9339 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9340 format %{ "XOR $dst,$dst\n\t"
9341 "CMP $p,$q\n\t"
9342 "SETlt $dst\n\t"
9343 "NEG $dst" %}
9344 ins_encode( OpcRegReg(0x33,dst,dst),
9345 OpcRegReg(0x3B,p,q),
9346 setLT_reg(dst), neg_reg(dst) );
9347 ins_pipe( pipe_slow );
9348 %}
9350 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9351 match(Set dst (CmpLTMask dst zero));
9352 effect( DEF dst, KILL cr );
9353 ins_cost(100);
9355 format %{ "SAR $dst,31" %}
9356 opcode(0xC1, 0x7); /* C1 /7 ib */
9357 ins_encode( RegOpcImm( dst, 0x1F ) );
9358 ins_pipe( ialu_reg );
9359 %}
9362 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9363 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9364 effect( KILL tmp, KILL cr );
9365 ins_cost(400);
9366 // annoyingly, $tmp has no edges so you cant ask for it in
9367 // any format or encoding
9368 format %{ "SUB $p,$q\n\t"
9369 "SBB ECX,ECX\n\t"
9370 "AND ECX,$y\n\t"
9371 "ADD $p,ECX" %}
9372 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9373 ins_pipe( pipe_cmplt );
9374 %}
9376 /* If I enable this, I encourage spilling in the inner loop of compress.
9377 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9378 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9379 effect( USE_KILL tmp, KILL cr );
9380 ins_cost(400);
9382 format %{ "SUB $p,$q\n\t"
9383 "SBB ECX,ECX\n\t"
9384 "AND ECX,$y\n\t"
9385 "ADD $p,ECX" %}
9386 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9387 %}
9388 */
9390 //----------Long Instructions------------------------------------------------
9391 // Add Long Register with Register
9392 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9393 match(Set dst (AddL dst src));
9394 effect(KILL cr);
9395 ins_cost(200);
9396 format %{ "ADD $dst.lo,$src.lo\n\t"
9397 "ADC $dst.hi,$src.hi" %}
9398 opcode(0x03, 0x13);
9399 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9400 ins_pipe( ialu_reg_reg_long );
9401 %}
9403 // Add Long Register with Immediate
9404 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9405 match(Set dst (AddL dst src));
9406 effect(KILL cr);
9407 format %{ "ADD $dst.lo,$src.lo\n\t"
9408 "ADC $dst.hi,$src.hi" %}
9409 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9410 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9411 ins_pipe( ialu_reg_long );
9412 %}
9414 // Add Long Register with Memory
9415 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9416 match(Set dst (AddL dst (LoadL mem)));
9417 effect(KILL cr);
9418 ins_cost(125);
9419 format %{ "ADD $dst.lo,$mem\n\t"
9420 "ADC $dst.hi,$mem+4" %}
9421 opcode(0x03, 0x13);
9422 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9423 ins_pipe( ialu_reg_long_mem );
9424 %}
9426 // Subtract Long Register with Register.
9427 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9428 match(Set dst (SubL dst src));
9429 effect(KILL cr);
9430 ins_cost(200);
9431 format %{ "SUB $dst.lo,$src.lo\n\t"
9432 "SBB $dst.hi,$src.hi" %}
9433 opcode(0x2B, 0x1B);
9434 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9435 ins_pipe( ialu_reg_reg_long );
9436 %}
9438 // Subtract Long Register with Immediate
9439 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9440 match(Set dst (SubL dst src));
9441 effect(KILL cr);
9442 format %{ "SUB $dst.lo,$src.lo\n\t"
9443 "SBB $dst.hi,$src.hi" %}
9444 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9445 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9446 ins_pipe( ialu_reg_long );
9447 %}
9449 // Subtract Long Register with Memory
9450 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9451 match(Set dst (SubL dst (LoadL mem)));
9452 effect(KILL cr);
9453 ins_cost(125);
9454 format %{ "SUB $dst.lo,$mem\n\t"
9455 "SBB $dst.hi,$mem+4" %}
9456 opcode(0x2B, 0x1B);
9457 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9458 ins_pipe( ialu_reg_long_mem );
9459 %}
9461 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9462 match(Set dst (SubL zero dst));
9463 effect(KILL cr);
9464 ins_cost(300);
9465 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9466 ins_encode( neg_long(dst) );
9467 ins_pipe( ialu_reg_reg_long );
9468 %}
9470 // And Long Register with Register
9471 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9472 match(Set dst (AndL dst src));
9473 effect(KILL cr);
9474 format %{ "AND $dst.lo,$src.lo\n\t"
9475 "AND $dst.hi,$src.hi" %}
9476 opcode(0x23,0x23);
9477 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9478 ins_pipe( ialu_reg_reg_long );
9479 %}
9481 // And Long Register with Immediate
9482 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9483 match(Set dst (AndL dst src));
9484 effect(KILL cr);
9485 format %{ "AND $dst.lo,$src.lo\n\t"
9486 "AND $dst.hi,$src.hi" %}
9487 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9488 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9489 ins_pipe( ialu_reg_long );
9490 %}
9492 // And Long Register with Memory
9493 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9494 match(Set dst (AndL dst (LoadL mem)));
9495 effect(KILL cr);
9496 ins_cost(125);
9497 format %{ "AND $dst.lo,$mem\n\t"
9498 "AND $dst.hi,$mem+4" %}
9499 opcode(0x23, 0x23);
9500 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9501 ins_pipe( ialu_reg_long_mem );
9502 %}
9504 // Or Long Register with Register
9505 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9506 match(Set dst (OrL dst src));
9507 effect(KILL cr);
9508 format %{ "OR $dst.lo,$src.lo\n\t"
9509 "OR $dst.hi,$src.hi" %}
9510 opcode(0x0B,0x0B);
9511 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9512 ins_pipe( ialu_reg_reg_long );
9513 %}
9515 // Or Long Register with Immediate
9516 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9517 match(Set dst (OrL dst src));
9518 effect(KILL cr);
9519 format %{ "OR $dst.lo,$src.lo\n\t"
9520 "OR $dst.hi,$src.hi" %}
9521 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9522 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9523 ins_pipe( ialu_reg_long );
9524 %}
9526 // Or Long Register with Memory
9527 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9528 match(Set dst (OrL dst (LoadL mem)));
9529 effect(KILL cr);
9530 ins_cost(125);
9531 format %{ "OR $dst.lo,$mem\n\t"
9532 "OR $dst.hi,$mem+4" %}
9533 opcode(0x0B,0x0B);
9534 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9535 ins_pipe( ialu_reg_long_mem );
9536 %}
9538 // Xor Long Register with Register
9539 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9540 match(Set dst (XorL dst src));
9541 effect(KILL cr);
9542 format %{ "XOR $dst.lo,$src.lo\n\t"
9543 "XOR $dst.hi,$src.hi" %}
9544 opcode(0x33,0x33);
9545 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9546 ins_pipe( ialu_reg_reg_long );
9547 %}
9549 // Xor Long Register with Immediate -1
9550 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9551 match(Set dst (XorL dst imm));
9552 format %{ "NOT $dst.lo\n\t"
9553 "NOT $dst.hi" %}
9554 ins_encode %{
9555 __ notl($dst$$Register);
9556 __ notl(HIGH_FROM_LOW($dst$$Register));
9557 %}
9558 ins_pipe( ialu_reg_long );
9559 %}
9561 // Xor Long Register with Immediate
9562 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9563 match(Set dst (XorL dst src));
9564 effect(KILL cr);
9565 format %{ "XOR $dst.lo,$src.lo\n\t"
9566 "XOR $dst.hi,$src.hi" %}
9567 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9568 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9569 ins_pipe( ialu_reg_long );
9570 %}
9572 // Xor Long Register with Memory
9573 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9574 match(Set dst (XorL dst (LoadL mem)));
9575 effect(KILL cr);
9576 ins_cost(125);
9577 format %{ "XOR $dst.lo,$mem\n\t"
9578 "XOR $dst.hi,$mem+4" %}
9579 opcode(0x33,0x33);
9580 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9581 ins_pipe( ialu_reg_long_mem );
9582 %}
9584 // Shift Left Long by 1
9585 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9586 predicate(UseNewLongLShift);
9587 match(Set dst (LShiftL dst cnt));
9588 effect(KILL cr);
9589 ins_cost(100);
9590 format %{ "ADD $dst.lo,$dst.lo\n\t"
9591 "ADC $dst.hi,$dst.hi" %}
9592 ins_encode %{
9593 __ addl($dst$$Register,$dst$$Register);
9594 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9595 %}
9596 ins_pipe( ialu_reg_long );
9597 %}
9599 // Shift Left Long by 2
9600 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9601 predicate(UseNewLongLShift);
9602 match(Set dst (LShiftL dst cnt));
9603 effect(KILL cr);
9604 ins_cost(100);
9605 format %{ "ADD $dst.lo,$dst.lo\n\t"
9606 "ADC $dst.hi,$dst.hi\n\t"
9607 "ADD $dst.lo,$dst.lo\n\t"
9608 "ADC $dst.hi,$dst.hi" %}
9609 ins_encode %{
9610 __ addl($dst$$Register,$dst$$Register);
9611 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9612 __ addl($dst$$Register,$dst$$Register);
9613 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9614 %}
9615 ins_pipe( ialu_reg_long );
9616 %}
9618 // Shift Left Long by 3
9619 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9620 predicate(UseNewLongLShift);
9621 match(Set dst (LShiftL dst cnt));
9622 effect(KILL cr);
9623 ins_cost(100);
9624 format %{ "ADD $dst.lo,$dst.lo\n\t"
9625 "ADC $dst.hi,$dst.hi\n\t"
9626 "ADD $dst.lo,$dst.lo\n\t"
9627 "ADC $dst.hi,$dst.hi\n\t"
9628 "ADD $dst.lo,$dst.lo\n\t"
9629 "ADC $dst.hi,$dst.hi" %}
9630 ins_encode %{
9631 __ addl($dst$$Register,$dst$$Register);
9632 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9633 __ addl($dst$$Register,$dst$$Register);
9634 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9635 __ addl($dst$$Register,$dst$$Register);
9636 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9637 %}
9638 ins_pipe( ialu_reg_long );
9639 %}
9641 // Shift Left Long by 1-31
9642 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9643 match(Set dst (LShiftL dst cnt));
9644 effect(KILL cr);
9645 ins_cost(200);
9646 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9647 "SHL $dst.lo,$cnt" %}
9648 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9649 ins_encode( move_long_small_shift(dst,cnt) );
9650 ins_pipe( ialu_reg_long );
9651 %}
9653 // Shift Left Long by 32-63
9654 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9655 match(Set dst (LShiftL dst cnt));
9656 effect(KILL cr);
9657 ins_cost(300);
9658 format %{ "MOV $dst.hi,$dst.lo\n"
9659 "\tSHL $dst.hi,$cnt-32\n"
9660 "\tXOR $dst.lo,$dst.lo" %}
9661 opcode(0xC1, 0x4); /* C1 /4 ib */
9662 ins_encode( move_long_big_shift_clr(dst,cnt) );
9663 ins_pipe( ialu_reg_long );
9664 %}
9666 // Shift Left Long by variable
9667 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9668 match(Set dst (LShiftL dst shift));
9669 effect(KILL cr);
9670 ins_cost(500+200);
9671 size(17);
9672 format %{ "TEST $shift,32\n\t"
9673 "JEQ,s small\n\t"
9674 "MOV $dst.hi,$dst.lo\n\t"
9675 "XOR $dst.lo,$dst.lo\n"
9676 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9677 "SHL $dst.lo,$shift" %}
9678 ins_encode( shift_left_long( dst, shift ) );
9679 ins_pipe( pipe_slow );
9680 %}
9682 // Shift Right Long by 1-31
9683 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9684 match(Set dst (URShiftL dst cnt));
9685 effect(KILL cr);
9686 ins_cost(200);
9687 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9688 "SHR $dst.hi,$cnt" %}
9689 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9690 ins_encode( move_long_small_shift(dst,cnt) );
9691 ins_pipe( ialu_reg_long );
9692 %}
9694 // Shift Right Long by 32-63
9695 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9696 match(Set dst (URShiftL dst cnt));
9697 effect(KILL cr);
9698 ins_cost(300);
9699 format %{ "MOV $dst.lo,$dst.hi\n"
9700 "\tSHR $dst.lo,$cnt-32\n"
9701 "\tXOR $dst.hi,$dst.hi" %}
9702 opcode(0xC1, 0x5); /* C1 /5 ib */
9703 ins_encode( move_long_big_shift_clr(dst,cnt) );
9704 ins_pipe( ialu_reg_long );
9705 %}
9707 // Shift Right Long by variable
9708 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9709 match(Set dst (URShiftL dst shift));
9710 effect(KILL cr);
9711 ins_cost(600);
9712 size(17);
9713 format %{ "TEST $shift,32\n\t"
9714 "JEQ,s small\n\t"
9715 "MOV $dst.lo,$dst.hi\n\t"
9716 "XOR $dst.hi,$dst.hi\n"
9717 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9718 "SHR $dst.hi,$shift" %}
9719 ins_encode( shift_right_long( dst, shift ) );
9720 ins_pipe( pipe_slow );
9721 %}
9723 // Shift Right Long by 1-31
9724 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9725 match(Set dst (RShiftL dst cnt));
9726 effect(KILL cr);
9727 ins_cost(200);
9728 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9729 "SAR $dst.hi,$cnt" %}
9730 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9731 ins_encode( move_long_small_shift(dst,cnt) );
9732 ins_pipe( ialu_reg_long );
9733 %}
9735 // Shift Right Long by 32-63
9736 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9737 match(Set dst (RShiftL dst cnt));
9738 effect(KILL cr);
9739 ins_cost(300);
9740 format %{ "MOV $dst.lo,$dst.hi\n"
9741 "\tSAR $dst.lo,$cnt-32\n"
9742 "\tSAR $dst.hi,31" %}
9743 opcode(0xC1, 0x7); /* C1 /7 ib */
9744 ins_encode( move_long_big_shift_sign(dst,cnt) );
9745 ins_pipe( ialu_reg_long );
9746 %}
9748 // Shift Right arithmetic Long by variable
9749 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9750 match(Set dst (RShiftL dst shift));
9751 effect(KILL cr);
9752 ins_cost(600);
9753 size(18);
9754 format %{ "TEST $shift,32\n\t"
9755 "JEQ,s small\n\t"
9756 "MOV $dst.lo,$dst.hi\n\t"
9757 "SAR $dst.hi,31\n"
9758 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9759 "SAR $dst.hi,$shift" %}
9760 ins_encode( shift_right_arith_long( dst, shift ) );
9761 ins_pipe( pipe_slow );
9762 %}
9765 //----------Double Instructions------------------------------------------------
9766 // Double Math
9768 // Compare & branch
9770 // P6 version of float compare, sets condition codes in EFLAGS
9771 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9772 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9773 match(Set cr (CmpD src1 src2));
9774 effect(KILL rax);
9775 ins_cost(150);
9776 format %{ "FLD $src1\n\t"
9777 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9778 "JNP exit\n\t"
9779 "MOV ah,1 // saw a NaN, set CF\n\t"
9780 "SAHF\n"
9781 "exit:\tNOP // avoid branch to branch" %}
9782 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9783 ins_encode( Push_Reg_D(src1),
9784 OpcP, RegOpc(src2),
9785 cmpF_P6_fixup );
9786 ins_pipe( pipe_slow );
9787 %}
9789 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{
9790 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9791 match(Set cr (CmpD src1 src2));
9792 ins_cost(150);
9793 format %{ "FLD $src1\n\t"
9794 "FUCOMIP ST,$src2 // P6 instruction" %}
9795 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9796 ins_encode( Push_Reg_D(src1),
9797 OpcP, RegOpc(src2));
9798 ins_pipe( pipe_slow );
9799 %}
9801 // Compare & branch
9802 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9803 predicate(UseSSE<=1);
9804 match(Set cr (CmpD src1 src2));
9805 effect(KILL rax);
9806 ins_cost(200);
9807 format %{ "FLD $src1\n\t"
9808 "FCOMp $src2\n\t"
9809 "FNSTSW AX\n\t"
9810 "TEST AX,0x400\n\t"
9811 "JZ,s flags\n\t"
9812 "MOV AH,1\t# unordered treat as LT\n"
9813 "flags:\tSAHF" %}
9814 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9815 ins_encode( Push_Reg_D(src1),
9816 OpcP, RegOpc(src2),
9817 fpu_flags);
9818 ins_pipe( pipe_slow );
9819 %}
9821 // Compare vs zero into -1,0,1
9822 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
9823 predicate(UseSSE<=1);
9824 match(Set dst (CmpD3 src1 zero));
9825 effect(KILL cr, KILL rax);
9826 ins_cost(280);
9827 format %{ "FTSTD $dst,$src1" %}
9828 opcode(0xE4, 0xD9);
9829 ins_encode( Push_Reg_D(src1),
9830 OpcS, OpcP, PopFPU,
9831 CmpF_Result(dst));
9832 ins_pipe( pipe_slow );
9833 %}
9835 // Compare into -1,0,1
9836 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
9837 predicate(UseSSE<=1);
9838 match(Set dst (CmpD3 src1 src2));
9839 effect(KILL cr, KILL rax);
9840 ins_cost(300);
9841 format %{ "FCMPD $dst,$src1,$src2" %}
9842 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9843 ins_encode( Push_Reg_D(src1),
9844 OpcP, RegOpc(src2),
9845 CmpF_Result(dst));
9846 ins_pipe( pipe_slow );
9847 %}
9849 // float compare and set condition codes in EFLAGS by XMM regs
9850 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{
9851 predicate(UseSSE>=2);
9852 match(Set cr (CmpD dst src));
9853 effect(KILL rax);
9854 ins_cost(125);
9855 format %{ "COMISD $dst,$src\n"
9856 "\tJNP exit\n"
9857 "\tMOV ah,1 // saw a NaN, set CF\n"
9858 "\tSAHF\n"
9859 "exit:\tNOP // avoid branch to branch" %}
9860 opcode(0x66, 0x0F, 0x2F);
9861 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup);
9862 ins_pipe( pipe_slow );
9863 %}
9865 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{
9866 predicate(UseSSE>=2);
9867 match(Set cr (CmpD dst src));
9868 ins_cost(100);
9869 format %{ "COMISD $dst,$src" %}
9870 opcode(0x66, 0x0F, 0x2F);
9871 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
9872 ins_pipe( pipe_slow );
9873 %}
9875 // float compare and set condition codes in EFLAGS by XMM regs
9876 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{
9877 predicate(UseSSE>=2);
9878 match(Set cr (CmpD dst (LoadD src)));
9879 effect(KILL rax);
9880 ins_cost(145);
9881 format %{ "COMISD $dst,$src\n"
9882 "\tJNP exit\n"
9883 "\tMOV ah,1 // saw a NaN, set CF\n"
9884 "\tSAHF\n"
9885 "exit:\tNOP // avoid branch to branch" %}
9886 opcode(0x66, 0x0F, 0x2F);
9887 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup);
9888 ins_pipe( pipe_slow );
9889 %}
9891 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{
9892 predicate(UseSSE>=2);
9893 match(Set cr (CmpD dst (LoadD src)));
9894 ins_cost(100);
9895 format %{ "COMISD $dst,$src" %}
9896 opcode(0x66, 0x0F, 0x2F);
9897 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src));
9898 ins_pipe( pipe_slow );
9899 %}
9901 // Compare into -1,0,1 in XMM
9902 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
9903 predicate(UseSSE>=2);
9904 match(Set dst (CmpD3 src1 src2));
9905 effect(KILL cr);
9906 ins_cost(255);
9907 format %{ "XOR $dst,$dst\n"
9908 "\tCOMISD $src1,$src2\n"
9909 "\tJP,s nan\n"
9910 "\tJEQ,s exit\n"
9911 "\tJA,s inc\n"
9912 "nan:\tDEC $dst\n"
9913 "\tJMP,s exit\n"
9914 "inc:\tINC $dst\n"
9915 "exit:"
9916 %}
9917 opcode(0x66, 0x0F, 0x2F);
9918 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2),
9919 CmpX_Result(dst));
9920 ins_pipe( pipe_slow );
9921 %}
9923 // Compare into -1,0,1 in XMM and memory
9924 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{
9925 predicate(UseSSE>=2);
9926 match(Set dst (CmpD3 src1 (LoadD mem)));
9927 effect(KILL cr);
9928 ins_cost(275);
9929 format %{ "COMISD $src1,$mem\n"
9930 "\tMOV $dst,0\t\t# do not blow flags\n"
9931 "\tJP,s nan\n"
9932 "\tJEQ,s exit\n"
9933 "\tJA,s inc\n"
9934 "nan:\tDEC $dst\n"
9935 "\tJMP,s exit\n"
9936 "inc:\tINC $dst\n"
9937 "exit:"
9938 %}
9939 opcode(0x66, 0x0F, 0x2F);
9940 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem),
9941 LdImmI(dst,0x0), CmpX_Result(dst));
9942 ins_pipe( pipe_slow );
9943 %}
9946 instruct subD_reg(regD dst, regD src) %{
9947 predicate (UseSSE <=1);
9948 match(Set dst (SubD dst src));
9950 format %{ "FLD $src\n\t"
9951 "DSUBp $dst,ST" %}
9952 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9953 ins_cost(150);
9954 ins_encode( Push_Reg_D(src),
9955 OpcP, RegOpc(dst) );
9956 ins_pipe( fpu_reg_reg );
9957 %}
9959 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9960 predicate (UseSSE <=1);
9961 match(Set dst (RoundDouble (SubD src1 src2)));
9962 ins_cost(250);
9964 format %{ "FLD $src2\n\t"
9965 "DSUB ST,$src1\n\t"
9966 "FSTP_D $dst\t# D-round" %}
9967 opcode(0xD8, 0x5);
9968 ins_encode( Push_Reg_D(src2),
9969 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9970 ins_pipe( fpu_mem_reg_reg );
9971 %}
9974 instruct subD_reg_mem(regD dst, memory src) %{
9975 predicate (UseSSE <=1);
9976 match(Set dst (SubD dst (LoadD src)));
9977 ins_cost(150);
9979 format %{ "FLD $src\n\t"
9980 "DSUBp $dst,ST" %}
9981 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9982 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9983 OpcP, RegOpc(dst) );
9984 ins_pipe( fpu_reg_mem );
9985 %}
9987 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
9988 predicate (UseSSE<=1);
9989 match(Set dst (AbsD src));
9990 ins_cost(100);
9991 format %{ "FABS" %}
9992 opcode(0xE1, 0xD9);
9993 ins_encode( OpcS, OpcP );
9994 ins_pipe( fpu_reg_reg );
9995 %}
9997 instruct absXD_reg( regXD dst ) %{
9998 predicate(UseSSE>=2);
9999 match(Set dst (AbsD dst));
10000 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
10001 ins_encode( AbsXD_encoding(dst));
10002 ins_pipe( pipe_slow );
10003 %}
10005 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
10006 predicate(UseSSE<=1);
10007 match(Set dst (NegD src));
10008 ins_cost(100);
10009 format %{ "FCHS" %}
10010 opcode(0xE0, 0xD9);
10011 ins_encode( OpcS, OpcP );
10012 ins_pipe( fpu_reg_reg );
10013 %}
10015 instruct negXD_reg( regXD dst ) %{
10016 predicate(UseSSE>=2);
10017 match(Set dst (NegD dst));
10018 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
10019 ins_encode %{
10020 __ xorpd($dst$$XMMRegister,
10021 ExternalAddress((address)double_signflip_pool));
10022 %}
10023 ins_pipe( pipe_slow );
10024 %}
10026 instruct addD_reg(regD dst, regD src) %{
10027 predicate(UseSSE<=1);
10028 match(Set dst (AddD dst src));
10029 format %{ "FLD $src\n\t"
10030 "DADD $dst,ST" %}
10031 size(4);
10032 ins_cost(150);
10033 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10034 ins_encode( Push_Reg_D(src),
10035 OpcP, RegOpc(dst) );
10036 ins_pipe( fpu_reg_reg );
10037 %}
10040 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10041 predicate(UseSSE<=1);
10042 match(Set dst (RoundDouble (AddD src1 src2)));
10043 ins_cost(250);
10045 format %{ "FLD $src2\n\t"
10046 "DADD ST,$src1\n\t"
10047 "FSTP_D $dst\t# D-round" %}
10048 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
10049 ins_encode( Push_Reg_D(src2),
10050 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
10051 ins_pipe( fpu_mem_reg_reg );
10052 %}
10055 instruct addD_reg_mem(regD dst, memory src) %{
10056 predicate(UseSSE<=1);
10057 match(Set dst (AddD dst (LoadD src)));
10058 ins_cost(150);
10060 format %{ "FLD $src\n\t"
10061 "DADDp $dst,ST" %}
10062 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
10063 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10064 OpcP, RegOpc(dst) );
10065 ins_pipe( fpu_reg_mem );
10066 %}
10068 // add-to-memory
10069 instruct addD_mem_reg(memory dst, regD src) %{
10070 predicate(UseSSE<=1);
10071 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
10072 ins_cost(150);
10074 format %{ "FLD_D $dst\n\t"
10075 "DADD ST,$src\n\t"
10076 "FST_D $dst" %}
10077 opcode(0xDD, 0x0);
10078 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
10079 Opcode(0xD8), RegOpc(src),
10080 set_instruction_start,
10081 Opcode(0xDD), RMopc_Mem(0x03,dst) );
10082 ins_pipe( fpu_reg_mem );
10083 %}
10085 instruct addD_reg_imm1(regD dst, immD1 src) %{
10086 predicate(UseSSE<=1);
10087 match(Set dst (AddD dst src));
10088 ins_cost(125);
10089 format %{ "FLD1\n\t"
10090 "DADDp $dst,ST" %}
10091 opcode(0xDE, 0x00);
10092 ins_encode( LdImmD(src),
10093 OpcP, RegOpc(dst) );
10094 ins_pipe( fpu_reg );
10095 %}
10097 instruct addD_reg_imm(regD dst, immD src) %{
10098 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10099 match(Set dst (AddD dst src));
10100 ins_cost(200);
10101 format %{ "FLD_D [$src]\n\t"
10102 "DADDp $dst,ST" %}
10103 opcode(0xDE, 0x00); /* DE /0 */
10104 ins_encode( LdImmD(src),
10105 OpcP, RegOpc(dst));
10106 ins_pipe( fpu_reg_mem );
10107 %}
10109 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
10110 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
10111 match(Set dst (RoundDouble (AddD src con)));
10112 ins_cost(200);
10113 format %{ "FLD_D [$con]\n\t"
10114 "DADD ST,$src\n\t"
10115 "FSTP_D $dst\t# D-round" %}
10116 opcode(0xD8, 0x00); /* D8 /0 */
10117 ins_encode( LdImmD(con),
10118 OpcP, RegOpc(src), Pop_Mem_D(dst));
10119 ins_pipe( fpu_mem_reg_con );
10120 %}
10122 // Add two double precision floating point values in xmm
10123 instruct addXD_reg(regXD dst, regXD src) %{
10124 predicate(UseSSE>=2);
10125 match(Set dst (AddD dst src));
10126 format %{ "ADDSD $dst,$src" %}
10127 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10128 ins_pipe( pipe_slow );
10129 %}
10131 instruct addXD_imm(regXD dst, immXD con) %{
10132 predicate(UseSSE>=2);
10133 match(Set dst (AddD dst con));
10134 format %{ "ADDSD $dst,[$con]" %}
10135 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) );
10136 ins_pipe( pipe_slow );
10137 %}
10139 instruct addXD_mem(regXD dst, memory mem) %{
10140 predicate(UseSSE>=2);
10141 match(Set dst (AddD dst (LoadD mem)));
10142 format %{ "ADDSD $dst,$mem" %}
10143 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem));
10144 ins_pipe( pipe_slow );
10145 %}
10147 // Sub two double precision floating point values in xmm
10148 instruct subXD_reg(regXD dst, regXD src) %{
10149 predicate(UseSSE>=2);
10150 match(Set dst (SubD dst src));
10151 format %{ "SUBSD $dst,$src" %}
10152 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10153 ins_pipe( pipe_slow );
10154 %}
10156 instruct subXD_imm(regXD dst, immXD con) %{
10157 predicate(UseSSE>=2);
10158 match(Set dst (SubD dst con));
10159 format %{ "SUBSD $dst,[$con]" %}
10160 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) );
10161 ins_pipe( pipe_slow );
10162 %}
10164 instruct subXD_mem(regXD dst, memory mem) %{
10165 predicate(UseSSE>=2);
10166 match(Set dst (SubD dst (LoadD mem)));
10167 format %{ "SUBSD $dst,$mem" %}
10168 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10169 ins_pipe( pipe_slow );
10170 %}
10172 // Mul two double precision floating point values in xmm
10173 instruct mulXD_reg(regXD dst, regXD src) %{
10174 predicate(UseSSE>=2);
10175 match(Set dst (MulD dst src));
10176 format %{ "MULSD $dst,$src" %}
10177 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10178 ins_pipe( pipe_slow );
10179 %}
10181 instruct mulXD_imm(regXD dst, immXD con) %{
10182 predicate(UseSSE>=2);
10183 match(Set dst (MulD dst con));
10184 format %{ "MULSD $dst,[$con]" %}
10185 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) );
10186 ins_pipe( pipe_slow );
10187 %}
10189 instruct mulXD_mem(regXD dst, memory mem) %{
10190 predicate(UseSSE>=2);
10191 match(Set dst (MulD dst (LoadD mem)));
10192 format %{ "MULSD $dst,$mem" %}
10193 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10194 ins_pipe( pipe_slow );
10195 %}
10197 // Div two double precision floating point values in xmm
10198 instruct divXD_reg(regXD dst, regXD src) %{
10199 predicate(UseSSE>=2);
10200 match(Set dst (DivD dst src));
10201 format %{ "DIVSD $dst,$src" %}
10202 opcode(0xF2, 0x0F, 0x5E);
10203 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10204 ins_pipe( pipe_slow );
10205 %}
10207 instruct divXD_imm(regXD dst, immXD con) %{
10208 predicate(UseSSE>=2);
10209 match(Set dst (DivD dst con));
10210 format %{ "DIVSD $dst,[$con]" %}
10211 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con));
10212 ins_pipe( pipe_slow );
10213 %}
10215 instruct divXD_mem(regXD dst, memory mem) %{
10216 predicate(UseSSE>=2);
10217 match(Set dst (DivD dst (LoadD mem)));
10218 format %{ "DIVSD $dst,$mem" %}
10219 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10220 ins_pipe( pipe_slow );
10221 %}
10224 instruct mulD_reg(regD dst, regD src) %{
10225 predicate(UseSSE<=1);
10226 match(Set dst (MulD dst src));
10227 format %{ "FLD $src\n\t"
10228 "DMULp $dst,ST" %}
10229 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10230 ins_cost(150);
10231 ins_encode( Push_Reg_D(src),
10232 OpcP, RegOpc(dst) );
10233 ins_pipe( fpu_reg_reg );
10234 %}
10236 // Strict FP instruction biases argument before multiply then
10237 // biases result to avoid double rounding of subnormals.
10238 //
10239 // scale arg1 by multiplying arg1 by 2^(-15360)
10240 // load arg2
10241 // multiply scaled arg1 by arg2
10242 // rescale product by 2^(15360)
10243 //
10244 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
10245 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10246 match(Set dst (MulD dst src));
10247 ins_cost(1); // Select this instruction for all strict FP double multiplies
10249 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10250 "DMULp $dst,ST\n\t"
10251 "FLD $src\n\t"
10252 "DMULp $dst,ST\n\t"
10253 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10254 "DMULp $dst,ST\n\t" %}
10255 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10256 ins_encode( strictfp_bias1(dst),
10257 Push_Reg_D(src),
10258 OpcP, RegOpc(dst),
10259 strictfp_bias2(dst) );
10260 ins_pipe( fpu_reg_reg );
10261 %}
10263 instruct mulD_reg_imm(regD dst, immD src) %{
10264 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10265 match(Set dst (MulD dst src));
10266 ins_cost(200);
10267 format %{ "FLD_D [$src]\n\t"
10268 "DMULp $dst,ST" %}
10269 opcode(0xDE, 0x1); /* DE /1 */
10270 ins_encode( LdImmD(src),
10271 OpcP, RegOpc(dst) );
10272 ins_pipe( fpu_reg_mem );
10273 %}
10276 instruct mulD_reg_mem(regD dst, memory src) %{
10277 predicate( UseSSE<=1 );
10278 match(Set dst (MulD dst (LoadD src)));
10279 ins_cost(200);
10280 format %{ "FLD_D $src\n\t"
10281 "DMULp $dst,ST" %}
10282 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
10283 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10284 OpcP, RegOpc(dst) );
10285 ins_pipe( fpu_reg_mem );
10286 %}
10288 //
10289 // Cisc-alternate to reg-reg multiply
10290 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
10291 predicate( UseSSE<=1 );
10292 match(Set dst (MulD src (LoadD mem)));
10293 ins_cost(250);
10294 format %{ "FLD_D $mem\n\t"
10295 "DMUL ST,$src\n\t"
10296 "FSTP_D $dst" %}
10297 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
10298 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
10299 OpcReg_F(src),
10300 Pop_Reg_D(dst) );
10301 ins_pipe( fpu_reg_reg_mem );
10302 %}
10305 // MACRO3 -- addD a mulD
10306 // This instruction is a '2-address' instruction in that the result goes
10307 // back to src2. This eliminates a move from the macro; possibly the
10308 // register allocator will have to add it back (and maybe not).
10309 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
10310 predicate( UseSSE<=1 );
10311 match(Set src2 (AddD (MulD src0 src1) src2));
10312 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10313 "DMUL ST,$src1\n\t"
10314 "DADDp $src2,ST" %}
10315 ins_cost(250);
10316 opcode(0xDD); /* LoadD DD /0 */
10317 ins_encode( Push_Reg_F(src0),
10318 FMul_ST_reg(src1),
10319 FAddP_reg_ST(src2) );
10320 ins_pipe( fpu_reg_reg_reg );
10321 %}
10324 // MACRO3 -- subD a mulD
10325 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
10326 predicate( UseSSE<=1 );
10327 match(Set src2 (SubD (MulD src0 src1) src2));
10328 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10329 "DMUL ST,$src1\n\t"
10330 "DSUBRp $src2,ST" %}
10331 ins_cost(250);
10332 ins_encode( Push_Reg_F(src0),
10333 FMul_ST_reg(src1),
10334 Opcode(0xDE), Opc_plus(0xE0,src2));
10335 ins_pipe( fpu_reg_reg_reg );
10336 %}
10339 instruct divD_reg(regD dst, regD src) %{
10340 predicate( UseSSE<=1 );
10341 match(Set dst (DivD dst src));
10343 format %{ "FLD $src\n\t"
10344 "FDIVp $dst,ST" %}
10345 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10346 ins_cost(150);
10347 ins_encode( Push_Reg_D(src),
10348 OpcP, RegOpc(dst) );
10349 ins_pipe( fpu_reg_reg );
10350 %}
10352 // Strict FP instruction biases argument before division then
10353 // biases result, to avoid double rounding of subnormals.
10354 //
10355 // scale dividend by multiplying dividend by 2^(-15360)
10356 // load divisor
10357 // divide scaled dividend by divisor
10358 // rescale quotient by 2^(15360)
10359 //
10360 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
10361 predicate (UseSSE<=1);
10362 match(Set dst (DivD dst src));
10363 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10364 ins_cost(01);
10366 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10367 "DMULp $dst,ST\n\t"
10368 "FLD $src\n\t"
10369 "FDIVp $dst,ST\n\t"
10370 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10371 "DMULp $dst,ST\n\t" %}
10372 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10373 ins_encode( strictfp_bias1(dst),
10374 Push_Reg_D(src),
10375 OpcP, RegOpc(dst),
10376 strictfp_bias2(dst) );
10377 ins_pipe( fpu_reg_reg );
10378 %}
10380 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10381 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
10382 match(Set dst (RoundDouble (DivD src1 src2)));
10384 format %{ "FLD $src1\n\t"
10385 "FDIV ST,$src2\n\t"
10386 "FSTP_D $dst\t# D-round" %}
10387 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10388 ins_encode( Push_Reg_D(src1),
10389 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
10390 ins_pipe( fpu_mem_reg_reg );
10391 %}
10394 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
10395 predicate(UseSSE<=1);
10396 match(Set dst (ModD dst src));
10397 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10399 format %{ "DMOD $dst,$src" %}
10400 ins_cost(250);
10401 ins_encode(Push_Reg_Mod_D(dst, src),
10402 emitModD(),
10403 Push_Result_Mod_D(src),
10404 Pop_Reg_D(dst));
10405 ins_pipe( pipe_slow );
10406 %}
10408 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
10409 predicate(UseSSE>=2);
10410 match(Set dst (ModD src0 src1));
10411 effect(KILL rax, KILL cr);
10413 format %{ "SUB ESP,8\t # DMOD\n"
10414 "\tMOVSD [ESP+0],$src1\n"
10415 "\tFLD_D [ESP+0]\n"
10416 "\tMOVSD [ESP+0],$src0\n"
10417 "\tFLD_D [ESP+0]\n"
10418 "loop:\tFPREM\n"
10419 "\tFWAIT\n"
10420 "\tFNSTSW AX\n"
10421 "\tSAHF\n"
10422 "\tJP loop\n"
10423 "\tFSTP_D [ESP+0]\n"
10424 "\tMOVSD $dst,[ESP+0]\n"
10425 "\tADD ESP,8\n"
10426 "\tFSTP ST0\t # Restore FPU Stack"
10427 %}
10428 ins_cost(250);
10429 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
10430 ins_pipe( pipe_slow );
10431 %}
10433 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
10434 predicate (UseSSE<=1);
10435 match(Set dst (SinD src));
10436 ins_cost(1800);
10437 format %{ "DSIN $dst" %}
10438 opcode(0xD9, 0xFE);
10439 ins_encode( OpcP, OpcS );
10440 ins_pipe( pipe_slow );
10441 %}
10443 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
10444 predicate (UseSSE>=2);
10445 match(Set dst (SinD dst));
10446 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10447 ins_cost(1800);
10448 format %{ "DSIN $dst" %}
10449 opcode(0xD9, 0xFE);
10450 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10451 ins_pipe( pipe_slow );
10452 %}
10454 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
10455 predicate (UseSSE<=1);
10456 match(Set dst (CosD src));
10457 ins_cost(1800);
10458 format %{ "DCOS $dst" %}
10459 opcode(0xD9, 0xFF);
10460 ins_encode( OpcP, OpcS );
10461 ins_pipe( pipe_slow );
10462 %}
10464 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
10465 predicate (UseSSE>=2);
10466 match(Set dst (CosD dst));
10467 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10468 ins_cost(1800);
10469 format %{ "DCOS $dst" %}
10470 opcode(0xD9, 0xFF);
10471 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10472 ins_pipe( pipe_slow );
10473 %}
10475 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
10476 predicate (UseSSE<=1);
10477 match(Set dst(TanD src));
10478 format %{ "DTAN $dst" %}
10479 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10480 Opcode(0xDD), Opcode(0xD8)); // fstp st
10481 ins_pipe( pipe_slow );
10482 %}
10484 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
10485 predicate (UseSSE>=2);
10486 match(Set dst(TanD dst));
10487 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10488 format %{ "DTAN $dst" %}
10489 ins_encode( Push_SrcXD(dst),
10490 Opcode(0xD9), Opcode(0xF2), // fptan
10491 Opcode(0xDD), Opcode(0xD8), // fstp st
10492 Push_ResultXD(dst) );
10493 ins_pipe( pipe_slow );
10494 %}
10496 instruct atanD_reg(regD dst, regD src) %{
10497 predicate (UseSSE<=1);
10498 match(Set dst(AtanD dst src));
10499 format %{ "DATA $dst,$src" %}
10500 opcode(0xD9, 0xF3);
10501 ins_encode( Push_Reg_D(src),
10502 OpcP, OpcS, RegOpc(dst) );
10503 ins_pipe( pipe_slow );
10504 %}
10506 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10507 predicate (UseSSE>=2);
10508 match(Set dst(AtanD dst src));
10509 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10510 format %{ "DATA $dst,$src" %}
10511 opcode(0xD9, 0xF3);
10512 ins_encode( Push_SrcXD(src),
10513 OpcP, OpcS, Push_ResultXD(dst) );
10514 ins_pipe( pipe_slow );
10515 %}
10517 instruct sqrtD_reg(regD dst, regD src) %{
10518 predicate (UseSSE<=1);
10519 match(Set dst (SqrtD src));
10520 format %{ "DSQRT $dst,$src" %}
10521 opcode(0xFA, 0xD9);
10522 ins_encode( Push_Reg_D(src),
10523 OpcS, OpcP, Pop_Reg_D(dst) );
10524 ins_pipe( pipe_slow );
10525 %}
10527 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10528 predicate (UseSSE<=1);
10529 match(Set Y (PowD X Y)); // Raise X to the Yth power
10530 effect(KILL rax, KILL rbx, KILL rcx);
10531 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10532 "FLD_D $X\n\t"
10533 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10535 "FDUP \t\t\t# Q Q\n\t"
10536 "FRNDINT\t\t\t# int(Q) Q\n\t"
10537 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10538 "FISTP dword [ESP]\n\t"
10539 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10540 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10541 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10542 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10543 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10544 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10545 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10546 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10547 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10548 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10549 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10550 "MOV [ESP+0],0\n\t"
10551 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10553 "ADD ESP,8"
10554 %}
10555 ins_encode( push_stack_temp_qword,
10556 Push_Reg_D(X),
10557 Opcode(0xD9), Opcode(0xF1), // fyl2x
10558 pow_exp_core_encoding,
10559 pop_stack_temp_qword);
10560 ins_pipe( pipe_slow );
10561 %}
10563 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
10564 predicate (UseSSE>=2);
10565 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10566 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
10567 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10568 "MOVSD [ESP],$src1\n\t"
10569 "FLD FPR1,$src1\n\t"
10570 "MOVSD [ESP],$src0\n\t"
10571 "FLD FPR1,$src0\n\t"
10572 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10574 "FDUP \t\t\t# Q Q\n\t"
10575 "FRNDINT\t\t\t# int(Q) Q\n\t"
10576 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10577 "FISTP dword [ESP]\n\t"
10578 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10579 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10580 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10581 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10582 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10583 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10584 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10585 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10586 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10587 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10588 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10589 "MOV [ESP+0],0\n\t"
10590 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10592 "FST_D [ESP]\n\t"
10593 "MOVSD $dst,[ESP]\n\t"
10594 "ADD ESP,8"
10595 %}
10596 ins_encode( push_stack_temp_qword,
10597 push_xmm_to_fpr1(src1),
10598 push_xmm_to_fpr1(src0),
10599 Opcode(0xD9), Opcode(0xF1), // fyl2x
10600 pow_exp_core_encoding,
10601 Push_ResultXD(dst) );
10602 ins_pipe( pipe_slow );
10603 %}
10606 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10607 predicate (UseSSE<=1);
10608 match(Set dpr1 (ExpD dpr1));
10609 effect(KILL rax, KILL rbx, KILL rcx);
10610 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
10611 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10612 "FMULP \t\t\t# Q=X*log2(e)\n\t"
10614 "FDUP \t\t\t# Q Q\n\t"
10615 "FRNDINT\t\t\t# int(Q) Q\n\t"
10616 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10617 "FISTP dword [ESP]\n\t"
10618 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10619 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10620 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10621 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10622 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10623 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10624 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10625 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10626 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10627 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10628 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10629 "MOV [ESP+0],0\n\t"
10630 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10632 "ADD ESP,8"
10633 %}
10634 ins_encode( push_stack_temp_qword,
10635 Opcode(0xD9), Opcode(0xEA), // fldl2e
10636 Opcode(0xDE), Opcode(0xC9), // fmulp
10637 pow_exp_core_encoding,
10638 pop_stack_temp_qword);
10639 ins_pipe( pipe_slow );
10640 %}
10642 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10643 predicate (UseSSE>=2);
10644 match(Set dst (ExpD src));
10645 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10646 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10647 "MOVSD [ESP],$src\n\t"
10648 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10649 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10651 "FDUP \t\t\t# Q Q\n\t"
10652 "FRNDINT\t\t\t# int(Q) Q\n\t"
10653 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10654 "FISTP dword [ESP]\n\t"
10655 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10656 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10657 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10658 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10659 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10660 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10661 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10662 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10663 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10664 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10665 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10666 "MOV [ESP+0],0\n\t"
10667 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10669 "FST_D [ESP]\n\t"
10670 "MOVSD $dst,[ESP]\n\t"
10671 "ADD ESP,8"
10672 %}
10673 ins_encode( Push_SrcXD(src),
10674 Opcode(0xD9), Opcode(0xEA), // fldl2e
10675 Opcode(0xDE), Opcode(0xC9), // fmulp
10676 pow_exp_core_encoding,
10677 Push_ResultXD(dst) );
10678 ins_pipe( pipe_slow );
10679 %}
10683 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
10684 predicate (UseSSE<=1);
10685 // The source Double operand on FPU stack
10686 match(Set dst (Log10D src));
10687 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10688 // fxch ; swap ST(0) with ST(1)
10689 // fyl2x ; compute log_10(2) * log_2(x)
10690 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10691 "FXCH \n\t"
10692 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10693 %}
10694 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10695 Opcode(0xD9), Opcode(0xC9), // fxch
10696 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10698 ins_pipe( pipe_slow );
10699 %}
10701 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10702 predicate (UseSSE>=2);
10703 effect(KILL cr);
10704 match(Set dst (Log10D src));
10705 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10706 // fyl2x ; compute log_10(2) * log_2(x)
10707 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10708 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10709 %}
10710 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10711 Push_SrcXD(src),
10712 Opcode(0xD9), Opcode(0xF1), // fyl2x
10713 Push_ResultXD(dst));
10715 ins_pipe( pipe_slow );
10716 %}
10718 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
10719 predicate (UseSSE<=1);
10720 // The source Double operand on FPU stack
10721 match(Set dst (LogD src));
10722 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10723 // fxch ; swap ST(0) with ST(1)
10724 // fyl2x ; compute log_e(2) * log_2(x)
10725 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10726 "FXCH \n\t"
10727 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10728 %}
10729 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10730 Opcode(0xD9), Opcode(0xC9), // fxch
10731 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10733 ins_pipe( pipe_slow );
10734 %}
10736 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10737 predicate (UseSSE>=2);
10738 effect(KILL cr);
10739 // The source and result Double operands in XMM registers
10740 match(Set dst (LogD src));
10741 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10742 // fyl2x ; compute log_e(2) * log_2(x)
10743 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10744 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10745 %}
10746 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10747 Push_SrcXD(src),
10748 Opcode(0xD9), Opcode(0xF1), // fyl2x
10749 Push_ResultXD(dst));
10750 ins_pipe( pipe_slow );
10751 %}
10753 //-------------Float Instructions-------------------------------
10754 // Float Math
10756 // Code for float compare:
10757 // fcompp();
10758 // fwait(); fnstsw_ax();
10759 // sahf();
10760 // movl(dst, unordered_result);
10761 // jcc(Assembler::parity, exit);
10762 // movl(dst, less_result);
10763 // jcc(Assembler::below, exit);
10764 // movl(dst, equal_result);
10765 // jcc(Assembler::equal, exit);
10766 // movl(dst, greater_result);
10767 // exit:
10769 // P6 version of float compare, sets condition codes in EFLAGS
10770 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10771 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10772 match(Set cr (CmpF src1 src2));
10773 effect(KILL rax);
10774 ins_cost(150);
10775 format %{ "FLD $src1\n\t"
10776 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10777 "JNP exit\n\t"
10778 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10779 "SAHF\n"
10780 "exit:\tNOP // avoid branch to branch" %}
10781 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10782 ins_encode( Push_Reg_D(src1),
10783 OpcP, RegOpc(src2),
10784 cmpF_P6_fixup );
10785 ins_pipe( pipe_slow );
10786 %}
10788 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{
10789 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10790 match(Set cr (CmpF src1 src2));
10791 ins_cost(100);
10792 format %{ "FLD $src1\n\t"
10793 "FUCOMIP ST,$src2 // P6 instruction" %}
10794 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10795 ins_encode( Push_Reg_D(src1),
10796 OpcP, RegOpc(src2));
10797 ins_pipe( pipe_slow );
10798 %}
10801 // Compare & branch
10802 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10803 predicate(UseSSE == 0);
10804 match(Set cr (CmpF src1 src2));
10805 effect(KILL rax);
10806 ins_cost(200);
10807 format %{ "FLD $src1\n\t"
10808 "FCOMp $src2\n\t"
10809 "FNSTSW AX\n\t"
10810 "TEST AX,0x400\n\t"
10811 "JZ,s flags\n\t"
10812 "MOV AH,1\t# unordered treat as LT\n"
10813 "flags:\tSAHF" %}
10814 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10815 ins_encode( Push_Reg_D(src1),
10816 OpcP, RegOpc(src2),
10817 fpu_flags);
10818 ins_pipe( pipe_slow );
10819 %}
10821 // Compare vs zero into -1,0,1
10822 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
10823 predicate(UseSSE == 0);
10824 match(Set dst (CmpF3 src1 zero));
10825 effect(KILL cr, KILL rax);
10826 ins_cost(280);
10827 format %{ "FTSTF $dst,$src1" %}
10828 opcode(0xE4, 0xD9);
10829 ins_encode( Push_Reg_D(src1),
10830 OpcS, OpcP, PopFPU,
10831 CmpF_Result(dst));
10832 ins_pipe( pipe_slow );
10833 %}
10835 // Compare into -1,0,1
10836 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
10837 predicate(UseSSE == 0);
10838 match(Set dst (CmpF3 src1 src2));
10839 effect(KILL cr, KILL rax);
10840 ins_cost(300);
10841 format %{ "FCMPF $dst,$src1,$src2" %}
10842 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10843 ins_encode( Push_Reg_D(src1),
10844 OpcP, RegOpc(src2),
10845 CmpF_Result(dst));
10846 ins_pipe( pipe_slow );
10847 %}
10849 // float compare and set condition codes in EFLAGS by XMM regs
10850 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{
10851 predicate(UseSSE>=1);
10852 match(Set cr (CmpF dst src));
10853 effect(KILL rax);
10854 ins_cost(145);
10855 format %{ "COMISS $dst,$src\n"
10856 "\tJNP exit\n"
10857 "\tMOV ah,1 // saw a NaN, set CF\n"
10858 "\tSAHF\n"
10859 "exit:\tNOP // avoid branch to branch" %}
10860 opcode(0x0F, 0x2F);
10861 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup);
10862 ins_pipe( pipe_slow );
10863 %}
10865 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{
10866 predicate(UseSSE>=1);
10867 match(Set cr (CmpF dst src));
10868 ins_cost(100);
10869 format %{ "COMISS $dst,$src" %}
10870 opcode(0x0F, 0x2F);
10871 ins_encode(OpcP, OpcS, RegReg(dst, src));
10872 ins_pipe( pipe_slow );
10873 %}
10875 // float compare and set condition codes in EFLAGS by XMM regs
10876 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{
10877 predicate(UseSSE>=1);
10878 match(Set cr (CmpF dst (LoadF src)));
10879 effect(KILL rax);
10880 ins_cost(165);
10881 format %{ "COMISS $dst,$src\n"
10882 "\tJNP exit\n"
10883 "\tMOV ah,1 // saw a NaN, set CF\n"
10884 "\tSAHF\n"
10885 "exit:\tNOP // avoid branch to branch" %}
10886 opcode(0x0F, 0x2F);
10887 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup);
10888 ins_pipe( pipe_slow );
10889 %}
10891 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{
10892 predicate(UseSSE>=1);
10893 match(Set cr (CmpF dst (LoadF src)));
10894 ins_cost(100);
10895 format %{ "COMISS $dst,$src" %}
10896 opcode(0x0F, 0x2F);
10897 ins_encode(OpcP, OpcS, RegMem(dst, src));
10898 ins_pipe( pipe_slow );
10899 %}
10901 // Compare into -1,0,1 in XMM
10902 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{
10903 predicate(UseSSE>=1);
10904 match(Set dst (CmpF3 src1 src2));
10905 effect(KILL cr);
10906 ins_cost(255);
10907 format %{ "XOR $dst,$dst\n"
10908 "\tCOMISS $src1,$src2\n"
10909 "\tJP,s nan\n"
10910 "\tJEQ,s exit\n"
10911 "\tJA,s inc\n"
10912 "nan:\tDEC $dst\n"
10913 "\tJMP,s exit\n"
10914 "inc:\tINC $dst\n"
10915 "exit:"
10916 %}
10917 opcode(0x0F, 0x2F);
10918 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst));
10919 ins_pipe( pipe_slow );
10920 %}
10922 // Compare into -1,0,1 in XMM and memory
10923 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{
10924 predicate(UseSSE>=1);
10925 match(Set dst (CmpF3 src1 (LoadF mem)));
10926 effect(KILL cr);
10927 ins_cost(275);
10928 format %{ "COMISS $src1,$mem\n"
10929 "\tMOV $dst,0\t\t# do not blow flags\n"
10930 "\tJP,s nan\n"
10931 "\tJEQ,s exit\n"
10932 "\tJA,s inc\n"
10933 "nan:\tDEC $dst\n"
10934 "\tJMP,s exit\n"
10935 "inc:\tINC $dst\n"
10936 "exit:"
10937 %}
10938 opcode(0x0F, 0x2F);
10939 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst));
10940 ins_pipe( pipe_slow );
10941 %}
10943 // Spill to obtain 24-bit precision
10944 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
10945 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10946 match(Set dst (SubF src1 src2));
10948 format %{ "FSUB $dst,$src1 - $src2" %}
10949 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10950 ins_encode( Push_Reg_F(src1),
10951 OpcReg_F(src2),
10952 Pop_Mem_F(dst) );
10953 ins_pipe( fpu_mem_reg_reg );
10954 %}
10955 //
10956 // This instruction does not round to 24-bits
10957 instruct subF_reg(regF dst, regF src) %{
10958 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10959 match(Set dst (SubF dst src));
10961 format %{ "FSUB $dst,$src" %}
10962 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10963 ins_encode( Push_Reg_F(src),
10964 OpcP, RegOpc(dst) );
10965 ins_pipe( fpu_reg_reg );
10966 %}
10968 // Spill to obtain 24-bit precision
10969 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
10970 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10971 match(Set dst (AddF src1 src2));
10973 format %{ "FADD $dst,$src1,$src2" %}
10974 opcode(0xD8, 0x0); /* D8 C0+i */
10975 ins_encode( Push_Reg_F(src2),
10976 OpcReg_F(src1),
10977 Pop_Mem_F(dst) );
10978 ins_pipe( fpu_mem_reg_reg );
10979 %}
10980 //
10981 // This instruction does not round to 24-bits
10982 instruct addF_reg(regF dst, regF src) %{
10983 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10984 match(Set dst (AddF dst src));
10986 format %{ "FLD $src\n\t"
10987 "FADDp $dst,ST" %}
10988 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10989 ins_encode( Push_Reg_F(src),
10990 OpcP, RegOpc(dst) );
10991 ins_pipe( fpu_reg_reg );
10992 %}
10994 // Add two single precision floating point values in xmm
10995 instruct addX_reg(regX dst, regX src) %{
10996 predicate(UseSSE>=1);
10997 match(Set dst (AddF dst src));
10998 format %{ "ADDSS $dst,$src" %}
10999 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
11000 ins_pipe( pipe_slow );
11001 %}
11003 instruct addX_imm(regX dst, immXF con) %{
11004 predicate(UseSSE>=1);
11005 match(Set dst (AddF dst con));
11006 format %{ "ADDSS $dst,[$con]" %}
11007 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) );
11008 ins_pipe( pipe_slow );
11009 %}
11011 instruct addX_mem(regX dst, memory mem) %{
11012 predicate(UseSSE>=1);
11013 match(Set dst (AddF dst (LoadF mem)));
11014 format %{ "ADDSS $dst,$mem" %}
11015 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem));
11016 ins_pipe( pipe_slow );
11017 %}
11019 // Subtract two single precision floating point values in xmm
11020 instruct subX_reg(regX dst, regX src) %{
11021 predicate(UseSSE>=1);
11022 match(Set dst (SubF dst src));
11023 format %{ "SUBSS $dst,$src" %}
11024 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
11025 ins_pipe( pipe_slow );
11026 %}
11028 instruct subX_imm(regX dst, immXF con) %{
11029 predicate(UseSSE>=1);
11030 match(Set dst (SubF dst con));
11031 format %{ "SUBSS $dst,[$con]" %}
11032 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) );
11033 ins_pipe( pipe_slow );
11034 %}
11036 instruct subX_mem(regX dst, memory mem) %{
11037 predicate(UseSSE>=1);
11038 match(Set dst (SubF dst (LoadF mem)));
11039 format %{ "SUBSS $dst,$mem" %}
11040 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
11041 ins_pipe( pipe_slow );
11042 %}
11044 // Multiply two single precision floating point values in xmm
11045 instruct mulX_reg(regX dst, regX src) %{
11046 predicate(UseSSE>=1);
11047 match(Set dst (MulF dst src));
11048 format %{ "MULSS $dst,$src" %}
11049 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
11050 ins_pipe( pipe_slow );
11051 %}
11053 instruct mulX_imm(regX dst, immXF con) %{
11054 predicate(UseSSE>=1);
11055 match(Set dst (MulF dst con));
11056 format %{ "MULSS $dst,[$con]" %}
11057 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) );
11058 ins_pipe( pipe_slow );
11059 %}
11061 instruct mulX_mem(regX dst, memory mem) %{
11062 predicate(UseSSE>=1);
11063 match(Set dst (MulF dst (LoadF mem)));
11064 format %{ "MULSS $dst,$mem" %}
11065 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
11066 ins_pipe( pipe_slow );
11067 %}
11069 // Divide two single precision floating point values in xmm
11070 instruct divX_reg(regX dst, regX src) %{
11071 predicate(UseSSE>=1);
11072 match(Set dst (DivF dst src));
11073 format %{ "DIVSS $dst,$src" %}
11074 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
11075 ins_pipe( pipe_slow );
11076 %}
11078 instruct divX_imm(regX dst, immXF con) %{
11079 predicate(UseSSE>=1);
11080 match(Set dst (DivF dst con));
11081 format %{ "DIVSS $dst,[$con]" %}
11082 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) );
11083 ins_pipe( pipe_slow );
11084 %}
11086 instruct divX_mem(regX dst, memory mem) %{
11087 predicate(UseSSE>=1);
11088 match(Set dst (DivF dst (LoadF mem)));
11089 format %{ "DIVSS $dst,$mem" %}
11090 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
11091 ins_pipe( pipe_slow );
11092 %}
11094 // Get the square root of a single precision floating point values in xmm
11095 instruct sqrtX_reg(regX dst, regX src) %{
11096 predicate(UseSSE>=1);
11097 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
11098 format %{ "SQRTSS $dst,$src" %}
11099 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11100 ins_pipe( pipe_slow );
11101 %}
11103 instruct sqrtX_mem(regX dst, memory mem) %{
11104 predicate(UseSSE>=1);
11105 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
11106 format %{ "SQRTSS $dst,$mem" %}
11107 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11108 ins_pipe( pipe_slow );
11109 %}
11111 // Get the square root of a double precision floating point values in xmm
11112 instruct sqrtXD_reg(regXD dst, regXD src) %{
11113 predicate(UseSSE>=2);
11114 match(Set dst (SqrtD src));
11115 format %{ "SQRTSD $dst,$src" %}
11116 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11117 ins_pipe( pipe_slow );
11118 %}
11120 instruct sqrtXD_mem(regXD dst, memory mem) %{
11121 predicate(UseSSE>=2);
11122 match(Set dst (SqrtD (LoadD mem)));
11123 format %{ "SQRTSD $dst,$mem" %}
11124 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11125 ins_pipe( pipe_slow );
11126 %}
11128 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
11129 predicate(UseSSE==0);
11130 match(Set dst (AbsF src));
11131 ins_cost(100);
11132 format %{ "FABS" %}
11133 opcode(0xE1, 0xD9);
11134 ins_encode( OpcS, OpcP );
11135 ins_pipe( fpu_reg_reg );
11136 %}
11138 instruct absX_reg(regX dst ) %{
11139 predicate(UseSSE>=1);
11140 match(Set dst (AbsF dst));
11141 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
11142 ins_encode( AbsXF_encoding(dst));
11143 ins_pipe( pipe_slow );
11144 %}
11146 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
11147 predicate(UseSSE==0);
11148 match(Set dst (NegF src));
11149 ins_cost(100);
11150 format %{ "FCHS" %}
11151 opcode(0xE0, 0xD9);
11152 ins_encode( OpcS, OpcP );
11153 ins_pipe( fpu_reg_reg );
11154 %}
11156 instruct negX_reg( regX dst ) %{
11157 predicate(UseSSE>=1);
11158 match(Set dst (NegF dst));
11159 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
11160 ins_encode( NegXF_encoding(dst));
11161 ins_pipe( pipe_slow );
11162 %}
11164 // Cisc-alternate to addF_reg
11165 // Spill to obtain 24-bit precision
11166 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11167 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11168 match(Set dst (AddF src1 (LoadF src2)));
11170 format %{ "FLD $src2\n\t"
11171 "FADD ST,$src1\n\t"
11172 "FSTP_S $dst" %}
11173 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11174 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11175 OpcReg_F(src1),
11176 Pop_Mem_F(dst) );
11177 ins_pipe( fpu_mem_reg_mem );
11178 %}
11179 //
11180 // Cisc-alternate to addF_reg
11181 // This instruction does not round to 24-bits
11182 instruct addF_reg_mem(regF dst, memory src) %{
11183 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11184 match(Set dst (AddF dst (LoadF src)));
11186 format %{ "FADD $dst,$src" %}
11187 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
11188 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
11189 OpcP, RegOpc(dst) );
11190 ins_pipe( fpu_reg_mem );
11191 %}
11193 // // Following two instructions for _222_mpegaudio
11194 // Spill to obtain 24-bit precision
11195 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
11196 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11197 match(Set dst (AddF src1 src2));
11199 format %{ "FADD $dst,$src1,$src2" %}
11200 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11201 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
11202 OpcReg_F(src2),
11203 Pop_Mem_F(dst) );
11204 ins_pipe( fpu_mem_reg_mem );
11205 %}
11207 // Cisc-spill variant
11208 // Spill to obtain 24-bit precision
11209 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
11210 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11211 match(Set dst (AddF src1 (LoadF src2)));
11213 format %{ "FADD $dst,$src1,$src2 cisc" %}
11214 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11215 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11216 set_instruction_start,
11217 OpcP, RMopc_Mem(secondary,src1),
11218 Pop_Mem_F(dst) );
11219 ins_pipe( fpu_mem_mem_mem );
11220 %}
11222 // Spill to obtain 24-bit precision
11223 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11224 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11225 match(Set dst (AddF src1 src2));
11227 format %{ "FADD $dst,$src1,$src2" %}
11228 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
11229 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11230 set_instruction_start,
11231 OpcP, RMopc_Mem(secondary,src1),
11232 Pop_Mem_F(dst) );
11233 ins_pipe( fpu_mem_mem_mem );
11234 %}
11237 // Spill to obtain 24-bit precision
11238 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11239 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11240 match(Set dst (AddF src1 src2));
11241 format %{ "FLD $src1\n\t"
11242 "FADD $src2\n\t"
11243 "FSTP_S $dst" %}
11244 opcode(0xD8, 0x00); /* D8 /0 */
11245 ins_encode( Push_Reg_F(src1),
11246 Opc_MemImm_F(src2),
11247 Pop_Mem_F(dst));
11248 ins_pipe( fpu_mem_reg_con );
11249 %}
11250 //
11251 // This instruction does not round to 24-bits
11252 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{
11253 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11254 match(Set dst (AddF src1 src2));
11255 format %{ "FLD $src1\n\t"
11256 "FADD $src2\n\t"
11257 "FSTP_S $dst" %}
11258 opcode(0xD8, 0x00); /* D8 /0 */
11259 ins_encode( Push_Reg_F(src1),
11260 Opc_MemImm_F(src2),
11261 Pop_Reg_F(dst));
11262 ins_pipe( fpu_reg_reg_con );
11263 %}
11265 // Spill to obtain 24-bit precision
11266 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
11267 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11268 match(Set dst (MulF src1 src2));
11270 format %{ "FLD $src1\n\t"
11271 "FMUL $src2\n\t"
11272 "FSTP_S $dst" %}
11273 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
11274 ins_encode( Push_Reg_F(src1),
11275 OpcReg_F(src2),
11276 Pop_Mem_F(dst) );
11277 ins_pipe( fpu_mem_reg_reg );
11278 %}
11279 //
11280 // This instruction does not round to 24-bits
11281 instruct mulF_reg(regF dst, regF src1, regF src2) %{
11282 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11283 match(Set dst (MulF src1 src2));
11285 format %{ "FLD $src1\n\t"
11286 "FMUL $src2\n\t"
11287 "FSTP_S $dst" %}
11288 opcode(0xD8, 0x1); /* D8 C8+i */
11289 ins_encode( Push_Reg_F(src2),
11290 OpcReg_F(src1),
11291 Pop_Reg_F(dst) );
11292 ins_pipe( fpu_reg_reg_reg );
11293 %}
11296 // Spill to obtain 24-bit precision
11297 // Cisc-alternate to reg-reg multiply
11298 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11299 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11300 match(Set dst (MulF src1 (LoadF src2)));
11302 format %{ "FLD_S $src2\n\t"
11303 "FMUL $src1\n\t"
11304 "FSTP_S $dst" %}
11305 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
11306 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11307 OpcReg_F(src1),
11308 Pop_Mem_F(dst) );
11309 ins_pipe( fpu_mem_reg_mem );
11310 %}
11311 //
11312 // This instruction does not round to 24-bits
11313 // Cisc-alternate to reg-reg multiply
11314 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
11315 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11316 match(Set dst (MulF src1 (LoadF src2)));
11318 format %{ "FMUL $dst,$src1,$src2" %}
11319 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
11320 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11321 OpcReg_F(src1),
11322 Pop_Reg_F(dst) );
11323 ins_pipe( fpu_reg_reg_mem );
11324 %}
11326 // Spill to obtain 24-bit precision
11327 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11328 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11329 match(Set dst (MulF src1 src2));
11331 format %{ "FMUL $dst,$src1,$src2" %}
11332 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
11333 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11334 set_instruction_start,
11335 OpcP, RMopc_Mem(secondary,src1),
11336 Pop_Mem_F(dst) );
11337 ins_pipe( fpu_mem_mem_mem );
11338 %}
11340 // Spill to obtain 24-bit precision
11341 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11342 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11343 match(Set dst (MulF src1 src2));
11345 format %{ "FMULc $dst,$src1,$src2" %}
11346 opcode(0xD8, 0x1); /* D8 /1*/
11347 ins_encode( Push_Reg_F(src1),
11348 Opc_MemImm_F(src2),
11349 Pop_Mem_F(dst));
11350 ins_pipe( fpu_mem_reg_con );
11351 %}
11352 //
11353 // This instruction does not round to 24-bits
11354 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{
11355 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11356 match(Set dst (MulF src1 src2));
11358 format %{ "FMULc $dst. $src1, $src2" %}
11359 opcode(0xD8, 0x1); /* D8 /1*/
11360 ins_encode( Push_Reg_F(src1),
11361 Opc_MemImm_F(src2),
11362 Pop_Reg_F(dst));
11363 ins_pipe( fpu_reg_reg_con );
11364 %}
11367 //
11368 // MACRO1 -- subsume unshared load into mulF
11369 // This instruction does not round to 24-bits
11370 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
11371 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11372 match(Set dst (MulF (LoadF mem1) src));
11374 format %{ "FLD $mem1 ===MACRO1===\n\t"
11375 "FMUL ST,$src\n\t"
11376 "FSTP $dst" %}
11377 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
11378 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
11379 OpcReg_F(src),
11380 Pop_Reg_F(dst) );
11381 ins_pipe( fpu_reg_reg_mem );
11382 %}
11383 //
11384 // MACRO2 -- addF a mulF which subsumed an unshared load
11385 // This instruction does not round to 24-bits
11386 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
11387 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11388 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
11389 ins_cost(95);
11391 format %{ "FLD $mem1 ===MACRO2===\n\t"
11392 "FMUL ST,$src1 subsume mulF left load\n\t"
11393 "FADD ST,$src2\n\t"
11394 "FSTP $dst" %}
11395 opcode(0xD9); /* LoadF D9 /0 */
11396 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
11397 FMul_ST_reg(src1),
11398 FAdd_ST_reg(src2),
11399 Pop_Reg_F(dst) );
11400 ins_pipe( fpu_reg_mem_reg_reg );
11401 %}
11403 // MACRO3 -- addF a mulF
11404 // This instruction does not round to 24-bits. It is a '2-address'
11405 // instruction in that the result goes back to src2. This eliminates
11406 // a move from the macro; possibly the register allocator will have
11407 // to add it back (and maybe not).
11408 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
11409 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11410 match(Set src2 (AddF (MulF src0 src1) src2));
11412 format %{ "FLD $src0 ===MACRO3===\n\t"
11413 "FMUL ST,$src1\n\t"
11414 "FADDP $src2,ST" %}
11415 opcode(0xD9); /* LoadF D9 /0 */
11416 ins_encode( Push_Reg_F(src0),
11417 FMul_ST_reg(src1),
11418 FAddP_reg_ST(src2) );
11419 ins_pipe( fpu_reg_reg_reg );
11420 %}
11422 // MACRO4 -- divF subF
11423 // This instruction does not round to 24-bits
11424 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
11425 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11426 match(Set dst (DivF (SubF src2 src1) src3));
11428 format %{ "FLD $src2 ===MACRO4===\n\t"
11429 "FSUB ST,$src1\n\t"
11430 "FDIV ST,$src3\n\t"
11431 "FSTP $dst" %}
11432 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11433 ins_encode( Push_Reg_F(src2),
11434 subF_divF_encode(src1,src3),
11435 Pop_Reg_F(dst) );
11436 ins_pipe( fpu_reg_reg_reg_reg );
11437 %}
11439 // Spill to obtain 24-bit precision
11440 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
11441 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11442 match(Set dst (DivF src1 src2));
11444 format %{ "FDIV $dst,$src1,$src2" %}
11445 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
11446 ins_encode( Push_Reg_F(src1),
11447 OpcReg_F(src2),
11448 Pop_Mem_F(dst) );
11449 ins_pipe( fpu_mem_reg_reg );
11450 %}
11451 //
11452 // This instruction does not round to 24-bits
11453 instruct divF_reg(regF dst, regF src) %{
11454 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11455 match(Set dst (DivF dst src));
11457 format %{ "FDIV $dst,$src" %}
11458 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11459 ins_encode( Push_Reg_F(src),
11460 OpcP, RegOpc(dst) );
11461 ins_pipe( fpu_reg_reg );
11462 %}
11465 // Spill to obtain 24-bit precision
11466 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11467 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11468 match(Set dst (ModF src1 src2));
11469 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11471 format %{ "FMOD $dst,$src1,$src2" %}
11472 ins_encode( Push_Reg_Mod_D(src1, src2),
11473 emitModD(),
11474 Push_Result_Mod_D(src2),
11475 Pop_Mem_F(dst));
11476 ins_pipe( pipe_slow );
11477 %}
11478 //
11479 // This instruction does not round to 24-bits
11480 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
11481 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11482 match(Set dst (ModF dst src));
11483 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11485 format %{ "FMOD $dst,$src" %}
11486 ins_encode(Push_Reg_Mod_D(dst, src),
11487 emitModD(),
11488 Push_Result_Mod_D(src),
11489 Pop_Reg_F(dst));
11490 ins_pipe( pipe_slow );
11491 %}
11493 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
11494 predicate(UseSSE>=1);
11495 match(Set dst (ModF src0 src1));
11496 effect(KILL rax, KILL cr);
11497 format %{ "SUB ESP,4\t # FMOD\n"
11498 "\tMOVSS [ESP+0],$src1\n"
11499 "\tFLD_S [ESP+0]\n"
11500 "\tMOVSS [ESP+0],$src0\n"
11501 "\tFLD_S [ESP+0]\n"
11502 "loop:\tFPREM\n"
11503 "\tFWAIT\n"
11504 "\tFNSTSW AX\n"
11505 "\tSAHF\n"
11506 "\tJP loop\n"
11507 "\tFSTP_S [ESP+0]\n"
11508 "\tMOVSS $dst,[ESP+0]\n"
11509 "\tADD ESP,4\n"
11510 "\tFSTP ST0\t # Restore FPU Stack"
11511 %}
11512 ins_cost(250);
11513 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
11514 ins_pipe( pipe_slow );
11515 %}
11518 //----------Arithmetic Conversion Instructions---------------------------------
11519 // The conversions operations are all Alpha sorted. Please keep it that way!
11521 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
11522 predicate(UseSSE==0);
11523 match(Set dst (RoundFloat src));
11524 ins_cost(125);
11525 format %{ "FST_S $dst,$src\t# F-round" %}
11526 ins_encode( Pop_Mem_Reg_F(dst, src) );
11527 ins_pipe( fpu_mem_reg );
11528 %}
11530 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
11531 predicate(UseSSE<=1);
11532 match(Set dst (RoundDouble src));
11533 ins_cost(125);
11534 format %{ "FST_D $dst,$src\t# D-round" %}
11535 ins_encode( Pop_Mem_Reg_D(dst, src) );
11536 ins_pipe( fpu_mem_reg );
11537 %}
11539 // Force rounding to 24-bit precision and 6-bit exponent
11540 instruct convD2F_reg(stackSlotF dst, regD src) %{
11541 predicate(UseSSE==0);
11542 match(Set dst (ConvD2F src));
11543 format %{ "FST_S $dst,$src\t# F-round" %}
11544 expand %{
11545 roundFloat_mem_reg(dst,src);
11546 %}
11547 %}
11549 // Force rounding to 24-bit precision and 6-bit exponent
11550 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
11551 predicate(UseSSE==1);
11552 match(Set dst (ConvD2F src));
11553 effect( KILL cr );
11554 format %{ "SUB ESP,4\n\t"
11555 "FST_S [ESP],$src\t# F-round\n\t"
11556 "MOVSS $dst,[ESP]\n\t"
11557 "ADD ESP,4" %}
11558 ins_encode( D2X_encoding(dst, src) );
11559 ins_pipe( pipe_slow );
11560 %}
11562 // Force rounding double precision to single precision
11563 instruct convXD2X_reg(regX dst, regXD src) %{
11564 predicate(UseSSE>=2);
11565 match(Set dst (ConvD2F src));
11566 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11567 opcode(0xF2, 0x0F, 0x5A);
11568 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11569 ins_pipe( pipe_slow );
11570 %}
11572 instruct convF2D_reg_reg(regD dst, regF src) %{
11573 predicate(UseSSE==0);
11574 match(Set dst (ConvF2D src));
11575 format %{ "FST_S $dst,$src\t# D-round" %}
11576 ins_encode( Pop_Reg_Reg_D(dst, src));
11577 ins_pipe( fpu_reg_reg );
11578 %}
11580 instruct convF2D_reg(stackSlotD dst, regF src) %{
11581 predicate(UseSSE==1);
11582 match(Set dst (ConvF2D src));
11583 format %{ "FST_D $dst,$src\t# D-round" %}
11584 expand %{
11585 roundDouble_mem_reg(dst,src);
11586 %}
11587 %}
11589 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
11590 predicate(UseSSE==1);
11591 match(Set dst (ConvF2D src));
11592 effect( KILL cr );
11593 format %{ "SUB ESP,4\n\t"
11594 "MOVSS [ESP] $src\n\t"
11595 "FLD_S [ESP]\n\t"
11596 "ADD ESP,4\n\t"
11597 "FSTP $dst\t# D-round" %}
11598 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst));
11599 ins_pipe( pipe_slow );
11600 %}
11602 instruct convX2XD_reg(regXD dst, regX src) %{
11603 predicate(UseSSE>=2);
11604 match(Set dst (ConvF2D src));
11605 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11606 opcode(0xF3, 0x0F, 0x5A);
11607 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11608 ins_pipe( pipe_slow );
11609 %}
11611 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11612 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11613 predicate(UseSSE<=1);
11614 match(Set dst (ConvD2I src));
11615 effect( KILL tmp, KILL cr );
11616 format %{ "FLD $src\t# Convert double to int \n\t"
11617 "FLDCW trunc mode\n\t"
11618 "SUB ESP,4\n\t"
11619 "FISTp [ESP + #0]\n\t"
11620 "FLDCW std/24-bit mode\n\t"
11621 "POP EAX\n\t"
11622 "CMP EAX,0x80000000\n\t"
11623 "JNE,s fast\n\t"
11624 "FLD_D $src\n\t"
11625 "CALL d2i_wrapper\n"
11626 "fast:" %}
11627 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
11628 ins_pipe( pipe_slow );
11629 %}
11631 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11632 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
11633 predicate(UseSSE>=2);
11634 match(Set dst (ConvD2I src));
11635 effect( KILL tmp, KILL cr );
11636 format %{ "CVTTSD2SI $dst, $src\n\t"
11637 "CMP $dst,0x80000000\n\t"
11638 "JNE,s fast\n\t"
11639 "SUB ESP, 8\n\t"
11640 "MOVSD [ESP], $src\n\t"
11641 "FLD_D [ESP]\n\t"
11642 "ADD ESP, 8\n\t"
11643 "CALL d2i_wrapper\n"
11644 "fast:" %}
11645 opcode(0x1); // double-precision conversion
11646 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11647 ins_pipe( pipe_slow );
11648 %}
11650 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11651 predicate(UseSSE<=1);
11652 match(Set dst (ConvD2L src));
11653 effect( KILL cr );
11654 format %{ "FLD $src\t# Convert double to long\n\t"
11655 "FLDCW trunc mode\n\t"
11656 "SUB ESP,8\n\t"
11657 "FISTp [ESP + #0]\n\t"
11658 "FLDCW std/24-bit mode\n\t"
11659 "POP EAX\n\t"
11660 "POP EDX\n\t"
11661 "CMP EDX,0x80000000\n\t"
11662 "JNE,s fast\n\t"
11663 "TEST EAX,EAX\n\t"
11664 "JNE,s fast\n\t"
11665 "FLD $src\n\t"
11666 "CALL d2l_wrapper\n"
11667 "fast:" %}
11668 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
11669 ins_pipe( pipe_slow );
11670 %}
11672 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11673 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
11674 predicate (UseSSE>=2);
11675 match(Set dst (ConvD2L src));
11676 effect( KILL cr );
11677 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11678 "MOVSD [ESP],$src\n\t"
11679 "FLD_D [ESP]\n\t"
11680 "FLDCW trunc mode\n\t"
11681 "FISTp [ESP + #0]\n\t"
11682 "FLDCW std/24-bit mode\n\t"
11683 "POP EAX\n\t"
11684 "POP EDX\n\t"
11685 "CMP EDX,0x80000000\n\t"
11686 "JNE,s fast\n\t"
11687 "TEST EAX,EAX\n\t"
11688 "JNE,s fast\n\t"
11689 "SUB ESP,8\n\t"
11690 "MOVSD [ESP],$src\n\t"
11691 "FLD_D [ESP]\n\t"
11692 "CALL d2l_wrapper\n"
11693 "fast:" %}
11694 ins_encode( XD2L_encoding(src) );
11695 ins_pipe( pipe_slow );
11696 %}
11698 // Convert a double to an int. Java semantics require we do complex
11699 // manglations in the corner cases. So we set the rounding mode to
11700 // 'zero', store the darned double down as an int, and reset the
11701 // rounding mode to 'nearest'. The hardware stores a flag value down
11702 // if we would overflow or converted a NAN; we check for this and
11703 // and go the slow path if needed.
11704 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11705 predicate(UseSSE==0);
11706 match(Set dst (ConvF2I src));
11707 effect( KILL tmp, KILL cr );
11708 format %{ "FLD $src\t# Convert float to int \n\t"
11709 "FLDCW trunc mode\n\t"
11710 "SUB ESP,4\n\t"
11711 "FISTp [ESP + #0]\n\t"
11712 "FLDCW std/24-bit mode\n\t"
11713 "POP EAX\n\t"
11714 "CMP EAX,0x80000000\n\t"
11715 "JNE,s fast\n\t"
11716 "FLD $src\n\t"
11717 "CALL d2i_wrapper\n"
11718 "fast:" %}
11719 // D2I_encoding works for F2I
11720 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
11721 ins_pipe( pipe_slow );
11722 %}
11724 // Convert a float in xmm to an int reg.
11725 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
11726 predicate(UseSSE>=1);
11727 match(Set dst (ConvF2I src));
11728 effect( KILL tmp, KILL cr );
11729 format %{ "CVTTSS2SI $dst, $src\n\t"
11730 "CMP $dst,0x80000000\n\t"
11731 "JNE,s fast\n\t"
11732 "SUB ESP, 4\n\t"
11733 "MOVSS [ESP], $src\n\t"
11734 "FLD [ESP]\n\t"
11735 "ADD ESP, 4\n\t"
11736 "CALL d2i_wrapper\n"
11737 "fast:" %}
11738 opcode(0x0); // single-precision conversion
11739 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11740 ins_pipe( pipe_slow );
11741 %}
11743 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11744 predicate(UseSSE==0);
11745 match(Set dst (ConvF2L src));
11746 effect( KILL cr );
11747 format %{ "FLD $src\t# Convert float to long\n\t"
11748 "FLDCW trunc mode\n\t"
11749 "SUB ESP,8\n\t"
11750 "FISTp [ESP + #0]\n\t"
11751 "FLDCW std/24-bit mode\n\t"
11752 "POP EAX\n\t"
11753 "POP EDX\n\t"
11754 "CMP EDX,0x80000000\n\t"
11755 "JNE,s fast\n\t"
11756 "TEST EAX,EAX\n\t"
11757 "JNE,s fast\n\t"
11758 "FLD $src\n\t"
11759 "CALL d2l_wrapper\n"
11760 "fast:" %}
11761 // D2L_encoding works for F2L
11762 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
11763 ins_pipe( pipe_slow );
11764 %}
11766 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11767 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
11768 predicate (UseSSE>=1);
11769 match(Set dst (ConvF2L src));
11770 effect( KILL cr );
11771 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11772 "MOVSS [ESP],$src\n\t"
11773 "FLD_S [ESP]\n\t"
11774 "FLDCW trunc mode\n\t"
11775 "FISTp [ESP + #0]\n\t"
11776 "FLDCW std/24-bit mode\n\t"
11777 "POP EAX\n\t"
11778 "POP EDX\n\t"
11779 "CMP EDX,0x80000000\n\t"
11780 "JNE,s fast\n\t"
11781 "TEST EAX,EAX\n\t"
11782 "JNE,s fast\n\t"
11783 "SUB ESP,4\t# Convert float to long\n\t"
11784 "MOVSS [ESP],$src\n\t"
11785 "FLD_S [ESP]\n\t"
11786 "ADD ESP,4\n\t"
11787 "CALL d2l_wrapper\n"
11788 "fast:" %}
11789 ins_encode( X2L_encoding(src) );
11790 ins_pipe( pipe_slow );
11791 %}
11793 instruct convI2D_reg(regD dst, stackSlotI src) %{
11794 predicate( UseSSE<=1 );
11795 match(Set dst (ConvI2D src));
11796 format %{ "FILD $src\n\t"
11797 "FSTP $dst" %}
11798 opcode(0xDB, 0x0); /* DB /0 */
11799 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
11800 ins_pipe( fpu_reg_mem );
11801 %}
11803 instruct convI2XD_reg(regXD dst, eRegI src) %{
11804 predicate( UseSSE>=2 && !UseXmmI2D );
11805 match(Set dst (ConvI2D src));
11806 format %{ "CVTSI2SD $dst,$src" %}
11807 opcode(0xF2, 0x0F, 0x2A);
11808 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11809 ins_pipe( pipe_slow );
11810 %}
11812 instruct convI2XD_mem(regXD dst, memory mem) %{
11813 predicate( UseSSE>=2 );
11814 match(Set dst (ConvI2D (LoadI mem)));
11815 format %{ "CVTSI2SD $dst,$mem" %}
11816 opcode(0xF2, 0x0F, 0x2A);
11817 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
11818 ins_pipe( pipe_slow );
11819 %}
11821 instruct convXI2XD_reg(regXD dst, eRegI src)
11822 %{
11823 predicate( UseSSE>=2 && UseXmmI2D );
11824 match(Set dst (ConvI2D src));
11826 format %{ "MOVD $dst,$src\n\t"
11827 "CVTDQ2PD $dst,$dst\t# i2d" %}
11828 ins_encode %{
11829 __ movdl($dst$$XMMRegister, $src$$Register);
11830 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11831 %}
11832 ins_pipe(pipe_slow); // XXX
11833 %}
11835 instruct convI2D_mem(regD dst, memory mem) %{
11836 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11837 match(Set dst (ConvI2D (LoadI mem)));
11838 format %{ "FILD $mem\n\t"
11839 "FSTP $dst" %}
11840 opcode(0xDB); /* DB /0 */
11841 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11842 Pop_Reg_D(dst));
11843 ins_pipe( fpu_reg_mem );
11844 %}
11846 // Convert a byte to a float; no rounding step needed.
11847 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
11848 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11849 match(Set dst (ConvI2F src));
11850 format %{ "FILD $src\n\t"
11851 "FSTP $dst" %}
11853 opcode(0xDB, 0x0); /* DB /0 */
11854 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
11855 ins_pipe( fpu_reg_mem );
11856 %}
11858 // In 24-bit mode, force exponent rounding by storing back out
11859 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
11860 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11861 match(Set dst (ConvI2F src));
11862 ins_cost(200);
11863 format %{ "FILD $src\n\t"
11864 "FSTP_S $dst" %}
11865 opcode(0xDB, 0x0); /* DB /0 */
11866 ins_encode( Push_Mem_I(src),
11867 Pop_Mem_F(dst));
11868 ins_pipe( fpu_mem_mem );
11869 %}
11871 // In 24-bit mode, force exponent rounding by storing back out
11872 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
11873 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11874 match(Set dst (ConvI2F (LoadI mem)));
11875 ins_cost(200);
11876 format %{ "FILD $mem\n\t"
11877 "FSTP_S $dst" %}
11878 opcode(0xDB); /* DB /0 */
11879 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11880 Pop_Mem_F(dst));
11881 ins_pipe( fpu_mem_mem );
11882 %}
11884 // This instruction does not round to 24-bits
11885 instruct convI2F_reg(regF dst, stackSlotI src) %{
11886 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11887 match(Set dst (ConvI2F src));
11888 format %{ "FILD $src\n\t"
11889 "FSTP $dst" %}
11890 opcode(0xDB, 0x0); /* DB /0 */
11891 ins_encode( Push_Mem_I(src),
11892 Pop_Reg_F(dst));
11893 ins_pipe( fpu_reg_mem );
11894 %}
11896 // This instruction does not round to 24-bits
11897 instruct convI2F_mem(regF dst, memory mem) %{
11898 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11899 match(Set dst (ConvI2F (LoadI mem)));
11900 format %{ "FILD $mem\n\t"
11901 "FSTP $dst" %}
11902 opcode(0xDB); /* DB /0 */
11903 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11904 Pop_Reg_F(dst));
11905 ins_pipe( fpu_reg_mem );
11906 %}
11908 // Convert an int to a float in xmm; no rounding step needed.
11909 instruct convI2X_reg(regX dst, eRegI src) %{
11910 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11911 match(Set dst (ConvI2F src));
11912 format %{ "CVTSI2SS $dst, $src" %}
11914 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
11915 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11916 ins_pipe( pipe_slow );
11917 %}
11919 instruct convXI2X_reg(regX dst, eRegI src)
11920 %{
11921 predicate( UseSSE>=2 && UseXmmI2F );
11922 match(Set dst (ConvI2F src));
11924 format %{ "MOVD $dst,$src\n\t"
11925 "CVTDQ2PS $dst,$dst\t# i2f" %}
11926 ins_encode %{
11927 __ movdl($dst$$XMMRegister, $src$$Register);
11928 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11929 %}
11930 ins_pipe(pipe_slow); // XXX
11931 %}
11933 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
11934 match(Set dst (ConvI2L src));
11935 effect(KILL cr);
11936 ins_cost(375);
11937 format %{ "MOV $dst.lo,$src\n\t"
11938 "MOV $dst.hi,$src\n\t"
11939 "SAR $dst.hi,31" %}
11940 ins_encode(convert_int_long(dst,src));
11941 ins_pipe( ialu_reg_reg_long );
11942 %}
11944 // Zero-extend convert int to long
11945 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
11946 match(Set dst (AndL (ConvI2L src) mask) );
11947 effect( KILL flags );
11948 ins_cost(250);
11949 format %{ "MOV $dst.lo,$src\n\t"
11950 "XOR $dst.hi,$dst.hi" %}
11951 opcode(0x33); // XOR
11952 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11953 ins_pipe( ialu_reg_reg_long );
11954 %}
11956 // Zero-extend long
11957 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11958 match(Set dst (AndL src mask) );
11959 effect( KILL flags );
11960 ins_cost(250);
11961 format %{ "MOV $dst.lo,$src.lo\n\t"
11962 "XOR $dst.hi,$dst.hi\n\t" %}
11963 opcode(0x33); // XOR
11964 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11965 ins_pipe( ialu_reg_reg_long );
11966 %}
11968 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11969 predicate (UseSSE<=1);
11970 match(Set dst (ConvL2D src));
11971 effect( KILL cr );
11972 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11973 "PUSH $src.lo\n\t"
11974 "FILD ST,[ESP + #0]\n\t"
11975 "ADD ESP,8\n\t"
11976 "FSTP_D $dst\t# D-round" %}
11977 opcode(0xDF, 0x5); /* DF /5 */
11978 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
11979 ins_pipe( pipe_slow );
11980 %}
11982 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
11983 predicate (UseSSE>=2);
11984 match(Set dst (ConvL2D src));
11985 effect( KILL cr );
11986 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11987 "PUSH $src.lo\n\t"
11988 "FILD_D [ESP]\n\t"
11989 "FSTP_D [ESP]\n\t"
11990 "MOVSD $dst,[ESP]\n\t"
11991 "ADD ESP,8" %}
11992 opcode(0xDF, 0x5); /* DF /5 */
11993 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
11994 ins_pipe( pipe_slow );
11995 %}
11997 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
11998 predicate (UseSSE>=1);
11999 match(Set dst (ConvL2F src));
12000 effect( KILL cr );
12001 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
12002 "PUSH $src.lo\n\t"
12003 "FILD_D [ESP]\n\t"
12004 "FSTP_S [ESP]\n\t"
12005 "MOVSS $dst,[ESP]\n\t"
12006 "ADD ESP,8" %}
12007 opcode(0xDF, 0x5); /* DF /5 */
12008 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
12009 ins_pipe( pipe_slow );
12010 %}
12012 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
12013 match(Set dst (ConvL2F src));
12014 effect( KILL cr );
12015 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
12016 "PUSH $src.lo\n\t"
12017 "FILD ST,[ESP + #0]\n\t"
12018 "ADD ESP,8\n\t"
12019 "FSTP_S $dst\t# F-round" %}
12020 opcode(0xDF, 0x5); /* DF /5 */
12021 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
12022 ins_pipe( pipe_slow );
12023 %}
12025 instruct convL2I_reg( eRegI dst, eRegL src ) %{
12026 match(Set dst (ConvL2I src));
12027 effect( DEF dst, USE src );
12028 format %{ "MOV $dst,$src.lo" %}
12029 ins_encode(enc_CopyL_Lo(dst,src));
12030 ins_pipe( ialu_reg_reg );
12031 %}
12034 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
12035 match(Set dst (MoveF2I src));
12036 effect( DEF dst, USE src );
12037 ins_cost(100);
12038 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
12039 opcode(0x8B);
12040 ins_encode( OpcP, RegMem(dst,src));
12041 ins_pipe( ialu_reg_mem );
12042 %}
12044 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
12045 predicate(UseSSE==0);
12046 match(Set dst (MoveF2I src));
12047 effect( DEF dst, USE src );
12049 ins_cost(125);
12050 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
12051 ins_encode( Pop_Mem_Reg_F(dst, src) );
12052 ins_pipe( fpu_mem_reg );
12053 %}
12055 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
12056 predicate(UseSSE>=1);
12057 match(Set dst (MoveF2I src));
12058 effect( DEF dst, USE src );
12060 ins_cost(95);
12061 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
12062 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst));
12063 ins_pipe( pipe_slow );
12064 %}
12066 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
12067 predicate(UseSSE>=2);
12068 match(Set dst (MoveF2I src));
12069 effect( DEF dst, USE src );
12070 ins_cost(85);
12071 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
12072 ins_encode( MovX2I_reg(dst, src));
12073 ins_pipe( pipe_slow );
12074 %}
12076 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
12077 match(Set dst (MoveI2F src));
12078 effect( DEF dst, USE src );
12080 ins_cost(100);
12081 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
12082 opcode(0x89);
12083 ins_encode( OpcPRegSS( dst, src ) );
12084 ins_pipe( ialu_mem_reg );
12085 %}
12088 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
12089 predicate(UseSSE==0);
12090 match(Set dst (MoveI2F src));
12091 effect(DEF dst, USE src);
12093 ins_cost(125);
12094 format %{ "FLD_S $src\n\t"
12095 "FSTP $dst\t# MoveI2F_stack_reg" %}
12096 opcode(0xD9); /* D9 /0, FLD m32real */
12097 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12098 Pop_Reg_F(dst) );
12099 ins_pipe( fpu_reg_mem );
12100 %}
12102 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
12103 predicate(UseSSE>=1);
12104 match(Set dst (MoveI2F src));
12105 effect( DEF dst, USE src );
12107 ins_cost(95);
12108 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
12109 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12110 ins_pipe( pipe_slow );
12111 %}
12113 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
12114 predicate(UseSSE>=2);
12115 match(Set dst (MoveI2F src));
12116 effect( DEF dst, USE src );
12118 ins_cost(85);
12119 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
12120 ins_encode( MovI2X_reg(dst, src) );
12121 ins_pipe( pipe_slow );
12122 %}
12124 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
12125 match(Set dst (MoveD2L src));
12126 effect(DEF dst, USE src);
12128 ins_cost(250);
12129 format %{ "MOV $dst.lo,$src\n\t"
12130 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
12131 opcode(0x8B, 0x8B);
12132 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
12133 ins_pipe( ialu_mem_long_reg );
12134 %}
12136 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
12137 predicate(UseSSE<=1);
12138 match(Set dst (MoveD2L src));
12139 effect(DEF dst, USE src);
12141 ins_cost(125);
12142 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
12143 ins_encode( Pop_Mem_Reg_D(dst, src) );
12144 ins_pipe( fpu_mem_reg );
12145 %}
12147 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
12148 predicate(UseSSE>=2);
12149 match(Set dst (MoveD2L src));
12150 effect(DEF dst, USE src);
12151 ins_cost(95);
12153 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
12154 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst));
12155 ins_pipe( pipe_slow );
12156 %}
12158 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
12159 predicate(UseSSE>=2);
12160 match(Set dst (MoveD2L src));
12161 effect(DEF dst, USE src, TEMP tmp);
12162 ins_cost(85);
12163 format %{ "MOVD $dst.lo,$src\n\t"
12164 "PSHUFLW $tmp,$src,0x4E\n\t"
12165 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
12166 ins_encode( MovXD2L_reg(dst, src, tmp) );
12167 ins_pipe( pipe_slow );
12168 %}
12170 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
12171 match(Set dst (MoveL2D src));
12172 effect(DEF dst, USE src);
12174 ins_cost(200);
12175 format %{ "MOV $dst,$src.lo\n\t"
12176 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
12177 opcode(0x89, 0x89);
12178 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
12179 ins_pipe( ialu_mem_long_reg );
12180 %}
12183 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
12184 predicate(UseSSE<=1);
12185 match(Set dst (MoveL2D src));
12186 effect(DEF dst, USE src);
12187 ins_cost(125);
12189 format %{ "FLD_D $src\n\t"
12190 "FSTP $dst\t# MoveL2D_stack_reg" %}
12191 opcode(0xDD); /* DD /0, FLD m64real */
12192 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12193 Pop_Reg_D(dst) );
12194 ins_pipe( fpu_reg_mem );
12195 %}
12198 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
12199 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
12200 match(Set dst (MoveL2D src));
12201 effect(DEF dst, USE src);
12203 ins_cost(95);
12204 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12205 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12206 ins_pipe( pipe_slow );
12207 %}
12209 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
12210 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
12211 match(Set dst (MoveL2D src));
12212 effect(DEF dst, USE src);
12214 ins_cost(95);
12215 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12216 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src));
12217 ins_pipe( pipe_slow );
12218 %}
12220 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
12221 predicate(UseSSE>=2);
12222 match(Set dst (MoveL2D src));
12223 effect(TEMP dst, USE src, TEMP tmp);
12224 ins_cost(85);
12225 format %{ "MOVD $dst,$src.lo\n\t"
12226 "MOVD $tmp,$src.hi\n\t"
12227 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
12228 ins_encode( MovL2XD_reg(dst, src, tmp) );
12229 ins_pipe( pipe_slow );
12230 %}
12232 // Replicate scalar to packed byte (1 byte) values in xmm
12233 instruct Repl8B_reg(regXD dst, regXD src) %{
12234 predicate(UseSSE>=2);
12235 match(Set dst (Replicate8B src));
12236 format %{ "MOVDQA $dst,$src\n\t"
12237 "PUNPCKLBW $dst,$dst\n\t"
12238 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12239 ins_encode( pshufd_8x8(dst, src));
12240 ins_pipe( pipe_slow );
12241 %}
12243 // Replicate scalar to packed byte (1 byte) values in xmm
12244 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
12245 predicate(UseSSE>=2);
12246 match(Set dst (Replicate8B src));
12247 format %{ "MOVD $dst,$src\n\t"
12248 "PUNPCKLBW $dst,$dst\n\t"
12249 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12250 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
12251 ins_pipe( pipe_slow );
12252 %}
12254 // Replicate scalar zero to packed byte (1 byte) values in xmm
12255 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
12256 predicate(UseSSE>=2);
12257 match(Set dst (Replicate8B zero));
12258 format %{ "PXOR $dst,$dst\t! replicate8B" %}
12259 ins_encode( pxor(dst, dst));
12260 ins_pipe( fpu_reg_reg );
12261 %}
12263 // Replicate scalar to packed shore (2 byte) values in xmm
12264 instruct Repl4S_reg(regXD dst, regXD src) %{
12265 predicate(UseSSE>=2);
12266 match(Set dst (Replicate4S src));
12267 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
12268 ins_encode( pshufd_4x16(dst, src));
12269 ins_pipe( fpu_reg_reg );
12270 %}
12272 // Replicate scalar to packed shore (2 byte) values in xmm
12273 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
12274 predicate(UseSSE>=2);
12275 match(Set dst (Replicate4S src));
12276 format %{ "MOVD $dst,$src\n\t"
12277 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
12278 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12279 ins_pipe( fpu_reg_reg );
12280 %}
12282 // Replicate scalar zero to packed short (2 byte) values in xmm
12283 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
12284 predicate(UseSSE>=2);
12285 match(Set dst (Replicate4S zero));
12286 format %{ "PXOR $dst,$dst\t! replicate4S" %}
12287 ins_encode( pxor(dst, dst));
12288 ins_pipe( fpu_reg_reg );
12289 %}
12291 // Replicate scalar to packed char (2 byte) values in xmm
12292 instruct Repl4C_reg(regXD dst, regXD src) %{
12293 predicate(UseSSE>=2);
12294 match(Set dst (Replicate4C src));
12295 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
12296 ins_encode( pshufd_4x16(dst, src));
12297 ins_pipe( fpu_reg_reg );
12298 %}
12300 // Replicate scalar to packed char (2 byte) values in xmm
12301 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
12302 predicate(UseSSE>=2);
12303 match(Set dst (Replicate4C src));
12304 format %{ "MOVD $dst,$src\n\t"
12305 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
12306 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12307 ins_pipe( fpu_reg_reg );
12308 %}
12310 // Replicate scalar zero to packed char (2 byte) values in xmm
12311 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
12312 predicate(UseSSE>=2);
12313 match(Set dst (Replicate4C zero));
12314 format %{ "PXOR $dst,$dst\t! replicate4C" %}
12315 ins_encode( pxor(dst, dst));
12316 ins_pipe( fpu_reg_reg );
12317 %}
12319 // Replicate scalar to packed integer (4 byte) values in xmm
12320 instruct Repl2I_reg(regXD dst, regXD src) %{
12321 predicate(UseSSE>=2);
12322 match(Set dst (Replicate2I src));
12323 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
12324 ins_encode( pshufd(dst, src, 0x00));
12325 ins_pipe( fpu_reg_reg );
12326 %}
12328 // Replicate scalar to packed integer (4 byte) values in xmm
12329 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
12330 predicate(UseSSE>=2);
12331 match(Set dst (Replicate2I src));
12332 format %{ "MOVD $dst,$src\n\t"
12333 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
12334 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
12335 ins_pipe( fpu_reg_reg );
12336 %}
12338 // Replicate scalar zero to packed integer (2 byte) values in xmm
12339 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
12340 predicate(UseSSE>=2);
12341 match(Set dst (Replicate2I zero));
12342 format %{ "PXOR $dst,$dst\t! replicate2I" %}
12343 ins_encode( pxor(dst, dst));
12344 ins_pipe( fpu_reg_reg );
12345 %}
12347 // Replicate scalar to packed single precision floating point values in xmm
12348 instruct Repl2F_reg(regXD dst, regXD src) %{
12349 predicate(UseSSE>=2);
12350 match(Set dst (Replicate2F src));
12351 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12352 ins_encode( pshufd(dst, src, 0xe0));
12353 ins_pipe( fpu_reg_reg );
12354 %}
12356 // Replicate scalar to packed single precision floating point values in xmm
12357 instruct Repl2F_regX(regXD dst, regX src) %{
12358 predicate(UseSSE>=2);
12359 match(Set dst (Replicate2F src));
12360 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12361 ins_encode( pshufd(dst, src, 0xe0));
12362 ins_pipe( fpu_reg_reg );
12363 %}
12365 // Replicate scalar to packed single precision floating point values in xmm
12366 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
12367 predicate(UseSSE>=2);
12368 match(Set dst (Replicate2F zero));
12369 format %{ "PXOR $dst,$dst\t! replicate2F" %}
12370 ins_encode( pxor(dst, dst));
12371 ins_pipe( fpu_reg_reg );
12372 %}
12374 // =======================================================================
12375 // fast clearing of an array
12376 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
12377 match(Set dummy (ClearArray cnt base));
12378 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12379 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
12380 "XOR EAX,EAX\n\t"
12381 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
12382 opcode(0,0x4);
12383 ins_encode( Opcode(0xD1), RegOpc(ECX),
12384 OpcRegReg(0x33,EAX,EAX),
12385 Opcode(0xF3), Opcode(0xAB) );
12386 ins_pipe( pipe_slow );
12387 %}
12389 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eBXRegI cnt2,
12390 eAXRegI result, regXD tmp1, regXD tmp2, eFlagsReg cr) %{
12391 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12392 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12394 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1, $tmp2" %}
12395 ins_encode %{
12396 __ string_compare($str1$$Register, $str2$$Register,
12397 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12398 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12399 %}
12400 ins_pipe( pipe_slow );
12401 %}
12403 // fast string equals
12404 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
12405 regXD tmp1, regXD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
12406 match(Set result (StrEquals (Binary str1 str2) cnt));
12407 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12409 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12410 ins_encode %{
12411 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
12412 $cnt$$Register, $result$$Register, $tmp3$$Register,
12413 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12414 %}
12415 ins_pipe( pipe_slow );
12416 %}
12418 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
12419 eBXRegI result, regXD tmp1, eCXRegI tmp2, eFlagsReg cr) %{
12420 predicate(UseSSE42Intrinsics);
12421 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12422 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp2, KILL cr);
12424 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp2, $tmp1" %}
12425 ins_encode %{
12426 __ string_indexof($str1$$Register, $str2$$Register,
12427 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12428 $tmp1$$XMMRegister, $tmp2$$Register);
12429 %}
12430 ins_pipe( pipe_slow );
12431 %}
12433 // fast array equals
12434 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
12435 regXD tmp1, regXD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
12436 %{
12437 match(Set result (AryEq ary1 ary2));
12438 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12439 //ins_cost(300);
12441 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12442 ins_encode %{
12443 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
12444 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12445 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12446 %}
12447 ins_pipe( pipe_slow );
12448 %}
12450 //----------Control Flow Instructions------------------------------------------
12451 // Signed compare Instructions
12452 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
12453 match(Set cr (CmpI op1 op2));
12454 effect( DEF cr, USE op1, USE op2 );
12455 format %{ "CMP $op1,$op2" %}
12456 opcode(0x3B); /* Opcode 3B /r */
12457 ins_encode( OpcP, RegReg( op1, op2) );
12458 ins_pipe( ialu_cr_reg_reg );
12459 %}
12461 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
12462 match(Set cr (CmpI op1 op2));
12463 effect( DEF cr, USE op1 );
12464 format %{ "CMP $op1,$op2" %}
12465 opcode(0x81,0x07); /* Opcode 81 /7 */
12466 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12467 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12468 ins_pipe( ialu_cr_reg_imm );
12469 %}
12471 // Cisc-spilled version of cmpI_eReg
12472 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
12473 match(Set cr (CmpI op1 (LoadI op2)));
12475 format %{ "CMP $op1,$op2" %}
12476 ins_cost(500);
12477 opcode(0x3B); /* Opcode 3B /r */
12478 ins_encode( OpcP, RegMem( op1, op2) );
12479 ins_pipe( ialu_cr_reg_mem );
12480 %}
12482 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
12483 match(Set cr (CmpI src zero));
12484 effect( DEF cr, USE src );
12486 format %{ "TEST $src,$src" %}
12487 opcode(0x85);
12488 ins_encode( OpcP, RegReg( src, src ) );
12489 ins_pipe( ialu_cr_reg_imm );
12490 %}
12492 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
12493 match(Set cr (CmpI (AndI src con) zero));
12495 format %{ "TEST $src,$con" %}
12496 opcode(0xF7,0x00);
12497 ins_encode( OpcP, RegOpc(src), Con32(con) );
12498 ins_pipe( ialu_cr_reg_imm );
12499 %}
12501 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
12502 match(Set cr (CmpI (AndI src mem) zero));
12504 format %{ "TEST $src,$mem" %}
12505 opcode(0x85);
12506 ins_encode( OpcP, RegMem( src, mem ) );
12507 ins_pipe( ialu_cr_reg_mem );
12508 %}
12510 // Unsigned compare Instructions; really, same as signed except they
12511 // produce an eFlagsRegU instead of eFlagsReg.
12512 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12513 match(Set cr (CmpU op1 op2));
12515 format %{ "CMPu $op1,$op2" %}
12516 opcode(0x3B); /* Opcode 3B /r */
12517 ins_encode( OpcP, RegReg( op1, op2) );
12518 ins_pipe( ialu_cr_reg_reg );
12519 %}
12521 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12522 match(Set cr (CmpU op1 op2));
12524 format %{ "CMPu $op1,$op2" %}
12525 opcode(0x81,0x07); /* Opcode 81 /7 */
12526 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12527 ins_pipe( ialu_cr_reg_imm );
12528 %}
12530 // // Cisc-spilled version of cmpU_eReg
12531 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12532 match(Set cr (CmpU op1 (LoadI op2)));
12534 format %{ "CMPu $op1,$op2" %}
12535 ins_cost(500);
12536 opcode(0x3B); /* Opcode 3B /r */
12537 ins_encode( OpcP, RegMem( op1, op2) );
12538 ins_pipe( ialu_cr_reg_mem );
12539 %}
12541 // // Cisc-spilled version of cmpU_eReg
12542 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12543 // match(Set cr (CmpU (LoadI op1) op2));
12544 //
12545 // format %{ "CMPu $op1,$op2" %}
12546 // ins_cost(500);
12547 // opcode(0x39); /* Opcode 39 /r */
12548 // ins_encode( OpcP, RegMem( op1, op2) );
12549 //%}
12551 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12552 match(Set cr (CmpU src zero));
12554 format %{ "TESTu $src,$src" %}
12555 opcode(0x85);
12556 ins_encode( OpcP, RegReg( src, src ) );
12557 ins_pipe( ialu_cr_reg_imm );
12558 %}
12560 // Unsigned pointer compare Instructions
12561 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12562 match(Set cr (CmpP op1 op2));
12564 format %{ "CMPu $op1,$op2" %}
12565 opcode(0x3B); /* Opcode 3B /r */
12566 ins_encode( OpcP, RegReg( op1, op2) );
12567 ins_pipe( ialu_cr_reg_reg );
12568 %}
12570 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12571 match(Set cr (CmpP op1 op2));
12573 format %{ "CMPu $op1,$op2" %}
12574 opcode(0x81,0x07); /* Opcode 81 /7 */
12575 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12576 ins_pipe( ialu_cr_reg_imm );
12577 %}
12579 // // Cisc-spilled version of cmpP_eReg
12580 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12581 match(Set cr (CmpP op1 (LoadP op2)));
12583 format %{ "CMPu $op1,$op2" %}
12584 ins_cost(500);
12585 opcode(0x3B); /* Opcode 3B /r */
12586 ins_encode( OpcP, RegMem( op1, op2) );
12587 ins_pipe( ialu_cr_reg_mem );
12588 %}
12590 // // Cisc-spilled version of cmpP_eReg
12591 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12592 // match(Set cr (CmpP (LoadP op1) op2));
12593 //
12594 // format %{ "CMPu $op1,$op2" %}
12595 // ins_cost(500);
12596 // opcode(0x39); /* Opcode 39 /r */
12597 // ins_encode( OpcP, RegMem( op1, op2) );
12598 //%}
12600 // Compare raw pointer (used in out-of-heap check).
12601 // Only works because non-oop pointers must be raw pointers
12602 // and raw pointers have no anti-dependencies.
12603 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12604 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12605 match(Set cr (CmpP op1 (LoadP op2)));
12607 format %{ "CMPu $op1,$op2" %}
12608 opcode(0x3B); /* Opcode 3B /r */
12609 ins_encode( OpcP, RegMem( op1, op2) );
12610 ins_pipe( ialu_cr_reg_mem );
12611 %}
12613 //
12614 // This will generate a signed flags result. This should be ok
12615 // since any compare to a zero should be eq/neq.
12616 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12617 match(Set cr (CmpP src zero));
12619 format %{ "TEST $src,$src" %}
12620 opcode(0x85);
12621 ins_encode( OpcP, RegReg( src, src ) );
12622 ins_pipe( ialu_cr_reg_imm );
12623 %}
12625 // Cisc-spilled version of testP_reg
12626 // This will generate a signed flags result. This should be ok
12627 // since any compare to a zero should be eq/neq.
12628 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12629 match(Set cr (CmpP (LoadP op) zero));
12631 format %{ "TEST $op,0xFFFFFFFF" %}
12632 ins_cost(500);
12633 opcode(0xF7); /* Opcode F7 /0 */
12634 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12635 ins_pipe( ialu_cr_reg_imm );
12636 %}
12638 // Yanked all unsigned pointer compare operations.
12639 // Pointer compares are done with CmpP which is already unsigned.
12641 //----------Max and Min--------------------------------------------------------
12642 // Min Instructions
12643 ////
12644 // *** Min and Max using the conditional move are slower than the
12645 // *** branch version on a Pentium III.
12646 // // Conditional move for min
12647 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12648 // effect( USE_DEF op2, USE op1, USE cr );
12649 // format %{ "CMOVlt $op2,$op1\t! min" %}
12650 // opcode(0x4C,0x0F);
12651 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12652 // ins_pipe( pipe_cmov_reg );
12653 //%}
12654 //
12655 //// Min Register with Register (P6 version)
12656 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12657 // predicate(VM_Version::supports_cmov() );
12658 // match(Set op2 (MinI op1 op2));
12659 // ins_cost(200);
12660 // expand %{
12661 // eFlagsReg cr;
12662 // compI_eReg(cr,op1,op2);
12663 // cmovI_reg_lt(op2,op1,cr);
12664 // %}
12665 //%}
12667 // Min Register with Register (generic version)
12668 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12669 match(Set dst (MinI dst src));
12670 effect(KILL flags);
12671 ins_cost(300);
12673 format %{ "MIN $dst,$src" %}
12674 opcode(0xCC);
12675 ins_encode( min_enc(dst,src) );
12676 ins_pipe( pipe_slow );
12677 %}
12679 // Max Register with Register
12680 // *** Min and Max using the conditional move are slower than the
12681 // *** branch version on a Pentium III.
12682 // // Conditional move for max
12683 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12684 // effect( USE_DEF op2, USE op1, USE cr );
12685 // format %{ "CMOVgt $op2,$op1\t! max" %}
12686 // opcode(0x4F,0x0F);
12687 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12688 // ins_pipe( pipe_cmov_reg );
12689 //%}
12690 //
12691 // // Max Register with Register (P6 version)
12692 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12693 // predicate(VM_Version::supports_cmov() );
12694 // match(Set op2 (MaxI op1 op2));
12695 // ins_cost(200);
12696 // expand %{
12697 // eFlagsReg cr;
12698 // compI_eReg(cr,op1,op2);
12699 // cmovI_reg_gt(op2,op1,cr);
12700 // %}
12701 //%}
12703 // Max Register with Register (generic version)
12704 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12705 match(Set dst (MaxI dst src));
12706 effect(KILL flags);
12707 ins_cost(300);
12709 format %{ "MAX $dst,$src" %}
12710 opcode(0xCC);
12711 ins_encode( max_enc(dst,src) );
12712 ins_pipe( pipe_slow );
12713 %}
12715 // ============================================================================
12716 // Branch Instructions
12717 // Jump Table
12718 instruct jumpXtnd(eRegI switch_val) %{
12719 match(Jump switch_val);
12720 ins_cost(350);
12722 format %{ "JMP [table_base](,$switch_val,1)\n\t" %}
12724 ins_encode %{
12725 address table_base = __ address_table_constant(_index2label);
12727 // Jump to Address(table_base + switch_reg)
12728 InternalAddress table(table_base);
12729 Address index(noreg, $switch_val$$Register, Address::times_1);
12730 __ jump(ArrayAddress(table, index));
12731 %}
12732 ins_pc_relative(1);
12733 ins_pipe(pipe_jmp);
12734 %}
12736 // Jump Direct - Label defines a relative address from JMP+1
12737 instruct jmpDir(label labl) %{
12738 match(Goto);
12739 effect(USE labl);
12741 ins_cost(300);
12742 format %{ "JMP $labl" %}
12743 size(5);
12744 opcode(0xE9);
12745 ins_encode( OpcP, Lbl( labl ) );
12746 ins_pipe( pipe_jmp );
12747 ins_pc_relative(1);
12748 %}
12750 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12751 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12752 match(If cop cr);
12753 effect(USE labl);
12755 ins_cost(300);
12756 format %{ "J$cop $labl" %}
12757 size(6);
12758 opcode(0x0F, 0x80);
12759 ins_encode( Jcc( cop, labl) );
12760 ins_pipe( pipe_jcc );
12761 ins_pc_relative(1);
12762 %}
12764 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12765 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12766 match(CountedLoopEnd cop cr);
12767 effect(USE labl);
12769 ins_cost(300);
12770 format %{ "J$cop $labl\t# Loop end" %}
12771 size(6);
12772 opcode(0x0F, 0x80);
12773 ins_encode( Jcc( cop, labl) );
12774 ins_pipe( pipe_jcc );
12775 ins_pc_relative(1);
12776 %}
12778 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12779 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12780 match(CountedLoopEnd cop cmp);
12781 effect(USE labl);
12783 ins_cost(300);
12784 format %{ "J$cop,u $labl\t# Loop end" %}
12785 size(6);
12786 opcode(0x0F, 0x80);
12787 ins_encode( Jcc( cop, labl) );
12788 ins_pipe( pipe_jcc );
12789 ins_pc_relative(1);
12790 %}
12792 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12793 match(CountedLoopEnd cop cmp);
12794 effect(USE labl);
12796 ins_cost(200);
12797 format %{ "J$cop,u $labl\t# Loop end" %}
12798 size(6);
12799 opcode(0x0F, 0x80);
12800 ins_encode( Jcc( cop, labl) );
12801 ins_pipe( pipe_jcc );
12802 ins_pc_relative(1);
12803 %}
12805 // Jump Direct Conditional - using unsigned comparison
12806 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12807 match(If cop cmp);
12808 effect(USE labl);
12810 ins_cost(300);
12811 format %{ "J$cop,u $labl" %}
12812 size(6);
12813 opcode(0x0F, 0x80);
12814 ins_encode(Jcc(cop, labl));
12815 ins_pipe(pipe_jcc);
12816 ins_pc_relative(1);
12817 %}
12819 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12820 match(If cop cmp);
12821 effect(USE labl);
12823 ins_cost(200);
12824 format %{ "J$cop,u $labl" %}
12825 size(6);
12826 opcode(0x0F, 0x80);
12827 ins_encode(Jcc(cop, labl));
12828 ins_pipe(pipe_jcc);
12829 ins_pc_relative(1);
12830 %}
12832 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12833 match(If cop cmp);
12834 effect(USE labl);
12836 ins_cost(200);
12837 format %{ $$template
12838 if ($cop$$cmpcode == Assembler::notEqual) {
12839 $$emit$$"JP,u $labl\n\t"
12840 $$emit$$"J$cop,u $labl"
12841 } else {
12842 $$emit$$"JP,u done\n\t"
12843 $$emit$$"J$cop,u $labl\n\t"
12844 $$emit$$"done:"
12845 }
12846 %}
12847 size(12);
12848 opcode(0x0F, 0x80);
12849 ins_encode %{
12850 Label* l = $labl$$label;
12851 $$$emit8$primary;
12852 emit_cc(cbuf, $secondary, Assembler::parity);
12853 int parity_disp = -1;
12854 bool ok = false;
12855 if ($cop$$cmpcode == Assembler::notEqual) {
12856 // the two jumps 6 bytes apart so the jump distances are too
12857 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12858 } else if ($cop$$cmpcode == Assembler::equal) {
12859 parity_disp = 6;
12860 ok = true;
12861 } else {
12862 ShouldNotReachHere();
12863 }
12864 emit_d32(cbuf, parity_disp);
12865 $$$emit8$primary;
12866 emit_cc(cbuf, $secondary, $cop$$cmpcode);
12867 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12868 emit_d32(cbuf, disp);
12869 %}
12870 ins_pipe(pipe_jcc);
12871 ins_pc_relative(1);
12872 %}
12874 // ============================================================================
12875 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12876 // array for an instance of the superklass. Set a hidden internal cache on a
12877 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12878 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12879 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12880 match(Set result (PartialSubtypeCheck sub super));
12881 effect( KILL rcx, KILL cr );
12883 ins_cost(1100); // slightly larger than the next version
12884 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12885 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12886 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12887 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12888 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12889 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12890 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12891 "miss:\t" %}
12893 opcode(0x1); // Force a XOR of EDI
12894 ins_encode( enc_PartialSubtypeCheck() );
12895 ins_pipe( pipe_slow );
12896 %}
12898 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12899 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12900 effect( KILL rcx, KILL result );
12902 ins_cost(1000);
12903 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12904 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12905 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12906 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12907 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12908 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12909 "miss:\t" %}
12911 opcode(0x0); // No need to XOR EDI
12912 ins_encode( enc_PartialSubtypeCheck() );
12913 ins_pipe( pipe_slow );
12914 %}
12916 // ============================================================================
12917 // Branch Instructions -- short offset versions
12918 //
12919 // These instructions are used to replace jumps of a long offset (the default
12920 // match) with jumps of a shorter offset. These instructions are all tagged
12921 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12922 // match rules in general matching. Instead, the ADLC generates a conversion
12923 // method in the MachNode which can be used to do in-place replacement of the
12924 // long variant with the shorter variant. The compiler will determine if a
12925 // branch can be taken by the is_short_branch_offset() predicate in the machine
12926 // specific code section of the file.
12928 // Jump Direct - Label defines a relative address from JMP+1
12929 instruct jmpDir_short(label labl) %{
12930 match(Goto);
12931 effect(USE labl);
12933 ins_cost(300);
12934 format %{ "JMP,s $labl" %}
12935 size(2);
12936 opcode(0xEB);
12937 ins_encode( OpcP, LblShort( labl ) );
12938 ins_pipe( pipe_jmp );
12939 ins_pc_relative(1);
12940 ins_short_branch(1);
12941 %}
12943 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12944 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12945 match(If cop cr);
12946 effect(USE labl);
12948 ins_cost(300);
12949 format %{ "J$cop,s $labl" %}
12950 size(2);
12951 opcode(0x70);
12952 ins_encode( JccShort( cop, labl) );
12953 ins_pipe( pipe_jcc );
12954 ins_pc_relative(1);
12955 ins_short_branch(1);
12956 %}
12958 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12959 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12960 match(CountedLoopEnd cop cr);
12961 effect(USE labl);
12963 ins_cost(300);
12964 format %{ "J$cop,s $labl\t# Loop end" %}
12965 size(2);
12966 opcode(0x70);
12967 ins_encode( JccShort( cop, labl) );
12968 ins_pipe( pipe_jcc );
12969 ins_pc_relative(1);
12970 ins_short_branch(1);
12971 %}
12973 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12974 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12975 match(CountedLoopEnd cop cmp);
12976 effect(USE labl);
12978 ins_cost(300);
12979 format %{ "J$cop,us $labl\t# Loop end" %}
12980 size(2);
12981 opcode(0x70);
12982 ins_encode( JccShort( cop, labl) );
12983 ins_pipe( pipe_jcc );
12984 ins_pc_relative(1);
12985 ins_short_branch(1);
12986 %}
12988 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12989 match(CountedLoopEnd cop cmp);
12990 effect(USE labl);
12992 ins_cost(300);
12993 format %{ "J$cop,us $labl\t# Loop end" %}
12994 size(2);
12995 opcode(0x70);
12996 ins_encode( JccShort( cop, labl) );
12997 ins_pipe( pipe_jcc );
12998 ins_pc_relative(1);
12999 ins_short_branch(1);
13000 %}
13002 // Jump Direct Conditional - using unsigned comparison
13003 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13004 match(If cop cmp);
13005 effect(USE labl);
13007 ins_cost(300);
13008 format %{ "J$cop,us $labl" %}
13009 size(2);
13010 opcode(0x70);
13011 ins_encode( JccShort( cop, labl) );
13012 ins_pipe( pipe_jcc );
13013 ins_pc_relative(1);
13014 ins_short_branch(1);
13015 %}
13017 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13018 match(If cop cmp);
13019 effect(USE labl);
13021 ins_cost(300);
13022 format %{ "J$cop,us $labl" %}
13023 size(2);
13024 opcode(0x70);
13025 ins_encode( JccShort( cop, labl) );
13026 ins_pipe( pipe_jcc );
13027 ins_pc_relative(1);
13028 ins_short_branch(1);
13029 %}
13031 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
13032 match(If cop cmp);
13033 effect(USE labl);
13035 ins_cost(300);
13036 format %{ $$template
13037 if ($cop$$cmpcode == Assembler::notEqual) {
13038 $$emit$$"JP,u,s $labl\n\t"
13039 $$emit$$"J$cop,u,s $labl"
13040 } else {
13041 $$emit$$"JP,u,s done\n\t"
13042 $$emit$$"J$cop,u,s $labl\n\t"
13043 $$emit$$"done:"
13044 }
13045 %}
13046 size(4);
13047 opcode(0x70);
13048 ins_encode %{
13049 Label* l = $labl$$label;
13050 emit_cc(cbuf, $primary, Assembler::parity);
13051 int parity_disp = -1;
13052 if ($cop$$cmpcode == Assembler::notEqual) {
13053 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
13054 } else if ($cop$$cmpcode == Assembler::equal) {
13055 parity_disp = 2;
13056 } else {
13057 ShouldNotReachHere();
13058 }
13059 emit_d8(cbuf, parity_disp);
13060 emit_cc(cbuf, $primary, $cop$$cmpcode);
13061 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
13062 emit_d8(cbuf, disp);
13063 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
13064 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp");
13065 %}
13066 ins_pipe(pipe_jcc);
13067 ins_pc_relative(1);
13068 ins_short_branch(1);
13069 %}
13071 // ============================================================================
13072 // Long Compare
13073 //
13074 // Currently we hold longs in 2 registers. Comparing such values efficiently
13075 // is tricky. The flavor of compare used depends on whether we are testing
13076 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
13077 // The GE test is the negated LT test. The LE test can be had by commuting
13078 // the operands (yielding a GE test) and then negating; negate again for the
13079 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
13080 // NE test is negated from that.
13082 // Due to a shortcoming in the ADLC, it mixes up expressions like:
13083 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
13084 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
13085 // are collapsed internally in the ADLC's dfa-gen code. The match for
13086 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
13087 // foo match ends up with the wrong leaf. One fix is to not match both
13088 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
13089 // both forms beat the trinary form of long-compare and both are very useful
13090 // on Intel which has so few registers.
13092 // Manifest a CmpL result in an integer register. Very painful.
13093 // This is the test to avoid.
13094 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
13095 match(Set dst (CmpL3 src1 src2));
13096 effect( KILL flags );
13097 ins_cost(1000);
13098 format %{ "XOR $dst,$dst\n\t"
13099 "CMP $src1.hi,$src2.hi\n\t"
13100 "JLT,s m_one\n\t"
13101 "JGT,s p_one\n\t"
13102 "CMP $src1.lo,$src2.lo\n\t"
13103 "JB,s m_one\n\t"
13104 "JEQ,s done\n"
13105 "p_one:\tINC $dst\n\t"
13106 "JMP,s done\n"
13107 "m_one:\tDEC $dst\n"
13108 "done:" %}
13109 ins_encode %{
13110 Label p_one, m_one, done;
13111 __ xorptr($dst$$Register, $dst$$Register);
13112 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
13113 __ jccb(Assembler::less, m_one);
13114 __ jccb(Assembler::greater, p_one);
13115 __ cmpl($src1$$Register, $src2$$Register);
13116 __ jccb(Assembler::below, m_one);
13117 __ jccb(Assembler::equal, done);
13118 __ bind(p_one);
13119 __ incrementl($dst$$Register);
13120 __ jmpb(done);
13121 __ bind(m_one);
13122 __ decrementl($dst$$Register);
13123 __ bind(done);
13124 %}
13125 ins_pipe( pipe_slow );
13126 %}
13128 //======
13129 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13130 // compares. Can be used for LE or GT compares by reversing arguments.
13131 // NOT GOOD FOR EQ/NE tests.
13132 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
13133 match( Set flags (CmpL src zero ));
13134 ins_cost(100);
13135 format %{ "TEST $src.hi,$src.hi" %}
13136 opcode(0x85);
13137 ins_encode( OpcP, RegReg_Hi2( src, src ) );
13138 ins_pipe( ialu_cr_reg_reg );
13139 %}
13141 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13142 // compares. Can be used for LE or GT compares by reversing arguments.
13143 // NOT GOOD FOR EQ/NE tests.
13144 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13145 match( Set flags (CmpL src1 src2 ));
13146 effect( TEMP tmp );
13147 ins_cost(300);
13148 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13149 "MOV $tmp,$src1.hi\n\t"
13150 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
13151 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
13152 ins_pipe( ialu_cr_reg_reg );
13153 %}
13155 // Long compares reg < zero/req OR reg >= zero/req.
13156 // Just a wrapper for a normal branch, plus the predicate test.
13157 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
13158 match(If cmp flags);
13159 effect(USE labl);
13160 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13161 expand %{
13162 jmpCon(cmp,flags,labl); // JLT or JGE...
13163 %}
13164 %}
13166 // Compare 2 longs and CMOVE longs.
13167 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
13168 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13169 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13170 ins_cost(400);
13171 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13172 "CMOV$cmp $dst.hi,$src.hi" %}
13173 opcode(0x0F,0x40);
13174 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13175 ins_pipe( pipe_cmov_reg_long );
13176 %}
13178 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
13179 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13180 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13181 ins_cost(500);
13182 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13183 "CMOV$cmp $dst.hi,$src.hi" %}
13184 opcode(0x0F,0x40);
13185 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13186 ins_pipe( pipe_cmov_reg_long );
13187 %}
13189 // Compare 2 longs and CMOVE ints.
13190 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
13191 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13192 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13193 ins_cost(200);
13194 format %{ "CMOV$cmp $dst,$src" %}
13195 opcode(0x0F,0x40);
13196 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13197 ins_pipe( pipe_cmov_reg );
13198 %}
13200 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
13201 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13202 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13203 ins_cost(250);
13204 format %{ "CMOV$cmp $dst,$src" %}
13205 opcode(0x0F,0x40);
13206 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13207 ins_pipe( pipe_cmov_mem );
13208 %}
13210 // Compare 2 longs and CMOVE ints.
13211 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
13212 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13213 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13214 ins_cost(200);
13215 format %{ "CMOV$cmp $dst,$src" %}
13216 opcode(0x0F,0x40);
13217 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13218 ins_pipe( pipe_cmov_reg );
13219 %}
13221 // Compare 2 longs and CMOVE doubles
13222 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
13223 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13224 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13225 ins_cost(200);
13226 expand %{
13227 fcmovD_regS(cmp,flags,dst,src);
13228 %}
13229 %}
13231 // Compare 2 longs and CMOVE doubles
13232 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
13233 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13234 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13235 ins_cost(200);
13236 expand %{
13237 fcmovXD_regS(cmp,flags,dst,src);
13238 %}
13239 %}
13241 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
13242 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13243 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13244 ins_cost(200);
13245 expand %{
13246 fcmovF_regS(cmp,flags,dst,src);
13247 %}
13248 %}
13250 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
13251 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13252 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13253 ins_cost(200);
13254 expand %{
13255 fcmovX_regS(cmp,flags,dst,src);
13256 %}
13257 %}
13259 //======
13260 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13261 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
13262 match( Set flags (CmpL src zero ));
13263 effect(TEMP tmp);
13264 ins_cost(200);
13265 format %{ "MOV $tmp,$src.lo\n\t"
13266 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
13267 ins_encode( long_cmp_flags0( src, tmp ) );
13268 ins_pipe( ialu_reg_reg_long );
13269 %}
13271 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13272 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
13273 match( Set flags (CmpL src1 src2 ));
13274 ins_cost(200+300);
13275 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13276 "JNE,s skip\n\t"
13277 "CMP $src1.hi,$src2.hi\n\t"
13278 "skip:\t" %}
13279 ins_encode( long_cmp_flags1( src1, src2 ) );
13280 ins_pipe( ialu_cr_reg_reg );
13281 %}
13283 // Long compare reg == zero/reg OR reg != zero/reg
13284 // Just a wrapper for a normal branch, plus the predicate test.
13285 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
13286 match(If cmp flags);
13287 effect(USE labl);
13288 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13289 expand %{
13290 jmpCon(cmp,flags,labl); // JEQ or JNE...
13291 %}
13292 %}
13294 // Compare 2 longs and CMOVE longs.
13295 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
13296 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13297 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13298 ins_cost(400);
13299 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13300 "CMOV$cmp $dst.hi,$src.hi" %}
13301 opcode(0x0F,0x40);
13302 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13303 ins_pipe( pipe_cmov_reg_long );
13304 %}
13306 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
13307 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13308 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13309 ins_cost(500);
13310 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13311 "CMOV$cmp $dst.hi,$src.hi" %}
13312 opcode(0x0F,0x40);
13313 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13314 ins_pipe( pipe_cmov_reg_long );
13315 %}
13317 // Compare 2 longs and CMOVE ints.
13318 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
13319 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13320 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13321 ins_cost(200);
13322 format %{ "CMOV$cmp $dst,$src" %}
13323 opcode(0x0F,0x40);
13324 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13325 ins_pipe( pipe_cmov_reg );
13326 %}
13328 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
13329 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13330 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13331 ins_cost(250);
13332 format %{ "CMOV$cmp $dst,$src" %}
13333 opcode(0x0F,0x40);
13334 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13335 ins_pipe( pipe_cmov_mem );
13336 %}
13338 // Compare 2 longs and CMOVE ints.
13339 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13340 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13341 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13342 ins_cost(200);
13343 format %{ "CMOV$cmp $dst,$src" %}
13344 opcode(0x0F,0x40);
13345 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13346 ins_pipe( pipe_cmov_reg );
13347 %}
13349 // Compare 2 longs and CMOVE doubles
13350 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13351 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13352 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13353 ins_cost(200);
13354 expand %{
13355 fcmovD_regS(cmp,flags,dst,src);
13356 %}
13357 %}
13359 // Compare 2 longs and CMOVE doubles
13360 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
13361 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13362 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13363 ins_cost(200);
13364 expand %{
13365 fcmovXD_regS(cmp,flags,dst,src);
13366 %}
13367 %}
13369 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13370 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13371 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13372 ins_cost(200);
13373 expand %{
13374 fcmovF_regS(cmp,flags,dst,src);
13375 %}
13376 %}
13378 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
13379 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13380 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13381 ins_cost(200);
13382 expand %{
13383 fcmovX_regS(cmp,flags,dst,src);
13384 %}
13385 %}
13387 //======
13388 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13389 // Same as cmpL_reg_flags_LEGT except must negate src
13390 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
13391 match( Set flags (CmpL src zero ));
13392 effect( TEMP tmp );
13393 ins_cost(300);
13394 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13395 "CMP $tmp,$src.lo\n\t"
13396 "SBB $tmp,$src.hi\n\t" %}
13397 ins_encode( long_cmp_flags3(src, tmp) );
13398 ins_pipe( ialu_reg_reg_long );
13399 %}
13401 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13402 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13403 // requires a commuted test to get the same result.
13404 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13405 match( Set flags (CmpL src1 src2 ));
13406 effect( TEMP tmp );
13407 ins_cost(300);
13408 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13409 "MOV $tmp,$src2.hi\n\t"
13410 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13411 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13412 ins_pipe( ialu_cr_reg_reg );
13413 %}
13415 // Long compares reg < zero/req OR reg >= zero/req.
13416 // Just a wrapper for a normal branch, plus the predicate test
13417 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13418 match(If cmp flags);
13419 effect(USE labl);
13420 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13421 ins_cost(300);
13422 expand %{
13423 jmpCon(cmp,flags,labl); // JGT or JLE...
13424 %}
13425 %}
13427 // Compare 2 longs and CMOVE longs.
13428 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13429 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13430 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13431 ins_cost(400);
13432 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13433 "CMOV$cmp $dst.hi,$src.hi" %}
13434 opcode(0x0F,0x40);
13435 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13436 ins_pipe( pipe_cmov_reg_long );
13437 %}
13439 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13440 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13441 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13442 ins_cost(500);
13443 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13444 "CMOV$cmp $dst.hi,$src.hi+4" %}
13445 opcode(0x0F,0x40);
13446 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13447 ins_pipe( pipe_cmov_reg_long );
13448 %}
13450 // Compare 2 longs and CMOVE ints.
13451 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
13452 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13453 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13454 ins_cost(200);
13455 format %{ "CMOV$cmp $dst,$src" %}
13456 opcode(0x0F,0x40);
13457 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13458 ins_pipe( pipe_cmov_reg );
13459 %}
13461 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
13462 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13463 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13464 ins_cost(250);
13465 format %{ "CMOV$cmp $dst,$src" %}
13466 opcode(0x0F,0x40);
13467 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13468 ins_pipe( pipe_cmov_mem );
13469 %}
13471 // Compare 2 longs and CMOVE ptrs.
13472 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13473 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13474 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13475 ins_cost(200);
13476 format %{ "CMOV$cmp $dst,$src" %}
13477 opcode(0x0F,0x40);
13478 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13479 ins_pipe( pipe_cmov_reg );
13480 %}
13482 // Compare 2 longs and CMOVE doubles
13483 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13484 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13485 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13486 ins_cost(200);
13487 expand %{
13488 fcmovD_regS(cmp,flags,dst,src);
13489 %}
13490 %}
13492 // Compare 2 longs and CMOVE doubles
13493 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
13494 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13495 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13496 ins_cost(200);
13497 expand %{
13498 fcmovXD_regS(cmp,flags,dst,src);
13499 %}
13500 %}
13502 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13503 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13504 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13505 ins_cost(200);
13506 expand %{
13507 fcmovF_regS(cmp,flags,dst,src);
13508 %}
13509 %}
13512 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
13513 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13514 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13515 ins_cost(200);
13516 expand %{
13517 fcmovX_regS(cmp,flags,dst,src);
13518 %}
13519 %}
13522 // ============================================================================
13523 // Procedure Call/Return Instructions
13524 // Call Java Static Instruction
13525 // Note: If this code changes, the corresponding ret_addr_offset() and
13526 // compute_padding() functions will have to be adjusted.
13527 instruct CallStaticJavaDirect(method meth) %{
13528 match(CallStaticJava);
13529 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
13530 effect(USE meth);
13532 ins_cost(300);
13533 format %{ "CALL,static " %}
13534 opcode(0xE8); /* E8 cd */
13535 ins_encode( pre_call_FPU,
13536 Java_Static_Call( meth ),
13537 call_epilog,
13538 post_call_FPU );
13539 ins_pipe( pipe_slow );
13540 ins_pc_relative(1);
13541 ins_alignment(4);
13542 %}
13544 // Call Java Static Instruction (method handle version)
13545 // Note: If this code changes, the corresponding ret_addr_offset() and
13546 // compute_padding() functions will have to be adjusted.
13547 instruct CallStaticJavaHandle(method meth, eBPRegP ebp) %{
13548 match(CallStaticJava);
13549 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
13550 effect(USE meth);
13551 // EBP is saved by all callees (for interpreter stack correction).
13552 // We use it here for a similar purpose, in {preserve,restore}_SP.
13554 ins_cost(300);
13555 format %{ "CALL,static/MethodHandle " %}
13556 opcode(0xE8); /* E8 cd */
13557 ins_encode( pre_call_FPU,
13558 preserve_SP,
13559 Java_Static_Call( meth ),
13560 restore_SP,
13561 call_epilog,
13562 post_call_FPU );
13563 ins_pipe( pipe_slow );
13564 ins_pc_relative(1);
13565 ins_alignment(4);
13566 %}
13568 // Call Java Dynamic Instruction
13569 // Note: If this code changes, the corresponding ret_addr_offset() and
13570 // compute_padding() functions will have to be adjusted.
13571 instruct CallDynamicJavaDirect(method meth) %{
13572 match(CallDynamicJava);
13573 effect(USE meth);
13575 ins_cost(300);
13576 format %{ "MOV EAX,(oop)-1\n\t"
13577 "CALL,dynamic" %}
13578 opcode(0xE8); /* E8 cd */
13579 ins_encode( pre_call_FPU,
13580 Java_Dynamic_Call( meth ),
13581 call_epilog,
13582 post_call_FPU );
13583 ins_pipe( pipe_slow );
13584 ins_pc_relative(1);
13585 ins_alignment(4);
13586 %}
13588 // Call Runtime Instruction
13589 instruct CallRuntimeDirect(method meth) %{
13590 match(CallRuntime );
13591 effect(USE meth);
13593 ins_cost(300);
13594 format %{ "CALL,runtime " %}
13595 opcode(0xE8); /* E8 cd */
13596 // Use FFREEs to clear entries in float stack
13597 ins_encode( pre_call_FPU,
13598 FFree_Float_Stack_All,
13599 Java_To_Runtime( meth ),
13600 post_call_FPU );
13601 ins_pipe( pipe_slow );
13602 ins_pc_relative(1);
13603 %}
13605 // Call runtime without safepoint
13606 instruct CallLeafDirect(method meth) %{
13607 match(CallLeaf);
13608 effect(USE meth);
13610 ins_cost(300);
13611 format %{ "CALL_LEAF,runtime " %}
13612 opcode(0xE8); /* E8 cd */
13613 ins_encode( pre_call_FPU,
13614 FFree_Float_Stack_All,
13615 Java_To_Runtime( meth ),
13616 Verify_FPU_For_Leaf, post_call_FPU );
13617 ins_pipe( pipe_slow );
13618 ins_pc_relative(1);
13619 %}
13621 instruct CallLeafNoFPDirect(method meth) %{
13622 match(CallLeafNoFP);
13623 effect(USE meth);
13625 ins_cost(300);
13626 format %{ "CALL_LEAF_NOFP,runtime " %}
13627 opcode(0xE8); /* E8 cd */
13628 ins_encode(Java_To_Runtime(meth));
13629 ins_pipe( pipe_slow );
13630 ins_pc_relative(1);
13631 %}
13634 // Return Instruction
13635 // Remove the return address & jump to it.
13636 instruct Ret() %{
13637 match(Return);
13638 format %{ "RET" %}
13639 opcode(0xC3);
13640 ins_encode(OpcP);
13641 ins_pipe( pipe_jmp );
13642 %}
13644 // Tail Call; Jump from runtime stub to Java code.
13645 // Also known as an 'interprocedural jump'.
13646 // Target of jump will eventually return to caller.
13647 // TailJump below removes the return address.
13648 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13649 match(TailCall jump_target method_oop );
13650 ins_cost(300);
13651 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13652 opcode(0xFF, 0x4); /* Opcode FF /4 */
13653 ins_encode( OpcP, RegOpc(jump_target) );
13654 ins_pipe( pipe_jmp );
13655 %}
13658 // Tail Jump; remove the return address; jump to target.
13659 // TailCall above leaves the return address around.
13660 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13661 match( TailJump jump_target ex_oop );
13662 ins_cost(300);
13663 format %{ "POP EDX\t# pop return address into dummy\n\t"
13664 "JMP $jump_target " %}
13665 opcode(0xFF, 0x4); /* Opcode FF /4 */
13666 ins_encode( enc_pop_rdx,
13667 OpcP, RegOpc(jump_target) );
13668 ins_pipe( pipe_jmp );
13669 %}
13671 // Create exception oop: created by stack-crawling runtime code.
13672 // Created exception is now available to this handler, and is setup
13673 // just prior to jumping to this handler. No code emitted.
13674 instruct CreateException( eAXRegP ex_oop )
13675 %{
13676 match(Set ex_oop (CreateEx));
13678 size(0);
13679 // use the following format syntax
13680 format %{ "# exception oop is in EAX; no code emitted" %}
13681 ins_encode();
13682 ins_pipe( empty );
13683 %}
13686 // Rethrow exception:
13687 // The exception oop will come in the first argument position.
13688 // Then JUMP (not call) to the rethrow stub code.
13689 instruct RethrowException()
13690 %{
13691 match(Rethrow);
13693 // use the following format syntax
13694 format %{ "JMP rethrow_stub" %}
13695 ins_encode(enc_rethrow);
13696 ins_pipe( pipe_jmp );
13697 %}
13699 // inlined locking and unlocking
13702 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
13703 match( Set cr (FastLock object box) );
13704 effect( TEMP tmp, TEMP scr );
13705 ins_cost(300);
13706 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
13707 ins_encode( Fast_Lock(object,box,tmp,scr) );
13708 ins_pipe( pipe_slow );
13709 ins_pc_relative(1);
13710 %}
13712 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13713 match( Set cr (FastUnlock object box) );
13714 effect( TEMP tmp );
13715 ins_cost(300);
13716 format %{ "FASTUNLOCK $object, $box, $tmp" %}
13717 ins_encode( Fast_Unlock(object,box,tmp) );
13718 ins_pipe( pipe_slow );
13719 ins_pc_relative(1);
13720 %}
13724 // ============================================================================
13725 // Safepoint Instruction
13726 instruct safePoint_poll(eFlagsReg cr) %{
13727 match(SafePoint);
13728 effect(KILL cr);
13730 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13731 // On SPARC that might be acceptable as we can generate the address with
13732 // just a sethi, saving an or. By polling at offset 0 we can end up
13733 // putting additional pressure on the index-0 in the D$. Because of
13734 // alignment (just like the situation at hand) the lower indices tend
13735 // to see more traffic. It'd be better to change the polling address
13736 // to offset 0 of the last $line in the polling page.
13738 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13739 ins_cost(125);
13740 size(6) ;
13741 ins_encode( Safepoint_Poll() );
13742 ins_pipe( ialu_reg_mem );
13743 %}
13745 //----------PEEPHOLE RULES-----------------------------------------------------
13746 // These must follow all instruction definitions as they use the names
13747 // defined in the instructions definitions.
13748 //
13749 // peepmatch ( root_instr_name [preceding_instruction]* );
13750 //
13751 // peepconstraint %{
13752 // (instruction_number.operand_name relational_op instruction_number.operand_name
13753 // [, ...] );
13754 // // instruction numbers are zero-based using left to right order in peepmatch
13755 //
13756 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13757 // // provide an instruction_number.operand_name for each operand that appears
13758 // // in the replacement instruction's match rule
13759 //
13760 // ---------VM FLAGS---------------------------------------------------------
13761 //
13762 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13763 //
13764 // Each peephole rule is given an identifying number starting with zero and
13765 // increasing by one in the order seen by the parser. An individual peephole
13766 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13767 // on the command-line.
13768 //
13769 // ---------CURRENT LIMITATIONS----------------------------------------------
13770 //
13771 // Only match adjacent instructions in same basic block
13772 // Only equality constraints
13773 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13774 // Only one replacement instruction
13775 //
13776 // ---------EXAMPLE----------------------------------------------------------
13777 //
13778 // // pertinent parts of existing instructions in architecture description
13779 // instruct movI(eRegI dst, eRegI src) %{
13780 // match(Set dst (CopyI src));
13781 // %}
13782 //
13783 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13784 // match(Set dst (AddI dst src));
13785 // effect(KILL cr);
13786 // %}
13787 //
13788 // // Change (inc mov) to lea
13789 // peephole %{
13790 // // increment preceeded by register-register move
13791 // peepmatch ( incI_eReg movI );
13792 // // require that the destination register of the increment
13793 // // match the destination register of the move
13794 // peepconstraint ( 0.dst == 1.dst );
13795 // // construct a replacement instruction that sets
13796 // // the destination to ( move's source register + one )
13797 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13798 // %}
13799 //
13800 // Implementation no longer uses movX instructions since
13801 // machine-independent system no longer uses CopyX nodes.
13802 //
13803 // peephole %{
13804 // peepmatch ( incI_eReg movI );
13805 // peepconstraint ( 0.dst == 1.dst );
13806 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13807 // %}
13808 //
13809 // peephole %{
13810 // peepmatch ( decI_eReg movI );
13811 // peepconstraint ( 0.dst == 1.dst );
13812 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13813 // %}
13814 //
13815 // peephole %{
13816 // peepmatch ( addI_eReg_imm movI );
13817 // peepconstraint ( 0.dst == 1.dst );
13818 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13819 // %}
13820 //
13821 // peephole %{
13822 // peepmatch ( addP_eReg_imm movP );
13823 // peepconstraint ( 0.dst == 1.dst );
13824 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13825 // %}
13827 // // Change load of spilled value to only a spill
13828 // instruct storeI(memory mem, eRegI src) %{
13829 // match(Set mem (StoreI mem src));
13830 // %}
13831 //
13832 // instruct loadI(eRegI dst, memory mem) %{
13833 // match(Set dst (LoadI mem));
13834 // %}
13835 //
13836 peephole %{
13837 peepmatch ( loadI storeI );
13838 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13839 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13840 %}
13842 //----------SMARTSPILL RULES---------------------------------------------------
13843 // These must follow all instruction definitions as they use the names
13844 // defined in the instructions definitions.