jdk8-mips64-public/hotspot: src/cpu/mips/vm/icache

     1 /*

     2  * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.

     3  * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.

     4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

     5  *

     6  * This code is free software; you can redistribute it and/or modify it

     7  * under the terms of the GNU General Public License version 2 only, as

     8  * published by the Free Software Foundation.

     9  *

    10  * This code is distributed in the hope that it will be useful, but WITHOUT

    11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    13  * version 2 for more details (a copy is included in the LICENSE file that

    14  * accompanied this code).

    15  *

    16  * You should have received a copy of the GNU General Public License version

    17  * 2 along with this work; if not, write to the Free Software Foundation,

    18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

    19  *

    20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

    21  * or visit www.oracle.com if you need additional information or have any

    22  * questions.

    23  *

    24  */

    26 #include "precompiled.hpp"

    27 #include "asm/macroAssembler.hpp"

    28 #include "runtime/icache.hpp"

    29 #include <asm/cachectl.h>

    30 #include <sys/cachectl.h>

    31 #include <sys/sysmips.h>

    33 #ifdef _LP64

    34   #define CACHE_OPT 1

    35 #endif

    37 //no need, we just call cacheflush system call to flush cache

    38 //update @jerome , 12/05/2006

    39 //flush cache is a very frequent operation, flush all the cache decrease the performance sharply, so i modify it.

    40 void ICacheStubGenerator::generate_icache_flush(ICache::flush_icache_stub_t* flush_icache_stub) {};

    42 void ICache::call_flush_stub(address start, int lines) {

    43 	//in fact, the current os implementation simply flush all ICACHE&DCACHE

    44 #ifndef CACHE_OPT

    45 	/* Loongson3A supports automatic synchronization between Icache and Dcache.

    46          * No manual synchronization is needed. */

    47 	cacheflush(start, lines * line_size , ICACHE);

    48 #endif

    49 //	sysmips(3, 0, 0, 0);

    50 }

    52 void ICache::invalidate_word(address addr) {

    53 	//cacheflush(addr, 4, ICACHE);

    55 #ifndef CACHE_OPT

    56 	cacheflush(addr,4, ICACHE);

    57 #endif

    58 //	sysmips(3, 0, 0, 0);

    59 }

    61 void ICache::invalidate_range(address start, int nbytes) {

    62 #ifndef CACHE_OPT

    63 	cacheflush(start, nbytes, ICACHE);

    64 #endif

    65 //	sysmips(3, 0, 0, 0);

    66 }

    68 void ICache::invalidate_all() {

    69 #ifndef CACHE_OPT

    70 	sysmips(3, 0, 0, 0);

    71 #endif

    72 }

src/cpu/mips/vm/icache_mips.cpp@d885f8d65c58