Mercurial > jdk8-mips64-public > hotspot / annotate
src/cpu/mips/vm/icache_mips.cpp@d885f8d65c58 (annotated)
src/cpu/mips/vm/icache_mips.cpp
Tue, 26 Jul 2016 17:06:17 +0800
- author
- fujie
- date
- Tue, 26 Jul 2016 17:06:17 +0800
- changeset 41
- d885f8d65c58
- parent 1
- 2d8a650513c2
- child 386
- f50649f9eda6
- permissions
- -rw-r--r--
Add multiply word to GPR instruction (mul) in MIPS assembler.
| aoqi@1 | 1 | /* |
| aoqi@1 | 2 | * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
| aoqi@1 | 3 | * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. |
| aoqi@1 | 4 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| aoqi@1 | 5 | * |
| aoqi@1 | 6 | * This code is free software; you can redistribute it and/or modify it |
| aoqi@1 | 7 | * under the terms of the GNU General Public License version 2 only, as |
| aoqi@1 | 8 | * published by the Free Software Foundation. |
| aoqi@1 | 9 | * |
| aoqi@1 | 10 | * This code is distributed in the hope that it will be useful, but WITHOUT |
| aoqi@1 | 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| aoqi@1 | 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| aoqi@1 | 13 | * version 2 for more details (a copy is included in the LICENSE file that |
| aoqi@1 | 14 | * accompanied this code). |
| aoqi@1 | 15 | * |
| aoqi@1 | 16 | * You should have received a copy of the GNU General Public License version |
| aoqi@1 | 17 | * 2 along with this work; if not, write to the Free Software Foundation, |
| aoqi@1 | 18 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
| aoqi@1 | 19 | * |
| aoqi@1 | 20 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| aoqi@1 | 21 | * or visit www.oracle.com if you need additional information or have any |
| aoqi@1 | 22 | * questions. |
| aoqi@1 | 23 | * |
| aoqi@1 | 24 | */ |
| aoqi@1 | 25 | |
| aoqi@1 | 26 | #include "precompiled.hpp" |
| aoqi@1 | 27 | #include "asm/macroAssembler.hpp" |
| aoqi@1 | 28 | #include "runtime/icache.hpp" |
| aoqi@1 | 29 | #include <asm/cachectl.h> |
| aoqi@1 | 30 | #include <sys/cachectl.h> |
| aoqi@1 | 31 | #include <sys/sysmips.h> |
| aoqi@1 | 32 | |
| aoqi@1 | 33 | #ifdef _LP64 |
| aoqi@1 | 34 | #define CACHE_OPT 1 |
| aoqi@1 | 35 | #endif |
| aoqi@1 | 36 | |
| aoqi@1 | 37 | //no need, we just call cacheflush system call to flush cache |
| aoqi@1 | 38 | //update @jerome , 12/05/2006 |
| aoqi@1 | 39 | //flush cache is a very frequent operation, flush all the cache decrease the performance sharply, so i modify it. |
| aoqi@1 | 40 | void ICacheStubGenerator::generate_icache_flush(ICache::flush_icache_stub_t* flush_icache_stub) {}; |
| aoqi@1 | 41 | |
| aoqi@1 | 42 | void ICache::call_flush_stub(address start, int lines) { |
| aoqi@1 | 43 | //in fact, the current os implementation simply flush all ICACHE&DCACHE |
| aoqi@1 | 44 | #ifndef CACHE_OPT |
| aoqi@1 | 45 | /* Loongson3A supports automatic synchronization between Icache and Dcache. |
| aoqi@1 | 46 | * No manual synchronization is needed. */ |
| aoqi@1 | 47 | cacheflush(start, lines * line_size , ICACHE); |
| aoqi@1 | 48 | #endif |
| aoqi@1 | 49 | // sysmips(3, 0, 0, 0); |
| aoqi@1 | 50 | } |
| aoqi@1 | 51 | |
| aoqi@1 | 52 | void ICache::invalidate_word(address addr) { |
| aoqi@1 | 53 | //cacheflush(addr, 4, ICACHE); |
| aoqi@1 | 54 | |
| aoqi@1 | 55 | #ifndef CACHE_OPT |
| aoqi@1 | 56 | cacheflush(addr,4, ICACHE); |
| aoqi@1 | 57 | #endif |
| aoqi@1 | 58 | // sysmips(3, 0, 0, 0); |
| aoqi@1 | 59 | } |
| aoqi@1 | 60 | |
| aoqi@1 | 61 | void ICache::invalidate_range(address start, int nbytes) { |
| aoqi@1 | 62 | #ifndef CACHE_OPT |
| aoqi@1 | 63 | cacheflush(start, nbytes, ICACHE); |
| aoqi@1 | 64 | #endif |
| aoqi@1 | 65 | // sysmips(3, 0, 0, 0); |
| aoqi@1 | 66 | } |
| aoqi@1 | 67 | |
| aoqi@1 | 68 | void ICache::invalidate_all() { |
| aoqi@1 | 69 | #ifndef CACHE_OPT |
| aoqi@1 | 70 | sysmips(3, 0, 0, 0); |
| aoqi@1 | 71 | #endif |
| aoqi@1 | 72 | } |
| aoqi@1 | 73 |
