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src/cpu/mips/vm/mips_64.ad@c9917fbd0a31
src/cpu/mips/vm/mips_64.ad
Thu, 11 Aug 2016 09:27:28 +0800
- author
- fujie
- date
- Thu, 11 Aug 2016 09:27:28 +0800
- changeset 60
- c9917fbd0a31
- parent 59
- 2dcecbdfda11
- child 61
- 17f070949775
- permissions
- -rw-r--r--
Performance of mod operation for long type is 100% up.
public class Test {
public static void main(String[] args) {
long LEN = 65000000;
long result = 0;
for(long j = 1; j < 20; j++) {
result = 0;
for(long i = 1; i < LEN; i++){
result += i % (j + 1);
}
}
System.out.println("result = " + result);
}
}
1 //
2 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
26 // GodSon3 Architecture Description File
28 //----------REGISTER DEFINITION BLOCK------------------------------------------
29 // This information is used by the matcher and the register allocator to
30 // describe individual registers and classes of registers within the target
31 // archtecture.
33 // format:
34 // reg_def name (call convention, c-call convention, ideal type, encoding);
35 // call convention :
36 // NS = No-Save
37 // SOC = Save-On-Call
38 // SOE = Save-On-Entry
39 // AS = Always-Save
40 // ideal type :
41 // see opto/opcodes.hpp for more info
42 // reg_class name (reg, ...);
43 // alloc_class name (reg, ...);
44 register %{
46 // General Registers
47 // Integer Registers
48 reg_def R0 ( NS, NS, Op_RegI, 0, VMRegImpl::Bad());
49 reg_def AT ( NS, NS, Op_RegI, 1, AT->as_VMReg());
50 reg_def AT_H ( NS, NS, Op_RegI, 1, AT->as_VMReg()->next());
51 reg_def V0 (SOC, SOC, Op_RegI, 2, V0->as_VMReg());
52 reg_def V0_H (SOC, SOC, Op_RegI, 2, V0->as_VMReg()->next());
53 reg_def V1 (SOC, SOC, Op_RegI, 3, V1->as_VMReg());
54 reg_def V1_H (SOC, SOC, Op_RegI, 3, V1->as_VMReg()->next());
55 reg_def A0 (SOC, SOC, Op_RegI, 4, A0->as_VMReg());
56 reg_def A0_H (SOC, SOC, Op_RegI, 4, A0->as_VMReg()->next());
57 reg_def A1 (SOC, SOC, Op_RegI, 5, A1->as_VMReg());
58 reg_def A1_H (SOC, SOC, Op_RegI, 5, A1->as_VMReg()->next());
59 reg_def A2 (SOC, SOC, Op_RegI, 6, A2->as_VMReg());
60 reg_def A2_H (SOC, SOC, Op_RegI, 6, A2->as_VMReg()->next());
61 reg_def A3 (SOC, SOC, Op_RegI, 7, A3->as_VMReg());
62 reg_def A3_H (SOC, SOC, Op_RegI, 7, A3->as_VMReg()->next());
63 reg_def A4 (SOC, SOC, Op_RegI, 8, A4->as_VMReg());
64 reg_def A4_H (SOC, SOC, Op_RegI, 8, A4->as_VMReg()->next());
65 reg_def A5 (SOC, SOC, Op_RegI, 9, A5->as_VMReg());
66 reg_def A5_H (SOC, SOC, Op_RegI, 9, A5->as_VMReg()->next());
67 reg_def A6 (SOC, SOC, Op_RegI, 10, A6->as_VMReg());
68 reg_def A6_H (SOC, SOC, Op_RegI, 10, A6->as_VMReg()->next());
69 reg_def A7 (SOC, SOC, Op_RegI, 11, A7->as_VMReg());
70 reg_def A7_H (SOC, SOC, Op_RegI, 11, A7->as_VMReg()->next());
71 reg_def T0 (SOC, SOC, Op_RegI, 12, T0->as_VMReg());
72 reg_def T0_H (SOC, SOC, Op_RegI, 12, T0->as_VMReg()->next());
73 reg_def T1 (SOC, SOC, Op_RegI, 13, T1->as_VMReg());
74 reg_def T1_H (SOC, SOC, Op_RegI, 13, T1->as_VMReg()->next());
75 reg_def T2 (SOC, SOC, Op_RegI, 14, T2->as_VMReg());
76 reg_def T2_H (SOC, SOC, Op_RegI, 14, T2->as_VMReg()->next());
77 reg_def T3 (SOC, SOC, Op_RegI, 15, T3->as_VMReg());
78 reg_def T3_H (SOC, SOC, Op_RegI, 15, T3->as_VMReg()->next());
79 reg_def S0 (SOC, SOE, Op_RegI, 16, S0->as_VMReg());
80 reg_def S0_H (SOC, SOE, Op_RegI, 16, S0->as_VMReg()->next());
81 reg_def S1 (SOC, SOE, Op_RegI, 17, S1->as_VMReg());
82 reg_def S1_H (SOC, SOE, Op_RegI, 17, S1->as_VMReg()->next());
83 reg_def S2 (SOC, SOE, Op_RegI, 18, S2->as_VMReg());
84 reg_def S2_H (SOC, SOE, Op_RegI, 18, S2->as_VMReg()->next());
85 reg_def S3 (SOC, SOE, Op_RegI, 19, S3->as_VMReg());
86 reg_def S3_H (SOC, SOE, Op_RegI, 19, S3->as_VMReg()->next());
87 reg_def S4 (SOC, SOE, Op_RegI, 20, S4->as_VMReg());
88 reg_def S4_H (SOC, SOE, Op_RegI, 20, S4->as_VMReg()->next());
89 reg_def S5 (SOC, SOE, Op_RegI, 21, S5->as_VMReg());
90 reg_def S6 (SOC, SOE, Op_RegI, 22, S6->as_VMReg());
91 reg_def S7 (SOC, SOE, Op_RegI, 23, S7->as_VMReg());
92 reg_def T8 (SOC, SOC, Op_RegI, 24, T8->as_VMReg());
93 reg_def T9 (SOC, SOC, Op_RegI, 25, T9->as_VMReg());
95 // Special Registers
96 reg_def K0 ( NS, NS, Op_RegI, 26, K0->as_VMReg());
97 reg_def K1 ( NS, NS, Op_RegI, 27, K1->as_VMReg());
98 reg_def GP ( NS, NS, Op_RegI, 28, GP->as_VMReg());
99 reg_def GP_H ( NS, NS, Op_RegI, 28, GP->as_VMReg()->next());
100 reg_def SP ( NS, NS, Op_RegI, 29, SP->as_VMReg());
101 reg_def SP_H ( NS, NS, Op_RegI, 29, SP->as_VMReg()->next());
102 reg_def FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
103 reg_def FP_H ( NS, NS, Op_RegI, 30, FP->as_VMReg()->next());
104 reg_def RA ( NS, NS, Op_RegI, 31, RA->as_VMReg());
105 reg_def RA_H ( NS, NS, Op_RegI, 31, RA->as_VMReg()->next());
107 // Floating registers.
108 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
109 reg_def F0_H ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()->next());
110 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
111 reg_def F1_H ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()->next());
112 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
113 reg_def F2_H ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()->next());
114 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
115 reg_def F3_H ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()->next());
116 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
117 reg_def F4_H ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()->next());
118 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
119 reg_def F5_H ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()->next());
120 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
121 reg_def F6_H ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()->next());
122 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
123 reg_def F7_H ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()->next());
124 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
125 reg_def F8_H ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()->next());
126 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
127 reg_def F9_H ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()->next());
128 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
129 reg_def F10_H ( SOC, SOC, Op_RegF, 10, F10->as_VMReg()->next());
130 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
131 reg_def F11_H ( SOC, SOC, Op_RegF, 11, F11->as_VMReg()->next());
132 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
133 reg_def F12_H ( SOC, SOC, Op_RegF, 12, F12->as_VMReg()->next());
134 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
135 reg_def F13_H ( SOC, SOC, Op_RegF, 13, F13->as_VMReg()->next());
136 reg_def F14 ( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
137 reg_def F14_H ( SOC, SOC, Op_RegF, 14, F14->as_VMReg()->next());
138 reg_def F15 ( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
139 reg_def F15_H ( SOC, SOC, Op_RegF, 15, F15->as_VMReg()->next());
140 reg_def F16 ( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
141 reg_def F16_H ( SOC, SOC, Op_RegF, 16, F16->as_VMReg()->next());
142 reg_def F17 ( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
143 reg_def F17_H ( SOC, SOC, Op_RegF, 17, F17->as_VMReg()->next());
144 reg_def F18 ( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
145 reg_def F18_H ( SOC, SOC, Op_RegF, 18, F18->as_VMReg()->next());
146 reg_def F19 ( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
147 reg_def F19_H ( SOC, SOC, Op_RegF, 19, F19->as_VMReg()->next());
148 reg_def F20 ( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
149 reg_def F20_H ( SOC, SOC, Op_RegF, 20, F20->as_VMReg()->next());
150 reg_def F21 ( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
151 reg_def F21_H ( SOC, SOC, Op_RegF, 21, F21->as_VMReg()->next());
152 reg_def F22 ( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
153 reg_def F22_H ( SOC, SOC, Op_RegF, 22, F22->as_VMReg()->next());
154 reg_def F23 ( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
155 reg_def F23_H ( SOC, SOC, Op_RegF, 23, F23->as_VMReg()->next());
156 reg_def F24 ( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
157 reg_def F24_H ( SOC, SOC, Op_RegF, 24, F24->as_VMReg()->next());
158 reg_def F25 ( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
159 reg_def F25_H ( SOC, SOC, Op_RegF, 25, F25->as_VMReg()->next());
160 reg_def F26 ( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
161 reg_def F26_H ( SOC, SOC, Op_RegF, 26, F26->as_VMReg()->next());
162 reg_def F27 ( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
163 reg_def F27_H ( SOC, SOC, Op_RegF, 27, F27->as_VMReg()->next());
164 reg_def F28 ( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
165 reg_def F28_H ( SOC, SOC, Op_RegF, 28, F28->as_VMReg()->next());
166 reg_def F29 ( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
167 reg_def F29_H ( SOC, SOC, Op_RegF, 29, F29->as_VMReg()->next());
168 reg_def F30 ( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
169 reg_def F30_H ( SOC, SOC, Op_RegF, 30, F30->as_VMReg()->next());
170 reg_def F31 ( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
171 reg_def F31_H ( SOC, SOC, Op_RegF, 31, F31->as_VMReg()->next());
174 // ----------------------------
175 // Special Registers
176 // Condition Codes Flag Registers
177 reg_def MIPS_FLAG (SOC, SOC, Op_RegFlags, 1, as_Register(1)->as_VMReg());
178 //S6 is used for get_thread(S6)
179 //S5 is uesd for heapbase of compressed oop
180 alloc_class chunk0( S0, S0_H,
181 S1, S1_H,
182 S2, S2_H,
183 S3, S3_H,
184 S4, S4_H,
185 T0, T0_H,
186 T1, T1_H,
187 T2, T2_H,
188 T3, T3_H,
189 V0, V0_H,
190 V1, V1_H,
191 A0, A0_H,
192 A1, A1_H,
193 A2, A2_H,
194 A3, A3_H,
195 A4, A4_H,
196 A5, A5_H,
197 A6, A6_H,
198 A7, A7_H,
199 RA, RA_H,
200 SP, SP_H,
201 FP, FP_H,
202 GP, GP_H );
204 alloc_class chunk1( F0, F0_H,
205 F1, F1_H,
206 F2, F2_H,
207 F3, F3_H,
208 F4, F4_H,
209 F5, F5_H,
210 F6, F6_H,
211 F7, F7_H,
212 F8, F8_H,
213 F9, F9_H,
214 F10, F10_H,
215 F11, F11_H,
216 F12, F12_H,
217 F13, F13_H,
218 F14, F14_H,
219 F15, F15_H,
220 F16, F16_H,
221 F17, F17_H,
222 F18, F18_H,
223 F19, F19_H,
224 F20, F20_H,
225 F21, F21_H,
226 F22, F22_H,
227 F23, F23_H,
228 F24, F24_H,
229 F25, F25_H,
230 F26, F26_H,
231 F27, F27_H,
232 F28, F28_H,
233 F29, F29_H,
234 F30, F30_H,
235 F31, F31_H);
237 alloc_class chunk2(MIPS_FLAG);
239 // Class for all registers
240 reg_class any_reg( T0, T0_H,
241 T1, T1_H,
242 T2, T2_H,
243 T3, T3_H,
244 A4, A4_H,
245 A5, A5_H,
246 A6, A6_H,
247 A7, A7_H,
248 S0, S0_H,
249 S1, S1_H,
250 S2, S2_H,
251 S3, S3_H,
252 S4, S4_H,
253 V0, V0_H,
254 V1, V1_H
255 );
257 // Class for general registers
258 reg_class g_reg( T0, T0_H,
259 T1, T1_H,
260 T2, T2_H,
261 T3, T3_H,
262 A4, A4_H,
263 A5, A5_H,
264 A6, A6_H,
265 A7, A7_H,
266 S0, S0_H,
267 S1, S1_H,
268 S2, S2_H,
269 S3, S3_H,
270 S4, S4_H,
271 V0, V0_H,
272 V1, V1_H,
273 A0, A0_H,
274 A1, A1_H,
275 A2, A2_H,
276 A3, A3_H );
278 reg_class s_reg( S0, S1, S2, S3, S4 );
279 reg_class s0_reg( S0 );
280 reg_class s1_reg( S1 );
281 reg_class s2_reg( S2 );
282 reg_class s3_reg( S3 );
283 reg_class s4_reg( S4 );
285 reg_class t_reg( T0, T1, T2, T3);
286 reg_class t0_reg( T0 );
287 reg_class t1_reg( T1 );
288 reg_class t2_reg( T2 );
289 reg_class t3_reg( T3 );
291 reg_class a0_reg( A0 );
292 reg_class a1_reg( A1 );
293 reg_class a2_reg( A2 );
294 reg_class a3_reg( A3 );
295 reg_class a4_reg( A4 );
296 reg_class a5_reg( A5 );
297 reg_class a6_reg( A6 );
298 reg_class a7_reg( A7 );
300 reg_class mips_flags(MIPS_FLAG);
302 // Class of registers that can appear in an address with no offset.
303 // EBP and ESP require an extra instruction byte for zero offset.
304 // Used in fast-unlock
305 //reg_class p_reg(EDX, EDI, ESI, EBX);
306 reg_class p_reg( T0, T0_H,
307 T1, T1_H,
308 T2, T2_H,
309 T3, T3_H,
311 A0, A0_H,
312 A1, A1_H,
313 A2, A2_H,
314 A3, A3_H,
315 A4, A4_H,
316 A5, A5_H,
317 A6, A6_H,
318 A7, A7_H,
320 S0, S0_H,
321 S1, S1_H,
322 S2, S2_H,
323 S3, S3_H,
324 S4, S4_H);
325 reg_class int_reg( T0, T1, T2, T3, S0, S1, S2, S3, S4, V0, V1, A0, A1, A2, A3, A4, A6, A7 );
326 reg_class sp_reg( SP, SP_H );
327 reg_class fp_reg( FP, FP_H );
330 reg_class long_reg(
331 T0, T0_H,
332 T1, T1_H,
333 T2, T2_H,
334 T3, T3_H,
336 A0, A0_H,
337 A1, A1_H,
338 A2, A2_H,
339 A3, A3_H,
340 A4, A4_H,
341 A5, A5_H,
342 A6, A6_H,
343 A7, A7_H,
345 S0, S0_H,
346 S1, S1_H,
347 S2, S2_H,
348 S3, S3_H,
349 S4, S4_H);
351 reg_class v0_long_reg( V0, V0_H );
352 reg_class v1_long_reg( V1, V1_H );
353 reg_class a0_long_reg( A0, A0_H );
354 reg_class a1_long_reg( A1, A1_H );
355 reg_class a2_long_reg( A2, A2_H );
356 reg_class a3_long_reg( A3, A3_H );
357 reg_class a4_long_reg( A4, A4_H );
358 reg_class a5_long_reg( A5, A5_H );
359 reg_class a6_long_reg( A6, A6_H );
360 reg_class a7_long_reg( A7, A7_H );
361 reg_class t0_long_reg( T0, T0_H );
362 reg_class t1_long_reg( T1, T1_H );
363 reg_class t2_long_reg( T2, T2_H );
364 reg_class t3_long_reg( T3, T3_H );
365 reg_class s0_long_reg( S0, S0_H );
366 reg_class s1_long_reg( S1, S1_H );
367 reg_class s2_long_reg( S2, S2_H );
368 reg_class s3_long_reg( S3, S3_H );
369 reg_class s4_long_reg( S4, S4_H );
371 // Floating point registers.
372 // 2012/8/23 Fu: F30/F31 are used as temporary registers in D2I
373 reg_class flt_reg( F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17 F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28);
374 reg_class dbl_reg( F0, F0_H,
375 F1, F1_H,
376 F2, F2_H,
377 F3, F3_H,
378 F4, F4_H,
379 F5, F5_H,
380 F6, F6_H,
381 F7, F7_H,
382 F8, F8_H,
383 F9, F9_H,
384 F10, F10_H,
385 F11, F11_H,
386 F12, F12_H,
387 F13, F13_H,
388 F14, F14_H,
389 F15, F15_H,
390 F16, F16_H,
391 F17, F17_H,
392 F18, F18_H,
393 F19, F19_H,
394 F20, F20_H,
395 F21, F21_H,
396 F22, F22_H,
397 F23, F23_H,
398 F24, F24_H,
399 F25, F25_H,
400 F26, F26_H,
401 F27, F27_H,
402 F28, F28_H,
403 F29, F29_H);
405 reg_class flt_arg0( F12 );
406 reg_class dbl_arg0( F12, F12_H );
407 reg_class dbl_arg1( F14, F14_H );
409 %}
411 //----------DEFINITION BLOCK---------------------------------------------------
412 // Define name --> value mappings to inform the ADLC of an integer valued name
413 // Current support includes integer values in the range [0, 0x7FFFFFFF]
414 // Format:
415 // int_def <name> ( <int_value>, <expression>);
416 // Generated Code in ad_<arch>.hpp
417 // #define <name> (<expression>)
418 // // value == <int_value>
419 // Generated code in ad_<arch>.cpp adlc_verification()
420 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
421 //
422 definitions %{
423 int_def DEFAULT_COST ( 100, 100);
424 int_def HUGE_COST (1000000, 1000000);
426 // Memory refs are twice as expensive as run-of-the-mill.
427 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
429 // Branches are even more expensive.
430 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
431 // we use jr instruction to construct call, so more expensive
432 // by yjl 2/28/2006
433 int_def CALL_COST ( 500, DEFAULT_COST * 5);
434 /*
435 int_def EQUAL ( 1, 1 );
436 int_def NOT_EQUAL ( 2, 2 );
437 int_def GREATER ( 3, 3 );
438 int_def GREATER_EQUAL ( 4, 4 );
439 int_def LESS ( 5, 5 );
440 int_def LESS_EQUAL ( 6, 6 );
441 */
442 %}
446 //----------SOURCE BLOCK-------------------------------------------------------
447 // This is a block of C++ code which provides values, functions, and
448 // definitions necessary in the rest of the architecture description
450 source_hpp %{
451 // Header information of the source block.
452 // Method declarations/definitions which are used outside
453 // the ad-scope can conveniently be defined here.
454 //
455 // To keep related declarations/definitions/uses close together,
456 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
458 class CallStubImpl {
460 //--------------------------------------------------------------
461 //---< Used for optimization in Compile::shorten_branches >---
462 //--------------------------------------------------------------
464 public:
465 // Size of call trampoline stub.
466 static uint size_call_trampoline() {
467 return 0; // no call trampolines on this platform
468 }
470 // number of relocations needed by a call trampoline stub
471 static uint reloc_call_trampoline() {
472 return 0; // no call trampolines on this platform
473 }
474 };
476 class HandlerImpl {
478 public:
480 static int emit_exception_handler(CodeBuffer &cbuf);
481 static int emit_deopt_handler(CodeBuffer& cbuf);
483 static uint size_exception_handler() {
484 // NativeCall instruction size is the same as NativeJump.
485 // exception handler starts out as jump and can be patched to
486 // a call be deoptimization. (4932387)
487 // Note that this value is also credited (in output.cpp) to
488 // the size of the code section.
489 // return NativeJump::instruction_size;
490 int size = NativeCall::instruction_size;
491 return round_to(size, 16);
492 }
494 #ifdef _LP64
495 static uint size_deopt_handler() {
496 int size = NativeCall::instruction_size;
497 return round_to(size, 16);
498 }
499 #else
500 static uint size_deopt_handler() {
501 // NativeCall instruction size is the same as NativeJump.
502 // exception handler starts out as jump and can be patched to
503 // a call be deoptimization. (4932387)
504 // Note that this value is also credited (in output.cpp) to
505 // the size of the code section.
506 return 5 + NativeJump::instruction_size; // pushl(); jmp;
507 }
508 #endif
509 };
511 %} // end source_hpp
513 source %{
515 #define NO_INDEX 0
516 #define RELOC_IMM64 Assembler::imm_operand
517 #define RELOC_DISP32 Assembler::disp32_operand
520 #define __ _masm.
523 // Emit exception handler code.
524 // Stuff framesize into a register and call a VM stub routine.
525 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
526 /*
527 // Note that the code buffer's insts_mark is always relative to insts.
528 // That's why we must use the macroassembler to generate a handler.
529 MacroAssembler _masm(&cbuf);
530 address base = __ start_a_stub(size_exception_handler());
531 if (base == NULL) return 0; // CodeBuffer::expand failed
532 int offset = __ offset();
533 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
534 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
535 __ end_a_stub();
536 return offset;
537 */
538 // Note that the code buffer's insts_mark is always relative to insts.
539 // That's why we must use the macroassembler to generate a handler.
540 MacroAssembler _masm(&cbuf);
541 address base =
542 __ start_a_stub(size_exception_handler());
543 if (base == NULL) return 0; // CodeBuffer::expand failed
544 int offset = __ offset();
546 __ block_comment("; emit_exception_handler");
548 /* 2012/9/25 FIXME Jin: According to X86, we should use direct jumpt.
549 * * However, this will trigger an assert after the 40th method:
550 * *
551 * * 39 b java.lang.Throwable::<init> (25 bytes)
552 * * --- ns java.lang.Throwable::fillInStackTrace
553 * * 40 !b java.net.URLClassLoader::findClass (29 bytes)
554 * * /vm/opto/runtime.cpp, 900 , assert(caller.is_compiled_frame(),"must be")
555 * * 40 made not entrant (2) java.net.URLClassLoader::findClass (29 bytes)
556 * *
557 * * If we change from JR to JALR, the assert will disappear, but WebClient will
558 * * fail after the 403th method with unknown reason.
559 * */
560 __ li48(T9, (long)OptoRuntime::exception_blob()->entry_point());
561 __ jr(T9);
562 __ delayed()->nop();
563 __ align(16);
564 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
565 __ end_a_stub();
566 return offset;
567 }
569 // Emit deopt handler code.
570 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
571 /*
572 // Note that the code buffer's insts_mark is always relative to insts.
573 // That's why we must use the macroassembler to generate a handler.
574 MacroAssembler _masm(&cbuf);
575 address base = __ start_a_stub(size_deopt_handler());
576 if (base == NULL) return 0; // CodeBuffer::expand failed
577 int offset = __ offset();
579 #ifdef _LP64
580 address the_pc = (address) __ pc();
581 Label next;
582 // push a "the_pc" on the stack without destroying any registers
583 // as they all may be live.
585 // push address of "next"
586 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
587 __ bind(next);
588 // adjust it so it matches "the_pc"
589 __ subptr(Address(rsp, 0), __ offset() - offset);
590 #else
591 InternalAddress here(__ pc());
592 __ pushptr(here.addr());
593 #endif
595 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
596 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
597 __ end_a_stub();
598 return offset;
599 */
600 // Note that the code buffer's insts_mark is always relative to insts.
601 // That's why we must use the macroassembler to generate a handler.
602 MacroAssembler _masm(&cbuf);
603 address base =
604 __ start_a_stub(size_deopt_handler());
606 // FIXME
607 if (base == NULL) return 0; // CodeBuffer::expand failed
608 int offset = __ offset();
610 __ block_comment("; emit_deopt_handler");
612 cbuf.set_insts_mark();
613 __ relocate(relocInfo::runtime_call_type);
615 __ li48(T9, (long)SharedRuntime::deopt_blob()->unpack());
616 __ jalr(T9);
617 __ delayed()->nop();
618 __ align(16);
619 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
620 __ end_a_stub();
621 return offset;
622 }
625 const bool Matcher::match_rule_supported(int opcode) {
626 if (!has_match_rule(opcode))
627 return false;
628 /*
629 switch (opcode) {
630 case Op_PopCountI:
631 case Op_PopCountL:
632 if (!UsePopCountInstruction)
633 return false;
634 break;
635 case Op_MulVI:
636 if ((UseSSE < 4) && (UseAVX < 1)) // only with SSE4_1 or AVX
637 return false;
638 break;
639 case Op_CompareAndSwapL:
640 #ifdef _LP64
641 case Op_CompareAndSwapP:
642 #endif
643 if (!VM_Version::supports_cx8())
644 return false;
645 break;
646 }
647 */
648 return true; // Per default match rules are supported.
649 }
651 //FIXME
652 // emit call stub, compiled java to interpreter
653 void emit_java_to_interp(CodeBuffer &cbuf ) {
654 // Stub is fixed up when the corresponding call is converted from calling
655 // compiled code to calling interpreted code.
656 // mov rbx,0
657 // jmp -1
659 address mark = cbuf.insts_mark(); // get mark within main instrs section
661 // Note that the code buffer's insts_mark is always relative to insts.
662 // That's why we must use the macroassembler to generate a stub.
663 MacroAssembler _masm(&cbuf);
665 address base =
666 __ start_a_stub(Compile::MAX_stubs_size);
667 if (base == NULL) return; // CodeBuffer::expand failed
668 // static stub relocation stores the instruction address of the call
670 __ relocate(static_stub_Relocation::spec(mark), 0);
672 /* 2012/10/29 Jin: Rmethod contains methodOop, it should be relocated for GC */
673 /*
674 int oop_index = __ oop_recorder()->allocate_index(NULL);
675 RelocationHolder rspec = oop_Relocation::spec(oop_index);
676 __ relocate(rspec);
677 */
679 // static stub relocation also tags the methodOop in the code-stream.
680 __ li48(S3, (long)0);
681 // This is recognized as unresolved by relocs/nativeInst/ic code
683 __ relocate(relocInfo::runtime_call_type);
685 cbuf.set_insts_mark();
686 address call_pc = (address)-1;
687 __ li48(AT, (long)call_pc);
688 __ jr(AT);
689 __ nop();
690 __ align(16);
691 __ end_a_stub();
692 // Update current stubs pointer and restore code_end.
693 }
695 // size of call stub, compiled java to interpretor
696 uint size_java_to_interp() {
697 int size = 4 * 4 + NativeCall::instruction_size; // sizeof(li48) + NativeCall::instruction_size
698 return round_to(size, 16);
699 }
701 // relocation entries for call stub, compiled java to interpreter
702 uint reloc_java_to_interp() {
703 return 16; // in emit_java_to_interp + in Java_Static_Call
704 }
706 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
707 if( Assembler::is_simm16(offset) ) return true;
708 else
709 {
710 assert(false, "Not implemented yet !" );
711 Unimplemented();
712 }
713 }
716 // No additional cost for CMOVL.
717 const int Matcher::long_cmove_cost() { return 0; }
719 // No CMOVF/CMOVD with SSE2
720 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
722 // Does the CPU require late expand (see block.cpp for description of late expand)?
723 const bool Matcher::require_postalloc_expand = false;
725 // Do we need to mask the count passed to shift instructions or does
726 // the cpu only look at the lower 5/6 bits anyway?
727 const bool Matcher::need_masked_shift_count = false;
729 bool Matcher::narrow_oop_use_complex_address() {
730 assert(UseCompressedOops, "only for compressed oops code");
731 return (LogMinObjAlignmentInBytes <= 3);
732 }
734 bool Matcher::narrow_klass_use_complex_address() {
735 assert(UseCompressedClassPointers, "only for compressed klass code");
736 return (LogKlassAlignmentInBytes <= 3);
737 }
739 // This is UltraSparc specific, true just means we have fast l2f conversion
740 const bool Matcher::convL2FSupported(void) {
741 return true;
742 }
746 // Max vector size in bytes. 0 if not supported.
747 const int Matcher::vector_width_in_bytes(BasicType bt) {
748 // return UseSSE >= 2 ? 8 : 0;
749 return 0;
750 }
752 // Register for MODI projection of divmodI
753 RegMask Matcher::modI_proj_mask() {
754 return P_REG_mask();
755 }
757 // Register for DIVL projection of divmodL
758 RegMask Matcher::divL_proj_mask() {
759 ShouldNotReachHere();
760 return RegMask();
761 }
763 int Matcher::regnum_to_fpu_offset(int regnum) {
764 return regnum - 32; // The FP registers are in the second chunk
765 }
768 const bool Matcher::isSimpleConstant64(jlong value) {
769 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
770 return false;
771 }
773 // Register for DIVI projection of divmodI
774 RegMask Matcher::divI_proj_mask() {
775 return P_REG_mask();
776 }
778 // Limits on vector size (number of elements) loaded into vector.
779 const int Matcher::max_vector_size(const BasicType bt) {
780 return vector_width_in_bytes(bt)/type2aelembytes(bt);
781 }
782 const int Matcher::min_vector_size(const BasicType bt) {
783 int max_size = max_vector_size(bt);
784 // Min size which can be loaded into vector is 4 bytes.
785 int size = (type2aelembytes(bt) == 1) ? 4 : 2;
786 return MIN2(size,max_size);
787 }
789 // Vector ideal reg
790 const int Matcher::vector_ideal_reg(int size) {
791 return 0;
792 }
794 // Only lowest bits of xmm reg are used for vector shift count.
795 const int Matcher::vector_shift_count_ideal_reg(int size) {
796 return Op_VecS;
797 }
799 // x86 supports misaligned vectors store/load.
800 const bool Matcher::misaligned_vectors_ok() {
801 return !AlignVector; // can be changed by flag
802 }
804 // Return whether or not this register is ever used as an argument. This
805 // function is used on startup to build the trampoline stubs in generateOptoStub.
806 // Registers not mentioned will be killed by the VM call in the trampoline, and
807 // arguments in those registers not be available to the callee.
808 bool Matcher::can_be_java_arg( int reg ) {
809 /* Refer to: [sharedRuntime_mips_64.cpp] SharedRuntime::java_calling_convention() */
810 if ( reg == T0_num || reg == T0_H_num
811 || reg == A0_num || reg == A0_H_num
812 || reg == A1_num || reg == A1_H_num
813 || reg == A2_num || reg == A2_H_num
814 || reg == A3_num || reg == A3_H_num
815 || reg == A4_num || reg == A4_H_num
816 || reg == A5_num || reg == A5_H_num
817 || reg == A6_num || reg == A6_H_num
818 || reg == A7_num || reg == A7_H_num )
819 return true;
821 if (reg >= F12_num && reg <= F19_num)
822 return true;
824 return false;
825 }
827 bool Matcher::is_spillable_arg( int reg ) {
828 return can_be_java_arg(reg);
829 }
831 //TODO: in MIPS i donot know LEE
832 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
833 // In 64 bit mode a code which use multiply when
834 // devisor is constant is faster than hardware
835 // DIV instruction (it uses MulHiL).
836 return false;
837 }
839 // Register for MODL projection of divmodL
840 RegMask Matcher::modL_proj_mask() {
841 ShouldNotReachHere();
842 return RegMask();
843 }
845 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
846 return FP_REG_mask();
847 }
849 // x86 AES instructions are compatible with SunJCE expanded
850 // keys, hence we do not need to pass the original key to stubs
851 const bool Matcher::pass_original_key_for_aes() {
852 return false;
853 }
855 // The address of the call instruction needs to be 16-byte aligned to
856 // ensure that it does not span a cache line so that it can be patched.
858 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
859 //lui
860 //ori
861 //dsll
862 //ori
864 //jalr
865 //nop
867 return round_to(current_offset, alignment_required()) - current_offset;
868 }
870 // The address of the call instruction needs to be 16-byte aligned to
871 // ensure that it does not span a cache line so that it can be patched.
872 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
873 //li64 <--- skip
875 //lui
876 //ori
877 //dsll
878 //ori
880 //jalr
881 //nop
883 current_offset += 4 * 6; // skip li64
884 return round_to(current_offset, alignment_required()) - current_offset;
885 }
887 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
888 //lui
889 //ori
890 //dsll
891 //ori
893 //jalr
894 //nop
896 return round_to(current_offset, alignment_required()) - current_offset;
897 }
899 int CallLeafDirectNode::compute_padding(int current_offset) const {
900 //lui
901 //ori
902 //dsll
903 //ori
905 //jalr
906 //nop
908 return round_to(current_offset, alignment_required()) - current_offset;
909 }
911 int CallRuntimeDirectNode::compute_padding(int current_offset) const {
912 //lui
913 //ori
914 //dsll
915 //ori
917 //jalr
918 //nop
920 return round_to(current_offset, alignment_required()) - current_offset;
921 }
923 // If CPU can load and store mis-aligned doubles directly then no fixup is
924 // needed. Else we split the double into 2 integer pieces and move it
925 // piece-by-piece. Only happens when passing doubles into C code as the
926 // Java calling convention forces doubles to be aligned.
927 const bool Matcher::misaligned_doubles_ok = false;
928 // Do floats take an entire double register or just half?
929 //const bool Matcher::float_in_double = true;
930 bool Matcher::float_in_double() { return false; }
931 // Do ints take an entire long register or just half?
932 const bool Matcher::int_in_long = false;
933 // Threshold size for cleararray.
934 const int Matcher::init_array_short_size = 8 * BytesPerLong;
935 // Is it better to copy float constants, or load them directly from memory?
936 // Intel can load a float constant from a direct address, requiring no
937 // extra registers. Most RISCs will have to materialize an address into a
938 // register first, so they would do better to copy the constant from stack.
939 const bool Matcher::rematerialize_float_constants = false;
940 // Advertise here if the CPU requires explicit rounding operations
941 // to implement the UseStrictFP mode.
942 const bool Matcher::strict_fp_requires_explicit_rounding = false;
943 // The ecx parameter to rep stos for the ClearArray node is in dwords.
944 const bool Matcher::init_array_count_is_in_bytes = false;
945 // Should the Matcher clone shifts on addressing modes, expecting them to
946 // be subsumed into complex addressing expressions or compute them into
947 // registers? True for Intel but false for most RISCs
948 const bool Matcher::clone_shift_expressions = false;
952 // Indicate if the safepoint node needs the polling page as an input.
953 // Since x86 does have absolute addressing, it doesn't.
954 bool SafePointNode::needs_polling_address_input() {
955 return false;
956 }
958 // !!!!! Special hack to get all type of calls to specify the byte offset
959 // from the start of the call to the point where the return address
960 // will point.
961 int MachCallStaticJavaNode::ret_addr_offset() {
962 assert(NativeCall::instruction_size == 24, "in MachCallStaticJavaNode::ret_addr_offset");
963 //The value ought to be 16 bytes.
964 //lui
965 //ori
966 //dsll
967 //ori
968 //jalr
969 //nop
970 return NativeCall::instruction_size;
971 }
973 int MachCallDynamicJavaNode::ret_addr_offset() {
974 /* 2012/9/10 Jin: must be kept in sync with Java_Dynamic_Call */
976 // return NativeCall::instruction_size;
977 assert(NativeCall::instruction_size == 24, "in MachCallDynamicJavaNode::ret_addr_offset");
978 //The value ought to be 4 + 16 bytes.
979 //lui IC_Klass,
980 //ori IC_Klass,
981 //dsll IC_Klass
982 //ori IC_Klass
983 //lui T9
984 //ori T9
985 //dsll T9
986 //ori T9
987 //jalr T9
988 //nop
989 return 6 * 4 + NativeCall::instruction_size;
991 }
993 /*
994 // EMIT_OPCODE()
995 void emit_opcode(CodeBuffer &cbuf, int code) {
996 *(cbuf.code_end()) = (unsigned char)code;
997 cbuf.set_code_end(cbuf.code_end() + 1);
998 }
999 */
1001 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
1002 int format) {
1003 cbuf.relocate(cbuf.insts_mark(), reloc, format);
1004 cbuf.insts()->emit_int32(d32);
1005 }
1007 //=============================================================================
1009 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1010 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1011 static enum RC rc_class( OptoReg::Name reg ) {
1012 if( !OptoReg::is_valid(reg) ) return rc_bad;
1013 if (OptoReg::is_stack(reg)) return rc_stack;
1014 VMReg r = OptoReg::as_VMReg(reg);
1015 if (r->is_Register()) return rc_int;
1016 assert(r->is_FloatRegister(), "must be");
1017 return rc_float;
1018 }
1020 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
1021 // Get registers to move
1022 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1023 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1024 OptoReg::Name dst_second = ra_->get_reg_second(this );
1025 OptoReg::Name dst_first = ra_->get_reg_first(this );
1027 enum RC src_second_rc = rc_class(src_second);
1028 enum RC src_first_rc = rc_class(src_first);
1029 enum RC dst_second_rc = rc_class(dst_second);
1030 enum RC dst_first_rc = rc_class(dst_first);
1032 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1034 // Generate spill code!
1035 int size = 0;
1037 if( src_first == dst_first && src_second == dst_second )
1038 return 0; // Self copy, no move
1040 if (src_first_rc == rc_stack) {
1041 // mem ->
1042 if (dst_first_rc == rc_stack) {
1043 // mem -> mem
1044 assert(src_second != dst_first, "overlap");
1045 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1046 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1047 // 64-bit
1048 int src_offset = ra_->reg2offset(src_first);
1049 int dst_offset = ra_->reg2offset(dst_first);
1050 if (cbuf) {
1051 MacroAssembler _masm(cbuf);
1052 __ ld(AT, Address(SP, src_offset));
1053 __ sd(AT, Address(SP, dst_offset));
1054 #ifndef PRODUCT
1055 } else {
1056 if(!do_size){
1057 if (size != 0) st->print("\n\t");
1058 st->print("ld AT, [SP + #%d]\t# 64-bit mem-mem spill 1\n\t"
1059 "sd AT, [SP + #%d]",
1060 src_offset, dst_offset);
1061 }
1062 #endif
1063 }
1064 size += 8;
1065 } else {
1066 // 32-bit
1067 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1068 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1069 // No pushl/popl, so:
1070 int src_offset = ra_->reg2offset(src_first);
1071 int dst_offset = ra_->reg2offset(dst_first);
1072 if (cbuf) {
1073 MacroAssembler _masm(cbuf);
1074 __ lw(AT, Address(SP, src_offset));
1075 __ sw(AT, Address(SP, dst_offset));
1076 #ifndef PRODUCT
1077 } else {
1078 if(!do_size){
1079 if (size != 0) st->print("\n\t");
1080 st->print("lw AT, [SP + #%d] spill 2\n\t"
1081 "sw AT, [SP + #%d]\n\t",
1082 src_offset, dst_offset);
1083 }
1084 #endif
1085 }
1086 size += 8;
1087 }
1088 return size;
1089 } else if (dst_first_rc == rc_int) {
1090 // mem -> gpr
1091 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1092 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1093 // 64-bit
1094 int offset = ra_->reg2offset(src_first);
1095 if (cbuf) {
1096 MacroAssembler _masm(cbuf);
1097 __ ld(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1098 #ifndef PRODUCT
1099 } else {
1100 if(!do_size){
1101 if (size != 0) st->print("\n\t");
1102 st->print("ld %s, [SP + #%d]\t# spill 3",
1103 Matcher::regName[dst_first],
1104 offset);
1105 }
1106 #endif
1107 }
1108 size += 4;
1109 } else {
1110 // 32-bit
1111 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1112 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1113 int offset = ra_->reg2offset(src_first);
1114 if (cbuf) {
1115 MacroAssembler _masm(cbuf);
1116 if (this->ideal_reg() == Op_RegI)
1117 __ lw(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1118 else
1119 __ lwu(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1120 #ifndef PRODUCT
1121 } else {
1122 if(!do_size){
1123 if (size != 0) st->print("\n\t");
1124 if (this->ideal_reg() == Op_RegI)
1125 st->print("lw %s, [SP + #%d]\t# spill 4",
1126 Matcher::regName[dst_first],
1127 offset);
1128 else
1129 st->print("lwu %s, [SP + #%d]\t# spill 5",
1130 Matcher::regName[dst_first],
1131 offset);
1132 }
1133 #endif
1134 }
1135 size += 4;
1136 }
1137 return size;
1138 } else if (dst_first_rc == rc_float) {
1139 // mem-> xmm
1140 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1141 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1142 // 64-bit
1143 int offset = ra_->reg2offset(src_first);
1144 if (cbuf) {
1145 MacroAssembler _masm(cbuf);
1146 __ ldc1( as_FloatRegister(Matcher::_regEncode[dst_first]), Address(SP, offset));
1147 #ifndef PRODUCT
1148 } else {
1149 if(!do_size){
1150 if (size != 0) st->print("\n\t");
1151 st->print("ldc1 %s, [SP + #%d]\t# spill 6",
1152 Matcher::regName[dst_first],
1153 offset);
1154 }
1155 #endif
1156 }
1157 size += 4;
1158 } else {
1159 // 32-bit
1160 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1161 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1162 int offset = ra_->reg2offset(src_first);
1163 if (cbuf) {
1164 MacroAssembler _masm(cbuf);
1165 __ lwc1( as_FloatRegister(Matcher::_regEncode[dst_first]), Address(SP, offset));
1166 #ifndef PRODUCT
1167 } else {
1168 if(!do_size){
1169 if (size != 0) st->print("\n\t");
1170 st->print("lwc1 %s, [SP + #%d]\t# spill 7",
1171 Matcher::regName[dst_first],
1172 offset);
1173 }
1174 #endif
1175 }
1176 size += 4;
1177 }
1178 return size;
1179 }
1180 } else if (src_first_rc == rc_int) {
1181 // gpr ->
1182 if (dst_first_rc == rc_stack) {
1183 // gpr -> mem
1184 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1185 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1186 // 64-bit
1187 int offset = ra_->reg2offset(dst_first);
1188 if (cbuf) {
1189 MacroAssembler _masm(cbuf);
1190 __ sd(as_Register(Matcher::_regEncode[src_first]), Address(SP, offset));
1191 #ifndef PRODUCT
1192 } else {
1193 if(!do_size){
1194 if (size != 0) st->print("\n\t");
1195 st->print("sd %s, [SP + #%d] # spill 8",
1196 Matcher::regName[src_first],
1197 offset);
1198 }
1199 #endif
1200 }
1201 size += 4;
1202 } else {
1203 // 32-bit
1204 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1205 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1206 int offset = ra_->reg2offset(dst_first);
1207 if (cbuf) {
1208 MacroAssembler _masm(cbuf);
1209 __ sw(as_Register(Matcher::_regEncode[src_first]), Address(SP, offset));
1210 #ifndef PRODUCT
1211 } else {
1212 if(!do_size){
1213 if (size != 0) st->print("\n\t");
1214 st->print("sw [SP + #%d], %s\t# spill 9",
1215 offset,
1216 Matcher::regName[src_first]);
1217 }
1218 #endif
1219 }
1220 size += 4;
1221 }
1222 return size;
1223 } else if (dst_first_rc == rc_int) {
1224 // gpr -> gpr
1225 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1226 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1227 // 64-bit
1228 if (cbuf) {
1229 MacroAssembler _masm(cbuf);
1230 __ move(as_Register(Matcher::_regEncode[dst_first]),
1231 as_Register(Matcher::_regEncode[src_first]));
1232 #ifndef PRODUCT
1233 } else {
1234 if(!do_size){
1235 if (size != 0) st->print("\n\t");
1236 st->print("move(64bit) %s, %s\t# spill 10",
1237 Matcher::regName[dst_first],
1238 Matcher::regName[src_first]);
1239 }
1240 #endif
1241 }
1242 size += 4;
1243 return size;
1244 } else {
1245 // 32-bit
1246 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1247 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1248 if (cbuf) {
1249 MacroAssembler _masm(cbuf);
1250 if (this->ideal_reg() == Op_RegI)
1251 __ move_u32(as_Register(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1252 else
1253 __ daddu(as_Register(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]), R0);
1255 #ifndef PRODUCT
1256 } else {
1257 if(!do_size){
1258 if (size != 0) st->print("\n\t");
1259 st->print("move(32-bit) %s, %s\t# spill 11",
1260 Matcher::regName[dst_first],
1261 Matcher::regName[src_first]);
1262 }
1263 #endif
1264 }
1265 size += 4;
1266 return size;
1267 }
1268 } else if (dst_first_rc == rc_float) {
1269 // gpr -> xmm
1270 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1271 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1272 // 64-bit
1273 if (cbuf) {
1274 MacroAssembler _masm(cbuf);
1275 __ dmtc1(as_Register(Matcher::_regEncode[src_first]), as_FloatRegister(Matcher::_regEncode[dst_first]));
1276 #ifndef PRODUCT
1277 } else {
1278 if(!do_size){
1279 if (size != 0) st->print("\n\t");
1280 st->print("dmtc1 %s, %s\t# spill 12",
1281 Matcher::regName[dst_first],
1282 Matcher::regName[src_first]);
1283 }
1284 #endif
1285 }
1286 size += 4;
1287 } else {
1288 // 32-bit
1289 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1290 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1291 if (cbuf) {
1292 MacroAssembler _masm(cbuf);
1293 __ mtc1( as_Register(Matcher::_regEncode[src_first]), as_FloatRegister(Matcher::_regEncode[dst_first]) );
1294 #ifndef PRODUCT
1295 } else {
1296 if(!do_size){
1297 if (size != 0) st->print("\n\t");
1298 st->print("mtc1 %s, %s\t# spill 13",
1299 Matcher::regName[dst_first],
1300 Matcher::regName[src_first]);
1301 }
1302 #endif
1303 }
1304 size += 4;
1305 }
1306 return size;
1307 }
1308 } else if (src_first_rc == rc_float) {
1309 // xmm ->
1310 if (dst_first_rc == rc_stack) {
1311 // xmm -> mem
1312 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1313 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1314 // 64-bit
1315 int offset = ra_->reg2offset(dst_first);
1316 if (cbuf) {
1317 MacroAssembler _masm(cbuf);
1318 __ sdc1( as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset) );
1319 #ifndef PRODUCT
1320 } else {
1321 if(!do_size){
1322 if (size != 0) st->print("\n\t");
1323 st->print("sdc1 %s, [SP + #%d]\t# spill 14",
1324 Matcher::regName[src_first],
1325 offset);
1326 }
1327 #endif
1328 }
1329 size += 4;
1330 } else {
1331 // 32-bit
1332 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1333 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1334 int offset = ra_->reg2offset(dst_first);
1335 if (cbuf) {
1336 MacroAssembler _masm(cbuf);
1337 __ swc1(as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset));
1338 #ifndef PRODUCT
1339 } else {
1340 if(!do_size){
1341 if (size != 0) st->print("\n\t");
1342 st->print("swc1 %s, [SP + #%d]\t# spill 15",
1343 Matcher::regName[src_first],
1344 offset);
1345 }
1346 #endif
1347 }
1348 size += 4;
1349 }
1350 return size;
1351 } else if (dst_first_rc == rc_int) {
1352 // xmm -> gpr
1353 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1354 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1355 // 64-bit
1356 if (cbuf) {
1357 MacroAssembler _masm(cbuf);
1358 __ dmfc1( as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1359 #ifndef PRODUCT
1360 } else {
1361 if(!do_size){
1362 if (size != 0) st->print("\n\t");
1363 st->print("dmfc1 %s, %s\t# spill 16",
1364 Matcher::regName[dst_first],
1365 Matcher::regName[src_first]);
1366 }
1367 #endif
1368 }
1369 size += 4;
1370 } else {
1371 // 32-bit
1372 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1373 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1374 if (cbuf) {
1375 MacroAssembler _masm(cbuf);
1376 __ mfc1( as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1377 #ifndef PRODUCT
1378 } else {
1379 if(!do_size){
1380 if (size != 0) st->print("\n\t");
1381 st->print("mfc1 %s, %s\t# spill 17",
1382 Matcher::regName[dst_first],
1383 Matcher::regName[src_first]);
1384 }
1385 #endif
1386 }
1387 size += 4;
1388 }
1389 return size;
1390 } else if (dst_first_rc == rc_float) {
1391 // xmm -> xmm
1392 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1393 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1394 // 64-bit
1395 if (cbuf) {
1396 MacroAssembler _masm(cbuf);
1397 __ mov_d( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1398 #ifndef PRODUCT
1399 } else {
1400 if(!do_size){
1401 if (size != 0) st->print("\n\t");
1402 st->print("mov_d %s, %s\t# spill 18",
1403 Matcher::regName[dst_first],
1404 Matcher::regName[src_first]);
1405 }
1406 #endif
1407 }
1408 size += 4;
1409 } else {
1410 // 32-bit
1411 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1412 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1413 if (cbuf) {
1414 MacroAssembler _masm(cbuf);
1415 __ mov_s( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1416 #ifndef PRODUCT
1417 } else {
1418 if(!do_size){
1419 if (size != 0) st->print("\n\t");
1420 st->print("mov_s %s, %s\t# spill 19",
1421 Matcher::regName[dst_first],
1422 Matcher::regName[src_first]);
1423 }
1424 #endif
1425 }
1426 size += 4;
1427 }
1428 return size;
1429 }
1430 }
1432 assert(0," foo ");
1433 Unimplemented();
1434 return size;
1436 }
1438 #ifndef PRODUCT
1439 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1440 implementation( NULL, ra_, false, st );
1441 }
1442 #endif
1444 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1445 implementation( &cbuf, ra_, false, NULL );
1446 }
1448 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1449 return implementation( NULL, ra_, true, NULL );
1450 }
1452 //=============================================================================
1453 #
1455 #ifndef PRODUCT
1456 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
1457 st->print("INT3");
1458 }
1459 #endif
1461 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc* ra_) const {
1462 MacroAssembler _masm(&cbuf);
1463 __ int3();
1464 }
1466 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
1467 return MachNode::size(ra_);
1468 }
1471 //=============================================================================
1472 #ifndef PRODUCT
1473 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1474 Compile *C = ra_->C;
1475 int framesize = C->frame_size_in_bytes();
1477 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1479 st->print("daddiu SP, SP, %d # Rlease stack @ MachEpilogNode",framesize);
1480 st->cr(); st->print("\t");
1481 st->print("ld RA, SP, %d # Restore RA @ MachEpilogNode", -8);
1482 st->cr(); st->print("\t");
1483 st->print("ld FP, SP, %d # Restore FP @ MachEpilogNode", -16);
1485 if( do_polling() && C->is_method_compilation() ) {
1486 st->print("Poll Safepoint # MachEpilogNode");
1487 }
1488 }
1489 #endif
1491 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1492 Compile *C = ra_->C;
1493 MacroAssembler _masm(&cbuf);
1494 int framesize = C->frame_size_in_bytes();
1496 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1498 __ daddiu(SP, SP, framesize);
1499 __ ld(RA, SP, -wordSize );
1500 __ ld(FP, SP, -wordSize*2 );
1502 /* 2012/11/19 Jin: The epilog in a RuntimeStub should not contain a safepoint */
1503 if( do_polling() && C->is_method_compilation() ) {
1504 #ifndef OPT_SAFEPOINT
1505 __ li48(AT, (long)os::get_polling_page());
1506 __ relocate(relocInfo::poll_return_type);
1507 __ lw(AT, AT, 0);
1508 #else
1509 __ lui(AT, Assembler::split_high((intptr_t)os::get_polling_page()));
1510 __ relocate(relocInfo::poll_return_type);
1511 __ lw(AT, AT, Assembler::split_low((intptr_t)os::get_polling_page()));
1512 #endif
1513 }
1514 }
1516 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1517 return MachNode::size(ra_); // too many variables; just compute it the hard way fujie debug
1518 }
1520 int MachEpilogNode::reloc() const {
1521 return 0; // a large enough number
1522 }
1524 const Pipeline * MachEpilogNode::pipeline() const {
1525 return MachNode::pipeline_class();
1526 }
1528 int MachEpilogNode::safepoint_offset() const { return 0; }
1530 //=============================================================================
1532 #ifndef PRODUCT
1533 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1534 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1535 int reg = ra_->get_reg_first(this);
1536 st->print("ADDI %s, SP, %d @BoxLockNode",Matcher::regName[reg],offset);
1537 }
1538 #endif
1541 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1542 return 4;
1543 }
1545 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1546 MacroAssembler _masm(&cbuf);
1547 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1548 int reg = ra_->get_encode(this);
1550 __ addi(as_Register(reg), SP, offset);
1551 /*
1552 if( offset >= 128 ) {
1553 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1554 emit_rm(cbuf, 0x2, reg, 0x04);
1555 emit_rm(cbuf, 0x0, 0x04, SP_enc);
1556 emit_d32(cbuf, offset);
1557 }
1558 else {
1559 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1560 emit_rm(cbuf, 0x1, reg, 0x04);
1561 emit_rm(cbuf, 0x0, 0x04, SP_enc);
1562 emit_d8(cbuf, offset);
1563 }
1564 */
1565 }
1568 //static int sizeof_FFree_Float_Stack_All = -1;
1570 int MachCallRuntimeNode::ret_addr_offset() {
1571 //lui
1572 //ori
1573 //dsll
1574 //ori
1575 //jalr
1576 //nop
1577 assert(NativeCall::instruction_size == 24, "in MachCallRuntimeNode::ret_addr_offset()");
1578 return NativeCall::instruction_size;
1579 // return 16;
1580 }
1586 //=============================================================================
1587 #ifndef PRODUCT
1588 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1589 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1590 }
1591 #endif
1593 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1594 MacroAssembler _masm(&cbuf);
1595 int i = 0;
1596 for(i = 0; i < _count; i++)
1597 __ nop();
1598 }
1600 uint MachNopNode::size(PhaseRegAlloc *) const {
1601 return 4 * _count;
1602 }
1603 const Pipeline* MachNopNode::pipeline() const {
1604 return MachNode::pipeline_class();
1605 }
1607 //=============================================================================
1609 //=============================================================================
1610 #ifndef PRODUCT
1611 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1612 st->print_cr("load_klass(AT, T0)");
1613 st->print_cr("\tbeq(AT, iCache, L)");
1614 st->print_cr("\tnop");
1615 st->print_cr("\tjmp(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type)");
1616 st->print_cr("\tnop");
1617 st->print_cr("\tnop");
1618 st->print_cr(" L:");
1619 }
1620 #endif
1623 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1624 MacroAssembler _masm(&cbuf);
1625 #ifdef ASSERT
1626 //uint code_size = cbuf.code_size();
1627 #endif
1628 int ic_reg = Matcher::inline_cache_reg_encode();
1629 Label L;
1630 Register receiver = T0;
1631 Register iCache = as_Register(ic_reg);
1632 __ load_klass(AT, receiver);
1633 __ beq(AT, iCache, L);
1634 __ nop();
1636 __ relocate(relocInfo::runtime_call_type);
1637 __ li48(T9, (long)SharedRuntime::get_ic_miss_stub());
1638 __ jr(T9);
1639 __ nop();
1641 /* WARNING these NOPs are critical so that verified entry point is properly
1642 * 8 bytes aligned for patching by NativeJump::patch_verified_entry() */
1643 __ align(CodeEntryAlignment);
1644 __ bind(L);
1645 }
1647 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1648 return MachNode::size(ra_);
1649 }
1653 //=============================================================================
1655 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
1657 int Compile::ConstantTable::calculate_table_base_offset() const {
1658 return 0; // absolute addressing, no offset
1659 }
1661 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1662 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1663 ShouldNotReachHere();
1664 }
1666 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1667 // Empty encoding
1668 }
1670 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1671 return 0;
1672 }
1674 #ifndef PRODUCT
1675 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1676 st->print("# MachConstantBaseNode (empty encoding)");
1677 }
1678 #endif
1681 //=============================================================================
1682 #ifndef PRODUCT
1683 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1684 Compile* C = ra_->C;
1686 int framesize = C->frame_size_in_bytes();
1687 int bangsize = C->bang_size_in_bytes();
1688 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1690 // Calls to C2R adapters often do not accept exceptional returns.
1691 // We require that their callers must bang for them. But be careful, because
1692 // some VM calls (such as call site linkage) can use several kilobytes of
1693 // stack. But the stack safety zone should account for that.
1694 // See bugs 4446381, 4468289, 4497237.
1695 if (C->need_stack_bang(bangsize)) {
1696 st->print_cr("# stack bang"); st->print("\t");
1697 }
1698 st->print("sd RA, (SP)-8 @ MachPrologNode\n\t");
1699 st->print("sd FP, (SP)-16 \n\t");
1700 st->print("daddiu FP, SP, -16 \n\t");
1701 st->print("daddiu SP, SP, -%d \t",framesize);
1702 }
1703 #endif
1706 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1707 Compile* C = ra_->C;
1708 MacroAssembler _masm(&cbuf);
1710 int framesize = C->frame_size_in_bytes();
1711 int bangsize = C->bang_size_in_bytes();
1713 // __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
1715 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1717 if (C->need_stack_bang(framesize)) {
1718 __ generate_stack_overflow_check(framesize);
1719 }
1721 __ sd(RA, SP, -wordSize);
1722 __ sd(FP, SP, -wordSize*2);
1723 __ daddiu(FP, SP, -wordSize*2);
1724 __ daddiu(SP, SP, -framesize);
1725 __ nop(); /* 2013.10.22 Jin: Make enough room for patch_verified_entry() */
1726 __ nop();
1728 C->set_frame_complete(cbuf.insts_size());
1729 if (C->has_mach_constant_base_node()) {
1730 // NOTE: We set the table base offset here because users might be
1731 // emitted before MachConstantBaseNode.
1732 Compile::ConstantTable& constant_table = C->constant_table();
1733 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1734 }
1736 }
1739 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1740 //fprintf(stderr, "\nPrologNode::size(ra_)= %d \n", MachNode::size(ra_));//fujie debug
1741 return MachNode::size(ra_); // too many variables; just compute it the hard way
1742 }
1744 int MachPrologNode::reloc() const {
1745 return 0; // a large enough number
1746 }
1748 %}
1750 //----------ENCODING BLOCK-----------------------------------------------------
1751 // This block specifies the encoding classes used by the compiler to output
1752 // byte streams. Encoding classes generate functions which are called by
1753 // Machine Instruction Nodes in order to generate the bit encoding of the
1754 // instruction. Operands specify their base encoding interface with the
1755 // interface keyword. There are currently supported four interfaces,
1756 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1757 // operand to generate a function which returns its register number when
1758 // queried. CONST_INTER causes an operand to generate a function which
1759 // returns the value of the constant when queried. MEMORY_INTER causes an
1760 // operand to generate four functions which return the Base Register, the
1761 // Index Register, the Scale Value, and the Offset Value of the operand when
1762 // queried. COND_INTER causes an operand to generate six functions which
1763 // return the encoding code (ie - encoding bits for the instruction)
1764 // associated with each basic boolean condition for a conditional instruction.
1765 // Instructions specify two basic values for encoding. They use the
1766 // ins_encode keyword to specify their encoding class (which must be one of
1767 // the class names specified in the encoding block), and they use the
1768 // opcode keyword to specify, in order, their primary, secondary, and
1769 // tertiary opcode. Only the opcode sections which a particular instruction
1770 // needs for encoding need to be specified.
1771 encode %{
1772 /*
1773 Alias:
1774 1044 b java.io.ObjectInputStream::readHandle (130 bytes)
1775 118 B14: # B19 B15 <- B13 Freq: 0.899955
1776 118 add S1, S2, V0 #@addP_reg_reg
1777 11c lb S0, [S1 + #-8257524] #@loadB
1778 120 BReq S0, #3, B19 #@branchConI_reg_imm P=0.100000 C=-1.000000
1779 */
1780 //Load byte signed
1781 enc_class load_B_enc (mRegI dst, memory mem) %{
1782 MacroAssembler _masm(&cbuf);
1783 int dst = $dst$$reg;
1784 int base = $mem$$base;
1785 int index = $mem$$index;
1786 int scale = $mem$$scale;
1787 int disp = $mem$$disp;
1789 guarantee(scale == 0, "scale is not zero !");
1791 if( index != 0 ) {
1792 __ addu(AT, as_Register(base), as_Register(index));
1793 if( Assembler::is_simm16(disp) ) {
1794 __ lb(as_Register(dst), AT, disp);
1795 } else {
1796 __ move(T9, disp);
1797 __ addu(AT, AT, T9);
1798 __ lb(as_Register(dst), AT, 0);
1799 }
1800 } else {
1801 if( Assembler::is_simm16(disp) ) {
1802 __ lb(as_Register(dst), as_Register(base), disp);
1803 } else {
1804 __ move(T9, disp);
1805 __ addu(AT, as_Register(base), T9);
1806 __ lb(as_Register(dst), AT, 0);
1807 }
1808 }
1809 %}
1811 //Load byte unsigned
1812 enc_class load_UB_enc (mRegI dst, memory mem) %{
1813 MacroAssembler _masm(&cbuf);
1814 int dst = $dst$$reg;
1815 int base = $mem$$base;
1816 int index = $mem$$index;
1817 int scale = $mem$$scale;
1818 int disp = $mem$$disp;
1820 guarantee(scale == 0, "scale is not zero !");
1822 if( index != 0 ) {
1823 __ daddu(AT, as_Register(base), as_Register(index));
1824 if( Assembler::is_simm16(disp) ) {
1825 __ lbu(as_Register(dst), AT, disp);
1826 } else {
1827 __ move(T9, disp);
1828 __ daddu(AT, AT, T9);
1829 __ lbu(as_Register(dst), AT, 0);
1830 }
1831 } else {
1832 if( Assembler::is_simm16(disp) ) {
1833 __ lbu(as_Register(dst), as_Register(base), disp);
1834 } else {
1835 __ move(T9, disp);
1836 __ daddu(AT, as_Register(base), T9);
1837 __ lbu(as_Register(dst), AT, 0);
1838 }
1839 }
1840 %}
1842 enc_class store_B_reg_enc (memory mem, mRegI src) %{
1843 MacroAssembler _masm(&cbuf);
1844 int src = $src$$reg;
1845 int base = $mem$$base;
1846 int index = $mem$$index;
1847 int scale = $mem$$scale;
1848 int disp = $mem$$disp;
1850 guarantee(scale == 0, "scale is not zero !");
1852 if( index != 0 ) {
1853 __ addu(AT, as_Register(base), as_Register(index));
1854 if( Assembler::is_simm16(disp) ) {
1855 __ sb(as_Register(src), AT, disp);
1856 } else {
1857 __ move(T9, disp);
1858 __ addu(AT, AT, T9);
1859 __ sb(as_Register(src), AT, 0);
1860 }
1861 } else {
1862 if( Assembler::is_simm16(disp) ) {
1863 __ sb(as_Register(src), as_Register(base), disp);
1864 } else {
1865 __ move(T9, disp);
1866 __ addu(AT, as_Register(base), T9);
1867 __ sb(as_Register(src), AT, 0);
1868 }
1869 }
1870 %}
1872 enc_class store_B_immI_enc (memory mem, immI8 src) %{
1873 MacroAssembler _masm(&cbuf);
1874 int base = $mem$$base;
1875 int index = $mem$$index;
1876 int scale = $mem$$scale;
1877 int disp = $mem$$disp;
1878 int value = $src$$constant;
1880 guarantee(scale == 0, "scale is not zero !");
1882 if( index != 0 ) {
1883 __ daddu(AT, as_Register(base), as_Register(index));
1884 if( Assembler::is_simm16(disp) ) {
1885 if (value == 0) {
1886 __ sync();
1887 __ sb(R0, AT, disp);
1888 } else {
1889 __ move(T9, value);
1890 __ sync();
1891 __ sb(T9, AT, disp);
1892 }
1893 } else {
1894 if (value == 0) {
1895 __ move(T9, disp);
1896 __ daddu(AT, AT, T9);
1897 __ sync();
1898 __ sb(R0, AT, 0);
1899 } else {
1900 __ move(T9, disp);
1901 __ daddu(AT, AT, T9);
1902 __ move(T9, value);
1903 __ sync();
1904 __ sb(T9, AT, 0);
1905 }
1906 }
1907 } else {
1908 if( Assembler::is_simm16(disp) ) {
1909 if (value == 0) {
1910 __ sync();
1911 __ sb(R0, as_Register(base), disp);
1912 } else {
1913 __ move(AT, value);
1914 __ sync();
1915 __ sb(AT, as_Register(base), disp);
1916 }
1917 } else {
1918 if (value == 0) {
1919 __ move(T9, disp);
1920 __ daddu(AT, as_Register(base), T9);
1921 __ sync();
1922 __ sb(R0, AT, 0);
1923 } else {
1924 __ move(T9, disp);
1925 __ daddu(AT, as_Register(base), T9);
1926 __ move(T9, value);
1927 __ sync();
1928 __ sb(T9, AT, 0);
1929 }
1930 }
1931 }
1932 %}
1934 // Load Short (16bit signed)
1935 enc_class load_S_enc (mRegI dst, memory mem) %{
1936 MacroAssembler _masm(&cbuf);
1937 int dst = $dst$$reg;
1938 int base = $mem$$base;
1939 int index = $mem$$index;
1940 int scale = $mem$$scale;
1941 int disp = $mem$$disp;
1943 guarantee(scale == 0, "scale is not zero !");
1945 if( index != 0 ) {
1946 __ addu(AT, as_Register(base), as_Register(index));
1947 if( Assembler::is_simm16(disp) ) {
1948 __ lh(as_Register(dst), AT, disp);
1949 } else {
1950 __ move(T9, disp);
1951 __ addu(AT, AT, T9);
1952 __ lh(as_Register(dst), AT, 0);
1953 }
1954 } else {
1955 if( Assembler::is_simm16(disp) ) {
1956 __ lh(as_Register(dst), as_Register(base), disp);
1957 } else {
1958 __ move(T9, disp);
1959 __ addu(AT, as_Register(base), T9);
1960 __ lh(as_Register(dst), AT, 0);
1961 }
1962 }
1963 %}
1965 // Load Char (16bit unsigned)
1966 enc_class load_C_enc (mRegI dst, memory mem) %{
1967 MacroAssembler _masm(&cbuf);
1968 int dst = $dst$$reg;
1969 int base = $mem$$base;
1970 int index = $mem$$index;
1971 int scale = $mem$$scale;
1972 int disp = $mem$$disp;
1974 guarantee(scale == 0, "scale is not zero !");
1976 if( index != 0 ) {
1977 __ daddu(AT, as_Register(base), as_Register(index));
1978 if( Assembler::is_simm16(disp) ) {
1979 __ lhu(as_Register(dst), AT, disp);
1980 } else {
1981 __ move(T9, disp);
1982 __ addu(AT, AT, T9);
1983 __ lhu(as_Register(dst), AT, 0);
1984 }
1985 } else {
1986 if( Assembler::is_simm16(disp) ) {
1987 __ lhu(as_Register(dst), as_Register(base), disp);
1988 } else {
1989 __ move(T9, disp);
1990 __ daddu(AT, as_Register(base), T9);
1991 __ lhu(as_Register(dst), AT, 0);
1992 }
1993 }
1994 %}
1996 // Store Char (16bit unsigned)
1997 enc_class store_C_reg_enc (memory mem, mRegI src) %{
1998 MacroAssembler _masm(&cbuf);
1999 int src = $src$$reg;
2000 int base = $mem$$base;
2001 int index = $mem$$index;
2002 int scale = $mem$$scale;
2003 int disp = $mem$$disp;
2005 guarantee(scale == 0, "scale is not zero !");
2007 if( index != 0 ) {
2008 __ addu(AT, as_Register(base), as_Register(index));
2009 if( Assembler::is_simm16(disp) ) {
2010 __ sh(as_Register(src), AT, disp);
2011 } else {
2012 __ move(T9, disp);
2013 __ addu(AT, AT, T9);
2014 __ sh(as_Register(src), AT, 0);
2015 }
2016 } else {
2017 if( Assembler::is_simm16(disp) ) {
2018 __ sh(as_Register(src), as_Register(base), disp);
2019 } else {
2020 __ move(T9, disp);
2021 __ addu(AT, as_Register(base), T9);
2022 __ sh(as_Register(src), AT, 0);
2023 }
2024 }
2025 %}
2027 enc_class load_I_enc (mRegI dst, memory mem) %{
2028 MacroAssembler _masm(&cbuf);
2029 int dst = $dst$$reg;
2030 int base = $mem$$base;
2031 int index = $mem$$index;
2032 int scale = $mem$$scale;
2033 int disp = $mem$$disp;
2035 guarantee(scale == 0, "scale is not zero !");
2037 if( index != 0 ) {
2038 __ addu(AT, as_Register(base), as_Register(index));
2039 if( Assembler::is_simm16(disp) ) {
2040 __ lw(as_Register(dst), AT, disp);
2041 } else {
2042 __ move(T9, disp);
2043 __ addu(AT, AT, T9);
2044 __ lw(as_Register(dst), AT, 0);
2045 }
2046 } else {
2047 if( Assembler::is_simm16(disp) ) {
2048 __ lw(as_Register(dst), as_Register(base), disp);
2049 } else {
2050 __ move(T9, disp);
2051 __ addu(AT, as_Register(base), T9);
2052 __ lw(as_Register(dst), AT, 0);
2053 }
2054 }
2055 %}
2057 enc_class store_I_reg_enc (memory mem, mRegI src) %{
2058 MacroAssembler _masm(&cbuf);
2059 int src = $src$$reg;
2060 int base = $mem$$base;
2061 int index = $mem$$index;
2062 int scale = $mem$$scale;
2063 int disp = $mem$$disp;
2065 guarantee(scale == 0, "scale is not zero !");
2067 if( index != 0 ) {
2068 __ addu(AT, as_Register(base), as_Register(index));
2069 if( Assembler::is_simm16(disp) ) {
2070 __ sw(as_Register(src), AT, disp);
2071 } else {
2072 __ move(T9, disp);
2073 __ addu(AT, AT, T9);
2074 __ sw(as_Register(src), AT, 0);
2075 }
2076 } else {
2077 if( Assembler::is_simm16(disp) ) {
2078 __ sw(as_Register(src), as_Register(base), disp);
2079 } else {
2080 __ move(T9, disp);
2081 __ addu(AT, as_Register(base), T9);
2082 __ sw(as_Register(src), AT, 0);
2083 }
2084 }
2085 %}
2087 enc_class store_I_immI_enc (memory mem, immI src) %{
2088 MacroAssembler _masm(&cbuf);
2089 int base = $mem$$base;
2090 int index = $mem$$index;
2091 int scale = $mem$$scale;
2092 int disp = $mem$$disp;
2093 int value = $src$$constant;
2095 guarantee(scale == 0, "scale is not zero !");
2097 if( index != 0 ) {
2098 __ daddu(AT, as_Register(base), as_Register(index));
2099 if( Assembler::is_simm16(disp) ) {
2100 if (value == 0) {
2101 __ sw(R0, AT, disp);
2102 } else {
2103 __ move(T9, value);
2104 __ sw(T9, AT, disp);
2105 }
2106 } else {
2107 if (value == 0) {
2108 __ move(T9, disp);
2109 __ addu(AT, AT, T9);
2110 __ sw(R0, AT, 0);
2111 } else {
2112 __ move(T9, disp);
2113 __ addu(AT, AT, T9);
2114 __ move(T9, value);
2115 __ sw(T9, AT, 0);
2116 }
2117 }
2118 } else {
2119 if( Assembler::is_simm16(disp) ) {
2120 if (value == 0) {
2121 __ sw(R0, as_Register(base), disp);
2122 } else {
2123 __ move(AT, value);
2124 __ sw(AT, as_Register(base), disp);
2125 }
2126 } else {
2127 if (value == 0) {
2128 __ move(T9, disp);
2129 __ addu(AT, as_Register(base), T9);
2130 __ sw(R0, AT, 0);
2131 } else {
2132 __ move(T9, disp);
2133 __ addu(AT, as_Register(base), T9);
2134 __ move(T9, value);
2135 __ sw(T9, AT, 0);
2136 }
2137 }
2138 }
2139 %}
2141 enc_class load_N_enc (mRegN dst, memory mem) %{
2142 MacroAssembler _masm(&cbuf);
2143 int dst = $dst$$reg;
2144 int base = $mem$$base;
2145 int index = $mem$$index;
2146 int scale = $mem$$scale;
2147 int disp = $mem$$disp;
2148 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2149 assert(disp_reloc == relocInfo::none, "cannot have disp");
2151 if( index != 0 ) {
2152 __ daddu(AT, as_Register(base), as_Register(index));
2153 if( Assembler::is_simm16(disp) ) {
2154 __ lwu(as_Register(dst), AT, disp);
2155 } else {
2156 __ li(T9, disp);
2157 __ daddu(AT, AT, T9);
2158 __ lwu(as_Register(dst), AT, 0);
2159 }
2160 } else {
2161 if( Assembler::is_simm16(disp) ) {
2162 __ lwu(as_Register(dst), as_Register(base), disp);
2163 } else {
2164 __ li(T9, disp);
2165 __ daddu(AT, as_Register(base), T9);
2166 __ lwu(as_Register(dst), AT, 0);
2167 }
2168 }
2170 %}
2171 enc_class load_P_enc (mRegP dst, memory mem) %{
2172 MacroAssembler _masm(&cbuf);
2173 int dst = $dst$$reg;
2174 int base = $mem$$base;
2175 int index = $mem$$index;
2176 int scale = $mem$$scale;
2177 int disp = $mem$$disp;
2178 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2179 assert(disp_reloc == relocInfo::none, "cannot have disp");
2181 if( index != 0 ) {
2182 __ daddu(AT, as_Register(base), as_Register(index));
2183 if( Assembler::is_simm16(disp) ) {
2184 __ ld(as_Register(dst), AT, disp);
2185 } else {
2186 __ li(T9, disp);
2187 __ daddu(AT, AT, T9);
2188 __ ld(as_Register(dst), AT, 0);
2189 }
2190 } else {
2191 if( Assembler::is_simm16(disp) ) {
2192 __ ld(as_Register(dst), as_Register(base), disp);
2193 } else {
2194 __ li(T9, disp);
2195 __ daddu(AT, as_Register(base), T9);
2196 __ ld(as_Register(dst), AT, 0);
2197 }
2198 }
2199 // if( disp_reloc != relocInfo::none) __ ld(as_Register(dst), as_Register(dst), 0);
2200 %}
2202 enc_class store_P_reg_enc (memory mem, mRegP src) %{
2203 MacroAssembler _masm(&cbuf);
2204 int src = $src$$reg;
2205 int base = $mem$$base;
2206 int index = $mem$$index;
2207 int scale = $mem$$scale;
2208 int disp = $mem$$disp;
2210 guarantee(scale == 0, "scale is not zero !");
2212 if( index != 0 ) {
2213 __ daddu(AT, as_Register(base), as_Register(index));
2214 if( Assembler::is_simm16(disp) ) {
2215 __ sd(as_Register(src), AT, disp);
2216 } else {
2217 __ move(T9, disp);
2218 __ daddu(AT, AT, T9);
2219 __ sd(as_Register(src), AT, 0);
2220 }
2221 } else {
2222 if( Assembler::is_simm16(disp) ) {
2223 __ sd(as_Register(src), as_Register(base), disp);
2224 } else {
2225 __ move(T9, disp);
2226 __ daddu(AT, as_Register(base), T9);
2227 __ sd(as_Register(src), AT, 0);
2228 }
2229 }
2230 %}
2232 enc_class store_N_reg_enc (memory mem, mRegN src) %{
2233 MacroAssembler _masm(&cbuf);
2234 int src = $src$$reg;
2235 int base = $mem$$base;
2236 int index = $mem$$index;
2237 int scale = $mem$$scale;
2238 int disp = $mem$$disp;
2240 guarantee(scale == 0, "scale is not zero !");
2242 if( index != 0 ) {
2243 __ addu(AT, as_Register(base), as_Register(index));
2244 if( Assembler::is_simm16(disp) ) {
2245 __ sw(as_Register(src), AT, disp);
2246 } else {
2247 __ move(T9, disp);
2248 __ addu(AT, AT, T9);
2249 __ sw(as_Register(src), AT, 0);
2250 }
2251 } else {
2252 if( Assembler::is_simm16(disp) ) {
2253 __ sw(as_Register(src), as_Register(base), disp);
2254 } else {
2255 __ move(T9, disp);
2256 __ addu(AT, as_Register(base), T9);
2257 __ sw(as_Register(src), AT, 0);
2258 }
2259 }
2260 %}
2262 enc_class store_P_immP_enc (memory mem, immP31 src) %{
2263 MacroAssembler _masm(&cbuf);
2264 int base = $mem$$base;
2265 int index = $mem$$index;
2266 int scale = $mem$$scale;
2267 int disp = $mem$$disp;
2268 long value = $src$$constant;
2270 guarantee(scale == 0, "scale is not zero !");
2272 if( index != 0 ) {
2273 __ daddu(AT, as_Register(base), as_Register(index));
2274 if( Assembler::is_simm16(disp) ) {
2275 if (value == 0) {
2276 __ sd(R0, AT, disp);
2277 } else {
2278 __ move(T9, value);
2279 __ sd(T9, AT, disp);
2280 }
2281 } else {
2282 if (value == 0) {
2283 __ move(T9, disp);
2284 __ daddu(AT, AT, T9);
2285 __ sd(R0, AT, 0);
2286 } else {
2287 __ move(T9, disp);
2288 __ daddu(AT, AT, T9);
2289 __ move(T9, value);
2290 __ sd(T9, AT, 0);
2291 }
2292 }
2293 } else {
2294 if( Assembler::is_simm16(disp) ) {
2295 if (value == 0) {
2296 __ sd(R0, as_Register(base), disp);
2297 } else {
2298 __ move(AT, value);
2299 __ sd(AT, as_Register(base), disp);
2300 }
2301 } else {
2302 if (value == 0) {
2303 __ move(T9, disp);
2304 __ daddu(AT, as_Register(base), T9);
2305 __ sd(R0, AT, 0);
2306 } else {
2307 __ move(T9, disp);
2308 __ daddu(AT, as_Register(base), T9);
2309 __ move(T9, value);
2310 __ sd(T9, AT, 0);
2311 }
2312 }
2313 }
2314 %}
2316 /*
2317 * 1d4 storeImmN [S0 + #16 (8-bit)], narrowoop: spec/benchmarks/_213_javac/Identifier:exact *
2318 * # compressed ptr ! Field: spec/benchmarks/_213_javac/Identifier.value
2319 * 0x00000055648065d4: daddu at, s0, zero
2320 * 0x00000055648065d8: lui t9, 0x0 ; {oop(a 'spec/benchmarks/_213_javac/Identifier')}
2321 * 0x00000055648065dc: ori t9, t9, 0xfffff610
2322 * 0x00000055648065e0: dsll t9, t9, 16
2323 * 0x00000055648065e4: ori t9, t9, 0xffffc628
2324 * 0x00000055648065e8: sw t9, 0x10(at)
2325 */
2326 enc_class storeImmN_enc (memory mem, immN src) %{
2327 MacroAssembler _masm(&cbuf);
2328 int base = $mem$$base;
2329 int index = $mem$$index;
2330 int scale = $mem$$scale;
2331 int disp = $mem$$disp;
2332 long * value = (long *)$src$$constant;
2334 if (value == NULL) {
2335 guarantee(Assembler::is_simm16(disp), "FIXME: disp is not simm16!");
2336 if (index == 0) {
2337 __ sw(R0, as_Register(base), disp);
2338 } else {
2339 __ daddu(AT, as_Register(base), as_Register(index));
2340 __ sw(R0, AT, disp);
2341 }
2343 return;
2344 }
2346 int oop_index = __ oop_recorder()->find_index((jobject)value);
2347 RelocationHolder rspec = oop_Relocation::spec(oop_index);
2349 guarantee(scale == 0, "FIXME: scale is not zero !");
2350 guarantee(value != 0, "FIXME: value is zero !");
2352 if (index != 0) {
2353 __ daddu(AT, as_Register(base), as_Register(index));
2354 if( Assembler::is_simm16(disp) ) {
2355 if(rspec.type() != relocInfo::none) {
2356 __ relocate(rspec, Assembler::narrow_oop_operand);
2357 __ li48(T9, oop_index);
2358 } else {
2359 __ move(T9, oop_index);
2360 }
2361 __ sw(T9, AT, disp);
2362 } else {
2363 __ move(T9, disp);
2364 __ addu(AT, AT, T9);
2366 if(rspec.type() != relocInfo::none) {
2367 __ relocate(rspec, Assembler::narrow_oop_operand);
2368 __ li48(T9, oop_index);
2369 } else {
2370 __ move(T9, oop_index);
2371 }
2372 __ sw(T9, AT, 0);
2373 }
2374 }
2375 else {
2376 if( Assembler::is_simm16(disp) ) {
2377 if($src->constant_reloc() != relocInfo::none) {
2378 __ relocate(rspec, Assembler::narrow_oop_operand);
2379 __ li48(T9, oop_index);
2380 }
2381 else {
2382 __ li48(T9, oop_index);
2383 }
2384 __ sw(T9, as_Register(base), disp);
2385 } else {
2386 __ move(T9, disp);
2387 __ daddu(AT, as_Register(base), T9);
2389 if($src->constant_reloc() != relocInfo::none){
2390 __ relocate(rspec, Assembler::narrow_oop_operand);
2391 __ li48(T9, oop_index);
2392 } else {
2393 __ li48(T9, oop_index);
2394 }
2395 __ sw(T9, AT, 0);
2396 }
2397 }
2398 %}
2400 enc_class storeImmNKlass_enc (memory mem, immNKlass src) %{
2401 MacroAssembler _masm(&cbuf);
2403 assert (UseCompressedOops, "should only be used for compressed headers");
2404 assert (__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
2406 int base = $mem$$base;
2407 int index = $mem$$index;
2408 int scale = $mem$$scale;
2409 int disp = $mem$$disp;
2410 long value = $src$$constant;
2412 guarantee(scale == 0, "scale is not zero !");
2414 int klass_index = __ oop_recorder()->find_index((Klass*)value);
2415 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
2416 long narrowp = Klass::encode_klass((Klass*)value);
2418 if(index!=0){
2419 __ daddu(AT, as_Register(base), as_Register(index));
2420 if( Assembler::is_simm16(disp) ) {
2421 if(rspec.type() != relocInfo::none){
2422 __ relocate(rspec, Assembler::narrow_oop_operand);
2423 __ li48(T9, narrowp);
2424 }
2425 else {
2426 __ li48(T9, narrowp);
2427 }
2428 __ sw(T9, AT, disp);
2429 } else {
2430 __ move(T9, disp);
2431 __ daddu(AT, AT, T9);
2433 if(rspec.type() != relocInfo::none){
2434 __ relocate(rspec, Assembler::narrow_oop_operand);
2435 __ li48(T9, narrowp);
2436 }
2437 else {
2438 __ li48(T9, narrowp);
2439 }
2441 __ sw(T9, AT, 0);
2442 }
2443 }
2444 else {
2445 if( Assembler::is_simm16(disp) ) {
2446 if(rspec.type() != relocInfo::none){
2447 __ relocate(rspec, Assembler::narrow_oop_operand);
2448 __ li48(T9, narrowp);
2449 }
2450 else {
2451 __ li48(T9, narrowp);
2452 }
2453 __ sw(T9, as_Register(base), disp);
2454 } else {
2455 __ move(T9, disp);
2456 __ daddu(AT, as_Register(base), T9);
2458 if(rspec.type() != relocInfo::none){
2459 __ relocate(rspec, Assembler::narrow_oop_operand);
2460 __ li48(T9, narrowp);
2461 }
2462 else {
2463 __ li48(T9, narrowp);
2464 }
2465 __ sw(T9, AT, 0);
2466 }
2467 }
2468 %}
2470 enc_class storeImmN0_enc(memory mem, ImmN0 src) %{
2471 MacroAssembler _masm(&cbuf);
2472 int base = $mem$$base;
2473 int index = $mem$$index;
2474 int scale = $mem$$scale;
2475 int disp = $mem$$disp;
2477 guarantee(scale == 0, "scale is not zero !");
2479 if(index!=0){
2480 __ daddu(AT, as_Register(base), as_Register(index));
2481 if( Assembler::is_simm16(disp) ) {
2482 __ sw(S5_heapbase, AT, disp);
2483 } else {
2484 __ move(T9, disp);
2485 __ daddu(AT, AT, T9);
2486 __ sw(S5_heapbase, AT, 0);
2487 }
2488 }
2489 else {
2490 if( Assembler::is_simm16(disp) ) {
2491 __ sw(S5_heapbase, as_Register(base), disp);
2492 } else {
2493 __ move(T9, disp);
2494 __ daddu(AT, as_Register(base), T9);
2495 __ sw(S5_heapbase, AT, 0);
2496 }
2497 }
2498 %}
2500 enc_class load_L_enc (mRegL dst, memory mem) %{
2501 MacroAssembler _masm(&cbuf);
2502 int base = $mem$$base;
2503 int index = $mem$$index;
2504 int scale = $mem$$scale;
2505 int disp = $mem$$disp;
2506 Register dst_reg = as_Register($dst$$reg);
2508 guarantee(scale == 0, "scale is not zero !");
2510 /*********************2013/03/27**************************
2511 * Jin: $base may contain a null object.
2512 * Server JIT force the exception_offset to be the pos of
2513 * the first instruction.
2514 * I insert such a 'null_check' at the beginning.
2515 *******************************************************/
2517 __ lw(AT, as_Register(base), 0);
2519 /*********************2012/10/04**************************
2520 * Error case found in SortTest
2521 * 337 b java.util.Arrays::sort1 (401 bytes)
2522 * B73:
2523 * d34 lw T4.lo, [T4 + #16] #@loadL-lo
2524 * lw T4.hi, [T4 + #16]+4 #@loadL-hi
2525 *
2526 * The original instructions generated here are :
2527 * __ lw(dst_lo, as_Register(base), disp);
2528 * __ lw(dst_hi, as_Register(base), disp + 4);
2529 *******************************************************/
2531 if( index != 0 ) {
2532 __ daddu(AT, as_Register(base), as_Register(index));
2533 if( Assembler::is_simm16(disp) ) {
2534 __ ld(dst_reg, AT, disp);
2535 } else {
2536 __ move(T9, disp);
2537 __ daddu(AT, AT, T9);
2538 __ ld(dst_reg, AT, 0);
2539 }
2540 } else {
2541 if( Assembler::is_simm16(disp) ) {
2542 __ move(AT, as_Register(base));
2543 __ ld(dst_reg, AT, disp);
2544 } else {
2545 __ move(T9, disp);
2546 __ daddu(AT, as_Register(base), T9);
2547 __ ld(dst_reg, AT, 0);
2548 }
2549 }
2550 %}
2552 enc_class store_L_reg_enc (memory mem, mRegL src) %{
2553 MacroAssembler _masm(&cbuf);
2554 int base = $mem$$base;
2555 int index = $mem$$index;
2556 int scale = $mem$$scale;
2557 int disp = $mem$$disp;
2558 Register src_reg = as_Register($src$$reg);
2560 guarantee(scale == 0, "scale is not zero !");
2562 if( index != 0 ) {
2563 __ daddu(AT, as_Register(base), as_Register(index));
2564 if( Assembler::is_simm16(disp) ) {
2565 __ sd(src_reg, AT, disp);
2566 } else {
2567 __ move(T9, disp);
2568 __ daddu(AT, AT, T9);
2569 __ sd(src_reg, AT, 0);
2570 }
2571 } else {
2572 if( Assembler::is_simm16(disp) ) {
2573 __ move(AT, as_Register(base));
2574 __ sd(src_reg, AT, disp);
2575 } else {
2576 __ move(T9, disp);
2577 __ daddu(AT, as_Register(base), T9);
2578 __ sd(src_reg, AT, 0);
2579 }
2580 }
2581 %}
2583 enc_class store_L_immL0_enc (memory mem, immL0 src) %{
2584 MacroAssembler _masm(&cbuf);
2585 int base = $mem$$base;
2586 int index = $mem$$index;
2587 int scale = $mem$$scale;
2588 int disp = $mem$$disp;
2590 guarantee(scale == 0, "scale is not zero !");
2592 if( index != 0 ) {
2593 __ daddu(AT, as_Register(base), as_Register(index));
2594 if( Assembler::is_simm16(disp) ) {
2595 __ sd(R0, AT, disp);
2596 } else {
2597 __ move(T9, disp);
2598 __ addu(AT, AT, T9);
2599 __ sd(R0, AT, 0);
2600 }
2601 } else {
2602 if( Assembler::is_simm16(disp) ) {
2603 __ move(AT, as_Register(base));
2604 __ sd(R0, AT, disp);
2605 } else {
2606 __ move(T9, disp);
2607 __ addu(AT, as_Register(base), T9);
2608 __ sd(R0, AT, 0);
2609 }
2610 }
2611 %}
2613 enc_class store_L_immL_enc (memory mem, immL src) %{
2614 MacroAssembler _masm(&cbuf);
2615 int base = $mem$$base;
2616 int index = $mem$$index;
2617 int scale = $mem$$scale;
2618 int disp = $mem$$disp;
2619 long imm = $src$$constant;
2621 guarantee(scale == 0, "scale is not zero !");
2623 if( index != 0 ) {
2624 __ daddu(AT, as_Register(base), as_Register(index));
2625 if( Assembler::is_simm16(disp) ) {
2626 __ li(T9, imm);
2627 __ sd(T9, AT, disp);
2628 } else {
2629 __ move(T9, disp);
2630 __ addu(AT, AT, T9);
2631 __ li(T9, imm);
2632 __ sd(T9, AT, 0);
2633 }
2634 } else {
2635 if( Assembler::is_simm16(disp) ) {
2636 __ move(AT, as_Register(base));
2637 __ li(T9, imm);
2638 __ sd(T9, AT, disp);
2639 } else {
2640 __ move(T9, disp);
2641 __ addu(AT, as_Register(base), T9);
2642 __ li(T9, imm);
2643 __ sd(T9, AT, 0);
2644 }
2645 }
2646 %}
2648 enc_class load_F_enc (regF dst, memory mem) %{
2649 MacroAssembler _masm(&cbuf);
2650 int base = $mem$$base;
2651 int index = $mem$$index;
2652 int scale = $mem$$scale;
2653 int disp = $mem$$disp;
2654 FloatRegister dst = $dst$$FloatRegister;
2656 guarantee(scale == 0, "scale is not zero !");
2658 if( index != 0 ) {
2659 __ daddu(AT, as_Register(base), as_Register(index));
2660 if( Assembler::is_simm16(disp) ) {
2661 __ lwc1(dst, AT, disp);
2662 } else {
2663 __ move(T9, disp);
2664 __ daddu(AT, AT, T9);
2665 __ lwc1(dst, AT, 0);
2666 }
2667 } else {
2668 if( Assembler::is_simm16(disp) ) {
2669 __ lwc1(dst, as_Register(base), disp);
2670 } else {
2671 __ move(T9, disp);
2672 __ daddu(AT, as_Register(base), T9);
2673 __ lwc1(dst, AT, 0);
2674 }
2675 }
2676 %}
2678 enc_class store_F_reg_enc (memory mem, regF src) %{
2679 MacroAssembler _masm(&cbuf);
2680 int base = $mem$$base;
2681 int index = $mem$$index;
2682 int scale = $mem$$scale;
2683 int disp = $mem$$disp;
2684 FloatRegister src = $src$$FloatRegister;
2686 guarantee(scale == 0, "scale is not zero !");
2688 if( index != 0 ) {
2689 __ daddu(AT, as_Register(base), as_Register(index));
2690 if( Assembler::is_simm16(disp) ) {
2691 __ swc1(src, AT, disp);
2692 } else {
2693 __ move(T9, disp);
2694 __ daddu(AT, AT, T9);
2695 __ swc1(src, AT, 0);
2696 }
2697 } else {
2698 if( Assembler::is_simm16(disp) ) {
2699 __ swc1(src, as_Register(base), disp);
2700 } else {
2701 __ move(T9, disp);
2702 __ daddu(AT, as_Register(base), T9);
2703 __ swc1(src, AT, 0);
2704 }
2705 }
2706 %}
2708 enc_class load_D_enc (regD dst, memory mem) %{
2709 MacroAssembler _masm(&cbuf);
2710 int base = $mem$$base;
2711 int index = $mem$$index;
2712 int scale = $mem$$scale;
2713 int disp = $mem$$disp;
2714 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
2716 guarantee(scale == 0, "scale is not zero !");
2718 if( index != 0 ) {
2719 __ daddu(AT, as_Register(base), as_Register(index));
2720 if( Assembler::is_simm16(disp) ) {
2721 __ ldc1(dst_reg, AT, disp);
2722 } else {
2723 __ move(T9, disp);
2724 __ addu(AT, AT, T9);
2725 __ ldc1(dst_reg, AT, 0);
2726 }
2727 } else {
2728 if( Assembler::is_simm16(disp) ) {
2729 __ ldc1(dst_reg, as_Register(base), disp);
2730 } else {
2731 __ move(T9, disp);
2732 __ addu(AT, as_Register(base), T9);
2733 __ ldc1(dst_reg, AT, 0);
2734 }
2735 }
2736 %}
2738 enc_class store_D_reg_enc (memory mem, regD src) %{
2739 MacroAssembler _masm(&cbuf);
2740 int base = $mem$$base;
2741 int index = $mem$$index;
2742 int scale = $mem$$scale;
2743 int disp = $mem$$disp;
2744 FloatRegister src_reg = as_FloatRegister($src$$reg);
2746 guarantee(scale == 0, "scale is not zero !");
2748 if( index != 0 ) {
2749 __ daddu(AT, as_Register(base), as_Register(index));
2750 if( Assembler::is_simm16(disp) ) {
2751 __ sdc1(src_reg, AT, disp);
2752 } else {
2753 __ move(T9, disp);
2754 __ addu(AT, AT, T9);
2755 __ sdc1(src_reg, AT, 0);
2756 }
2757 } else {
2758 if( Assembler::is_simm16(disp) ) {
2759 __ sdc1(src_reg, as_Register(base), disp);
2760 } else {
2761 __ move(T9, disp);
2762 __ addu(AT, as_Register(base), T9);
2763 __ sdc1(src_reg, AT, 0);
2764 }
2765 }
2766 %}
2768 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
2769 MacroAssembler _masm(&cbuf);
2770 // This is the instruction starting address for relocation info.
2771 __ block_comment("Java_To_Runtime");
2772 cbuf.set_insts_mark();
2773 __ relocate(relocInfo::runtime_call_type);
2775 __ li48(T9, (long)$meth$$method);
2776 __ jalr(T9);
2777 __ nop();
2778 %}
2780 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2781 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2782 // who we intended to call.
2783 MacroAssembler _masm(&cbuf);
2784 cbuf.set_insts_mark();
2786 if ( !_method ) {
2787 __ relocate(relocInfo::runtime_call_type);
2788 //emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
2789 // runtime_call_Relocation::spec(), RELOC_IMM32 );
2790 } else if(_optimized_virtual) {
2791 __ relocate(relocInfo::opt_virtual_call_type);
2792 //emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
2793 // opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
2794 } else {
2795 __ relocate(relocInfo::static_call_type);
2796 //emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
2797 // static_call_Relocation::spec(), RELOC_IMM32 );
2798 }
2800 __ li(T9, $meth$$method);
2801 __ jalr(T9);
2802 __ nop();
2803 if( _method ) { // Emit stub for static call
2804 emit_java_to_interp(cbuf);
2805 }
2806 %}
2809 /*
2810 * [Ref: LIR_Assembler::ic_call() ]
2811 */
2812 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2813 MacroAssembler _masm(&cbuf);
2814 __ block_comment("Java_Dynamic_Call");
2815 __ ic_call((address)$meth$$method);
2816 %}
2818 enc_class call_epilog %{
2819 /*
2820 if( VerifyStackAtCalls ) {
2821 // Check that stack depth is unchanged: find majik cookie on stack
2822 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP,-3*VMRegImpl::slots_per_word));
2823 if(framesize >= 128) {
2824 emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood
2825 emit_d8(cbuf,0xBC);
2826 emit_d8(cbuf,0x24);
2827 emit_d32(cbuf,framesize); // Find majik cookie from ESP
2828 emit_d32(cbuf, 0xbadb100d);
2829 }
2830 else {
2831 emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood
2832 emit_d8(cbuf,0x7C);
2833 emit_d8(cbuf,0x24);
2834 emit_d8(cbuf,framesize); // Find majik cookie from ESP
2835 emit_d32(cbuf, 0xbadb100d);
2836 }
2837 // jmp EQ around INT3
2838 // QQQ TODO
2839 const int jump_around = 5; // size of call to breakpoint, 1 for CC
2840 emit_opcode(cbuf,0x74);
2841 emit_d8(cbuf, jump_around);
2842 // QQQ temporary
2843 emit_break(cbuf);
2844 // Die if stack mismatch
2845 // emit_opcode(cbuf,0xCC);
2846 }
2847 */
2848 %}
2852 enc_class Set_Flags_After_Fast_Lock_Unlock(FlagsReg cr) %{
2853 Register flags = $cr$$Register;
2854 Label L;
2856 MacroAssembler _masm(&cbuf);
2858 __ addu(flags, R0, R0);
2859 __ beq(AT, R0, L);
2860 __ delayed()->nop();
2861 __ move(flags, 0xFFFFFFFF);
2862 __ bind(L);
2863 %}
2865 enc_class enc_PartialSubtypeCheck(mRegP result, mRegP sub, mRegP super) %{
2866 Register result = $result$$Register;
2867 Register sub = $sub$$Register;
2868 Register super = $super$$Register;
2869 Register length = T8;
2870 Register tmp = T9;
2871 Label miss;
2873 /* 2012/9/28 Jin: result may be the same as sub
2874 * 47c B40: # B21 B41 <- B20 Freq: 0.155379
2875 * 47c partialSubtypeCheck result=S1, sub=S1, super=S3, length=S0
2876 * 4bc mov S2, NULL #@loadConP
2877 * 4c0 beq S1, S2, B21 #@branchConP P=0.999999 C=-1.000000
2878 */
2879 MacroAssembler _masm(&cbuf);
2880 Label done;
2881 __ check_klass_subtype_slow_path(sub, super, length, tmp,
2882 NULL, &miss,
2883 /*set_cond_codes:*/ true);
2884 /* 2013/7/22 Jin: Refer to X86_64's RDI */
2885 __ move(result, 0);
2886 __ b(done);
2887 __ nop();
2889 __ bind(miss);
2890 __ move(result, 1);
2891 __ bind(done);
2892 %}
2894 %}
2897 //---------MIPS FRAME--------------------------------------------------------------
2898 // Definition of frame structure and management information.
2899 //
2900 // S T A C K L A Y O U T Allocators stack-slot number
2901 // | (to get allocators register number
2902 // G Owned by | | v add SharedInfo::stack0)
2903 // r CALLER | |
2904 // o | +--------+ pad to even-align allocators stack-slot
2905 // w V | pad0 | numbers; owned by CALLER
2906 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2907 // h ^ | in | 5
2908 // | | args | 4 Holes in incoming args owned by SELF
2909 // | | old | | 3
2910 // | | SP-+--------+----> Matcher::_old_SP, even aligned
2911 // v | | ret | 3 return address
2912 // Owned by +--------+
2913 // Self | pad2 | 2 pad to align old SP
2914 // | +--------+ 1
2915 // | | locks | 0
2916 // | +--------+----> SharedInfo::stack0, even aligned
2917 // | | pad1 | 11 pad to align new SP
2918 // | +--------+
2919 // | | | 10
2920 // | | spills | 9 spills
2921 // V | | 8 (pad0 slot for callee)
2922 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2923 // ^ | out | 7
2924 // | | args | 6 Holes in outgoing args owned by CALLEE
2925 // Owned by new | |
2926 // Callee SP-+--------+----> Matcher::_new_SP, even aligned
2927 // | |
2928 //
2929 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2930 // known from SELF's arguments and the Java calling convention.
2931 // Region 6-7 is determined per call site.
2932 // Note 2: If the calling convention leaves holes in the incoming argument
2933 // area, those holes are owned by SELF. Holes in the outgoing area
2934 // are owned by the CALLEE. Holes should not be nessecary in the
2935 // incoming area, as the Java calling convention is completely under
2936 // the control of the AD file. Doubles can be sorted and packed to
2937 // avoid holes. Holes in the outgoing arguments may be nessecary for
2938 // varargs C calling conventions.
2939 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2940 // even aligned with pad0 as needed.
2941 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2942 // region 6-11 is even aligned; it may be padded out more so that
2943 // the region from SP to FP meets the minimum stack alignment.
2944 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2945 // alignment. Region 11, pad1, may be dynamically extended so that
2946 // SP meets the minimum alignment.
2949 frame %{
2951 stack_direction(TOWARDS_LOW);
2953 // These two registers define part of the calling convention
2954 // between compiled code and the interpreter.
2955 // SEE StartI2CNode::calling_convention & StartC2INode::calling_convention & StartOSRNode::calling_convention
2956 // for more information. by yjl 3/16/2006
2958 inline_cache_reg(T1); // Inline Cache Register
2959 interpreter_method_oop_reg(S3); // Method Oop Register when calling interpreter
2960 /*
2961 inline_cache_reg(T1); // Inline Cache Register or methodOop for I2C
2962 interpreter_arg_ptr_reg(A0); // Argument pointer for I2C adapters
2963 */
2965 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2966 cisc_spilling_operand_name(indOffset32);
2968 // Number of stack slots consumed by locking an object
2969 // generate Compile::sync_stack_slots
2970 #ifdef _LP64
2971 sync_stack_slots(2);
2972 #else
2973 sync_stack_slots(1);
2974 #endif
2976 frame_pointer(SP);
2978 // Interpreter stores its frame pointer in a register which is
2979 // stored to the stack by I2CAdaptors.
2980 // I2CAdaptors convert from interpreted java to compiled java.
2982 interpreter_frame_pointer(FP);
2984 // generate Matcher::stack_alignment
2985 stack_alignment(StackAlignmentInBytes); //wordSize = sizeof(char*);
2987 // Number of stack slots between incoming argument block and the start of
2988 // a new frame. The PROLOG must add this many slots to the stack. The
2989 // EPILOG must remove this many slots. Intel needs one slot for
2990 // return address.
2991 // generate Matcher::in_preserve_stack_slots
2992 //in_preserve_stack_slots(VerifyStackAtCalls + 2); //Now VerifyStackAtCalls is defined as false ! Leave one stack slot for ra and fp
2993 in_preserve_stack_slots(4); //Now VerifyStackAtCalls is defined as false ! Leave two stack slots for ra and fp
2995 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2996 // for calls to C. Supports the var-args backing area for register parms.
2997 varargs_C_out_slots_killed(0);
2999 // The after-PROLOG location of the return address. Location of
3000 // return address specifies a type (REG or STACK) and a number
3001 // representing the register number (i.e. - use a register name) or
3002 // stack slot.
3003 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3004 // Otherwise, it is above the locks and verification slot and alignment word
3005 //return_addr(STACK -1+ round_to(1+VerifyStackAtCalls+Compile::current()->sync()*Compile::current()->sync_stack_slots(),WordsPerLong));
3006 return_addr(REG RA);
3008 // Body of function which returns an integer array locating
3009 // arguments either in registers or in stack slots. Passed an array
3010 // of ideal registers called "sig" and a "length" count. Stack-slot
3011 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3012 // arguments for a CALLEE. Incoming stack arguments are
3013 // automatically biased by the preserve_stack_slots field above.
3016 // will generated to Matcher::calling_convention(OptoRegPair *sig, uint length, bool is_outgoing)
3017 // StartNode::calling_convention call this. by yjl 3/16/2006
3018 calling_convention %{
3019 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3020 %}
3025 // Body of function which returns an integer array locating
3026 // arguments either in registers or in stack slots. Passed an array
3027 // of ideal registers called "sig" and a "length" count. Stack-slot
3028 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3029 // arguments for a CALLEE. Incoming stack arguments are
3030 // automatically biased by the preserve_stack_slots field above.
3033 // SEE CallRuntimeNode::calling_convention for more information. by yjl 3/16/2006
3034 c_calling_convention %{
3035 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3036 %}
3039 // Location of C & interpreter return values
3040 // register(s) contain(s) return value for Op_StartI2C and Op_StartOSR.
3041 // SEE Matcher::match. by yjl 3/16/2006
3042 c_return_value %{
3043 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3044 /* -- , -- , Op_RegN, Op_RegI, Op_RegP, Op_RegF, Op_RegD, Op_RegL */
3045 static int lo[Op_RegL+1] = { 0, 0, V0_num, V0_num, V0_num, F0_num, F0_num, V0_num };
3046 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, V0_H_num, OptoReg::Bad, F0_H_num, V0_H_num };
3047 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3048 %}
3050 // Location of return values
3051 // register(s) contain(s) return value for Op_StartC2I and Op_Start.
3052 // SEE Matcher::match. by yjl 3/16/2006
3054 return_value %{
3055 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3056 /* -- , -- , Op_RegN, Op_RegI, Op_RegP, Op_RegF, Op_RegD, Op_RegL */
3057 static int lo[Op_RegL+1] = { 0, 0, V0_num, V0_num, V0_num, F0_num, F0_num, V0_num };
3058 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, V0_H_num, OptoReg::Bad, F0_H_num, V0_H_num};
3059 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3060 %}
3062 %}
3064 //----------ATTRIBUTES---------------------------------------------------------
3065 //----------Operand Attributes-------------------------------------------------
3066 op_attrib op_cost(0); // Required cost attribute
3068 //----------Instruction Attributes---------------------------------------------
3069 ins_attrib ins_cost(100); // Required cost attribute
3070 ins_attrib ins_size(32); // Required size attribute (in bits)
3071 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3072 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3073 // non-matching short branch variant of some
3074 // long branch?
3075 ins_attrib ins_alignment(4); // Required alignment attribute (must be a power of 2)
3076 // specifies the alignment that some part of the instruction (not
3077 // necessarily the start) requires. If > 1, a compute_padding()
3078 // function must be provided for the instruction
3080 //----------OPERANDS-----------------------------------------------------------
3081 // Operand definitions must precede instruction definitions for correct parsing
3082 // in the ADLC because operands constitute user defined types which are used in
3083 // instruction definitions.
3086 // Flags register, used as output of compare instructions
3087 operand FlagsReg() %{
3088 constraint(ALLOC_IN_RC(mips_flags));
3089 match(RegFlags);
3091 format %{ "EFLAGS" %}
3092 interface(REG_INTER);
3093 %}
3095 //----------Simple Operands----------------------------------------------------
3096 //TODO: Should we need to define some more special immediate number ?
3097 // Immediate Operands
3098 // Integer Immediate
3099 operand immI() %{
3100 match(ConI);
3101 //TODO: should not match immI8 here LEE
3102 match(immI8);
3104 op_cost(20);
3105 format %{ %}
3106 interface(CONST_INTER);
3107 %}
3109 // Long Immediate 8-bit
3110 operand immL8()
3111 %{
3112 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3113 match(ConL);
3115 op_cost(5);
3116 format %{ %}
3117 interface(CONST_INTER);
3118 %}
3120 // Constant for test vs zero
3121 operand immI0() %{
3122 predicate(n->get_int() == 0);
3123 match(ConI);
3125 op_cost(0);
3126 format %{ %}
3127 interface(CONST_INTER);
3128 %}
3130 // Constant for increment
3131 operand immI1() %{
3132 predicate(n->get_int() == 1);
3133 match(ConI);
3135 op_cost(0);
3136 format %{ %}
3137 interface(CONST_INTER);
3138 %}
3140 // Constant for decrement
3141 operand immI_M1() %{
3142 predicate(n->get_int() == -1);
3143 match(ConI);
3145 op_cost(0);
3146 format %{ %}
3147 interface(CONST_INTER);
3148 %}
3150 // Valid scale values for addressing modes
3151 operand immI2() %{
3152 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3153 match(ConI);
3155 format %{ %}
3156 interface(CONST_INTER);
3157 %}
3159 operand immI8() %{
3160 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3161 match(ConI);
3163 op_cost(5);
3164 format %{ %}
3165 interface(CONST_INTER);
3166 %}
3168 operand immI16() %{
3169 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3170 match(ConI);
3172 op_cost(10);
3173 format %{ %}
3174 interface(CONST_INTER);
3175 %}
3177 // Constant for long shifts
3178 operand immI_32() %{
3179 predicate( n->get_int() == 32 );
3180 match(ConI);
3182 op_cost(0);
3183 format %{ %}
3184 interface(CONST_INTER);
3185 %}
3187 operand immI_1_31() %{
3188 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3189 match(ConI);
3191 op_cost(0);
3192 format %{ %}
3193 interface(CONST_INTER);
3194 %}
3196 operand immI_32_63() %{
3197 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3198 match(ConI);
3199 op_cost(0);
3201 format %{ %}
3202 interface(CONST_INTER);
3203 %}
3205 operand immI16_sub() %{
3206 predicate((-32767 <= n->get_int()) && (n->get_int() <= 32767));
3207 match(ConI);
3209 op_cost(10);
3210 format %{ %}
3211 interface(CONST_INTER);
3212 %}
3214 operand immI_0_65535() %{
3215 predicate( n->get_int() >= 0 && n->get_int() <= 65535 );
3216 match(ConI);
3217 op_cost(0);
3219 format %{ %}
3220 interface(CONST_INTER);
3221 %}
3223 operand immI_1() %{
3224 predicate( n->get_int() == 1 );
3225 match(ConI);
3227 op_cost(0);
3228 format %{ %}
3229 interface(CONST_INTER);
3230 %}
3232 operand immI_2() %{
3233 predicate( n->get_int() == 2 );
3234 match(ConI);
3236 op_cost(0);
3237 format %{ %}
3238 interface(CONST_INTER);
3239 %}
3241 operand immI_3() %{
3242 predicate( n->get_int() == 3 );
3243 match(ConI);
3245 op_cost(0);
3246 format %{ %}
3247 interface(CONST_INTER);
3248 %}
3250 // Immediates for special shifts (sign extend)
3252 // Constants for increment
3253 operand immI_16() %{
3254 predicate( n->get_int() == 16 );
3255 match(ConI);
3257 format %{ %}
3258 interface(CONST_INTER);
3259 %}
3261 operand immI_24() %{
3262 predicate( n->get_int() == 24 );
3263 match(ConI);
3265 format %{ %}
3266 interface(CONST_INTER);
3267 %}
3269 // Constant for byte-wide masking
3270 operand immI_255() %{
3271 predicate( n->get_int() == 255 );
3272 match(ConI);
3274 format %{ %}
3275 interface(CONST_INTER);
3276 %}
3278 // Pointer Immediate
3279 operand immP() %{
3280 match(ConP);
3282 op_cost(10);
3283 format %{ %}
3284 interface(CONST_INTER);
3285 %}
3287 operand immP31()
3288 %{
3289 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3290 && (n->get_ptr() >> 31) == 0);
3291 match(ConP);
3293 op_cost(5);
3294 format %{ %}
3295 interface(CONST_INTER);
3296 %}
3298 // NULL Pointer Immediate
3299 operand immP0() %{
3300 predicate( n->get_ptr() == 0 );
3301 match(ConP);
3302 op_cost(0);
3304 format %{ %}
3305 interface(CONST_INTER);
3306 %}
3308 // Pointer Immediate
3309 operand immN() %{
3310 match(ConN);
3312 op_cost(10);
3313 format %{ %}
3314 interface(CONST_INTER);
3315 %}
3317 operand immNKlass() %{
3318 match(ConNKlass);
3320 op_cost(10);
3321 format %{ %}
3322 interface(CONST_INTER);
3323 %}
3325 // NULL Pointer Immediate
3326 operand immN0() %{
3327 predicate(n->get_narrowcon() == 0);
3328 match(ConN);
3330 op_cost(5);
3331 format %{ %}
3332 interface(CONST_INTER);
3333 %}
3335 // Long Immediate
3336 operand immL() %{
3337 match(ConL);
3339 op_cost(20);
3340 format %{ %}
3341 interface(CONST_INTER);
3342 %}
3344 // Long Immediate zero
3345 operand immL0() %{
3346 predicate( n->get_long() == 0L );
3347 match(ConL);
3348 op_cost(0);
3350 format %{ %}
3351 interface(CONST_INTER);
3352 %}
3354 // Long Immediate zero
3355 operand immL_M1() %{
3356 predicate( n->get_long() == -1L );
3357 match(ConL);
3358 op_cost(0);
3360 format %{ %}
3361 interface(CONST_INTER);
3362 %}
3364 // Long immediate from 0 to 127.
3365 // Used for a shorter form of long mul by 10.
3366 operand immL_127() %{
3367 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
3368 match(ConL);
3369 op_cost(0);
3371 format %{ %}
3372 interface(CONST_INTER);
3373 %}
3376 // Long Immediate: low 32-bit mask
3377 operand immL_32bits() %{
3378 predicate(n->get_long() == 0xFFFFFFFFL);
3379 match(ConL);
3380 op_cost(20);
3382 format %{ %}
3383 interface(CONST_INTER);
3384 %}
3386 // Long Immediate 32-bit signed
3387 operand immL32()
3388 %{
3389 predicate(n->get_long() == (int) (n->get_long()));
3390 match(ConL);
3392 op_cost(15);
3393 format %{ %}
3394 interface(CONST_INTER);
3395 %}
3398 //single-precision floating-point zero
3399 operand immF0() %{
3400 predicate(jint_cast(n->getf()) == 0);
3401 match(ConF);
3403 op_cost(5);
3404 format %{ %}
3405 interface(CONST_INTER);
3406 %}
3408 //single-precision floating-point immediate
3409 operand immF() %{
3410 match(ConF);
3412 op_cost(20);
3413 format %{ %}
3414 interface(CONST_INTER);
3415 %}
3417 //double-precision floating-point zero
3418 operand immD0() %{
3419 predicate(jlong_cast(n->getd()) == 0);
3420 match(ConD);
3422 op_cost(5);
3423 format %{ %}
3424 interface(CONST_INTER);
3425 %}
3427 //double-precision floating-point immediate
3428 operand immD() %{
3429 match(ConD);
3431 op_cost(20);
3432 format %{ %}
3433 interface(CONST_INTER);
3434 %}
3436 // Register Operands
3437 // Integer Register
3438 operand mRegI() %{
3439 constraint(ALLOC_IN_RC(int_reg));
3440 match(RegI);
3441 match(s_RegI);
3442 match(t_RegI);
3444 format %{ %}
3445 interface(REG_INTER);
3446 %}
3449 // Subset of Integer Registers
3450 operand s_RegI(mRegI reg) %{
3451 constraint(ALLOC_IN_RC(s_reg));
3452 match(reg);
3453 match(mS0RegI);
3454 match(mS1RegI);
3455 match(mS2RegI);
3456 match(mS3RegI);
3457 match(mS4RegI);
3459 format %{ %}
3460 interface(REG_INTER);
3461 %}
3463 operand mS0RegI(s_RegI reg) %{
3464 constraint(ALLOC_IN_RC(s0_reg));
3465 match(reg);
3466 match(mRegI);
3468 format %{ "S0" %}
3469 interface(REG_INTER);
3470 %}
3472 operand mS1RegI(s_RegI reg) %{
3473 constraint(ALLOC_IN_RC(s1_reg));
3474 match(reg);
3475 match(mRegI);
3477 format %{ "S1" %}
3478 interface(REG_INTER);
3479 %}
3481 operand mS2RegI(s_RegI reg) %{
3482 constraint(ALLOC_IN_RC(s2_reg));
3483 match(reg);
3484 match(mRegI);
3486 format %{ "S0" %}
3487 interface(REG_INTER);
3488 %}
3490 operand mS3RegI(s_RegI reg) %{
3491 constraint(ALLOC_IN_RC(s3_reg));
3492 match(reg);
3493 match(mRegI);
3495 format %{ "S3" %}
3496 interface(REG_INTER);
3497 %}
3499 operand mS4RegI(s_RegI reg) %{
3500 constraint(ALLOC_IN_RC(s4_reg));
3501 match(reg);
3502 match(mRegI);
3504 format %{ "S4" %}
3505 interface(REG_INTER);
3506 %}
3508 // Subset of Integer Registers
3509 operand t_RegI(mRegI reg) %{
3510 constraint(ALLOC_IN_RC(t_reg));
3511 match(reg);
3512 match(mT0RegI);
3513 match(mT1RegI);
3514 match(mT2RegI);
3515 match(mT3RegI);
3517 format %{ %}
3518 interface(REG_INTER);
3519 %}
3521 operand mT0RegI(t_RegI reg) %{
3522 constraint(ALLOC_IN_RC(t0_reg));
3523 match(reg);
3524 match(mRegI);
3526 format %{ "T0" %}
3527 interface(REG_INTER);
3528 %}
3530 operand mT1RegI(t_RegI reg) %{
3531 constraint(ALLOC_IN_RC(t1_reg));
3532 match(reg);
3533 match(mRegI);
3535 format %{ "T1" %}
3536 interface(REG_INTER);
3537 %}
3539 operand mT2RegI(t_RegI reg) %{
3540 constraint(ALLOC_IN_RC(t2_reg));
3541 match(reg);
3542 match(mRegI);
3544 format %{ "T2" %}
3545 interface(REG_INTER);
3546 %}
3548 operand mT3RegI(t_RegI reg) %{
3549 constraint(ALLOC_IN_RC(t3_reg));
3550 match(reg);
3551 match(mRegI);
3553 format %{ "T3" %}
3554 interface(REG_INTER);
3555 %}
3557 operand mRegN() %{
3558 constraint(ALLOC_IN_RC(int_reg));
3559 match(RegN);
3561 match(t0_RegN);
3562 match(t1_RegN);
3563 match(t2_RegN);
3564 match(t3_RegN);
3566 match(a3_RegN);
3567 format %{ %}
3568 interface(REG_INTER);
3569 %}
3571 operand t0_RegN() %{
3572 constraint(ALLOC_IN_RC(t0_reg));
3573 match(RegN);
3574 match(mRegN);
3576 format %{ %}
3577 interface(REG_INTER);
3578 %}
3580 operand t1_RegN() %{
3581 constraint(ALLOC_IN_RC(t1_reg));
3582 match(RegN);
3583 match(mRegN);
3585 format %{ %}
3586 interface(REG_INTER);
3587 %}
3589 operand t2_RegN() %{
3590 constraint(ALLOC_IN_RC(t2_reg));
3591 match(RegN);
3592 match(mRegN);
3594 format %{ %}
3595 interface(REG_INTER);
3596 %}
3598 operand t3_RegN() %{
3599 constraint(ALLOC_IN_RC(t3_reg));
3600 match(RegN);
3601 match(mRegN);
3603 format %{ %}
3604 interface(REG_INTER);
3605 %}
3607 operand a3_RegN() %{
3608 constraint(ALLOC_IN_RC(a3_reg));
3609 match(RegN);
3610 match(mRegN);
3612 format %{ %}
3613 interface(REG_INTER);
3614 %}
3615 // Pointer Register
3616 operand mRegP() %{
3617 constraint(ALLOC_IN_RC(p_reg));
3618 match(RegP);
3620 match(t0_RegP);
3621 match(t1_RegP);
3622 match(t2_RegP);
3623 match(t3_RegP);
3624 match(a3_RegP);
3625 match(a4_RegP);
3626 match(a5_RegP);
3627 match(a6_RegP);
3628 match(a7_RegP);
3630 match(a0_RegP);
3632 match(s0_RegP);
3633 match(s1_RegP);
3634 match(s2_RegP);
3635 match(s3_RegP);
3636 match(s4_RegP);
3637 //match(s5_RegP);
3638 // match(s7_RegP);
3640 //match(mSPRegP);
3641 //match(mFPRegP);
3643 format %{ %}
3644 interface(REG_INTER);
3645 %}
3647 operand a0_RegP()
3648 %{
3649 constraint(ALLOC_IN_RC(a0_long_reg));
3650 match(RegP);
3651 match(mRegP);
3653 format %{ %}
3654 interface(REG_INTER);
3655 %}
3657 operand s0_RegP()
3658 %{
3659 constraint(ALLOC_IN_RC(s0_long_reg));
3660 match(RegP);
3661 match(mRegP);
3663 format %{ %}
3664 interface(REG_INTER);
3665 %}
3667 operand s1_RegP()
3668 %{
3669 constraint(ALLOC_IN_RC(s1_long_reg));
3670 match(RegP);
3671 match(mRegP);
3673 format %{ %}
3674 interface(REG_INTER);
3675 %}
3677 operand s2_RegP()
3678 %{
3679 constraint(ALLOC_IN_RC(s2_long_reg));
3680 match(RegP);
3681 match(mRegP);
3683 format %{ %}
3684 interface(REG_INTER);
3685 %}
3687 operand s3_RegP()
3688 %{
3689 constraint(ALLOC_IN_RC(s3_long_reg));
3690 match(RegP);
3691 match(mRegP);
3693 format %{ %}
3694 interface(REG_INTER);
3695 %}
3697 operand s4_RegP()
3698 %{
3699 constraint(ALLOC_IN_RC(s4_long_reg));
3700 match(RegP);
3701 match(mRegP);
3703 format %{ %}
3704 interface(REG_INTER);
3705 %}
3707 operand t0_RegP()
3708 %{
3709 constraint(ALLOC_IN_RC(t0_long_reg));
3710 match(RegP);
3711 match(mRegP);
3713 format %{ %}
3714 interface(REG_INTER);
3715 %}
3717 operand t1_RegP()
3718 %{
3719 constraint(ALLOC_IN_RC(t1_long_reg));
3720 match(RegP);
3721 match(mRegP);
3723 format %{ %}
3724 interface(REG_INTER);
3725 %}
3727 operand t2_RegP()
3728 %{
3729 constraint(ALLOC_IN_RC(t2_long_reg));
3730 match(RegP);
3731 match(mRegP);
3733 format %{ %}
3734 interface(REG_INTER);
3735 %}
3737 operand t3_RegP()
3738 %{
3739 constraint(ALLOC_IN_RC(t3_long_reg));
3740 match(RegP);
3741 match(mRegP);
3743 format %{ %}
3744 interface(REG_INTER);
3745 %}
3747 operand a3_RegP()
3748 %{
3749 constraint(ALLOC_IN_RC(a3_long_reg));
3750 match(RegP);
3751 match(mRegP);
3753 format %{ %}
3754 interface(REG_INTER);
3755 %}
3757 operand a4_RegP()
3758 %{
3759 constraint(ALLOC_IN_RC(a4_long_reg));
3760 match(RegP);
3761 match(mRegP);
3763 format %{ %}
3764 interface(REG_INTER);
3765 %}
3768 operand a5_RegP()
3769 %{
3770 constraint(ALLOC_IN_RC(a5_long_reg));
3771 match(RegP);
3772 match(mRegP);
3774 format %{ %}
3775 interface(REG_INTER);
3776 %}
3778 operand a6_RegP()
3779 %{
3780 constraint(ALLOC_IN_RC(a6_long_reg));
3781 match(RegP);
3782 match(mRegP);
3784 format %{ %}
3785 interface(REG_INTER);
3786 %}
3788 operand a7_RegP()
3789 %{
3790 constraint(ALLOC_IN_RC(a7_long_reg));
3791 match(RegP);
3792 match(mRegP);
3794 format %{ %}
3795 interface(REG_INTER);
3796 %}
3798 /*
3799 operand mSPRegP(mRegP reg) %{
3800 constraint(ALLOC_IN_RC(sp_reg));
3801 match(reg);
3803 format %{ "SP" %}
3804 interface(REG_INTER);
3805 %}
3807 operand mFPRegP(mRegP reg) %{
3808 constraint(ALLOC_IN_RC(fp_reg));
3809 match(reg);
3811 format %{ "FP" %}
3812 interface(REG_INTER);
3813 %}
3814 */
3816 operand mRegL() %{
3817 constraint(ALLOC_IN_RC(long_reg));
3818 match(RegL);
3819 match(v0RegL);
3820 match(v1RegL);
3821 match(a0RegL);
3822 match(a1RegL);
3823 match(a2RegL);
3824 match(a3RegL);
3825 match(t0RegL);
3826 match(t1RegL);
3827 match(t2RegL);
3828 match(t3RegL);
3829 match(a4RegL);
3830 match(a5RegL);
3831 match(a6RegL);
3832 match(a7RegL);
3834 format %{ %}
3835 interface(REG_INTER);
3836 %}
3838 operand v0RegL() %{
3839 constraint(ALLOC_IN_RC(v0_long_reg));
3840 match(RegL);
3841 match(mRegL);
3843 format %{ %}
3844 interface(REG_INTER);
3845 %}
3847 operand v1RegL() %{
3848 constraint(ALLOC_IN_RC(v1_long_reg));
3849 match(RegL);
3850 match(mRegL);
3852 format %{ %}
3853 interface(REG_INTER);
3854 %}
3856 operand a0RegL() %{
3857 constraint(ALLOC_IN_RC(a0_long_reg));
3858 match(RegL);
3859 match(mRegL);
3861 format %{ "A0" %}
3862 interface(REG_INTER);
3863 %}
3865 operand a1RegL() %{
3866 constraint(ALLOC_IN_RC(a1_long_reg));
3867 match(RegL);
3868 match(mRegL);
3870 format %{ %}
3871 interface(REG_INTER);
3872 %}
3874 operand a2RegL() %{
3875 constraint(ALLOC_IN_RC(a2_long_reg));
3876 match(RegL);
3877 match(mRegL);
3879 format %{ %}
3880 interface(REG_INTER);
3881 %}
3883 operand a3RegL() %{
3884 constraint(ALLOC_IN_RC(a3_long_reg));
3885 match(RegL);
3886 match(mRegL);
3888 format %{ %}
3889 interface(REG_INTER);
3890 %}
3892 operand t0RegL() %{
3893 constraint(ALLOC_IN_RC(t0_long_reg));
3894 match(RegL);
3895 match(mRegL);
3897 format %{ %}
3898 interface(REG_INTER);
3899 %}
3901 operand t1RegL() %{
3902 constraint(ALLOC_IN_RC(t1_long_reg));
3903 match(RegL);
3904 match(mRegL);
3906 format %{ %}
3907 interface(REG_INTER);
3908 %}
3910 operand t2RegL() %{
3911 constraint(ALLOC_IN_RC(t2_long_reg));
3912 match(RegL);
3913 match(mRegL);
3915 format %{ %}
3916 interface(REG_INTER);
3917 %}
3919 operand t3RegL() %{
3920 constraint(ALLOC_IN_RC(t3_long_reg));
3921 match(RegL);
3922 match(mRegL);
3924 format %{ %}
3925 interface(REG_INTER);
3926 %}
3928 operand a4RegL() %{
3929 constraint(ALLOC_IN_RC(a4_long_reg));
3930 match(RegL);
3931 match(mRegL);
3933 format %{ %}
3934 interface(REG_INTER);
3935 %}
3937 operand a5RegL() %{
3938 constraint(ALLOC_IN_RC(a5_long_reg));
3939 match(RegL);
3940 match(mRegL);
3942 format %{ %}
3943 interface(REG_INTER);
3944 %}
3946 operand a6RegL() %{
3947 constraint(ALLOC_IN_RC(a6_long_reg));
3948 match(RegL);
3949 match(mRegL);
3951 format %{ %}
3952 interface(REG_INTER);
3953 %}
3955 operand a7RegL() %{
3956 constraint(ALLOC_IN_RC(a7_long_reg));
3957 match(RegL);
3958 match(mRegL);
3960 format %{ %}
3961 interface(REG_INTER);
3962 %}
3964 // Floating register operands
3965 operand regF() %{
3966 constraint(ALLOC_IN_RC(flt_reg));
3967 match(RegF);
3969 format %{ %}
3970 interface(REG_INTER);
3971 %}
3973 //Double Precision Floating register operands
3974 operand regD() %{
3975 constraint(ALLOC_IN_RC(dbl_reg));
3976 match(RegD);
3978 format %{ %}
3979 interface(REG_INTER);
3980 %}
3982 //----------Memory Operands----------------------------------------------------
3983 // Indirect Memory Operand
3984 operand indirect(mRegP reg) %{
3985 constraint(ALLOC_IN_RC(p_reg));
3986 op_cost(10);
3987 match(reg);
3989 format %{ "[$reg] @ indirect" %}
3990 interface(MEMORY_INTER) %{
3991 base($reg);
3992 index(0x0); /* NO_INDEX */
3993 scale(0x0);
3994 disp(0x0);
3995 %}
3996 %}
3998 // Indirect Memory Plus Short Offset Operand
3999 operand indOffset8(mRegP reg, immL8 off)
4000 %{
4001 constraint(ALLOC_IN_RC(p_reg));
4002 op_cost(10);
4003 match(AddP reg off);
4005 format %{ "[$reg + $off (8-bit)] @ indOffset8" %}
4006 interface(MEMORY_INTER) %{
4007 base($reg);
4008 index(0x0); /* NO_INDEX */
4009 scale(0x0);
4010 disp($off);
4011 %}
4012 %}
4014 //FIXME: I think it's better to limit the immI to be 16-bit at most!
4015 // Indirect Memory Plus Long Offset Operand
4016 operand indOffset32(mRegP reg, immL32 off) %{
4017 constraint(ALLOC_IN_RC(p_reg));
4018 op_cost(20);
4019 match(AddP reg off);
4021 format %{ "[$reg + $off (32-bit)] @ indOffset32" %}
4022 interface(MEMORY_INTER) %{
4023 base($reg);
4024 index(0x0); /* NO_INDEX */
4025 scale(0x0);
4026 disp($off);
4027 %}
4028 %}
4030 /*
4031 2012/8/15 Jin: indOffset32X will cause a very large offseet(more than 16-bit).
4033 MIPS:
4034 lui t5, 0x3218 ; {oop('java/lang/System')}
4035 addiu t5, t5, 0x1ac8
4036 lw t5, 0x15c(t5)
4038 X86:
4039 move 0x15c, ebx ; {oop('java/lang/System')}
4040 move 0x3c247320(ebx), ebx
4041 */
4042 /*
4043 // Indirect Memory Plus Long Offset Operand
4044 operand indOffset32X(mRegI reg, immP off) %{
4045 match(AddP off reg);
4047 format %{ "indOffset32X [$reg + $off]" %}
4048 interface(MEMORY_INTER) %{
4049 base($reg);
4050 // index(0x4);
4051 index(0x0);
4052 scale(0x0);
4053 disp($off);
4054 %}
4055 %}
4056 */
4058 // Indirect Memory Plus Index Register
4059 operand indIndex(mRegP addr, mRegL index) %{
4060 constraint(ALLOC_IN_RC(p_reg));
4061 match(AddP addr index);
4063 op_cost(10);
4064 format %{"[$addr + $index] @ indIndex" %}
4065 interface(MEMORY_INTER) %{
4066 base($addr);
4067 index($index);
4068 scale(0x0);
4069 disp(0x0);
4070 %}
4071 %}
4073 operand indirectNarrowKlass(mRegN reg)
4074 %{
4075 predicate(Universe::narrow_klass_shift() == 0);
4076 constraint(ALLOC_IN_RC(p_reg));
4077 op_cost(10);
4078 match(DecodeNKlass reg);
4080 format %{ "[$reg] @ indirectNarrowKlass" %}
4081 interface(MEMORY_INTER) %{
4082 base($reg);
4083 index(0x4);
4084 scale(0x0);
4085 disp(0x0);
4086 %}
4087 %}
4089 operand indOffset8NarrowKlass(mRegN reg, immL8 off)
4090 %{
4091 predicate(Universe::narrow_klass_shift() == 0);
4092 constraint(ALLOC_IN_RC(p_reg));
4093 op_cost(10);
4094 match(AddP (DecodeNKlass reg) off);
4096 format %{ "[$reg + $off (8-bit)] @ indOffset8NarrowKlass" %}
4097 interface(MEMORY_INTER) %{
4098 base($reg);
4099 index(0x4);
4100 scale(0x0);
4101 disp($off);
4102 %}
4103 %}
4105 operand indOffset32NarrowKlass(mRegN reg, immL32 off)
4106 %{
4107 predicate(Universe::narrow_klass_shift() == 0);
4108 constraint(ALLOC_IN_RC(p_reg));
4109 op_cost(10);
4110 match(AddP (DecodeNKlass reg) off);
4112 format %{ "[$reg + $off (32-bit)] @ indOffset32NarrowKlass" %}
4113 interface(MEMORY_INTER) %{
4114 base($reg);
4115 index(0x4);
4116 scale(0x0);
4117 disp($off);
4118 %}
4119 %}
4121 operand indIndexOffsetNarrowKlass(mRegN reg, mRegL lreg, immL32 off)
4122 %{
4123 predicate(Universe::narrow_klass_shift() == 0);
4124 constraint(ALLOC_IN_RC(p_reg));
4125 match(AddP (AddP (DecodeNKlass reg) lreg) off);
4127 op_cost(10);
4128 format %{"[$reg + $off + $lreg] @ indIndexOffsetNarrowKlass" %}
4129 interface(MEMORY_INTER) %{
4130 base($reg);
4131 index($lreg);
4132 scale(0x0);
4133 disp($off);
4134 %}
4135 %}
4137 operand indIndexNarrowKlass(mRegN reg, mRegL lreg)
4138 %{
4139 predicate(Universe::narrow_klass_shift() == 0);
4140 constraint(ALLOC_IN_RC(p_reg));
4141 match(AddP (DecodeNKlass reg) lreg);
4143 op_cost(10);
4144 format %{"[$reg + $lreg] @ indIndexNarrowKlass" %}
4145 interface(MEMORY_INTER) %{
4146 base($reg);
4147 index($lreg);
4148 scale(0x0);
4149 disp(0x0);
4150 %}
4151 %}
4153 // Indirect Memory Operand
4154 operand indirectNarrow(mRegN reg)
4155 %{
4156 predicate(Universe::narrow_oop_shift() == 0);
4157 constraint(ALLOC_IN_RC(p_reg));
4158 op_cost(10);
4159 match(DecodeN reg);
4161 format %{ "[$reg] @ indirectNarrow" %}
4162 interface(MEMORY_INTER) %{
4163 base($reg);
4164 index(0x0);
4165 scale(0x0);
4166 disp(0x0);
4167 %}
4168 %}
4170 //----------Load Long Memory Operands------------------------------------------
4171 // The load-long idiom will use it's address expression again after loading
4172 // the first word of the long. If the load-long destination overlaps with
4173 // registers used in the addressing expression, the 2nd half will be loaded
4174 // from a clobbered address. Fix this by requiring that load-long use
4175 // address registers that do not overlap with the load-long target.
4177 // load-long support
4178 operand load_long_RegP() %{
4179 constraint(ALLOC_IN_RC(p_reg));
4180 match(RegP);
4181 match(mRegP);
4182 op_cost(100);
4183 format %{ %}
4184 interface(REG_INTER);
4185 %}
4187 // Indirect Memory Operand Long
4188 operand load_long_indirect(load_long_RegP reg) %{
4189 constraint(ALLOC_IN_RC(p_reg));
4190 match(reg);
4192 format %{ "[$reg]" %}
4193 interface(MEMORY_INTER) %{
4194 base($reg);
4195 index(0x0); /* FIXME: In X86, index==0 means none indirect register. While In MIPS, we indicates 0 for the same meaning */
4196 scale(0x0);
4197 disp(0x0);
4198 %}
4199 %}
4201 // Indirect Memory Plus Long Offset Operand
4202 operand load_long_indOffset32(load_long_RegP reg, immL32 off) %{
4203 match(AddP reg off);
4205 format %{ "[$reg + $off]" %}
4206 interface(MEMORY_INTER) %{
4207 base($reg);
4208 index(0x0);
4209 scale(0x0);
4210 disp($off);
4211 %}
4212 %}
4214 //----------Conditional Branch Operands----------------------------------------
4215 // Comparison Op - This is the operation of the comparison, and is limited to
4216 // the following set of codes:
4217 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4218 //
4219 // Other attributes of the comparison, such as unsignedness, are specified
4220 // by the comparison instruction that sets a condition code flags register.
4221 // That result is represented by a flags operand whose subtype is appropriate
4222 // to the unsignedness (etc.) of the comparison.
4223 //
4224 // Later, the instruction which matches both the Comparison Op (a Bool) and
4225 // the flags (produced by the Cmp) specifies the coding of the comparison op
4226 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4228 // Comparision Code
4229 operand cmpOp() %{
4230 match(Bool);
4232 format %{ "" %}
4233 interface(COND_INTER) %{
4234 equal(0x01);
4235 not_equal(0x02);
4236 greater(0x03);
4237 greater_equal(0x04);
4238 less(0x05);
4239 less_equal(0x06);
4240 overflow(0x7);
4241 no_overflow(0x8);
4242 %}
4243 %}
4246 // Comparision Code
4247 // Comparison Code, unsigned compare. Used by FP also, with
4248 // C2 (unordered) turned into GT or LT already. The other bits
4249 // C0 and C3 are turned into Carry & Zero flags.
4250 operand cmpOpU() %{
4251 match(Bool);
4253 format %{ "" %}
4254 interface(COND_INTER) %{
4255 equal(0x01);
4256 not_equal(0x02);
4257 greater(0x03);
4258 greater_equal(0x04);
4259 less(0x05);
4260 less_equal(0x06);
4261 overflow(0x7);
4262 no_overflow(0x8);
4263 %}
4264 %}
4266 /*
4267 // Comparison Code, unsigned compare. Used by FP also, with
4268 // C2 (unordered) turned into GT or LT already. The other bits
4269 // C0 and C3 are turned into Carry & Zero flags.
4270 operand cmpOpU() %{
4271 match(Bool);
4273 format %{ "" %}
4274 interface(COND_INTER) %{
4275 equal(0x4);
4276 not_equal(0x5);
4277 less(0x2);
4278 greater_equal(0x3);
4279 less_equal(0x6);
4280 greater(0x7);
4281 %}
4282 %}
4283 */
4284 /*
4285 // Comparison Code for FP conditional move
4286 operand cmpOp_fcmov() %{
4287 match(Bool);
4289 format %{ "" %}
4290 interface(COND_INTER) %{
4291 equal (0x01);
4292 not_equal (0x02);
4293 greater (0x03);
4294 greater_equal(0x04);
4295 less (0x05);
4296 less_equal (0x06);
4297 %}
4298 %}
4300 // Comparision Code used in long compares
4301 operand cmpOp_commute() %{
4302 match(Bool);
4304 format %{ "" %}
4305 interface(COND_INTER) %{
4306 equal(0x4);
4307 not_equal(0x5);
4308 less(0xF);
4309 greater_equal(0xE);
4310 less_equal(0xD);
4311 greater(0xC);
4312 %}
4313 %}
4314 */
4316 /*
4317 //----------Special Memory Operands--------------------------------------------
4318 // Stack Slot Operand - This operand is used for loading and storing temporary
4319 // values on the stack where a match requires a value to
4320 // flow through memory.
4321 operand stackSlotP(sRegP reg) %{
4322 constraint(ALLOC_IN_RC(stack_slots));
4323 // No match rule because this operand is only generated in matching
4324 op_cost(50);
4325 format %{ "[$reg]" %}
4326 interface(MEMORY_INTER) %{
4327 base(0x1d); // SP
4328 index(0x0); // No Index
4329 scale(0x0); // No Scale
4330 disp($reg); // Stack Offset
4331 %}
4332 %}
4334 operand stackSlotI(sRegI reg) %{
4335 constraint(ALLOC_IN_RC(stack_slots));
4336 // No match rule because this operand is only generated in matching
4337 op_cost(50);
4338 format %{ "[$reg]" %}
4339 interface(MEMORY_INTER) %{
4340 base(0x1d); // SP
4341 index(0x0); // No Index
4342 scale(0x0); // No Scale
4343 disp($reg); // Stack Offset
4344 %}
4345 %}
4347 operand stackSlotF(sRegF reg) %{
4348 constraint(ALLOC_IN_RC(stack_slots));
4349 // No match rule because this operand is only generated in matching
4350 op_cost(50);
4351 format %{ "[$reg]" %}
4352 interface(MEMORY_INTER) %{
4353 base(0x1d); // SP
4354 index(0x0); // No Index
4355 scale(0x0); // No Scale
4356 disp($reg); // Stack Offset
4357 %}
4358 %}
4360 operand stackSlotD(sRegD reg) %{
4361 constraint(ALLOC_IN_RC(stack_slots));
4362 // No match rule because this operand is only generated in matching
4363 op_cost(50);
4364 format %{ "[$reg]" %}
4365 interface(MEMORY_INTER) %{
4366 base(0x1d); // SP
4367 index(0x0); // No Index
4368 scale(0x0); // No Scale
4369 disp($reg); // Stack Offset
4370 %}
4371 %}
4373 operand stackSlotL(sRegL reg) %{
4374 constraint(ALLOC_IN_RC(stack_slots));
4375 // No match rule because this operand is only generated in matching
4376 op_cost(50);
4377 format %{ "[$reg]" %}
4378 interface(MEMORY_INTER) %{
4379 base(0x1d); // SP
4380 index(0x0); // No Index
4381 scale(0x0); // No Scale
4382 disp($reg); // Stack Offset
4383 %}
4384 %}
4385 */
4388 //------------------------OPERAND CLASSES--------------------------------------
4389 //opclass memory( direct, indirect, indOffset16, indOffset32, indOffset32X, indIndexOffset );
4390 opclass memory( indirect, indirectNarrow, indOffset8, indOffset32, indIndex, load_long_indirect, load_long_indOffset32 );
4393 //----------PIPELINE-----------------------------------------------------------
4394 // Rules which define the behavior of the target architectures pipeline.
4396 pipeline %{
4398 //----------ATTRIBUTES---------------------------------------------------------
4399 attributes %{
4400 fixed_size_instructions; // Fixed size instructions
4401 branch_has_delay_slot; // branch have delay slot in gs2
4402 max_instructions_per_bundle = 1; // 1 instruction per bundle
4403 max_bundles_per_cycle = 4; // Up to 4 bundles per cycle
4404 bundle_unit_size=4;
4405 instruction_unit_size = 4; // An instruction is 4 bytes long
4406 instruction_fetch_unit_size = 16; // The processor fetches one line
4407 instruction_fetch_units = 1; // of 16 bytes
4409 // List of nop instructions
4410 nops( MachNop );
4411 %}
4413 //----------RESOURCES----------------------------------------------------------
4414 // Resources are the functional units available to the machine
4416 resources(D1, D2, D3, D4, DECODE = D1 | D2 | D3| D4, ALU1, ALU2, ALU = ALU1 | ALU2, FPU1, FPU2, FPU = FPU1 | FPU2, MEM, BR);
4418 //----------PIPELINE DESCRIPTION-----------------------------------------------
4419 // Pipeline Description specifies the stages in the machine's pipeline
4421 // IF: fetch
4422 // ID: decode
4423 // RD: read
4424 // CA: caculate
4425 // WB: write back
4426 // CM: commit
4428 pipe_desc(IF, ID, RD, CA, WB, CM);
4431 //----------PIPELINE CLASSES---------------------------------------------------
4432 // Pipeline Classes describe the stages in which input and output are
4433 // referenced by the hardware pipeline.
4435 //No.1 Integer ALU reg-reg operation : dst <-- reg1 op reg2
4436 pipe_class ialu_regI_regI(mRegI dst, mRegI src1, mRegI src2) %{
4437 single_instruction;
4438 src1 : RD(read);
4439 src2 : RD(read);
4440 dst : WB(write)+1;
4441 DECODE : ID;
4442 ALU : CA;
4443 %}
4445 //No.19 Integer mult operation : dst <-- reg1 mult reg2
4446 pipe_class ialu_mult(mRegI dst, mRegI src1, mRegI src2) %{
4447 src1 : RD(read);
4448 src2 : RD(read);
4449 dst : WB(write)+5;
4450 DECODE : ID;
4451 ALU2 : CA;
4452 %}
4454 pipe_class mulL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
4455 src1 : RD(read);
4456 src2 : RD(read);
4457 dst : WB(write)+10;
4458 DECODE : ID;
4459 ALU2 : CA;
4460 %}
4462 //No.19 Integer div operation : dst <-- reg1 div reg2
4463 pipe_class ialu_div(mRegI dst, mRegI src1, mRegI src2) %{
4464 src1 : RD(read);
4465 src2 : RD(read);
4466 dst : WB(write)+10;
4467 DECODE : ID;
4468 ALU2 : CA;
4469 %}
4471 //No.19 Integer mod operation : dst <-- reg1 mod reg2
4472 pipe_class ialu_mod(mRegI dst, mRegI src1, mRegI src2) %{
4473 instruction_count(2);
4474 src1 : RD(read);
4475 src2 : RD(read);
4476 dst : WB(write)+10;
4477 DECODE : ID;
4478 ALU2 : CA;
4479 %}
4481 //No.15 Long ALU reg-reg operation : dst <-- reg1 op reg2
4482 pipe_class ialu_regL_regL(mRegL dst, mRegL src1, mRegL src2) %{
4483 instruction_count(2);
4484 src1 : RD(read);
4485 src2 : RD(read);
4486 dst : WB(write);
4487 DECODE : ID;
4488 ALU : CA;
4489 %}
4491 //No.18 Long ALU reg-imm16 operation : dst <-- reg1 op imm16
4492 pipe_class ialu_regL_imm16(mRegL dst, mRegL src) %{
4493 instruction_count(2);
4494 src : RD(read);
4495 dst : WB(write);
4496 DECODE : ID;
4497 ALU : CA;
4498 %}
4500 //no.16 load Long from memory :
4501 pipe_class ialu_loadL(mRegL dst, memory mem) %{
4502 instruction_count(2);
4503 mem : RD(read);
4504 dst : WB(write)+5;
4505 DECODE : ID;
4506 MEM : RD;
4507 %}
4509 //No.17 Store Long to Memory :
4510 pipe_class ialu_storeL(mRegL src, memory mem) %{
4511 instruction_count(2);
4512 mem : RD(read);
4513 src : RD(read);
4514 DECODE : ID;
4515 MEM : RD;
4516 %}
4518 //No.2 Integer ALU reg-imm16 operation : dst <-- reg1 op imm16
4519 pipe_class ialu_regI_imm16(mRegI dst, mRegI src) %{
4520 single_instruction;
4521 src : RD(read);
4522 dst : WB(write);
4523 DECODE : ID;
4524 ALU : CA;
4525 %}
4527 //No.3 Integer move operation : dst <-- reg
4528 pipe_class ialu_regI_mov(mRegI dst, mRegI src) %{
4529 src : RD(read);
4530 dst : WB(write);
4531 DECODE : ID;
4532 ALU : CA;
4533 %}
4535 //No.4 No instructions : do nothing
4536 pipe_class empty( ) %{
4537 instruction_count(0);
4538 %}
4540 //No.5 UnConditional branch :
4541 pipe_class pipe_jump( label labl ) %{
4542 multiple_bundles;
4543 DECODE : ID;
4544 BR : RD;
4545 %}
4547 //No.6 ALU Conditional branch :
4548 pipe_class pipe_alu_branch(mRegI src1, mRegI src2, label labl ) %{
4549 multiple_bundles;
4550 src1 : RD(read);
4551 src2 : RD(read);
4552 DECODE : ID;
4553 BR : RD;
4554 %}
4556 //no.7 load integer from memory :
4557 pipe_class ialu_loadI(mRegI dst, memory mem) %{
4558 mem : RD(read);
4559 dst : WB(write)+3;
4560 DECODE : ID;
4561 MEM : RD;
4562 %}
4564 //No.8 Store Integer to Memory :
4565 pipe_class ialu_storeI(mRegI src, memory mem) %{
4566 mem : RD(read);
4567 src : RD(read);
4568 DECODE : ID;
4569 MEM : RD;
4570 %}
4573 //No.10 Floating FPU reg-reg operation : dst <-- reg1 op reg2
4574 pipe_class fpu_regF_regF(regF dst, regF src1, regF src2) %{
4575 src1 : RD(read);
4576 src2 : RD(read);
4577 dst : WB(write);
4578 DECODE : ID;
4579 FPU : CA;
4580 %}
4582 //No.22 Floating div operation : dst <-- reg1 div reg2
4583 pipe_class fpu_div(regF dst, regF src1, regF src2) %{
4584 src1 : RD(read);
4585 src2 : RD(read);
4586 dst : WB(write);
4587 DECODE : ID;
4588 FPU2 : CA;
4589 %}
4591 pipe_class fcvt_I2D(regD dst, mRegI src) %{
4592 src : RD(read);
4593 dst : WB(write);
4594 DECODE : ID;
4595 FPU1 : CA;
4596 %}
4598 pipe_class fcvt_D2I(mRegI dst, regD src) %{
4599 src : RD(read);
4600 dst : WB(write);
4601 DECODE : ID;
4602 FPU1 : CA;
4603 %}
4605 pipe_class pipe_mfc1(mRegI dst, regD src) %{
4606 src : RD(read);
4607 dst : WB(write);
4608 DECODE : ID;
4609 MEM : RD;
4610 %}
4612 pipe_class pipe_mtc1(regD dst, mRegI src) %{
4613 src : RD(read);
4614 dst : WB(write);
4615 DECODE : ID;
4616 MEM : RD(5);
4617 %}
4619 //No.23 Floating sqrt operation : dst <-- reg1 sqrt reg2
4620 pipe_class fpu_sqrt(regF dst, regF src1, regF src2) %{
4621 multiple_bundles;
4622 src1 : RD(read);
4623 src2 : RD(read);
4624 dst : WB(write);
4625 DECODE : ID;
4626 FPU2 : CA;
4627 %}
4629 //No.11 Load Floating from Memory :
4630 pipe_class fpu_loadF(regF dst, memory mem) %{
4631 instruction_count(1);
4632 mem : RD(read);
4633 dst : WB(write)+3;
4634 DECODE : ID;
4635 MEM : RD;
4636 %}
4638 //No.12 Store Floating to Memory :
4639 pipe_class fpu_storeF(regF src, memory mem) %{
4640 instruction_count(1);
4641 mem : RD(read);
4642 src : RD(read);
4643 DECODE : ID;
4644 MEM : RD;
4645 %}
4647 //No.13 FPU Conditional branch :
4648 pipe_class pipe_fpu_branch(regF src1, regF src2, label labl ) %{
4649 multiple_bundles;
4650 src1 : RD(read);
4651 src2 : RD(read);
4652 DECODE : ID;
4653 BR : RD;
4654 %}
4656 //No.14 Floating FPU reg operation : dst <-- op reg
4657 pipe_class fpu1_regF(regF dst, regF src) %{
4658 src : RD(read);
4659 dst : WB(write);
4660 DECODE : ID;
4661 FPU : CA;
4662 %}
4664 pipe_class long_memory_op() %{
4665 instruction_count(10); multiple_bundles; force_serialization;
4666 fixed_latency(30);
4667 %}
4669 pipe_class simple_call() %{
4670 instruction_count(10); multiple_bundles; force_serialization;
4671 fixed_latency(200);
4672 BR : RD;
4673 %}
4675 pipe_class call() %{
4676 instruction_count(10); multiple_bundles; force_serialization;
4677 fixed_latency(200);
4678 %}
4680 //FIXME:
4681 //No.9 Piple slow : for multi-instructions
4682 pipe_class pipe_slow( ) %{
4683 instruction_count(20);
4684 force_serialization;
4685 multiple_bundles;
4686 fixed_latency(50);
4687 %}
4689 %}
4693 //----------INSTRUCTIONS-------------------------------------------------------
4694 //
4695 // match -- States which machine-independent subtree may be replaced
4696 // by this instruction.
4697 // ins_cost -- The estimated cost of this instruction is used by instruction
4698 // selection to identify a minimum cost tree of machine
4699 // instructions that matches a tree of machine-independent
4700 // instructions.
4701 // format -- A string providing the disassembly for this instruction.
4702 // The value of an instruction's operand may be inserted
4703 // by referring to it with a '$' prefix.
4704 // opcode -- Three instruction opcodes may be provided. These are referred
4705 // to within an encode class as $primary, $secondary, and $tertiary
4706 // respectively. The primary opcode is commonly used to
4707 // indicate the type of machine instruction, while secondary
4708 // and tertiary are often used for prefix options or addressing
4709 // modes.
4710 // ins_encode -- A list of encode classes with parameters. The encode class
4711 // name must have been defined in an 'enc_class' specification
4712 // in the encode section of the architecture description.
4715 // Load Integer
4716 instruct loadI(mRegI dst, memory mem) %{
4717 match(Set dst (LoadI mem));
4719 ins_cost(125);
4720 format %{ "lw $dst, $mem #@loadI" %}
4721 ins_encode (load_I_enc(dst, mem));
4722 ins_pipe( ialu_loadI );
4723 %}
4725 // Load Long.
4726 instruct loadL(mRegL dst, memory mem) %{
4727 // predicate(!((LoadLNode*)n)->require_atomic_access());
4728 match(Set dst (LoadL mem));
4730 ins_cost(250);
4731 format %{ "ld $dst, $mem #@loadL" %}
4732 ins_encode(load_L_enc(dst, mem));
4733 ins_pipe( ialu_loadL );
4734 %}
4736 // Load Long - UNaligned
4737 instruct loadL_unaligned(mRegL dst, memory mem) %{
4738 match(Set dst (LoadL_unaligned mem));
4740 // FIXME: Jin: Need more effective ldl/ldr
4741 ins_cost(450);
4742 format %{ "ld $dst, $mem #@loadL_unaligned\n\t" %}
4743 ins_encode(load_L_enc(dst, mem));
4744 ins_pipe( ialu_loadL );
4745 %}
4747 // Store Long
4748 instruct storeL_reg(memory mem, mRegL src) %{
4749 predicate(!((StoreLNode*)n)->require_atomic_access());
4750 match(Set mem (StoreL mem src));
4752 ins_cost(200);
4753 format %{ "sd $mem, $src #@storeL_reg\n" %}
4754 ins_encode(store_L_reg_enc(mem, src));
4755 ins_pipe( ialu_storeL );
4756 %}
4758 //FIXME:volatile! atomic!
4759 // Volatile Store Long. Must be atomic, so move it into
4760 // the FP TOS and then do a 64-bit FIST. Has to probe the
4761 // target address before the store (for null-ptr checks)
4762 // so the memory operand is used twice in the encoding.
4763 instruct storeL_reg_atomic(memory mem, mRegL src) %{
4764 predicate(((StoreLNode*)n)->require_atomic_access());
4765 match(Set mem (StoreL mem src));
4767 ins_cost(200);
4768 format %{ "sw $mem, $src #@storeL_reg_atomic\n\t"
4769 "sw $mem+4, $src.hi #@storeL_reg_atomic" %}
4770 ins_encode %{
4771 Register src = as_Register($src$$reg);
4773 int base = $mem$$base;
4774 int index = $mem$$index;
4775 int scale = $mem$$scale;
4776 int disp = $mem$$disp;
4778 // assert(false, "storeL_reg_atomic should store a long value atomically");
4780 if( scale != 0 ) Unimplemented();
4781 if( index != 0 ) {
4782 if( Assembler::is_simm16(disp) ) {
4783 __ addu(AT, as_Register(base), as_Register(index));
4784 __ sd(src, AT, disp);
4785 } else {
4786 __ addu(AT, as_Register(base), as_Register(index));
4787 __ move(T9, disp);
4788 __ addu(AT, AT, T9);
4789 __ sd(src, AT, 0);
4790 }
4791 } else {
4792 if( Assembler::is_simm16(disp) ) {
4793 __ move(AT, as_Register(base));
4794 __ sd(src, AT, disp);
4795 } else {
4796 __ move(AT, as_Register(base));
4797 __ move(T9, disp);
4798 __ addu(AT, AT, T9);
4799 __ sd(src, AT, 0);
4800 }
4801 }
4803 %}
4804 ins_pipe( ialu_storeL );
4805 %}
4807 instruct storeL_immL0(memory mem, immL0 zero) %{
4808 match(Set mem (StoreL mem zero));
4810 ins_cost(180);
4811 format %{ "sd $mem, zero #@storeL_immL0" %}
4812 ins_encode(store_L_immL0_enc(mem, zero));
4813 ins_pipe( ialu_storeL );
4814 %}
4816 instruct storeL_imm(memory mem, immL src) %{
4817 match(Set mem (StoreL mem src));
4819 ins_cost(200);
4820 format %{ "sw $mem, $src #@storeL_imm" %}
4821 ins_encode(store_L_immL_enc(mem, src));
4822 ins_pipe( ialu_storeL );
4823 %}
4825 // Load Compressed Pointer
4826 instruct loadN(mRegN dst, memory mem)
4827 %{
4828 match(Set dst (LoadN mem));
4830 ins_cost(125); // XXX
4831 format %{ "lwu $dst, $mem\t# compressed ptr @ loadN" %}
4832 //TODO: Address should be implemented
4833 /*
4834 ins_encode %{
4835 __ lwu($dst$$Register, $mem$$Address);
4836 %}
4837 */
4838 ins_encode (load_N_enc(dst, mem));
4839 ins_pipe( ialu_loadI ); // XXX
4840 %}
4842 // Load Pointer
4843 instruct loadP(mRegP dst, memory mem) %{
4844 match(Set dst (LoadP mem));
4846 ins_cost(125);
4847 format %{ "ld $dst, $mem #@loadP" %}
4848 ins_encode (load_P_enc(dst, mem));
4849 ins_pipe( ialu_loadI );
4850 %}
4852 // Load Klass Pointer
4853 instruct loadKlass(mRegP dst, memory mem) %{
4854 match(Set dst (LoadKlass mem));
4856 ins_cost(125);
4857 format %{ "MOV $dst,$mem @ loadKlass" %}
4858 ins_encode (load_P_enc(dst, mem));
4859 ins_pipe( ialu_loadI );
4860 %}
4862 // Load narrow Klass Pointer
4863 instruct loadNKlass(mRegN dst, memory mem)
4864 %{
4865 match(Set dst (LoadNKlass mem));
4867 ins_cost(125); // XXX
4868 format %{ "lwu $dst, $mem\t# compressed klass ptr" %}
4869 ins_encode (load_N_enc(dst, mem));
4870 /*
4871 ins_encode %{
4872 __ lwu($dst$$Register, $mem$$Address);
4873 %}
4874 */
4875 ins_pipe( ialu_loadI ); // XXX
4876 %}
4878 // Load Constant
4879 instruct loadConI(mRegI dst, immI src) %{
4880 match(Set dst src);
4882 format %{ "mov $dst, $src #@loadConI" %}
4883 ins_encode %{
4884 Register dst = $dst$$Register;
4885 int value = $src$$constant;
4886 __ move(dst, value);
4887 %}
4888 ins_pipe( ialu_regI_regI );
4889 %}
4892 instruct loadConL(mRegL dst, immL src) %{
4893 match(Set dst src);
4894 // effect(ILL cr);
4895 ins_cost(200);
4896 format %{ "li $dst, $src #@loadConL\t"
4897 %}
4898 ins_encode %{
4899 Register dst_reg = as_Register($dst$$reg);
4900 __ li(dst_reg, (long)$src$$constant);
4901 %}
4902 ins_pipe( ialu_regL_regL );
4903 %}
4906 // Load Range
4907 instruct loadRange(mRegI dst, memory mem) %{
4908 match(Set dst (LoadRange mem));
4910 ins_cost(125);
4911 format %{ "MOV $dst,$mem @ loadRange" %}
4912 ins_encode(load_I_enc(dst, mem));
4913 ins_pipe( ialu_loadI );
4914 %}
4917 instruct storeP(memory mem, mRegP src ) %{
4918 match(Set mem (StoreP mem src));
4920 ins_cost(125);
4921 format %{ "sd $src, $mem #@storeP" %}
4922 ins_encode(store_P_reg_enc(mem, src));
4923 ins_pipe( ialu_storeI );
4924 %}
4926 /*
4927 [Ref: loadConP]
4929 Error:
4930 0x2d4b6d40: lui t9, 0x4f <--- handle
4931 0x2d4b6d44: addiu t9, t9, 0xffff808c
4932 0x2d4b6d48: sw t9, 0x4(s2)
4934 OK:
4935 0x2cc5ed40: lui t9, 0x336a <--- klass
4936 0x2cc5ed44: addiu t9, t9, 0x5a10
4937 0x2cc5ed48: sw t9, 0x4(s2)
4938 */
4939 // Store Pointer Immediate; null pointers or constant oops that do not
4940 // need card-mark barriers.
4942 // Store NULL Pointer, mark word, or other simple pointer constant.
4943 instruct storeImmP(memory mem, immP31 src) %{
4944 match(Set mem (StoreP mem src));
4946 ins_cost(150);
4947 format %{ "mov $mem, $src #@storeImmP" %}
4948 ins_encode(store_P_immP_enc(mem, src));
4949 ins_pipe( ialu_storeI );
4950 %}
4952 // Store Byte Immediate
4953 instruct storeImmB(memory mem, immI8 src) %{
4954 match(Set mem (StoreB mem src));
4956 ins_cost(150);
4957 format %{ "movb $mem, $src #@storeImmB" %}
4958 ins_encode(store_B_immI_enc(mem, src));
4959 ins_pipe( ialu_storeI );
4960 %}
4962 // Store Compressed Pointer
4963 instruct storeN(memory mem, mRegN src)
4964 %{
4965 match(Set mem (StoreN mem src));
4967 ins_cost(125); // XXX
4968 format %{ "sw $mem, $src\t# compressed ptr @ storeN" %}
4969 ins_encode(store_N_reg_enc(mem, src));
4970 ins_pipe( ialu_storeI );
4971 %}
4973 instruct storeNKlass(memory mem, mRegN src)
4974 %{
4975 match(Set mem (StoreNKlass mem src));
4977 ins_cost(125); // XXX
4978 format %{ "sw $mem, $src\t# compressed klass ptr" %}
4979 ins_encode(store_N_reg_enc(mem, src));
4980 ins_pipe( ialu_storeI );
4981 %}
4983 instruct storeImmN0(memory mem, immN0 zero)
4984 %{
4985 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
4986 match(Set mem (StoreN mem zero));
4988 ins_cost(125); // XXX
4989 format %{ "storeN0 $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
4990 ins_encode(storeImmN0_enc(mem, zero));
4991 ins_pipe( ialu_storeI );
4992 %}
4994 instruct storeImmN(memory mem, immN src)
4995 %{
4996 match(Set mem (StoreN mem src));
4998 ins_cost(150); // XXX
4999 format %{ "storeImmN $mem, $src\t# compressed ptr @ storeImmN" %}
5000 ins_encode(storeImmN_enc(mem, src));
5001 ins_pipe( ialu_storeI );
5002 %}
5004 instruct storeImmNKlass(memory mem, immNKlass src)
5005 %{
5006 match(Set mem (StoreNKlass mem src));
5008 ins_cost(150); // XXX
5009 format %{ "sw $mem, $src\t# compressed klass ptr" %}
5010 ins_encode(storeImmNKlass_enc(mem, src));
5011 ins_pipe( ialu_storeI );
5012 %}
5014 // Store Byte
5015 instruct storeB(memory mem, mRegI src) %{
5016 match(Set mem (StoreB mem src));
5018 ins_cost(125);
5019 format %{ "sb $src, $mem #@storeB" %}
5020 ins_encode(store_B_reg_enc(mem, src));
5021 ins_pipe( ialu_storeI );
5022 %}
5024 // Load Byte (8bit signed)
5025 instruct loadB(mRegI dst, memory mem) %{
5026 match(Set dst (LoadB mem));
5028 ins_cost(125);
5029 format %{ "lb $dst, $mem #@loadB" %}
5030 ins_encode(load_B_enc(dst, mem));
5031 ins_pipe( ialu_loadI );
5032 %}
5034 // Load Byte (8bit UNsigned)
5035 instruct loadUB(mRegI dst, memory mem) %{
5036 match(Set dst (LoadUB mem));
5038 ins_cost(125);
5039 format %{ "lbu $dst, $mem #@loadUB" %}
5040 ins_encode(load_UB_enc(dst, mem));
5041 ins_pipe( ialu_loadI );
5042 %}
5044 // Load Short (16bit signed)
5045 instruct loadS(mRegI dst, memory mem) %{
5046 match(Set dst (LoadS mem));
5048 ins_cost(125);
5049 format %{ "lh $dst, $mem #@loadS" %}
5050 ins_encode(load_S_enc(dst, mem));
5051 ins_pipe( ialu_loadI );
5052 %}
5054 //TODO: check if it is necessery to do 'prefetch' in the future(which means never). LEE
5055 instruct prefetchAllocNTA( memory mem ) %{
5056 match(PrefetchAllocation mem);
5057 ins_cost(400);
5058 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write just sync" %}
5059 ins_encode %{
5060 __ sync();
5061 %}
5062 ins_pipe(pipe_slow);
5063 %}
5065 // Store Integer Immediate
5066 instruct storeImmI(memory mem, immI src) %{
5067 match(Set mem (StoreI mem src));
5069 ins_cost(150);
5070 format %{ "mov $mem, $src #@storeImmI" %}
5071 ins_encode(store_I_immI_enc(mem, src));
5072 ins_pipe( ialu_storeI );
5073 %}
5075 // Store Integer
5076 instruct storeI(memory mem, mRegI src) %{
5077 match(Set mem (StoreI mem src));
5079 ins_cost(125);
5080 format %{ "sw $mem, $src #@storeI" %}
5081 ins_encode(store_I_reg_enc(mem, src));
5082 ins_pipe( ialu_storeI );
5083 %}
5085 // Load Float
5086 instruct loadF(regF dst, memory mem) %{
5087 match(Set dst (LoadF mem));
5089 ins_cost(150);
5090 format %{ "loadF $dst, $mem #@loadF" %}
5091 ins_encode(load_F_enc(dst, mem));
5092 ins_pipe( ialu_loadI );
5093 %}
5095 instruct loadConP(mRegP dst, immP src) %{
5096 match(Set dst src);
5098 format %{ "li $dst, $src #@loadConP" %}
5100 ins_encode %{
5101 Register dst = $dst$$Register;
5102 long* value = (long*)$src$$constant;
5103 bool is_need_reloc = $src->constant_reloc() != relocInfo::none;
5105 /* During GC, klassOop may be moved to new position in the heap.
5106 * It must be relocated.
5107 * Refer: [c1_LIRAssembler_mips.cpp] jobject2reg()
5108 */
5109 if (is_need_reloc) {
5110 if($src->constant_reloc() == relocInfo::metadata_type){
5111 int klass_index = __ oop_recorder()->find_index((Klass*)value);
5112 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5114 __ relocate(rspec);
5115 __ li48(dst, (long)value);
5116 }
5118 if($src->constant_reloc() == relocInfo::oop_type){
5119 int oop_index = __ oop_recorder()->find_index((jobject)value);
5120 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5122 __ relocate(rspec);
5123 __ li48(dst, (long)value);
5124 }
5125 } else {
5126 __ li48(dst, (long)value);
5127 }
5128 %}
5130 ins_pipe( ialu_regI_regI );
5131 %}
5133 instruct loadConP0(mRegP dst, immP0 src)
5134 %{
5135 match(Set dst src);
5137 ins_cost(50);
5138 format %{ "mov $dst, R0\t# ptr" %}
5139 ins_encode %{
5140 Register dst_reg = $dst$$Register;
5141 __ move(dst_reg, R0);
5142 %}
5143 ins_pipe( ialu_regI_regI );
5144 %}
5146 instruct loadConN0(mRegN dst, immN0 src, FlagsReg cr) %{
5147 match(Set dst src);
5148 effect(KILL cr);
5149 format %{ "move $dst, R0\t# compressed NULL ptr" %}
5150 ins_encode %{
5151 __ move($dst$$Register, R0);
5152 %}
5153 ins_pipe( ialu_regI_regI );
5154 %}
5156 instruct loadConN(mRegN dst, immN src) %{
5157 match(Set dst src);
5159 ins_cost(125);
5160 format %{ "li $dst, $src\t# compressed ptr @ loadConN" %}
5161 ins_encode %{
5162 address con = (address)$src$$constant;
5163 if (con == NULL) {
5164 ShouldNotReachHere();
5165 } else {
5166 assert (UseCompressedOops, "should only be used for compressed headers");
5167 assert (Universe::heap() != NULL, "java heap should be initialized");
5168 assert (__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
5170 Register dst = $dst$$Register;
5171 long* value = (long*)$src$$constant;
5172 int oop_index = __ oop_recorder()->find_index((jobject)value);
5173 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5174 if(rspec.type()!=relocInfo::none){
5175 __ relocate(rspec, Assembler::narrow_oop_operand);
5176 __ li48(dst, oop_index);
5177 }
5178 else {
5179 __ li48(dst, oop_index);
5180 }
5181 }
5182 %}
5183 ins_pipe( ialu_regI_regI ); // XXX
5184 %}
5186 instruct loadConNKlass(mRegN dst, immNKlass src) %{
5187 match(Set dst src);
5189 ins_cost(125);
5190 format %{ "li $dst, $src\t# compressed klass ptr" %}
5191 ins_encode %{
5192 address con = (address)$src$$constant;
5193 if (con == NULL) {
5194 ShouldNotReachHere();
5195 } else {
5196 Register dst = $dst$$Register;
5197 long* value = (long*)$src$$constant;
5199 int klass_index = __ oop_recorder()->find_index((Klass*)value);
5200 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5201 long narrowp = (long)Klass::encode_klass((Klass*)value);
5203 if(rspec.type()!=relocInfo::none){
5204 __ relocate(rspec, Assembler::narrow_oop_operand);
5205 __ li48(dst, narrowp);
5206 }
5207 else {
5208 __ li48(dst, narrowp);
5209 }
5210 }
5211 %}
5212 ins_pipe( ialu_regI_regI ); // XXX
5213 %}
5215 /*
5216 // Load Stack Slot
5217 instruct loadSSI(mRegI dst, stackSlotI src) %{
5218 match(Set dst src);
5219 ins_cost(25);
5221 format %{ "MOV $dst,$src #@loadSSI" %}
5222 ins_encode %{
5223 Register dst = $dst$$Register;
5225 int base = $src$$base;
5226 int index = $src$$index;
5227 int scale = $src$$scale;
5228 int disp = $src$$disp;
5230 fprintf(stderr, "\n?????????????????????????\n");//fujie debug
5231 if( scale != 0 ) Unimplemented();
5232 if( index != 0 ) {
5233 __ add(AT, as_Register(base), as_Register(index));
5234 __ lw(dst, AT, disp);
5235 } else {
5236 __ lw(dst, as_Register(base), disp);
5237 }
5239 %}
5241 ins_pipe( ialu_reg_mem );
5242 %}
5244 // Load Stack Slot
5245 instruct loadSSP(mRegP dst, stackSlotP src) %{
5246 match(Set dst src);
5247 ins_cost(25);
5249 format %{ "MOV $dst,$src #@loadSSP" %}
5250 ins_encode %{
5251 Register dst = $dst$$Register;
5253 int base = $src$$base;
5254 int index = $src$$index;
5255 int scale = $src$$scale;
5256 int disp = $src$$disp;
5258 fprintf(stderr, "\n?????????????????????????\n");//fujie debug
5259 if( scale != 0 ) Unimplemented();
5260 if( index != 0 ) {
5261 __ add(AT, as_Register(base), as_Register(index));
5262 __ lw(dst, AT, disp);
5263 } else {
5264 __ lw(dst, as_Register(base), disp);
5265 }
5267 %}
5269 ins_pipe( ialu_reg_mem );
5270 %}
5271 */
5273 //FIXME
5274 // Tail Call; Jump from runtime stub to Java code.
5275 // Also known as an 'interprocedural jump'.
5276 // Target of jump will eventually return to caller.
5277 // TailJump below removes the return address.
5278 instruct TailCalljmpInd(mRegP jump_target, mRegP method_oop) %{
5279 match(TailCall jump_target method_oop );
5280 ins_cost(300);
5281 format %{ "JMP $jump_target \t# @TailCalljmpInd" %}
5283 ins_encode %{
5284 Register target = $jump_target$$Register;
5285 Register oop = $method_oop$$Register;
5287 /* 2012/10/12 Jin: RA will be used in generate_forward_exception() */
5288 __ push(RA);
5290 __ move(S3, oop);
5291 __ jr(target);
5292 __ nop();
5293 %}
5295 ins_pipe( pipe_jump );
5296 %}
5298 // Create exception oop: created by stack-crawling runtime code.
5299 // Created exception is now available to this handler, and is setup
5300 // just prior to jumping to this handler. No code emitted.
5301 instruct CreateException( a0_RegP ex_oop )
5302 %{
5303 match(Set ex_oop (CreateEx));
5305 // use the following format syntax
5306 format %{ "# exception oop is in A0; no code emitted @CreateException" %}
5307 ins_encode %{
5308 /* Jin: X86 leaves this function empty */
5309 __ block_comment("CreateException is empty in X86/MIPS");
5310 %}
5311 ins_pipe( empty );
5312 // ins_pipe( pipe_jump );
5313 %}
5316 /* 2012/9/14 Jin: The mechanism of exception handling is clear now.
5318 - Common try/catch:
5319 2012/9/14 Jin: [stubGenerator_mips.cpp] generate_forward_exception()
5320 |- V0, V1 are created
5321 |- T9 <= SharedRuntime::exception_handler_for_return_address
5322 `- jr T9
5323 `- the caller's exception_handler
5324 `- jr OptoRuntime::exception_blob
5325 `- here
5326 - Rethrow(e.g. 'unwind'):
5327 * The callee:
5328 |- an exception is triggered during execution
5329 `- exits the callee method through RethrowException node
5330 |- The callee pushes exception_oop(T0) and exception_pc(RA)
5331 `- The callee jumps to OptoRuntime::rethrow_stub()
5332 * In OptoRuntime::rethrow_stub:
5333 |- The VM calls _rethrow_Java to determine the return address in the caller method
5334 `- exits the stub with tailjmpInd
5335 |- pops exception_oop(V0) and exception_pc(V1)
5336 `- jumps to the return address(usually an exception_handler)
5337 * The caller:
5338 `- continues processing the exception_blob with V0/V1
5339 */
5341 /*
5342 Disassembling OptoRuntime::rethrow_stub()
5344 ; locals
5345 0x2d3bf320: addiu sp, sp, 0xfffffff8
5346 0x2d3bf324: sw ra, 0x4(sp)
5347 0x2d3bf328: sw fp, 0x0(sp)
5348 0x2d3bf32c: addu fp, sp, zero
5349 0x2d3bf330: addiu sp, sp, 0xfffffff0
5350 0x2d3bf334: sw ra, 0x8(sp)
5351 0x2d3bf338: sw t0, 0x4(sp)
5352 0x2d3bf33c: sw sp, 0x0(sp)
5354 ; get_thread(S2)
5355 0x2d3bf340: addu s2, sp, zero
5356 0x2d3bf344: srl s2, s2, 12
5357 0x2d3bf348: sll s2, s2, 2
5358 0x2d3bf34c: lui at, 0x2c85
5359 0x2d3bf350: addu at, at, s2
5360 0x2d3bf354: lw s2, 0xffffcc80(at)
5362 0x2d3bf358: lw s0, 0x0(sp)
5363 0x2d3bf35c: sw s0, 0x118(s2) // last_sp -> threa
5364 0x2d3bf360: sw s2, 0xc(sp)
5366 ; OptoRuntime::rethrow_C(oopDesc* exception, JavaThread* thread, address ret_pc)
5367 0x2d3bf364: lw a0, 0x4(sp)
5368 0x2d3bf368: lw a1, 0xc(sp)
5369 0x2d3bf36c: lw a2, 0x8(sp)
5370 ;; Java_To_Runtime
5371 0x2d3bf370: lui t9, 0x2c34
5372 0x2d3bf374: addiu t9, t9, 0xffff8a48
5373 0x2d3bf378: jalr t9
5374 0x2d3bf37c: nop
5376 0x2d3bf380: addu s3, v0, zero ; S3: SharedRuntime::raw_exception_handler_for_return_address()
5378 0x2d3bf384: lw s0, 0xc(sp)
5379 0x2d3bf388: sw zero, 0x118(s0)
5380 0x2d3bf38c: sw zero, 0x11c(s0)
5381 0x2d3bf390: lw s1, 0x144(s0) ; ex_oop: S1
5382 0x2d3bf394: addu s2, s0, zero
5383 0x2d3bf398: sw zero, 0x144(s2)
5384 0x2d3bf39c: lw s0, 0x4(s2)
5385 0x2d3bf3a0: addiu s4, zero, 0x0
5386 0x2d3bf3a4: bne s0, s4, 0x2d3bf3d4
5387 0x2d3bf3a8: nop
5388 0x2d3bf3ac: addiu sp, sp, 0x10
5389 0x2d3bf3b0: addiu sp, sp, 0x8
5390 0x2d3bf3b4: lw ra, 0xfffffffc(sp)
5391 0x2d3bf3b8: lw fp, 0xfffffff8(sp)
5392 0x2d3bf3bc: lui at, 0x2b48
5393 0x2d3bf3c0: lw at, 0x100(at)
5395 ; tailjmpInd: Restores exception_oop & exception_pc
5396 0x2d3bf3c4: addu v1, ra, zero
5397 0x2d3bf3c8: addu v0, s1, zero
5398 0x2d3bf3cc: jr s3
5399 0x2d3bf3d0: nop
5400 ; Exception:
5401 0x2d3bf3d4: lui s1, 0x2cc8 ; generate_forward_exception()
5402 0x2d3bf3d8: addiu s1, s1, 0x40
5403 0x2d3bf3dc: addiu s2, zero, 0x0
5404 0x2d3bf3e0: addiu sp, sp, 0x10
5405 0x2d3bf3e4: addiu sp, sp, 0x8
5406 0x2d3bf3e8: lw ra, 0xfffffffc(sp)
5407 0x2d3bf3ec: lw fp, 0xfffffff8(sp)
5408 0x2d3bf3f0: lui at, 0x2b48
5409 0x2d3bf3f4: lw at, 0x100(at)
5410 ; TailCalljmpInd
5411 __ push(RA); ; to be used in generate_forward_exception()
5412 0x2d3bf3f8: addu t7, s2, zero
5413 0x2d3bf3fc: jr s1
5414 0x2d3bf400: nop
5415 */
5416 // Rethrow exception:
5417 // The exception oop will come in the first argument position.
5418 // Then JUMP (not call) to the rethrow stub code.
5419 instruct RethrowException()
5420 %{
5421 match(Rethrow);
5423 // use the following format syntax
5424 format %{ "JMP rethrow_stub #@RethrowException" %}
5425 ins_encode %{
5426 __ block_comment("@ RethrowException");
5428 cbuf.set_insts_mark();
5429 cbuf.relocate(cbuf.insts_mark(), runtime_call_Relocation::spec());
5431 // call OptoRuntime::rethrow_stub to get the exception handler in parent method
5432 __ li(T9, OptoRuntime::rethrow_stub());
5433 __ jr(T9);
5434 __ nop();
5435 %}
5436 ins_pipe( pipe_jump );
5437 %}
5439 instruct branchConP_zero(cmpOpU cmp, mRegP op1, immP0 zero, label labl) %{
5440 match(If cmp (CmpP op1 zero));
5441 effect(USE labl);
5443 ins_cost(180);
5444 format %{ "b$cmp $op1, R0, $labl #@branchConP_zero" %}
5446 ins_encode %{
5447 Register op1 = $op1$$Register;
5448 Register op2 = R0;
5449 Label &L = *($labl$$label);
5450 int flag = $cmp$$cmpcode;
5452 switch(flag)
5453 {
5454 case 0x01: //equal
5455 if (&L)
5456 __ beq(op1, op2, L);
5457 else
5458 __ beq(op1, op2, (int)0);
5459 break;
5460 case 0x02: //not_equal
5461 if (&L)
5462 __ bne(op1, op2, L);
5463 else
5464 __ bne(op1, op2, (int)0);
5465 break;
5466 /*
5467 case 0x03: //above
5468 __ sltu(AT, op2, op1);
5469 if(&L)
5470 __ bne(R0, AT, L);
5471 else
5472 __ bne(R0, AT, (int)0);
5473 break;
5474 case 0x04: //above_equal
5475 __ sltu(AT, op1, op2);
5476 if(&L)
5477 __ beq(AT, R0, L);
5478 else
5479 __ beq(AT, R0, (int)0);
5480 break;
5481 case 0x05: //below
5482 __ sltu(AT, op1, op2);
5483 if(&L)
5484 __ bne(R0, AT, L);
5485 else
5486 __ bne(R0, AT, (int)0);
5487 break;
5488 case 0x06: //below_equal
5489 __ sltu(AT, op2, op1);
5490 if(&L)
5491 __ beq(AT, R0, L);
5492 else
5493 __ beq(AT, R0, (int)0);
5494 break;
5495 */
5496 default:
5497 Unimplemented();
5498 }
5499 __ nop();
5500 %}
5502 ins_pc_relative(1);
5503 ins_pipe( pipe_alu_branch );
5504 %}
5507 instruct branchConP(cmpOpU cmp, mRegP op1, mRegP op2, label labl) %{
5508 match(If cmp (CmpP op1 op2));
5509 // predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
5510 effect(USE labl);
5512 ins_cost(200);
5513 format %{ "b$cmp $op1, $op2, $labl #@branchConP" %}
5515 ins_encode %{
5516 Register op1 = $op1$$Register;
5517 Register op2 = $op2$$Register;
5518 Label &L = *($labl$$label);
5519 int flag = $cmp$$cmpcode;
5521 switch(flag)
5522 {
5523 case 0x01: //equal
5524 if (&L)
5525 __ beq(op1, op2, L);
5526 else
5527 __ beq(op1, op2, (int)0);
5528 break;
5529 case 0x02: //not_equal
5530 if (&L)
5531 __ bne(op1, op2, L);
5532 else
5533 __ bne(op1, op2, (int)0);
5534 break;
5535 case 0x03: //above
5536 __ sltu(AT, op2, op1);
5537 if(&L)
5538 __ bne(R0, AT, L);
5539 else
5540 __ bne(R0, AT, (int)0);
5541 break;
5542 case 0x04: //above_equal
5543 __ sltu(AT, op1, op2);
5544 if(&L)
5545 __ beq(AT, R0, L);
5546 else
5547 __ beq(AT, R0, (int)0);
5548 break;
5549 case 0x05: //below
5550 __ sltu(AT, op1, op2);
5551 if(&L)
5552 __ bne(R0, AT, L);
5553 else
5554 __ bne(R0, AT, (int)0);
5555 break;
5556 case 0x06: //below_equal
5557 __ sltu(AT, op2, op1);
5558 if(&L)
5559 __ beq(AT, R0, L);
5560 else
5561 __ beq(AT, R0, (int)0);
5562 break;
5563 default:
5564 Unimplemented();
5565 }
5566 __ nop();
5567 %}
5569 ins_pc_relative(1);
5570 ins_pipe( pipe_alu_branch );
5571 %}
5573 instruct cmpN_null_branch(cmpOp cmp, mRegN op1, immN0 null, label labl) %{
5574 match(If cmp (CmpN op1 null));
5575 effect(USE labl);
5577 ins_cost(180);
5578 format %{ "CMP $op1,0\t! compressed ptr\n\t"
5579 "BP$cmp $labl" %}
5580 ins_encode %{
5581 Register op1 = $op1$$Register;
5582 Register op2 = R0;
5583 Label &L = *($labl$$label);
5584 int flag = $cmp$$cmpcode;
5586 switch(flag)
5587 {
5588 case 0x01: //equal
5589 if (&L)
5590 __ beq(op1, op2, L);
5591 else
5592 __ beq(op1, op2, (int)0);
5593 break;
5594 case 0x02: //not_equal
5595 if (&L)
5596 __ bne(op1, op2, L);
5597 else
5598 __ bne(op1, op2, (int)0);
5599 break;
5600 default:
5601 Unimplemented();
5602 }
5603 __ nop();
5604 %}
5605 //TODO: pipe_branchP or create pipe_branchN LEE
5606 ins_pc_relative(1);
5607 ins_pipe( pipe_alu_branch );
5608 %}
5610 instruct cmpN_reg_branch(cmpOp cmp, mRegN op1, mRegN op2, label labl) %{
5611 match(If cmp (CmpN op1 op2));
5612 effect(USE labl);
5614 ins_cost(180);
5615 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
5616 "BP$cmp $labl" %}
5617 ins_encode %{
5618 Register op1_reg = $op1$$Register;
5619 Register op2_reg = $op2$$Register;
5620 Label &L = *($labl$$label);
5621 int flag = $cmp$$cmpcode;
5623 switch(flag)
5624 {
5625 case 0x01: //equal
5626 if (&L)
5627 __ beq(op1_reg, op2_reg, L);
5628 else
5629 __ beq(op1_reg, op2_reg, (int)0);
5630 break;
5631 case 0x02: //not_equal
5632 if (&L)
5633 __ bne(op1_reg, op2_reg, L);
5634 else
5635 __ bne(op1_reg, op2_reg, (int)0);
5636 break;
5637 case 0x03: //above
5638 __ sltu(AT, op2_reg, op1_reg);
5639 if(&L)
5640 __ bne(R0, AT, L);
5641 else
5642 __ bne(R0, AT, (int)0);
5643 break;
5644 case 0x04: //above_equal
5645 __ sltu(AT, op1_reg, op2_reg);
5646 if(&L)
5647 __ beq(AT, R0, L);
5648 else
5649 __ beq(AT, R0, (int)0);
5650 break;
5651 case 0x05: //below
5652 __ sltu(AT, op1_reg, op2_reg);
5653 if(&L)
5654 __ bne(R0, AT, L);
5655 else
5656 __ bne(R0, AT, (int)0);
5657 break;
5658 case 0x06: //below_equal
5659 __ sltu(AT, op2_reg, op1_reg);
5660 if(&L)
5661 __ beq(AT, R0, L);
5662 else
5663 __ beq(AT, R0, (int)0);
5664 break;
5665 default:
5666 Unimplemented();
5667 }
5668 __ nop();
5669 %}
5670 ins_pc_relative(1);
5671 ins_pipe( pipe_alu_branch );
5672 %}
5674 instruct branchConIU_reg_reg(cmpOpU cmp, mRegI src1, mRegI src2, label labl) %{
5675 match( If cmp (CmpU src1 src2) );
5676 effect(USE labl);
5677 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_reg" %}
5679 ins_encode %{
5680 Register op1 = $src1$$Register;
5681 Register op2 = $src2$$Register;
5682 Label &L = *($labl$$label);
5683 int flag = $cmp$$cmpcode;
5685 switch(flag)
5686 {
5687 case 0x01: //equal
5688 if (&L)
5689 __ beq(op1, op2, L);
5690 else
5691 __ beq(op1, op2, (int)0);
5692 break;
5693 case 0x02: //not_equal
5694 if (&L)
5695 __ bne(op1, op2, L);
5696 else
5697 __ bne(op1, op2, (int)0);
5698 break;
5699 case 0x03: //above
5700 __ sltu(AT, op2, op1);
5701 if(&L)
5702 __ bne(AT, R0, L);
5703 else
5704 __ bne(AT, R0, (int)0);
5705 break;
5706 case 0x04: //above_equal
5707 __ sltu(AT, op1, op2);
5708 if(&L)
5709 __ beq(AT, R0, L);
5710 else
5711 __ beq(AT, R0, (int)0);
5712 break;
5713 case 0x05: //below
5714 __ sltu(AT, op1, op2);
5715 if(&L)
5716 __ bne(AT, R0, L);
5717 else
5718 __ bne(AT, R0, (int)0);
5719 break;
5720 case 0x06: //below_equal
5721 __ sltu(AT, op2, op1);
5722 if(&L)
5723 __ beq(AT, R0, L);
5724 else
5725 __ beq(AT, R0, (int)0);
5726 break;
5727 default:
5728 Unimplemented();
5729 }
5730 __ nop();
5731 %}
5733 ins_pc_relative(1);
5734 ins_pipe( pipe_alu_branch );
5735 %}
5738 instruct branchConIU_reg_imm(cmpOpU cmp, mRegI src1, immI src2, label labl) %{
5739 match( If cmp (CmpU src1 src2) );
5740 effect(USE labl);
5741 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_imm" %}
5743 ins_encode %{
5744 Register op1 = $src1$$Register;
5745 int val = $src2$$constant;
5746 Label &L = *($labl$$label);
5747 int flag = $cmp$$cmpcode;
5749 __ move(AT, val);
5750 switch(flag)
5751 {
5752 case 0x01: //equal
5753 if (&L)
5754 __ beq(op1, AT, L);
5755 else
5756 __ beq(op1, AT, (int)0);
5757 break;
5758 case 0x02: //not_equal
5759 if (&L)
5760 __ bne(op1, AT, L);
5761 else
5762 __ bne(op1, AT, (int)0);
5763 break;
5764 case 0x03: //above
5765 __ sltu(AT, AT, op1);
5766 if(&L)
5767 __ bne(R0, AT, L);
5768 else
5769 __ bne(R0, AT, (int)0);
5770 break;
5771 case 0x04: //above_equal
5772 __ sltu(AT, op1, AT);
5773 if(&L)
5774 __ beq(AT, R0, L);
5775 else
5776 __ beq(AT, R0, (int)0);
5777 break;
5778 case 0x05: //below
5779 __ sltu(AT, op1, AT);
5780 if(&L)
5781 __ bne(R0, AT, L);
5782 else
5783 __ bne(R0, AT, (int)0);
5784 break;
5785 case 0x06: //below_equal
5786 __ sltu(AT, AT, op1);
5787 if(&L)
5788 __ beq(AT, R0, L);
5789 else
5790 __ beq(AT, R0, (int)0);
5791 break;
5792 default:
5793 Unimplemented();
5794 }
5795 __ nop();
5796 %}
5798 ins_pc_relative(1);
5799 ins_pipe( pipe_alu_branch );
5800 %}
5802 instruct branchConI_reg_reg(cmpOp cmp, mRegI src1, mRegI src2, label labl) %{
5803 match( If cmp (CmpI src1 src2) );
5804 effect(USE labl);
5805 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_reg" %}
5807 ins_encode %{
5808 Register op1 = $src1$$Register;
5809 Register op2 = $src2$$Register;
5810 Label &L = *($labl$$label);
5811 int flag = $cmp$$cmpcode;
5813 switch(flag)
5814 {
5815 case 0x01: //equal
5816 if (&L)
5817 __ beq(op1, op2, L);
5818 else
5819 __ beq(op1, op2, (int)0);
5820 break;
5821 case 0x02: //not_equal
5822 if (&L)
5823 __ bne(op1, op2, L);
5824 else
5825 __ bne(op1, op2, (int)0);
5826 break;
5827 case 0x03: //above
5828 __ slt(AT, op2, op1);
5829 if(&L)
5830 __ bne(R0, AT, L);
5831 else
5832 __ bne(R0, AT, (int)0);
5833 break;
5834 case 0x04: //above_equal
5835 __ slt(AT, op1, op2);
5836 if(&L)
5837 __ beq(AT, R0, L);
5838 else
5839 __ beq(AT, R0, (int)0);
5840 break;
5841 case 0x05: //below
5842 __ slt(AT, op1, op2);
5843 if(&L)
5844 __ bne(R0, AT, L);
5845 else
5846 __ bne(R0, AT, (int)0);
5847 break;
5848 case 0x06: //below_equal
5849 __ slt(AT, op2, op1);
5850 if(&L)
5851 __ beq(AT, R0, L);
5852 else
5853 __ beq(AT, R0, (int)0);
5854 break;
5855 default:
5856 Unimplemented();
5857 }
5858 __ nop();
5859 %}
5861 ins_pc_relative(1);
5862 ins_pipe( pipe_alu_branch );
5863 %}
5865 instruct branchConI_reg_imm0(cmpOp cmp, mRegI src1, immI0 src2, label labl) %{
5866 match( If cmp (CmpI src1 src2) );
5867 effect(USE labl);
5868 ins_cost(170);
5869 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm0" %}
5871 ins_encode %{
5872 Register op1 = $src1$$Register;
5873 // int val = $src2$$constant;
5874 Label &L = *($labl$$label);
5875 int flag = $cmp$$cmpcode;
5877 //__ move(AT, val);
5878 switch(flag)
5879 {
5880 case 0x01: //equal
5881 if (&L)
5882 __ beq(op1, R0, L);
5883 else
5884 __ beq(op1, R0, (int)0);
5885 break;
5886 case 0x02: //not_equal
5887 if (&L)
5888 __ bne(op1, R0, L);
5889 else
5890 __ bne(op1, R0, (int)0);
5891 break;
5892 case 0x03: //greater
5893 if(&L)
5894 __ bgtz(op1, L);
5895 else
5896 __ bgtz(op1, (int)0);
5897 break;
5898 case 0x04: //greater_equal
5899 if(&L)
5900 __ bgez(op1, L);
5901 else
5902 __ bgez(op1, (int)0);
5903 break;
5904 case 0x05: //less
5905 if(&L)
5906 __ bltz(op1, L);
5907 else
5908 __ bltz(op1, (int)0);
5909 break;
5910 case 0x06: //less_equal
5911 if(&L)
5912 __ blez(op1, L);
5913 else
5914 __ blez(op1, (int)0);
5915 break;
5916 default:
5917 Unimplemented();
5918 }
5919 __ nop();
5920 %}
5922 ins_pc_relative(1);
5923 ins_pipe( pipe_alu_branch );
5924 %}
5927 instruct branchConI_reg_imm(cmpOp cmp, mRegI src1, immI src2, label labl) %{
5928 match( If cmp (CmpI src1 src2) );
5929 effect(USE labl);
5930 ins_cost(200);
5931 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm" %}
5933 ins_encode %{
5934 Register op1 = $src1$$Register;
5935 int val = $src2$$constant;
5936 Label &L = *($labl$$label);
5937 int flag = $cmp$$cmpcode;
5939 __ move(AT, val);
5940 switch(flag)
5941 {
5942 case 0x01: //equal
5943 if (&L)
5944 __ beq(op1, AT, L);
5945 else
5946 __ beq(op1, AT, (int)0);
5947 break;
5948 case 0x02: //not_equal
5949 if (&L)
5950 __ bne(op1, AT, L);
5951 else
5952 __ bne(op1, AT, (int)0);
5953 break;
5954 case 0x03: //greater
5955 __ slt(AT, AT, op1);
5956 if(&L)
5957 __ bne(R0, AT, L);
5958 else
5959 __ bne(R0, AT, (int)0);
5960 break;
5961 case 0x04: //greater_equal
5962 __ slt(AT, op1, AT);
5963 if(&L)
5964 __ beq(AT, R0, L);
5965 else
5966 __ beq(AT, R0, (int)0);
5967 break;
5968 case 0x05: //less
5969 __ slt(AT, op1, AT);
5970 if(&L)
5971 __ bne(R0, AT, L);
5972 else
5973 __ bne(R0, AT, (int)0);
5974 break;
5975 case 0x06: //less_equal
5976 __ slt(AT, AT, op1);
5977 if(&L)
5978 __ beq(AT, R0, L);
5979 else
5980 __ beq(AT, R0, (int)0);
5981 break;
5982 default:
5983 Unimplemented();
5984 }
5985 __ nop();
5986 %}
5988 ins_pc_relative(1);
5989 ins_pipe( pipe_alu_branch );
5990 %}
5992 instruct branchConIU_reg_imm0(cmpOpU cmp, mRegI src1, immI0 zero, label labl) %{
5993 match( If cmp (CmpU src1 zero) );
5994 effect(USE labl);
5995 format %{ "BR$cmp $src1, zero, $labl #@branchConIU_reg_imm0" %}
5997 ins_encode %{
5998 Register op1 = $src1$$Register;
5999 Label &L = *($labl$$label);
6000 int flag = $cmp$$cmpcode;
6002 switch(flag)
6003 {
6004 case 0x01: //equal
6005 if (&L)
6006 __ beq(op1, R0, L);
6007 else
6008 __ beq(op1, R0, (int)0);
6009 break;
6010 case 0x02: //not_equal
6011 if (&L)
6012 __ bne(op1, R0, L);
6013 else
6014 __ bne(op1, R0, (int)0);
6015 break;
6016 case 0x03: //above
6017 if(&L)
6018 __ bne(R0, op1, L);
6019 else
6020 __ bne(R0, op1, (int)0);
6021 break;
6022 case 0x04: //above_equal
6023 if(&L)
6024 __ beq(R0, R0, L);
6025 else
6026 __ beq(R0, R0, (int)0);
6027 break;
6028 case 0x05: //below
6029 return;
6030 break;
6031 case 0x06: //below_equal
6032 if(&L)
6033 __ beq(op1, R0, L);
6034 else
6035 __ beq(op1, R0, (int)0);
6036 break;
6037 default:
6038 Unimplemented();
6039 }
6040 __ nop();
6041 %}
6043 ins_pc_relative(1);
6044 ins_pipe( pipe_alu_branch );
6045 %}
6048 instruct branchConIU_reg_immI16(cmpOpU cmp, mRegI src1, immI16 src2, label labl) %{
6049 match( If cmp (CmpU src1 src2) );
6050 effect(USE labl);
6051 ins_cost(180);
6052 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_immI16" %}
6054 ins_encode %{
6055 Register op1 = $src1$$Register;
6056 int val = $src2$$constant;
6057 Label &L = *($labl$$label);
6058 int flag = $cmp$$cmpcode;
6060 switch(flag)
6061 {
6062 case 0x01: //equal
6063 __ move(AT, val);
6064 if (&L)
6065 __ beq(op1, AT, L);
6066 else
6067 __ beq(op1, AT, (int)0);
6068 break;
6069 case 0x02: //not_equal
6070 __ move(AT, val);
6071 if (&L)
6072 __ bne(op1, AT, L);
6073 else
6074 __ bne(op1, AT, (int)0);
6075 break;
6076 case 0x03: //above
6077 __ move(AT, val);
6078 __ sltu(AT, AT, op1);
6079 if(&L)
6080 __ bne(R0, AT, L);
6081 else
6082 __ bne(R0, AT, (int)0);
6083 break;
6084 case 0x04: //above_equal
6085 __ sltiu(AT, op1, val);
6086 if(&L)
6087 __ beq(AT, R0, L);
6088 else
6089 __ beq(AT, R0, (int)0);
6090 break;
6091 case 0x05: //below
6092 __ sltiu(AT, op1, val);
6093 if(&L)
6094 __ bne(R0, AT, L);
6095 else
6096 __ bne(R0, AT, (int)0);
6097 break;
6098 case 0x06: //below_equal
6099 __ move(AT, val);
6100 __ sltu(AT, AT, op1);
6101 if(&L)
6102 __ beq(AT, R0, L);
6103 else
6104 __ beq(AT, R0, (int)0);
6105 break;
6106 default:
6107 Unimplemented();
6108 }
6109 __ nop();
6110 %}
6112 ins_pc_relative(1);
6113 ins_pipe( pipe_alu_branch );
6114 %}
6117 instruct branchConL_regL_regL(cmpOp cmp, mRegL src1, mRegL src2, label labl) %{
6118 match( If cmp (CmpL src1 src2) );
6119 effect(USE labl);
6120 format %{ "BR$cmp $src1, $src2, $labl #@branchConL_regL_regL" %}
6121 ins_cost(250);
6123 ins_encode %{
6124 Register opr1_reg = as_Register($src1$$reg);
6125 Register opr2_reg = as_Register($src2$$reg);
6127 Label &target = *($labl$$label);
6128 int flag = $cmp$$cmpcode;
6130 switch(flag)
6131 {
6132 case 0x01: //equal
6133 if (&target)
6134 __ beq(opr1_reg, opr2_reg, target);
6135 else
6136 __ beq(opr1_reg, opr2_reg, (int)0);
6137 __ delayed()->nop();
6138 break;
6140 case 0x02: //not_equal
6141 if(&target)
6142 __ bne(opr1_reg, opr2_reg, target);
6143 else
6144 __ bne(opr1_reg, opr2_reg, (int)0);
6145 __ delayed()->nop();
6146 break;
6148 case 0x03: //greater
6149 __ slt(AT, opr2_reg, opr1_reg);
6150 if(&target)
6151 __ bne(AT, R0, target);
6152 else
6153 __ bne(AT, R0, (int)0);
6154 __ delayed()->nop();
6155 break;
6157 case 0x04: //greater_equal
6158 __ slt(AT, opr1_reg, opr2_reg);
6159 if(&target)
6160 __ beq(AT, R0, target);
6161 else
6162 __ beq(AT, R0, (int)0);
6163 __ delayed()->nop();
6165 break;
6167 case 0x05: //less
6168 __ slt(AT, opr1_reg, opr2_reg);
6169 if(&target)
6170 __ bne(AT, R0, target);
6171 else
6172 __ bne(AT, R0, (int)0);
6173 __ delayed()->nop();
6175 break;
6177 case 0x06: //less_equal
6178 __ slt(AT, opr2_reg, opr1_reg);
6180 if(&target)
6181 __ beq(AT, R0, target);
6182 else
6183 __ beq(AT, R0, (int)0);
6184 __ delayed()->nop();
6186 break;
6188 default:
6189 Unimplemented();
6190 }
6191 %}
6194 ins_pc_relative(1);
6195 ins_pipe( pipe_alu_branch );
6196 %}
6198 instruct branchConI_reg_imm16_sub(cmpOp cmp, mRegI src1, immI16_sub src2, label labl) %{
6199 match( If cmp (CmpI src1 src2) );
6200 effect(USE labl);
6201 ins_cost(180);
6202 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm16_sub" %}
6204 ins_encode %{
6205 Register op1 = $src1$$Register;
6206 int val = $src2$$constant;
6207 Label &L = *($labl$$label);
6208 int flag = $cmp$$cmpcode;
6210 __ addiu32(AT, op1, -1 * val);
6211 switch(flag)
6212 {
6213 case 0x01: //equal
6214 if (&L)
6215 __ beq(R0, AT, L);
6216 else
6217 __ beq(R0, AT, (int)0);
6218 break;
6219 case 0x02: //not_equal
6220 if (&L)
6221 __ bne(R0, AT, L);
6222 else
6223 __ bne(R0, AT, (int)0);
6224 break;
6225 case 0x03: //greater
6226 if(&L)
6227 __ bgtz(AT, L);
6228 else
6229 __ bgtz(AT, (int)0);
6230 break;
6231 case 0x04: //greater_equal
6232 if(&L)
6233 __ bgez(AT, L);
6234 else
6235 __ bgez(AT, (int)0);
6236 break;
6237 case 0x05: //less
6238 if(&L)
6239 __ bltz(AT, L);
6240 else
6241 __ bltz(AT, (int)0);
6242 break;
6243 case 0x06: //less_equal
6244 if(&L)
6245 __ blez(AT, L);
6246 else
6247 __ blez(AT, (int)0);
6248 break;
6249 default:
6250 Unimplemented();
6251 }
6252 __ nop();
6253 %}
6255 ins_pc_relative(1);
6256 ins_pipe( pipe_alu_branch );
6257 %}
6259 instruct branchConL_regL_immL0(cmpOp cmp, mRegL src1, immL0 zero, label labl) %{
6260 match( If cmp (CmpL src1 zero) );
6261 effect(USE labl);
6262 format %{ "BR$cmp $src1, zero, $labl #@branchConL_regL_immL0" %}
6263 ins_cost(220);
6265 ins_encode %{
6266 Register opr1_reg = as_Register($src1$$reg);
6267 Label &target = *($labl$$label);
6268 int flag = $cmp$$cmpcode;
6270 switch(flag)
6271 {
6272 case 0x01: //equal
6273 if (&target)
6274 __ beq(opr1_reg, R0, target);
6275 else
6276 __ beq(opr1_reg, R0, int(0));
6277 break;
6279 case 0x02: //not_equal
6280 if(&target)
6281 __ bne(opr1_reg, R0, target);
6282 else
6283 __ bne(opr1_reg, R0, (int)0);
6284 break;
6286 case 0x03: //greater
6287 if(&target)
6288 __ bgtz(opr1_reg, target);
6289 else
6290 __ bgtz(opr1_reg, (int)0);
6291 break;
6293 case 0x04: //greater_equal
6294 if(&target)
6295 __ bgez(opr1_reg, target);
6296 else
6297 __ bgez(opr1_reg, (int)0);
6298 break;
6300 case 0x05: //less
6301 __ slt(AT, opr1_reg, R0);
6302 if(&target)
6303 __ bne(AT, R0, target);
6304 else
6305 __ bne(AT, R0, (int)0);
6306 break;
6308 case 0x06: //less_equal
6309 if (&target)
6310 __ blez(opr1_reg, target);
6311 else
6312 __ blez(opr1_reg, int(0));
6313 break;
6315 default:
6316 Unimplemented();
6317 }
6318 __ delayed()->nop();
6319 %}
6322 ins_pc_relative(1);
6323 ins_pipe( pipe_alu_branch );
6324 %}
6326 /*
6327 // Conditional Direct Branch
6328 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
6329 match(If cmp icc);
6330 effect(USE labl);
6332 size(8);
6333 ins_cost(BRANCH_COST);
6334 format %{ "BP$cmp $icc,$labl" %}
6335 // Prim = bits 24-22, Secnd = bits 31-30
6336 ins_encode( enc_bp( labl, cmp, icc ) );
6337 ins_pc_relative(1);
6338 ins_pipe(br_cc);
6339 %}
6340 */
6342 //FIXME
6343 instruct branchConF_reg_reg(cmpOp cmp, regF src1, regF src2, label labl) %{
6344 match( If cmp (CmpF src1 src2) );
6345 effect(USE labl);
6346 format %{ "BR$cmp $src1, $src2, $labl #@branchConF_reg_reg" %}
6348 ins_encode %{
6349 FloatRegister reg_op1 = $src1$$FloatRegister;
6350 FloatRegister reg_op2 = $src2$$FloatRegister;
6351 Label &L = *($labl$$label);
6352 int flag = $cmp$$cmpcode;
6354 switch(flag)
6355 {
6356 case 0x01: //equal
6357 __ c_eq_s(reg_op1, reg_op2);
6358 if (&L)
6359 __ bc1t(L);
6360 else
6361 __ bc1t((int)0);
6362 break;
6363 case 0x02: //not_equal
6364 __ c_ueq_s(reg_op1, reg_op2);
6365 if (&L)
6366 __ bc1f(L);
6367 else
6368 __ bc1f((int)0);
6369 break;
6370 case 0x03: //greater
6371 __ c_ule_s(reg_op1, reg_op2);
6372 if(&L)
6373 __ bc1f(L);
6374 else
6375 __ bc1f((int)0);
6376 break;
6377 case 0x04: //greater_equal
6378 __ c_ult_s(reg_op1, reg_op2);
6379 if(&L)
6380 __ bc1f(L);
6381 else
6382 __ bc1f((int)0);
6383 break;
6384 case 0x05: //less
6385 __ c_ult_s(reg_op1, reg_op2);
6386 if(&L)
6387 __ bc1t(L);
6388 else
6389 __ bc1t((int)0);
6390 break;
6391 case 0x06: //less_equal
6392 __ c_ule_s(reg_op1, reg_op2);
6393 if(&L)
6394 __ bc1t(L);
6395 else
6396 __ bc1t((int)0);
6397 break;
6398 default:
6399 Unimplemented();
6400 }
6401 __ nop();
6402 %}
6404 ins_pc_relative(1);
6405 ins_pipe(pipe_slow);
6406 %}
6408 instruct branchConD_reg_reg(cmpOp cmp, regD src1, regD src2, label labl) %{
6409 match( If cmp (CmpD src1 src2) );
6410 effect(USE labl);
6411 format %{ "BR$cmp $src1, $src2, $labl #@branchConD_reg_reg" %}
6413 ins_encode %{
6414 FloatRegister reg_op1 = $src1$$FloatRegister;
6415 FloatRegister reg_op2 = $src2$$FloatRegister;
6416 Label &L = *($labl$$label);
6417 int flag = $cmp$$cmpcode;
6419 switch(flag)
6420 {
6421 case 0x01: //equal
6422 __ c_eq_d(reg_op1, reg_op2);
6423 if (&L)
6424 __ bc1t(L);
6425 else
6426 __ bc1t((int)0);
6427 break;
6428 case 0x02: //not_equal
6429 //2016/4/19 aoqi: c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs.
6430 __ c_eq_d(reg_op1, reg_op2);
6431 if (&L)
6432 __ bc1f(L);
6433 else
6434 __ bc1f((int)0);
6435 break;
6436 case 0x03: //greater
6437 __ c_ule_d(reg_op1, reg_op2);
6438 if(&L)
6439 __ bc1f(L);
6440 else
6441 __ bc1f((int)0);
6442 break;
6443 case 0x04: //greater_equal
6444 __ c_ult_d(reg_op1, reg_op2);
6445 if(&L)
6446 __ bc1f(L);
6447 else
6448 __ bc1f((int)0);
6449 break;
6450 case 0x05: //less
6451 __ c_ult_d(reg_op1, reg_op2);
6452 if(&L)
6453 __ bc1t(L);
6454 else
6455 __ bc1t((int)0);
6456 break;
6457 case 0x06: //less_equal
6458 __ c_ule_d(reg_op1, reg_op2);
6459 if(&L)
6460 __ bc1t(L);
6461 else
6462 __ bc1t((int)0);
6463 break;
6464 default:
6465 Unimplemented();
6466 }
6467 __ nop();
6468 %}
6470 ins_pc_relative(1);
6471 ins_pipe(pipe_slow);
6472 %}
6475 // Call Runtime Instruction
6476 instruct CallRuntimeDirect(method meth) %{
6477 match(CallRuntime );
6478 effect(USE meth);
6480 ins_cost(300);
6481 format %{ "CALL,runtime #@CallRuntimeDirect" %}
6482 ins_encode( Java_To_Runtime( meth ) );
6483 ins_pipe( pipe_slow );
6484 ins_alignment(16);
6485 %}
6489 //------------------------MemBar Instructions-------------------------------
6490 //Memory barrier flavors
6492 instruct membar_acquire() %{
6493 match(MemBarAcquire);
6494 match(LoadFence);
6495 ins_cost(400);
6497 format %{ "MEMBAR-acquire" %}
6498 // ins_encode( enc_membar_acquire );
6499 ins_encode %{
6500 __ sync();
6501 %}
6502 ins_pipe(pipe_slow);
6503 %}
6505 instruct membar_acquire_lock() %{
6506 match(MemBarAcquireLock);
6507 ins_cost(400);
6508 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock just sync)" %}
6509 ins_encode %{
6510 __ sync();
6511 %}
6512 ins_pipe(pipe_slow);
6513 %}
6515 instruct membar_release() %{
6516 match(MemBarRelease);
6517 match(StoreFence);
6518 ins_cost(400);
6520 format %{ "MEMBAR-release" %}
6522 ins_encode %{
6523 __ sync();
6524 %}
6526 ins_pipe(pipe_slow);
6527 %}
6529 instruct membar_release_lock() %{
6530 match(MemBarReleaseLock);
6531 ins_cost(400);
6532 format %{ "MEMBAR-release (a FastiUnlock follows so just sync)" %}
6534 ins_encode %{
6535 __ sync();
6536 %}
6537 ins_pipe(pipe_slow);
6538 %}
6540 instruct membar_volatile() %{
6541 match(MemBarVolatile);
6542 ins_cost(400);
6544 format %{ "MEMBAR-volatile" %}
6545 /* ins_encode( enc_membar_volatile ); */
6546 ins_encode %{
6547 if( !os::is_MP() ) return; // Not needed on single CPU
6548 __ sync();
6550 %}
6551 ins_pipe(pipe_slow);
6552 %}
6554 instruct unnecessary_membar_volatile() %{
6555 match(MemBarVolatile);
6556 predicate(Matcher::post_store_load_barrier(n));
6557 ins_cost(400);
6558 format %{ "MEMBAR-volatile (unnecessary so just sync)" %}
6559 ins_encode %{
6560 __ sync();
6561 %}
6562 ins_pipe(pipe_slow);
6563 %}
6565 instruct membar_storestore() %{
6566 match(MemBarStoreStore);
6567 format %{ "MEMBAR-storestore (sync)" %}
6568 ins_encode %{
6569 __ sync();
6570 %}
6571 ins_cost(400);
6572 ins_pipe(pipe_slow);
6573 %}
6575 //----------Move Instructions--------------------------------------------------
6576 instruct castX2P(mRegP dst, mRegL src) %{
6577 match(Set dst (CastX2P src));
6578 format %{ "castX2P $dst, $src @ castX2P" %}
6579 ins_encode %{
6580 Register src = $src$$Register;
6581 Register dst = $dst$$Register;
6583 if(src != dst)
6584 __ move(dst, src);
6585 %}
6586 ins_cost(10);
6587 ins_pipe( ialu_regI_mov );
6588 %}
6590 instruct castP2X(mRegL dst, mRegP src ) %{
6591 match(Set dst (CastP2X src));
6593 format %{ "mov $dst, $src\t #@castP2X" %}
6594 ins_encode %{
6595 Register src = $src$$Register;
6596 Register dst = $dst$$Register;
6598 if(src != dst)
6599 __ move(dst, src);
6600 %}
6601 ins_pipe( ialu_regI_mov );
6602 %}
6604 instruct MoveF2I_reg_reg(mRegI dst, regF src) %{
6605 match(Set dst (MoveF2I src));
6606 effect(DEF dst, USE src);
6607 ins_cost(85);
6608 format %{ "MoveF2I $dst, $src @ MoveF2I_reg_reg" %}
6609 ins_encode %{
6610 Register dst = as_Register($dst$$reg);
6611 FloatRegister src = as_FloatRegister($src$$reg);
6613 __ mfc1(dst, src);
6614 %}
6615 ins_pipe( pipe_slow );
6616 %}
6618 instruct MoveI2F_reg_reg(regF dst, mRegI src) %{
6619 match(Set dst (MoveI2F src));
6620 effect(DEF dst, USE src);
6621 ins_cost(85);
6622 format %{ "MoveI2F $dst, $src @ MoveI2F_reg_reg" %}
6623 ins_encode %{
6624 Register src = as_Register($src$$reg);
6625 FloatRegister dst = as_FloatRegister($dst$$reg);
6627 __ mtc1(src, dst);
6628 %}
6629 ins_pipe( pipe_slow );
6630 %}
6632 instruct MoveD2L_reg_reg(mRegL dst, regD src) %{
6633 match(Set dst (MoveD2L src));
6634 effect(DEF dst, USE src);
6635 ins_cost(85);
6636 format %{ "MoveD2L $dst, $src @ MoveD2L_reg_reg" %}
6637 ins_encode %{
6638 Register dst = as_Register($dst$$reg);
6639 FloatRegister src = as_FloatRegister($src$$reg);
6641 __ dmfc1(dst, src);
6642 %}
6643 ins_pipe( pipe_slow );
6644 %}
6646 instruct MoveL2D_reg_reg(regD dst, mRegL src) %{
6647 match(Set dst (MoveL2D src));
6648 effect(DEF dst, USE src);
6649 ins_cost(85);
6650 format %{ "MoveL2D $dst, $src @ MoveL2D_reg_reg" %}
6651 ins_encode %{
6652 FloatRegister dst = as_FloatRegister($dst$$reg);
6653 Register src = as_Register($src$$reg);
6655 __ dmtc1(src, dst);
6656 %}
6657 ins_pipe( pipe_slow );
6658 %}
6660 //----------Conditional Move---------------------------------------------------
6661 // Conditional move
6662 instruct cmovI_cmpI_reg_reg(mRegI dst, mRegI src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
6663 match(Set dst (CMoveI (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
6664 ins_cost(80);
6665 format %{
6666 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpI_reg_reg\n"
6667 "\tCMOV $dst,$src \t @cmovI_cmpI_reg_reg"
6668 %}
6670 ins_encode %{
6671 Register op1 = $tmp1$$Register;
6672 Register op2 = $tmp2$$Register;
6673 Register dst = $dst$$Register;
6674 Register src = $src$$Register;
6675 int flag = $cop$$cmpcode;
6677 switch(flag)
6678 {
6679 case 0x01: //equal
6680 __ subu32(AT, op1, op2);
6681 __ movz(dst, src, AT);
6682 break;
6684 case 0x02: //not_equal
6685 __ subu32(AT, op1, op2);
6686 __ movn(dst, src, AT);
6687 break;
6689 case 0x03: //great
6690 __ slt(AT, op2, op1);
6691 __ movn(dst, src, AT);
6692 break;
6694 case 0x04: //great_equal
6695 __ slt(AT, op1, op2);
6696 __ movz(dst, src, AT);
6697 break;
6699 case 0x05: //less
6700 __ slt(AT, op1, op2);
6701 __ movn(dst, src, AT);
6702 break;
6704 case 0x06: //less_equal
6705 __ slt(AT, op2, op1);
6706 __ movz(dst, src, AT);
6707 break;
6709 default:
6710 Unimplemented();
6711 }
6712 %}
6714 ins_pipe( pipe_slow );
6715 %}
6717 instruct cmovI_cmpP_reg_reg(mRegI dst, mRegI src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
6718 match(Set dst (CMoveI (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
6719 ins_cost(80);
6720 format %{
6721 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpP_reg_reg\n\t"
6722 "CMOV $dst,$src\t @cmovI_cmpP_reg_reg"
6723 %}
6724 ins_encode %{
6725 Register op1 = $tmp1$$Register;
6726 Register op2 = $tmp2$$Register;
6727 Register dst = $dst$$Register;
6728 Register src = $src$$Register;
6729 int flag = $cop$$cmpcode;
6731 switch(flag)
6732 {
6733 case 0x01: //equal
6734 __ subu(AT, op1, op2);
6735 __ movz(dst, src, AT);
6736 break;
6738 case 0x02: //not_equal
6739 __ subu(AT, op1, op2);
6740 __ movn(dst, src, AT);
6741 break;
6743 case 0x03: //above
6744 __ sltu(AT, op2, op1);
6745 __ movn(dst, src, AT);
6746 break;
6748 case 0x04: //above_equal
6749 __ sltu(AT, op1, op2);
6750 __ movz(dst, src, AT);
6751 break;
6753 case 0x05: //below
6754 __ sltu(AT, op1, op2);
6755 __ movn(dst, src, AT);
6756 break;
6758 case 0x06: //below_equal
6759 __ sltu(AT, op2, op1);
6760 __ movz(dst, src, AT);
6761 break;
6763 default:
6764 Unimplemented();
6765 }
6766 %}
6768 ins_pipe( pipe_slow );
6769 %}
6771 instruct cmovI_cmpN_reg_reg(mRegI dst, mRegI src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
6772 match(Set dst (CMoveI (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
6773 ins_cost(80);
6774 format %{
6775 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpN_reg_reg\n\t"
6776 "CMOV $dst,$src\t @cmovI_cmpN_reg_reg"
6777 %}
6778 ins_encode %{
6779 Register op1 = $tmp1$$Register;
6780 Register op2 = $tmp2$$Register;
6781 Register dst = $dst$$Register;
6782 Register src = $src$$Register;
6783 int flag = $cop$$cmpcode;
6785 switch(flag)
6786 {
6787 case 0x01: //equal
6788 __ subu32(AT, op1, op2);
6789 __ movz(dst, src, AT);
6790 break;
6792 case 0x02: //not_equal
6793 __ subu32(AT, op1, op2);
6794 __ movn(dst, src, AT);
6795 break;
6797 case 0x03: //above
6798 __ sltu(AT, op2, op1);
6799 __ movn(dst, src, AT);
6800 break;
6802 case 0x04: //above_equal
6803 __ sltu(AT, op1, op2);
6804 __ movz(dst, src, AT);
6805 break;
6807 case 0x05: //below
6808 __ sltu(AT, op1, op2);
6809 __ movn(dst, src, AT);
6810 break;
6812 case 0x06: //below_equal
6813 __ sltu(AT, op2, op1);
6814 __ movz(dst, src, AT);
6815 break;
6817 default:
6818 Unimplemented();
6819 }
6820 %}
6822 ins_pipe( pipe_slow );
6823 %}
6825 instruct cmovP_cmpN_reg_reg(mRegP dst, mRegP src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
6826 match(Set dst (CMoveP (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
6827 ins_cost(80);
6828 format %{
6829 "CMPU$cop $tmp1,$tmp2\t @cmovP_cmpN_reg_reg\n\t"
6830 "CMOV $dst,$src\t @cmovP_cmpN_reg_reg"
6831 %}
6832 ins_encode %{
6833 Register op1 = $tmp1$$Register;
6834 Register op2 = $tmp2$$Register;
6835 Register dst = $dst$$Register;
6836 Register src = $src$$Register;
6837 int flag = $cop$$cmpcode;
6839 switch(flag)
6840 {
6841 case 0x01: //equal
6842 __ subu32(AT, op1, op2);
6843 __ movz(dst, src, AT);
6844 break;
6846 case 0x02: //not_equal
6847 __ subu32(AT, op1, op2);
6848 __ movn(dst, src, AT);
6849 break;
6851 case 0x03: //above
6852 __ sltu(AT, op2, op1);
6853 __ movn(dst, src, AT);
6854 break;
6856 case 0x04: //above_equal
6857 __ sltu(AT, op1, op2);
6858 __ movz(dst, src, AT);
6859 break;
6861 case 0x05: //below
6862 __ sltu(AT, op1, op2);
6863 __ movn(dst, src, AT);
6864 break;
6866 case 0x06: //below_equal
6867 __ sltu(AT, op2, op1);
6868 __ movz(dst, src, AT);
6869 break;
6871 default:
6872 Unimplemented();
6873 }
6874 %}
6876 ins_pipe( pipe_slow );
6877 %}
6879 instruct cmovN_cmpP_reg_reg(mRegN dst, mRegN src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
6880 match(Set dst (CMoveN (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
6881 ins_cost(80);
6882 format %{
6883 "CMPU$cop $tmp1,$tmp2\t @cmovN_cmpP_reg_reg\n\t"
6884 "CMOV $dst,$src\t @cmovN_cmpP_reg_reg"
6885 %}
6886 ins_encode %{
6887 Register op1 = $tmp1$$Register;
6888 Register op2 = $tmp2$$Register;
6889 Register dst = $dst$$Register;
6890 Register src = $src$$Register;
6891 int flag = $cop$$cmpcode;
6893 switch(flag)
6894 {
6895 case 0x01: //equal
6896 __ subu(AT, op1, op2);
6897 __ movz(dst, src, AT);
6898 break;
6900 case 0x02: //not_equal
6901 __ subu(AT, op1, op2);
6902 __ movn(dst, src, AT);
6903 break;
6905 case 0x03: //above
6906 __ sltu(AT, op2, op1);
6907 __ movn(dst, src, AT);
6908 break;
6910 case 0x04: //above_equal
6911 __ sltu(AT, op1, op2);
6912 __ movz(dst, src, AT);
6913 break;
6915 case 0x05: //below
6916 __ sltu(AT, op1, op2);
6917 __ movn(dst, src, AT);
6918 break;
6920 case 0x06: //below_equal
6921 __ sltu(AT, op2, op1);
6922 __ movz(dst, src, AT);
6923 break;
6925 default:
6926 Unimplemented();
6927 }
6928 %}
6930 ins_pipe( pipe_slow );
6931 %}
6933 instruct cmovP_cmpD_reg_reg(mRegP dst, mRegP src, regD tmp1, regD tmp2, cmpOp cop ) %{
6934 match(Set dst (CMoveP (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
6935 ins_cost(80);
6936 format %{
6937 "CMP$cop $tmp1, $tmp2\t @cmovP_cmpD_reg_reg\n"
6938 "\tCMOV $dst,$src \t @cmovP_cmpD_reg_reg"
6939 %}
6940 ins_encode %{
6941 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
6942 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
6943 Register dst = as_Register($dst$$reg);
6944 Register src = as_Register($src$$reg);
6946 int flag = $cop$$cmpcode;
6948 switch(flag)
6949 {
6950 case 0x01: //equal
6951 __ c_eq_d(reg_op1, reg_op2);
6952 __ movt(dst, src);
6953 break;
6954 case 0x02: //not_equal
6955 __ c_eq_d(reg_op1, reg_op2);
6956 __ movf(dst, src);
6957 break;
6958 case 0x03: //greater
6959 __ c_ole_d(reg_op1, reg_op2);
6960 __ movf(dst, src);
6961 break;
6962 case 0x04: //greater_equal
6963 __ c_olt_d(reg_op1, reg_op2);
6964 __ movf(dst, src);
6965 break;
6966 case 0x05: //less
6967 __ c_ult_d(reg_op1, reg_op2);
6968 __ movt(dst, src);
6969 break;
6970 case 0x06: //less_equal
6971 __ c_ule_d(reg_op1, reg_op2);
6972 __ movt(dst, src);
6973 break;
6974 default:
6975 Unimplemented();
6976 }
6977 %}
6979 ins_pipe( pipe_slow );
6980 %}
6983 instruct cmovN_cmpN_reg_reg(mRegN dst, mRegN src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
6984 match(Set dst (CMoveN (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
6985 ins_cost(80);
6986 format %{
6987 "CMPU$cop $tmp1,$tmp2\t @cmovN_cmpN_reg_reg\n\t"
6988 "CMOV $dst,$src\t @cmovN_cmpN_reg_reg"
6989 %}
6990 ins_encode %{
6991 Register op1 = $tmp1$$Register;
6992 Register op2 = $tmp2$$Register;
6993 Register dst = $dst$$Register;
6994 Register src = $src$$Register;
6995 int flag = $cop$$cmpcode;
6997 switch(flag)
6998 {
6999 case 0x01: //equal
7000 __ subu32(AT, op1, op2);
7001 __ movz(dst, src, AT);
7002 break;
7004 case 0x02: //not_equal
7005 __ subu32(AT, op1, op2);
7006 __ movn(dst, src, AT);
7007 break;
7009 case 0x03: //above
7010 __ sltu(AT, op2, op1);
7011 __ movn(dst, src, AT);
7012 break;
7014 case 0x04: //above_equal
7015 __ sltu(AT, op1, op2);
7016 __ movz(dst, src, AT);
7017 break;
7019 case 0x05: //below
7020 __ sltu(AT, op1, op2);
7021 __ movn(dst, src, AT);
7022 break;
7024 case 0x06: //below_equal
7025 __ sltu(AT, op2, op1);
7026 __ movz(dst, src, AT);
7027 break;
7029 default:
7030 Unimplemented();
7031 }
7032 %}
7034 ins_pipe( pipe_slow );
7035 %}
7038 instruct cmovI_cmpU_reg_reg(mRegI dst, mRegI src, mRegI tmp1, mRegI tmp2, cmpOpU cop ) %{
7039 match(Set dst (CMoveI (Binary cop (CmpU tmp1 tmp2)) (Binary dst src)));
7040 ins_cost(80);
7041 format %{
7042 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpU_reg_reg\n\t"
7043 "CMOV $dst,$src\t @cmovI_cmpU_reg_reg"
7044 %}
7045 ins_encode %{
7046 Register op1 = $tmp1$$Register;
7047 Register op2 = $tmp2$$Register;
7048 Register dst = $dst$$Register;
7049 Register src = $src$$Register;
7050 int flag = $cop$$cmpcode;
7052 switch(flag)
7053 {
7054 case 0x01: //equal
7055 __ subu(AT, op1, op2);
7056 __ movz(dst, src, AT);
7057 break;
7059 case 0x02: //not_equal
7060 __ subu(AT, op1, op2);
7061 __ movn(dst, src, AT);
7062 break;
7064 case 0x03: //above
7065 __ sltu(AT, op2, op1);
7066 __ movn(dst, src, AT);
7067 break;
7069 case 0x04: //above_equal
7070 __ sltu(AT, op1, op2);
7071 __ movz(dst, src, AT);
7072 break;
7074 case 0x05: //below
7075 __ sltu(AT, op1, op2);
7076 __ movn(dst, src, AT);
7077 break;
7079 case 0x06: //below_equal
7080 __ sltu(AT, op2, op1);
7081 __ movz(dst, src, AT);
7082 break;
7084 default:
7085 Unimplemented();
7086 }
7087 %}
7089 ins_pipe( pipe_slow );
7090 %}
7092 instruct cmovI_cmpL_reg_reg(mRegI dst, mRegI src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
7093 match(Set dst (CMoveI (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
7094 ins_cost(80);
7095 format %{
7096 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpL_reg_reg\n"
7097 "\tCMOV $dst,$src \t @cmovI_cmpL_reg_reg"
7098 %}
7099 ins_encode %{
7100 Register opr1 = as_Register($tmp1$$reg);
7101 Register opr2 = as_Register($tmp2$$reg);
7102 Register dst = $dst$$Register;
7103 Register src = $src$$Register;
7104 int flag = $cop$$cmpcode;
7106 switch(flag)
7107 {
7108 case 0x01: //equal
7109 __ subu(AT, opr1, opr2);
7110 __ movz(dst, src, AT);
7111 break;
7113 case 0x02: //not_equal
7114 __ subu(AT, opr1, opr2);
7115 __ movn(dst, src, AT);
7116 break;
7118 case 0x03: //greater
7119 __ slt(AT, opr2, opr1);
7120 __ movn(dst, src, AT);
7121 break;
7123 case 0x04: //greater_equal
7124 __ slt(AT, opr1, opr2);
7125 __ movz(dst, src, AT);
7126 break;
7128 case 0x05: //less
7129 __ slt(AT, opr1, opr2);
7130 __ movn(dst, src, AT);
7131 break;
7133 case 0x06: //less_equal
7134 __ slt(AT, opr2, opr1);
7135 __ movz(dst, src, AT);
7136 break;
7138 default:
7139 Unimplemented();
7140 }
7141 %}
7143 ins_pipe( pipe_slow );
7144 %}
7146 instruct cmovP_cmpL_reg_reg(mRegP dst, mRegP src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
7147 match(Set dst (CMoveP (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
7148 ins_cost(80);
7149 format %{
7150 "CMP$cop $tmp1, $tmp2\t @cmovP_cmpL_reg_reg\n"
7151 "\tCMOV $dst,$src \t @cmovP_cmpL_reg_reg"
7152 %}
7153 ins_encode %{
7154 Register opr1 = as_Register($tmp1$$reg);
7155 Register opr2 = as_Register($tmp2$$reg);
7156 Register dst = $dst$$Register;
7157 Register src = $src$$Register;
7158 int flag = $cop$$cmpcode;
7160 switch(flag)
7161 {
7162 case 0x01: //equal
7163 __ subu(AT, opr1, opr2);
7164 __ movz(dst, src, AT);
7165 break;
7167 case 0x02: //not_equal
7168 __ subu(AT, opr1, opr2);
7169 __ movn(dst, src, AT);
7170 break;
7172 case 0x03: //greater
7173 __ slt(AT, opr2, opr1);
7174 __ movn(dst, src, AT);
7175 break;
7177 case 0x04: //greater_equal
7178 __ slt(AT, opr1, opr2);
7179 __ movz(dst, src, AT);
7180 break;
7182 case 0x05: //less
7183 __ slt(AT, opr1, opr2);
7184 __ movn(dst, src, AT);
7185 break;
7187 case 0x06: //less_equal
7188 __ slt(AT, opr2, opr1);
7189 __ movz(dst, src, AT);
7190 break;
7192 default:
7193 Unimplemented();
7194 }
7195 %}
7197 ins_pipe( pipe_slow );
7198 %}
7200 instruct cmovI_cmpD_reg_reg(mRegI dst, mRegI src, regD tmp1, regD tmp2, cmpOp cop ) %{
7201 match(Set dst (CMoveI (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
7202 ins_cost(80);
7203 format %{
7204 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpD_reg_reg\n"
7205 "\tCMOV $dst,$src \t @cmovI_cmpD_reg_reg"
7206 %}
7207 ins_encode %{
7208 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
7209 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
7210 Register dst = as_Register($dst$$reg);
7211 Register src = as_Register($src$$reg);
7213 int flag = $cop$$cmpcode;
7215 switch(flag)
7216 {
7217 case 0x01: //equal
7218 __ c_eq_d(reg_op1, reg_op2);
7219 __ movt(dst, src);
7220 break;
7221 case 0x02: //not_equal
7222 //2016/4/19 aoqi: See instruct branchConD_reg_reg. The change in branchConD_reg_reg fixed a bug. It seems similar here, so I made thesame change.
7223 __ c_eq_d(reg_op1, reg_op2);
7224 __ movf(dst, src);
7225 break;
7226 case 0x03: //greater
7227 __ c_ole_d(reg_op1, reg_op2);
7228 __ movf(dst, src);
7229 break;
7230 case 0x04: //greater_equal
7231 __ c_olt_d(reg_op1, reg_op2);
7232 __ movf(dst, src);
7233 break;
7234 case 0x05: //less
7235 __ c_ult_d(reg_op1, reg_op2);
7236 __ movt(dst, src);
7237 break;
7238 case 0x06: //less_equal
7239 __ c_ule_d(reg_op1, reg_op2);
7240 __ movt(dst, src);
7241 break;
7242 default:
7243 Unimplemented();
7244 }
7245 %}
7247 ins_pipe( pipe_slow );
7248 %}
7251 instruct cmovP_cmpP_reg_reg(mRegP dst, mRegP src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
7252 match(Set dst (CMoveP (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
7253 ins_cost(80);
7254 format %{
7255 "CMPU$cop $tmp1,$tmp2\t @cmovP_cmpP_reg_reg\n\t"
7256 "CMOV $dst,$src\t @cmovP_cmpP_reg_reg"
7257 %}
7258 ins_encode %{
7259 Register op1 = $tmp1$$Register;
7260 Register op2 = $tmp2$$Register;
7261 Register dst = $dst$$Register;
7262 Register src = $src$$Register;
7263 int flag = $cop$$cmpcode;
7265 switch(flag)
7266 {
7267 case 0x01: //equal
7268 __ subu(AT, op1, op2);
7269 __ movz(dst, src, AT);
7270 break;
7272 case 0x02: //not_equal
7273 __ subu(AT, op1, op2);
7274 __ movn(dst, src, AT);
7275 break;
7277 case 0x03: //above
7278 __ sltu(AT, op2, op1);
7279 __ movn(dst, src, AT);
7280 break;
7282 case 0x04: //above_equal
7283 __ sltu(AT, op1, op2);
7284 __ movz(dst, src, AT);
7285 break;
7287 case 0x05: //below
7288 __ sltu(AT, op1, op2);
7289 __ movn(dst, src, AT);
7290 break;
7292 case 0x06: //below_equal
7293 __ sltu(AT, op2, op1);
7294 __ movz(dst, src, AT);
7295 break;
7297 default:
7298 Unimplemented();
7299 }
7300 %}
7302 ins_pipe( pipe_slow );
7303 %}
7305 instruct cmovP_cmpI_reg_reg(mRegP dst, mRegP src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
7306 match(Set dst (CMoveP (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
7307 ins_cost(80);
7308 format %{
7309 "CMP$cop $tmp1,$tmp2\t @cmovP_cmpI_reg_reg\n\t"
7310 "CMOV $dst,$src\t @cmovP_cmpI_reg_reg"
7311 %}
7312 ins_encode %{
7313 Register op1 = $tmp1$$Register;
7314 Register op2 = $tmp2$$Register;
7315 Register dst = $dst$$Register;
7316 Register src = $src$$Register;
7317 int flag = $cop$$cmpcode;
7319 switch(flag)
7320 {
7321 case 0x01: //equal
7322 __ subu32(AT, op1, op2);
7323 __ movz(dst, src, AT);
7324 break;
7326 case 0x02: //not_equal
7327 __ subu32(AT, op1, op2);
7328 __ movn(dst, src, AT);
7329 break;
7331 case 0x03: //above
7332 __ slt(AT, op2, op1);
7333 __ movn(dst, src, AT);
7334 break;
7336 case 0x04: //above_equal
7337 __ slt(AT, op1, op2);
7338 __ movz(dst, src, AT);
7339 break;
7341 case 0x05: //below
7342 __ slt(AT, op1, op2);
7343 __ movn(dst, src, AT);
7344 break;
7346 case 0x06: //below_equal
7347 __ slt(AT, op2, op1);
7348 __ movz(dst, src, AT);
7349 break;
7351 default:
7352 Unimplemented();
7353 }
7354 %}
7356 ins_pipe( pipe_slow );
7357 %}
7359 instruct cmovN_cmpI_reg_reg(mRegN dst, mRegN src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
7360 match(Set dst (CMoveN (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
7361 ins_cost(80);
7362 format %{
7363 "CMP$cop $tmp1,$tmp2\t @cmovN_cmpI_reg_reg\n\t"
7364 "CMOV $dst,$src\t @cmovN_cmpI_reg_reg"
7365 %}
7366 ins_encode %{
7367 Register op1 = $tmp1$$Register;
7368 Register op2 = $tmp2$$Register;
7369 Register dst = $dst$$Register;
7370 Register src = $src$$Register;
7371 int flag = $cop$$cmpcode;
7373 switch(flag)
7374 {
7375 case 0x01: //equal
7376 __ subu32(AT, op1, op2);
7377 __ movz(dst, src, AT);
7378 break;
7380 case 0x02: //not_equal
7381 __ subu32(AT, op1, op2);
7382 __ movn(dst, src, AT);
7383 break;
7385 case 0x03: //above
7386 __ slt(AT, op2, op1);
7387 __ movn(dst, src, AT);
7388 break;
7390 case 0x04: //above_equal
7391 __ slt(AT, op1, op2);
7392 __ movz(dst, src, AT);
7393 break;
7395 case 0x05: //below
7396 __ slt(AT, op1, op2);
7397 __ movn(dst, src, AT);
7398 break;
7400 case 0x06: //below_equal
7401 __ slt(AT, op2, op1);
7402 __ movz(dst, src, AT);
7403 break;
7405 default:
7406 Unimplemented();
7407 }
7408 %}
7410 ins_pipe( pipe_slow );
7411 %}
7414 instruct cmovL_cmpI_reg_reg(mRegL dst, mRegL src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
7415 match(Set dst (CMoveL (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
7416 ins_cost(80);
7417 format %{
7418 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpI_reg_reg\n"
7419 "\tCMOV $dst,$src \t @cmovL_cmpI_reg_reg"
7420 %}
7422 ins_encode %{
7423 Register op1 = $tmp1$$Register;
7424 Register op2 = $tmp2$$Register;
7425 Register dst = as_Register($dst$$reg);
7426 Register src = as_Register($src$$reg);
7427 int flag = $cop$$cmpcode;
7429 switch(flag)
7430 {
7431 case 0x01: //equal
7432 __ subu32(AT, op1, op2);
7433 __ movz(dst, src, AT);
7434 break;
7436 case 0x02: //not_equal
7437 __ subu32(AT, op1, op2);
7438 __ movn(dst, src, AT);
7439 break;
7441 case 0x03: //great
7442 __ slt(AT, op2, op1);
7443 __ movn(dst, src, AT);
7444 break;
7446 case 0x04: //great_equal
7447 __ slt(AT, op1, op2);
7448 __ movz(dst, src, AT);
7449 break;
7451 case 0x05: //less
7452 __ slt(AT, op1, op2);
7453 __ movn(dst, src, AT);
7454 break;
7456 case 0x06: //less_equal
7457 __ slt(AT, op2, op1);
7458 __ movz(dst, src, AT);
7459 break;
7461 default:
7462 Unimplemented();
7463 }
7464 %}
7466 ins_pipe( pipe_slow );
7467 %}
7469 instruct cmovL_cmpL_reg_reg(mRegL dst, mRegL src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
7470 match(Set dst (CMoveL (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
7471 ins_cost(80);
7472 format %{
7473 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpL_reg_reg\n"
7474 "\tCMOV $dst,$src \t @cmovL_cmpL_reg_reg"
7475 %}
7476 ins_encode %{
7477 Register opr1 = as_Register($tmp1$$reg);
7478 Register opr2 = as_Register($tmp2$$reg);
7479 Register dst = as_Register($dst$$reg);
7480 Register src = as_Register($src$$reg);
7481 int flag = $cop$$cmpcode;
7483 switch(flag)
7484 {
7485 case 0x01: //equal
7486 __ subu(AT, opr1, opr2);
7487 __ movz(dst, src, AT);
7488 break;
7490 case 0x02: //not_equal
7491 __ subu(AT, opr1, opr2);
7492 __ movn(dst, src, AT);
7493 break;
7495 case 0x03: //greater
7496 __ slt(AT, opr2, opr1);
7497 __ movn(dst, src, AT);
7498 break;
7500 case 0x04: //greater_equal
7501 __ slt(AT, opr1, opr2);
7502 __ movz(dst, src, AT);
7503 break;
7505 case 0x05: //less
7506 __ slt(AT, opr1, opr2);
7507 __ movn(dst, src, AT);
7508 break;
7510 case 0x06: //less_equal
7511 __ slt(AT, opr2, opr1);
7512 __ movz(dst, src, AT);
7513 break;
7515 default:
7516 Unimplemented();
7517 }
7518 %}
7520 ins_pipe( pipe_slow );
7521 %}
7523 instruct cmovL_cmpN_reg_reg(mRegL dst, mRegL src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
7524 match(Set dst (CMoveL (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
7525 ins_cost(80);
7526 format %{
7527 "CMPU$cop $tmp1,$tmp2\t @cmovL_cmpN_reg_reg\n\t"
7528 "CMOV $dst,$src\t @cmovL_cmpN_reg_reg"
7529 %}
7530 ins_encode %{
7531 Register op1 = $tmp1$$Register;
7532 Register op2 = $tmp2$$Register;
7533 Register dst = $dst$$Register;
7534 Register src = $src$$Register;
7535 int flag = $cop$$cmpcode;
7537 switch(flag)
7538 {
7539 case 0x01: //equal
7540 __ subu32(AT, op1, op2);
7541 __ movz(dst, src, AT);
7542 break;
7544 case 0x02: //not_equal
7545 __ subu32(AT, op1, op2);
7546 __ movn(dst, src, AT);
7547 break;
7549 case 0x03: //above
7550 __ sltu(AT, op2, op1);
7551 __ movn(dst, src, AT);
7552 break;
7554 case 0x04: //above_equal
7555 __ sltu(AT, op1, op2);
7556 __ movz(dst, src, AT);
7557 break;
7559 case 0x05: //below
7560 __ sltu(AT, op1, op2);
7561 __ movn(dst, src, AT);
7562 break;
7564 case 0x06: //below_equal
7565 __ sltu(AT, op2, op1);
7566 __ movz(dst, src, AT);
7567 break;
7569 default:
7570 Unimplemented();
7571 }
7572 %}
7574 ins_pipe( pipe_slow );
7575 %}
7578 instruct cmovL_cmpD_reg_reg(mRegL dst, mRegL src, regD tmp1, regD tmp2, cmpOp cop ) %{
7579 match(Set dst (CMoveL (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
7580 ins_cost(80);
7581 format %{
7582 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpD_reg_reg\n"
7583 "\tCMOV $dst,$src \t @cmovL_cmpD_reg_reg"
7584 %}
7585 ins_encode %{
7586 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
7587 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
7588 Register dst = as_Register($dst$$reg);
7589 Register src = as_Register($src$$reg);
7591 int flag = $cop$$cmpcode;
7593 switch(flag)
7594 {
7595 case 0x01: //equal
7596 __ c_eq_d(reg_op1, reg_op2);
7597 __ movt(dst, src);
7598 break;
7599 case 0x02: //not_equal
7600 __ c_eq_d(reg_op1, reg_op2);
7601 __ movf(dst, src);
7602 break;
7603 case 0x03: //greater
7604 __ c_ole_d(reg_op1, reg_op2);
7605 __ movf(dst, src);
7606 break;
7607 case 0x04: //greater_equal
7608 __ c_olt_d(reg_op1, reg_op2);
7609 __ movf(dst, src);
7610 break;
7611 case 0x05: //less
7612 __ c_ult_d(reg_op1, reg_op2);
7613 __ movt(dst, src);
7614 break;
7615 case 0x06: //less_equal
7616 __ c_ule_d(reg_op1, reg_op2);
7617 __ movt(dst, src);
7618 break;
7619 default:
7620 Unimplemented();
7621 }
7622 %}
7624 ins_pipe( pipe_slow );
7625 %}
7627 instruct cmovD_cmpD_reg_reg(regD dst, regD src, regD tmp1, regD tmp2, cmpOp cop ) %{
7628 match(Set dst (CMoveD (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
7629 ins_cost(200);
7630 format %{
7631 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpD_reg_reg\n"
7632 "\tCMOV $dst,$src \t @cmovD_cmpD_reg_reg"
7633 %}
7634 ins_encode %{
7635 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
7636 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
7637 FloatRegister dst = as_FloatRegister($dst$$reg);
7638 FloatRegister src = as_FloatRegister($src$$reg);
7640 int flag = $cop$$cmpcode;
7642 Label L;
7644 switch(flag)
7645 {
7646 case 0x01: //equal
7647 __ c_eq_d(reg_op1, reg_op2);
7648 __ bc1f(L);
7649 __ nop();
7650 __ mov_d(dst, src);
7651 __ bind(L);
7652 break;
7653 case 0x02: //not_equal
7654 //2016/4/19 aoqi: See instruct branchConD_reg_reg. The change in branchConD_reg_reg fixed a bug. It seems similar here, so I made thesame change.
7655 __ c_eq_d(reg_op1, reg_op2);
7656 __ bc1t(L);
7657 __ nop();
7658 __ mov_d(dst, src);
7659 __ bind(L);
7660 break;
7661 case 0x03: //greater
7662 __ c_ole_d(reg_op1, reg_op2);
7663 __ bc1t(L);
7664 __ nop();
7665 __ mov_d(dst, src);
7666 __ bind(L);
7667 break;
7668 case 0x04: //greater_equal
7669 __ c_olt_d(reg_op1, reg_op2);
7670 __ bc1t(L);
7671 __ nop();
7672 __ mov_d(dst, src);
7673 __ bind(L);
7674 break;
7675 case 0x05: //less
7676 __ c_ult_d(reg_op1, reg_op2);
7677 __ bc1f(L);
7678 __ nop();
7679 __ mov_d(dst, src);
7680 __ bind(L);
7681 break;
7682 case 0x06: //less_equal
7683 __ c_ule_d(reg_op1, reg_op2);
7684 __ bc1f(L);
7685 __ nop();
7686 __ mov_d(dst, src);
7687 __ bind(L);
7688 break;
7689 default:
7690 Unimplemented();
7691 }
7692 %}
7694 ins_pipe( pipe_slow );
7695 %}
7697 instruct cmovF_cmpI_reg_reg(regF dst, regF src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
7698 match(Set dst (CMoveF (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
7699 ins_cost(200);
7700 format %{
7701 "CMP$cop $tmp1, $tmp2\t @cmovF_cmpI_reg_reg\n"
7702 "\tCMOV $dst, $src \t @cmovF_cmpI_reg_reg"
7703 %}
7705 ins_encode %{
7706 Register op1 = $tmp1$$Register;
7707 Register op2 = $tmp2$$Register;
7708 FloatRegister dst = as_FloatRegister($dst$$reg);
7709 FloatRegister src = as_FloatRegister($src$$reg);
7710 int flag = $cop$$cmpcode;
7711 Label L;
7713 switch(flag)
7714 {
7715 case 0x01: //equal
7716 __ bne(op1, op2, L);
7717 __ nop();
7718 __ mov_s(dst, src);
7719 __ bind(L);
7720 break;
7721 case 0x02: //not_equal
7722 __ beq(op1, op2, L);
7723 __ nop();
7724 __ mov_s(dst, src);
7725 __ bind(L);
7726 break;
7727 case 0x03: //great
7728 __ slt(AT, op2, op1);
7729 __ beq(AT, R0, L);
7730 __ nop();
7731 __ mov_s(dst, src);
7732 __ bind(L);
7733 break;
7734 case 0x04: //great_equal
7735 __ slt(AT, op1, op2);
7736 __ bne(AT, R0, L);
7737 __ nop();
7738 __ mov_s(dst, src);
7739 __ bind(L);
7740 break;
7741 case 0x05: //less
7742 __ slt(AT, op1, op2);
7743 __ beq(AT, R0, L);
7744 __ nop();
7745 __ mov_s(dst, src);
7746 __ bind(L);
7747 break;
7748 case 0x06: //less_equal
7749 __ slt(AT, op2, op1);
7750 __ bne(AT, R0, L);
7751 __ nop();
7752 __ mov_s(dst, src);
7753 __ bind(L);
7754 break;
7755 default:
7756 Unimplemented();
7757 }
7758 %}
7760 ins_pipe( pipe_slow );
7761 %}
7763 instruct cmovD_cmpI_reg_reg(regD dst, regD src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
7764 match(Set dst (CMoveD (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
7765 ins_cost(200);
7766 format %{
7767 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpI_reg_reg\n"
7768 "\tCMOV $dst, $src \t @cmovD_cmpI_reg_reg"
7769 %}
7771 ins_encode %{
7772 Register op1 = $tmp1$$Register;
7773 Register op2 = $tmp2$$Register;
7774 FloatRegister dst = as_FloatRegister($dst$$reg);
7775 FloatRegister src = as_FloatRegister($src$$reg);
7776 int flag = $cop$$cmpcode;
7777 Label L;
7779 switch(flag)
7780 {
7781 case 0x01: //equal
7782 __ bne(op1, op2, L);
7783 __ nop();
7784 __ mov_d(dst, src);
7785 __ bind(L);
7786 break;
7787 case 0x02: //not_equal
7788 __ beq(op1, op2, L);
7789 __ nop();
7790 __ mov_d(dst, src);
7791 __ bind(L);
7792 break;
7793 case 0x03: //great
7794 __ slt(AT, op2, op1);
7795 __ beq(AT, R0, L);
7796 __ nop();
7797 __ mov_d(dst, src);
7798 __ bind(L);
7799 break;
7800 case 0x04: //great_equal
7801 __ slt(AT, op1, op2);
7802 __ bne(AT, R0, L);
7803 __ nop();
7804 __ mov_d(dst, src);
7805 __ bind(L);
7806 break;
7807 case 0x05: //less
7808 __ slt(AT, op1, op2);
7809 __ beq(AT, R0, L);
7810 __ nop();
7811 __ mov_d(dst, src);
7812 __ bind(L);
7813 break;
7814 case 0x06: //less_equal
7815 __ slt(AT, op2, op1);
7816 __ bne(AT, R0, L);
7817 __ nop();
7818 __ mov_d(dst, src);
7819 __ bind(L);
7820 break;
7821 default:
7822 Unimplemented();
7823 }
7824 %}
7826 ins_pipe( pipe_slow );
7827 %}
7829 instruct cmovD_cmpP_reg_reg(regD dst, regD src, mRegP tmp1, mRegP tmp2, cmpOp cop ) %{
7830 match(Set dst (CMoveD (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
7831 ins_cost(200);
7832 format %{
7833 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpP_reg_reg\n"
7834 "\tCMOV $dst, $src \t @cmovD_cmpP_reg_reg"
7835 %}
7837 ins_encode %{
7838 Register op1 = $tmp1$$Register;
7839 Register op2 = $tmp2$$Register;
7840 FloatRegister dst = as_FloatRegister($dst$$reg);
7841 FloatRegister src = as_FloatRegister($src$$reg);
7842 int flag = $cop$$cmpcode;
7843 Label L;
7845 switch(flag)
7846 {
7847 case 0x01: //equal
7848 __ bne(op1, op2, L);
7849 __ nop();
7850 __ mov_d(dst, src);
7851 __ bind(L);
7852 break;
7853 case 0x02: //not_equal
7854 __ beq(op1, op2, L);
7855 __ nop();
7856 __ mov_d(dst, src);
7857 __ bind(L);
7858 break;
7859 case 0x03: //great
7860 __ slt(AT, op2, op1);
7861 __ beq(AT, R0, L);
7862 __ nop();
7863 __ mov_d(dst, src);
7864 __ bind(L);
7865 break;
7866 case 0x04: //great_equal
7867 __ slt(AT, op1, op2);
7868 __ bne(AT, R0, L);
7869 __ nop();
7870 __ mov_d(dst, src);
7871 __ bind(L);
7872 break;
7873 case 0x05: //less
7874 __ slt(AT, op1, op2);
7875 __ beq(AT, R0, L);
7876 __ nop();
7877 __ mov_d(dst, src);
7878 __ bind(L);
7879 break;
7880 case 0x06: //less_equal
7881 __ slt(AT, op2, op1);
7882 __ bne(AT, R0, L);
7883 __ nop();
7884 __ mov_d(dst, src);
7885 __ bind(L);
7886 break;
7887 default:
7888 Unimplemented();
7889 }
7890 %}
7892 ins_pipe( pipe_slow );
7893 %}
7895 //FIXME
7896 instruct cmovI_cmpF_reg_reg(mRegI dst, mRegI src, regF tmp1, regF tmp2, cmpOp cop ) %{
7897 match(Set dst (CMoveI (Binary cop (CmpF tmp1 tmp2)) (Binary dst src)));
7898 ins_cost(80);
7899 format %{
7900 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpF_reg_reg\n"
7901 "\tCMOV $dst,$src \t @cmovI_cmpF_reg_reg"
7902 %}
7904 ins_encode %{
7905 FloatRegister reg_op1 = $tmp1$$FloatRegister;
7906 FloatRegister reg_op2 = $tmp2$$FloatRegister;
7907 Register dst = $dst$$Register;
7908 Register src = $src$$Register;
7909 int flag = $cop$$cmpcode;
7911 switch(flag)
7912 {
7913 case 0x01: //equal
7914 __ c_ueq_s(reg_op1, reg_op2);
7915 __ movt(dst, src);
7916 break;
7917 case 0x02: //not_equal
7918 __ c_eq_s(reg_op1, reg_op2);
7919 __ movf(dst, src);
7920 break;
7921 case 0x03: //greater
7922 __ c_ole_s(reg_op1, reg_op2);
7923 __ movf(dst, src);
7924 break;
7925 case 0x04: //greater_equal
7926 __ c_olt_s(reg_op1, reg_op2);
7927 __ movf(dst, src);
7928 break;
7929 case 0x05: //less
7930 __ c_ult_s(reg_op1, reg_op2);
7931 __ movt(dst, src);
7932 break;
7933 case 0x06: //less_equal
7934 __ c_ule_s(reg_op1, reg_op2);
7935 __ movt(dst, src);
7936 break;
7937 default:
7938 Unimplemented();
7939 }
7940 %}
7941 ins_pipe( pipe_slow );
7942 %}
7944 instruct cmovF_cmpF_reg_reg(regF dst, regF src, regF tmp1, regF tmp2, cmpOp cop ) %{
7945 match(Set dst (CMoveF (Binary cop (CmpF tmp1 tmp2)) (Binary dst src)));
7946 ins_cost(200);
7947 format %{
7948 "CMP$cop $tmp1, $tmp2\t @cmovF_cmpF_reg_reg\n"
7949 "\tCMOV $dst,$src \t @cmovF_cmpF_reg_reg"
7950 %}
7952 ins_encode %{
7953 FloatRegister reg_op1 = $tmp1$$FloatRegister;
7954 FloatRegister reg_op2 = $tmp2$$FloatRegister;
7955 FloatRegister dst = $dst$$FloatRegister;
7956 FloatRegister src = $src$$FloatRegister;
7957 Label L;
7958 int flag = $cop$$cmpcode;
7960 switch(flag)
7961 {
7962 case 0x01: //equal
7963 __ c_ueq_s(reg_op1, reg_op2);
7964 __ bc1f(L);
7965 __ nop();
7966 __ mov_s(dst, src);
7967 __ bind(L);
7968 break;
7969 case 0x02: //not_equal
7970 __ c_eq_s(reg_op1, reg_op2);
7971 __ bc1t(L);
7972 __ nop();
7973 __ mov_s(dst, src);
7974 __ bind(L);
7975 break;
7976 case 0x03: //greater
7977 __ c_ole_s(reg_op1, reg_op2);
7978 __ bc1t(L);
7979 __ nop();
7980 __ mov_s(dst, src);
7981 __ bind(L);
7982 break;
7983 case 0x04: //greater_equal
7984 __ c_olt_s(reg_op1, reg_op2);
7985 __ bc1t(L);
7986 __ nop();
7987 __ mov_s(dst, src);
7988 __ bind(L);
7989 break;
7990 case 0x05: //less
7991 __ c_ult_s(reg_op1, reg_op2);
7992 __ bc1f(L);
7993 __ nop();
7994 __ mov_s(dst, src);
7995 __ bind(L);
7996 break;
7997 case 0x06: //less_equal
7998 __ c_ule_s(reg_op1, reg_op2);
7999 __ bc1f(L);
8000 __ nop();
8001 __ mov_s(dst, src);
8002 __ bind(L);
8003 break;
8004 default:
8005 Unimplemented();
8006 }
8007 %}
8008 ins_pipe( pipe_slow );
8009 %}
8011 // Manifest a CmpL result in an integer register. Very painful.
8012 // This is the test to avoid.
8013 instruct cmpL3_reg_reg(mRegI dst, mRegL src1, mRegL src2) %{
8014 match(Set dst (CmpL3 src1 src2));
8015 ins_cost(1000);
8016 format %{ "cmpL3 $dst, $src1, $src2 @ cmpL3_reg_reg" %}
8017 ins_encode %{
8018 Register opr1 = as_Register($src1$$reg);
8019 Register opr2 = as_Register($src2$$reg);
8020 Register dst = as_Register($dst$$reg);
8022 Label p_one, done;
8024 __ subu(dst, opr1, opr2);
8026 __ beq(dst, R0, done);
8027 __ nop();
8029 __ bgtz(dst, done);
8030 __ delayed()->addiu32(dst, R0, 1);
8032 __ addiu32(dst, R0, -1);
8034 __ bind(done);
8035 %}
8036 ins_pipe( pipe_slow );
8037 %}
8039 //
8040 // less_rsult = 1
8041 // greater_result = -1
8042 // equal_result = 0
8043 // nan_result = -1
8044 //
8045 instruct cmpF3_reg_reg(mRegI dst, regF src1, regF src2) %{
8046 match(Set dst (CmpF3 src1 src2));
8047 ins_cost(1000);
8048 format %{ "cmpF3 $dst, $src1, $src2 @ cmpF3_reg_reg" %}
8049 ins_encode %{
8050 FloatRegister src1 = as_FloatRegister($src1$$reg);
8051 FloatRegister src2 = as_FloatRegister($src2$$reg);
8052 Register dst = as_Register($dst$$reg);
8054 Label EQU, LESS, DONE;
8056 __ move(dst, -1);
8057 __ c_eq_s(src1, src2);
8058 __ bc1t(EQU);
8059 __ nop();
8060 __ c_olt_s(src1, src2);
8061 __ bc1t(LESS);
8062 __ nop();
8063 __ beq(R0, R0, DONE);
8064 __ nop();
8065 __ bind(EQU);
8066 __ move(dst, 0);
8067 __ beq(R0, R0, DONE);
8068 __ nop();
8069 __ bind(LESS);
8070 __ move(dst, 1);
8071 __ bind(DONE);
8072 %}
8073 ins_pipe( pipe_slow );
8074 %}
8076 instruct cmpD3_reg_reg(mRegI dst, regD src1, regD src2) %{
8077 match(Set dst (CmpD3 src1 src2));
8078 ins_cost(1000);
8079 format %{ "cmpD3 $dst, $src1, $src2 @ cmpD3_reg_reg" %}
8080 ins_encode %{
8081 FloatRegister src1 = as_FloatRegister($src1$$reg);
8082 FloatRegister src2 = as_FloatRegister($src2$$reg);
8083 Register dst = as_Register($dst$$reg);
8085 Label EQU, LESS, DONE;
8087 __ move(dst, -1);
8088 __ c_eq_d(src1, src2);
8089 __ bc1t(EQU);
8090 __ nop();
8091 __ c_olt_d(src1, src2);
8092 __ bc1t(LESS);
8093 __ nop();
8094 __ beq(R0, R0, DONE);
8095 __ nop();
8096 __ bind(EQU);
8097 __ move(dst, 0);
8098 __ beq(R0, R0, DONE);
8099 __ nop();
8100 __ bind(LESS);
8101 __ move(dst, 1);
8102 __ bind(DONE);
8103 %}
8104 ins_pipe( pipe_slow );
8105 %}
8107 instruct clear_array(mRegL cnt, mRegP base, Universe dummy) %{
8108 match(Set dummy (ClearArray cnt base));
8109 format %{ "CLEAR_ARRAY base = $base, cnt = $cnt # Clear doublewords" %}
8110 ins_encode %{
8111 //Assume cnt is the number of bytes in an array to be cleared,
8112 //and base points to the starting address of the array.
8113 Register base = $base$$Register;
8114 Register num = $cnt$$Register;
8115 Label Loop, done;
8117 /* 2012/9/21 Jin: according to X86, $cnt is caculated by doublewords(8 bytes) */
8118 __ move(T9, num); /* T9 = words */
8119 __ beq(T9, R0, done);
8120 __ nop();
8121 __ move(AT, base);
8123 __ bind(Loop);
8124 __ sd(R0, Address(AT, 0));
8125 __ daddi(AT, AT, wordSize);
8126 __ daddi(T9, T9, -1);
8127 __ bne(T9, R0, Loop);
8128 __ delayed()->nop();
8129 __ bind(done);
8130 %}
8131 ins_pipe( pipe_slow );
8132 %}
8134 instruct string_compare(mRegP str1, mRegI cnt1, mRegP str2, mRegI cnt2, mRegI result) %{
8135 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
8137 format %{ "String Compare $str1[len: $cnt1], $str2[len: $cnt2] -> $result @ string_compare" %}
8138 ins_encode %{
8139 // Get the first character position in both strings
8140 // [8] char array, [12] offset, [16] count
8141 Register str1 = $str1$$Register;
8142 Register str2 = $str2$$Register;
8143 Register cnt1 = $cnt1$$Register;
8144 Register cnt2 = $cnt2$$Register;
8145 Register result = $result$$Register;
8147 Register tmp1 = T8;
8148 Register tmp2 = T9;
8149 Register tmp3 = S7;
8151 Label L, Loop, haveResult, LoopEnd, done;
8153 /* 2013/7/9 Jin: StrComp is totally redefined in OpenJDK 8 */
8155 // Let tmp1 point to the first character of str1 (if str1 is not empty).
8156 __ move(tmp1, str1);
8158 // Let tmp2 point to the first character of str2 (if str2 is not empty).
8159 __ move(tmp2, str2);
8161 // compute the shorter length (in tmp3) and difference of lengths (in result)
8162 __ move(tmp3, cnt1);
8163 __ slt(AT, cnt1, cnt2);
8164 __ bne(AT, R0, L);
8165 __ nop();
8166 __ move(tmp3, cnt2); //Now the shorter length is in tmp3.
8167 __ bind(L);
8169 if ($str1$$Register != $result$$Register) __ push(str1);
8170 __ subu(result, cnt1, cnt2);
8171 __ push(result); // result holds the difference of two lengths
8173 //Begin to compare str1 and str2.
8174 __ bind(Loop);
8175 __ beq(tmp3, R0, LoopEnd);
8176 __ nop();
8178 // compare current character
8179 __ lhu(AT, tmp1, 0);
8180 __ lhu(str1, tmp2, 0);
8181 __ bne(AT, str1, haveResult);
8182 __ nop();
8183 __ addi(tmp1, tmp1, 2);
8184 __ addi(tmp2, tmp2, 2);
8185 __ b(Loop);
8186 __ delayed()->addi(tmp3, tmp3, -1);
8188 __ bind(LoopEnd);
8189 __ pop(result);
8190 __ beq(R0, R0, done);
8191 __ nop();
8193 __ bind(haveResult);
8194 __ subu(result, AT, str1);
8195 __ pop(AT);
8197 __ bind(done);
8198 if ($str1$$Register != $result$$Register) __ pop(str1);
8199 %}
8201 ins_pipe( pipe_slow );
8202 %}
8204 //----------Arithmetic Instructions-------------------------------------------
8205 //----------Addition Instructions---------------------------------------------
8206 instruct addI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
8207 match(Set dst (AddI src1 src2));
8209 format %{ "add $dst, $src1, $src2 #@addI_Reg_Reg" %}
8210 ins_encode %{
8211 Register dst = $dst$$Register;
8212 Register src1 = $src1$$Register;
8213 Register src2 = $src2$$Register;
8214 __ addu32(dst, src1, src2);
8215 %}
8216 ins_pipe( ialu_regI_regI );
8217 %}
8219 instruct addI_Reg_imm(mRegI dst, mRegI src1, immI src2) %{
8220 match(Set dst (AddI src1 src2));
8222 format %{ "add $dst, $src1, $src2 #@addI_Reg_imm" %}
8223 ins_encode %{
8224 Register dst = $dst$$Register;
8225 Register src1 = $src1$$Register;
8226 int imm = $src2$$constant;
8228 if(Assembler::is_simm16(imm)) {
8229 __ addiu32(dst, src1, imm);
8230 } else {
8231 __ move(AT, imm);
8232 __ addu32(dst, src1, AT);
8233 }
8234 %}
8235 ins_pipe( ialu_regI_regI );
8236 %}
8238 instruct addP_reg_reg(mRegP dst, mRegP src1, mRegL src2) %{
8239 match(Set dst (AddP src1 src2));
8241 format %{ "dadd $dst, $src1, $src2 #@addP_reg_reg" %}
8243 ins_encode %{
8244 Register dst = $dst$$Register;
8245 Register src1 = $src1$$Register;
8246 Register src2 = $src2$$Register;
8247 __ daddu(dst, src1, src2);
8248 %}
8250 ins_pipe( ialu_regI_regI );
8251 %}
8253 instruct addP_reg_imm(mRegP dst, mRegP src1, immL32 src2) %{
8254 match(Set dst (AddP src1 src2));
8255 // effect(KILL cr);
8257 format %{ "daddi $dst, $src1, $src2 #@addP_reg_imm" %}
8258 ins_encode %{
8259 Register src1 = $src1$$Register;
8260 long src2 = $src2$$constant;
8261 Register dst = $dst$$Register;
8263 if(Assembler::is_simm16(src2)) {
8264 __ daddiu(dst, src1, src2);
8265 } else {
8266 __ li(AT, src2);
8267 __ daddu(dst, src1, AT);
8268 }
8269 %}
8270 ins_pipe( ialu_regI_imm16 );
8271 %}
8273 // Add Long Register with Register
8274 instruct addL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
8275 match(Set dst (AddL src1 src2));
8276 ins_cost(200);
8277 format %{ "ADD $dst, $src1, $src2 #@addL_Reg_Reg\t" %}
8279 ins_encode %{
8280 Register dst_reg = as_Register($dst$$reg);
8281 Register src1_reg = as_Register($src1$$reg);
8282 Register src2_reg = as_Register($src2$$reg);
8284 __ daddu(dst_reg, src1_reg, src2_reg);
8285 %}
8287 ins_pipe( ialu_regL_regL );
8288 %}
8290 //----------Subtraction Instructions-------------------------------------------
8291 // Integer Subtraction Instructions
8292 instruct subI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
8293 match(Set dst (SubI src1 src2));
8295 format %{ "sub $dst, $src1, $src2 #@subI_Reg_Reg" %}
8296 ins_encode %{
8297 Register dst = $dst$$Register;
8298 Register src1 = $src1$$Register;
8299 Register src2 = $src2$$Register;
8300 __ subu32(dst, src1, src2);
8301 %}
8302 ins_pipe( ialu_regI_regI );
8303 %}
8305 instruct subI_Reg_imm(mRegI dst, mRegI src1, immI src2) %{
8306 match(Set dst (SubI src1 src2));
8308 format %{ "sub $dst, $src1, $src2 #@subI_Reg_imm" %}
8309 ins_encode %{
8310 Register dst = $dst$$Register;
8311 Register src1 = $src1$$Register;
8312 __ move(AT, -1 * $src2$$constant);
8313 __ addu32(dst, src1, AT);
8314 %}
8315 ins_pipe( ialu_regI_regI );
8316 %}
8318 // Subtract Long Register with Register.
8319 instruct subL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
8320 match(Set dst (SubL src1 src2));
8321 ins_cost(200);
8322 format %{ "SubL $dst, $src1, $src2 @ subL_Reg_Reg" %}
8323 ins_encode %{
8324 Register dst = as_Register($dst$$reg);
8325 Register src1 = as_Register($src1$$reg);
8326 Register src2 = as_Register($src2$$reg);
8328 __ subu(dst, src1, src2);
8329 %}
8330 ins_pipe( ialu_regL_regL );
8331 %}
8333 // Integer MOD with Register
8334 instruct modI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
8335 match(Set dst (ModI src1 src2));
8336 ins_cost(300);
8337 format %{ "modi $dst, $src1, $src2 @ modI_Reg_Reg" %}
8338 ins_encode %{
8339 Register dst = $dst$$Register;
8340 Register src1 = $src1$$Register;
8341 Register src2 = $src2$$Register;
8343 //if (UseLoongsonISA) {
8344 if (0) {
8345 // 2016.08.10
8346 // Experiments show that gsmod is slower that div+mfhi.
8347 // So I just disable it here.
8348 __ gsmod(dst, src1, src2);
8349 } else {
8350 __ div(src1, src2);
8351 __ mfhi(dst);
8352 }
8353 %}
8355 //ins_pipe( ialu_mod );
8356 ins_pipe( ialu_regI_regI );
8357 %}
8359 instruct modL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
8360 match(Set dst (ModL src1 src2));
8361 format %{ "modL $dst, $src1, $src2 @modL_reg_reg" %}
8363 ins_encode %{
8364 Register dst = as_Register($dst$$reg);
8365 Register op1 = as_Register($src1$$reg);
8366 Register op2 = as_Register($src2$$reg);
8368 if (UseLoongsonISA) {
8369 __ gsdmod(dst, op1, op2);
8370 } else {
8371 __ ddiv(op1, op2);
8372 __ mfhi(dst);
8373 }
8374 %}
8375 ins_pipe( pipe_slow );
8376 %}
8378 instruct mulI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
8379 match(Set dst (MulI src1 src2));
8381 ins_cost(300);
8382 format %{ "mul $dst, $src1, $src2 @ mulI_Reg_Reg" %}
8383 ins_encode %{
8384 Register src1 = $src1$$Register;
8385 Register src2 = $src2$$Register;
8386 Register dst = $dst$$Register;
8388 __ mul(dst, src1, src2);
8389 %}
8390 ins_pipe( ialu_mult );
8391 %}
8393 instruct maddI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2, mRegI src3) %{
8394 match(Set dst (AddI (MulI src1 src2) src3));
8396 ins_cost(999);
8397 format %{ "madd $dst, $src1 * $src2 + $src3 #@maddI_Reg_Reg" %}
8398 ins_encode %{
8399 Register src1 = $src1$$Register;
8400 Register src2 = $src2$$Register;
8401 Register src3 = $src3$$Register;
8402 Register dst = $dst$$Register;
8404 __ mtlo(src3);
8405 __ madd(src1, src2);
8406 __ mflo(dst);
8407 %}
8408 ins_pipe( ialu_mult );
8409 %}
8411 instruct divI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
8412 match(Set dst (DivI src1 src2));
8414 ins_cost(300);
8415 format %{ "div $dst, $src1, $src2 @ divI_Reg_Reg" %}
8416 ins_encode %{
8417 Register src1 = $src1$$Register;
8418 Register src2 = $src2$$Register;
8419 Register dst = $dst$$Register;
8421 /* 2012/4/21 Jin: In MIPS, div does not cause exception.
8422 We must trap an exception manually. */
8423 __ teq(R0, src2, 0x7);
8425 if (UseLoongsonISA) {
8426 __ gsdiv(dst, src1, src2);
8427 } else {
8428 __ div(src1, src2);
8430 __ nop();
8431 __ nop();
8432 __ mflo(dst);
8433 }
8434 %}
8435 ins_pipe( ialu_mod );
8436 %}
8438 instruct divF_Reg_Reg(regF dst, regF src1, regF src2) %{
8439 match(Set dst (DivF src1 src2));
8441 ins_cost(300);
8442 format %{ "divF $dst, $src1, $src2 @ divF_Reg_Reg" %}
8443 ins_encode %{
8444 FloatRegister src1 = $src1$$FloatRegister;
8445 FloatRegister src2 = $src2$$FloatRegister;
8446 FloatRegister dst = $dst$$FloatRegister;
8448 /* Here do we need to trap an exception manually ? */
8449 __ div_s(dst, src1, src2);
8450 %}
8451 ins_pipe( pipe_slow );
8452 %}
8454 instruct divD_Reg_Reg(regD dst, regD src1, regD src2) %{
8455 match(Set dst (DivD src1 src2));
8457 ins_cost(300);
8458 format %{ "divD $dst, $src1, $src2 @ divD_Reg_Reg" %}
8459 ins_encode %{
8460 FloatRegister src1 = $src1$$FloatRegister;
8461 FloatRegister src2 = $src2$$FloatRegister;
8462 FloatRegister dst = $dst$$FloatRegister;
8464 /* Here do we need to trap an exception manually ? */
8465 __ div_d(dst, src1, src2);
8466 %}
8467 ins_pipe( pipe_slow );
8468 %}
8470 instruct divF_Reg_immF(regF dst, regF src1, immF src2, regF tmp) %{
8471 match(Set dst (DivF src1 src2));
8472 effect(TEMP tmp);
8474 ins_cost(300);
8475 format %{ "divF $dst, $src1, $src2 [tmp = $tmp] @ divF_Reg_immF" %}
8476 ins_encode %{
8477 FloatRegister src1 = $src1$$FloatRegister;
8478 FloatRegister tmp = $tmp$$FloatRegister;
8479 FloatRegister dst = $dst$$FloatRegister;
8481 jfloat jf = $src2$$constant;
8482 address const_addr = __ float_constant(jf);
8483 assert (const_addr != NULL, "must create float constant in the constant table");
8485 __ relocate(relocInfo::internal_pc_type);
8486 __ li(AT, const_addr);
8487 __ lwc1(tmp, AT, 0);
8489 __ div_s(dst, src1, tmp);
8490 %}
8491 ins_pipe( pipe_slow );
8492 %}
8495 instruct mulL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
8496 match(Set dst (MulL src1 src2));
8497 format %{ "mulL $dst, $src1, $src2 @mulL_reg_reg" %}
8498 ins_encode %{
8499 Register dst = as_Register($dst$$reg);
8500 Register op1 = as_Register($src1$$reg);
8501 Register op2 = as_Register($src2$$reg);
8503 if (UseLoongsonISA) {
8504 __ gsdmult(dst, op1, op2);
8505 } else {
8506 __ dmult(op1, op2);
8507 __ mflo(dst);
8508 }
8509 %}
8510 ins_pipe( pipe_slow );
8511 %}
8513 instruct divL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
8514 match(Set dst (DivL src1 src2));
8515 format %{ "divL $dst, $src1, $src2 @divL_reg_reg" %}
8517 ins_encode %{
8518 Register dst = as_Register($dst$$reg);
8519 Register op1 = as_Register($src1$$reg);
8520 Register op2 = as_Register($src2$$reg);
8522 if (UseLoongsonISA) {
8523 __ gsddiv(dst, op1, op2);
8524 } else {
8525 __ ddiv(op1, op2);
8526 __ mflo(dst);
8527 }
8528 %}
8529 ins_pipe( pipe_slow );
8530 %}
8532 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8533 match(Set dst (AddF src1 src2));
8534 format %{ "AddF $dst, $src1, $src2 @addF_reg_reg" %}
8535 ins_encode %{
8536 FloatRegister src1 = as_FloatRegister($src1$$reg);
8537 FloatRegister src2 = as_FloatRegister($src2$$reg);
8538 FloatRegister dst = as_FloatRegister($dst$$reg);
8540 __ add_s(dst, src1, src2);
8541 %}
8542 ins_pipe( fpu_regF_regF );
8543 %}
8545 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8546 match(Set dst (SubF src1 src2));
8547 format %{ "SubF $dst, $src1, $src2 @subF_reg_reg" %}
8548 ins_encode %{
8549 FloatRegister src1 = as_FloatRegister($src1$$reg);
8550 FloatRegister src2 = as_FloatRegister($src2$$reg);
8551 FloatRegister dst = as_FloatRegister($dst$$reg);
8553 __ sub_s(dst, src1, src2);
8554 %}
8555 ins_pipe( fpu_regF_regF );
8556 %}
8557 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8558 match(Set dst (AddD src1 src2));
8559 format %{ "AddD $dst, $src1, $src2 @addD_reg_reg" %}
8560 ins_encode %{
8561 FloatRegister src1 = as_FloatRegister($src1$$reg);
8562 FloatRegister src2 = as_FloatRegister($src2$$reg);
8563 FloatRegister dst = as_FloatRegister($dst$$reg);
8565 __ add_d(dst, src1, src2);
8566 %}
8567 ins_pipe( fpu_regF_regF );
8568 %}
8570 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8571 match(Set dst (SubD src1 src2));
8572 format %{ "SubD $dst, $src1, $src2 @subD_reg_reg" %}
8573 ins_encode %{
8574 FloatRegister src1 = as_FloatRegister($src1$$reg);
8575 FloatRegister src2 = as_FloatRegister($src2$$reg);
8576 FloatRegister dst = as_FloatRegister($dst$$reg);
8578 __ sub_d(dst, src1, src2);
8579 %}
8580 ins_pipe( fpu_regF_regF );
8581 %}
8583 instruct negF_reg(regF dst, regF src) %{
8584 match(Set dst (NegF src));
8585 format %{ "negF $dst, $src @negF_reg" %}
8586 ins_encode %{
8587 FloatRegister src = as_FloatRegister($src$$reg);
8588 FloatRegister dst = as_FloatRegister($dst$$reg);
8590 __ neg_s(dst, src);
8591 %}
8592 ins_pipe( fpu_regF_regF );
8593 %}
8595 instruct negD_reg(regD dst, regD src) %{
8596 match(Set dst (NegD src));
8597 format %{ "negD $dst, $src @negD_reg" %}
8598 ins_encode %{
8599 FloatRegister src = as_FloatRegister($src$$reg);
8600 FloatRegister dst = as_FloatRegister($dst$$reg);
8602 __ neg_d(dst, src);
8603 %}
8604 ins_pipe( fpu_regF_regF );
8605 %}
8608 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8609 match(Set dst (MulF src1 src2));
8610 format %{ "MULF $dst, $src1, $src2 @mulF_reg_reg" %}
8611 ins_encode %{
8612 FloatRegister src1 = $src1$$FloatRegister;
8613 FloatRegister src2 = $src2$$FloatRegister;
8614 FloatRegister dst = $dst$$FloatRegister;
8616 __ mul_s(dst, src1, src2);
8617 %}
8618 ins_pipe( fpu_regF_regF );
8619 %}
8621 // Mul two double precision floating piont number
8622 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8623 match(Set dst (MulD src1 src2));
8624 format %{ "MULD $dst, $src1, $src2 @mulD_reg_reg" %}
8625 ins_encode %{
8626 FloatRegister src1 = $src1$$FloatRegister;
8627 FloatRegister src2 = $src2$$FloatRegister;
8628 FloatRegister dst = $dst$$FloatRegister;
8630 __ mul_d(dst, src1, src2);
8631 %}
8632 ins_pipe( fpu_regF_regF );
8633 %}
8635 instruct absF_reg(regF dst, regF src) %{
8636 match(Set dst (AbsF src));
8637 ins_cost(100);
8638 format %{ "absF $dst, $src @absF_reg" %}
8639 ins_encode %{
8640 FloatRegister src = as_FloatRegister($src$$reg);
8641 FloatRegister dst = as_FloatRegister($dst$$reg);
8643 __ abs_s(dst, src);
8644 %}
8645 ins_pipe( fpu_regF_regF );
8646 %}
8649 // intrinsics for math_native.
8650 // AbsD SqrtD CosD SinD TanD LogD Log10D
8652 instruct absD_reg(regD dst, regD src) %{
8653 match(Set dst (AbsD src));
8654 ins_cost(100);
8655 format %{ "absD $dst, $src @absD_reg" %}
8656 ins_encode %{
8657 FloatRegister src = as_FloatRegister($src$$reg);
8658 FloatRegister dst = as_FloatRegister($dst$$reg);
8660 __ abs_d(dst, src);
8661 %}
8662 ins_pipe( fpu_regF_regF );
8663 %}
8665 instruct sqrtD_reg(regD dst, regD src) %{
8666 match(Set dst (SqrtD src));
8667 ins_cost(100);
8668 format %{ "SqrtD $dst, $src @sqrtD_reg" %}
8669 ins_encode %{
8670 FloatRegister src = as_FloatRegister($src$$reg);
8671 FloatRegister dst = as_FloatRegister($dst$$reg);
8673 __ sqrt_d(dst, src);
8674 %}
8675 ins_pipe( fpu_regF_regF );
8676 %}
8678 //----------------------------------Logical Instructions----------------------
8679 //__________________________________Integer Logical Instructions-------------
8681 //And Instuctions
8682 // And Register with Immediate
8683 instruct andI_Reg_imm(mRegI dst, mRegI src1, immI src2) %{
8684 match(Set dst (AndI src1 src2));
8686 format %{ "and $dst, $src1, $src2 #@andI_Reg_imm" %}
8687 ins_encode %{
8688 Register dst = $dst$$Register;
8689 Register src = $src1$$Register;
8690 int val = $src2$$constant;
8692 __ move(AT, val);
8693 __ andr(dst, src, AT);
8694 %}
8695 ins_pipe( ialu_regI_regI );
8696 %}
8698 instruct andI_Reg_imm_0_65535(mRegI dst, mRegI src1, immI_0_65535 src2) %{
8699 match(Set dst (AndI src1 src2));
8700 ins_cost(60);
8702 format %{ "and $dst, $src1, $src2 #@andI_Reg_imm_0_65535" %}
8703 ins_encode %{
8704 Register dst = $dst$$Register;
8705 Register src = $src1$$Register;
8706 int val = $src2$$constant;
8708 __ andi(dst, src, val);
8709 %}
8710 ins_pipe( ialu_regI_regI );
8711 %}
8713 instruct andI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
8714 match(Set dst (AndI src1 src2));
8716 format %{ "and $dst, $src1, $src2 #@andI_Reg_Reg" %}
8717 ins_encode %{
8718 Register dst = $dst$$Register;
8719 Register src1 = $src1$$Register;
8720 Register src2 = $src2$$Register;
8721 __ andr(dst, src1, src2);
8722 %}
8723 ins_pipe( ialu_regI_regI );
8724 %}
8726 // And Long Register with Register
8727 instruct andL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
8728 match(Set dst (AndL src1 src2));
8729 format %{ "AND $dst, $src1, $src2 @ andL_Reg_Reg\n\t" %}
8730 ins_encode %{
8731 Register dst_reg = as_Register($dst$$reg);
8732 Register src1_reg = as_Register($src1$$reg);
8733 Register src2_reg = as_Register($src2$$reg);
8735 __ andr(dst_reg, src1_reg, src2_reg);
8736 %}
8737 ins_pipe( ialu_regL_regL );
8738 %}
8740 // Or Long Register with Register
8741 instruct orL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
8742 match(Set dst (OrL src1 src2));
8743 format %{ "OR $dst, $src1, $src2 @ orL_Reg_Reg\t" %}
8744 ins_encode %{
8745 Register dst_reg = $dst$$Register;
8746 Register src1_reg = $src1$$Register;
8747 Register src2_reg = $src2$$Register;
8749 __ orr(dst_reg, src1_reg, src2_reg);
8750 %}
8751 ins_pipe( ialu_regL_regL );
8752 %}
8754 // Xor Long Register with Register
8755 instruct xorL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
8756 match(Set dst (XorL src1 src2));
8757 format %{ "XOR $dst, $src1, $src2 @ xorL_Reg_Reg\t" %}
8758 ins_encode %{
8759 Register dst_reg = as_Register($dst$$reg);
8760 Register src1_reg = as_Register($src1$$reg);
8761 Register src2_reg = as_Register($src2$$reg);
8763 __ xorr(dst_reg, src1_reg, src2_reg);
8764 %}
8765 ins_pipe( ialu_regL_regL );
8766 %}
8768 // Shift Left by 8-bit immediate
8769 instruct salI_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
8770 match(Set dst (LShiftI src shift));
8772 format %{ "SHL $dst, $src, $shift #@salI_Reg_imm" %}
8773 ins_encode %{
8774 Register src = $src$$Register;
8775 Register dst = $dst$$Register;
8776 int shamt = $shift$$constant;
8778 /*
8779 094 SHL S0, S0, #-7 #@salI_Reg_imm
8780 static int insn_RRSO(int rt, int rd, int sa, int op) { return (rt<<16) | (rd<<11) | (sa<<6) | op; }
8781 void sll (Register rd, Register rt , int sa) {
8782 emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), sa, sll_op));
8783 }
8784 */
8786 if(0 <= shamt && shamt < 32) __ sll(dst, src, shamt);
8787 else {
8788 __ move(AT, shamt);
8789 __ sllv(dst, src, AT);
8790 }
8791 %}
8792 ins_pipe( ialu_regI_regI );
8793 %}
8795 // Shift Left by 8-bit immediate
8796 instruct salI_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
8797 match(Set dst (LShiftI src shift));
8799 format %{ "SHL $dst, $src, $shift #@salI_Reg_Reg" %}
8800 ins_encode %{
8801 Register src = $src$$Register;
8802 Register dst = $dst$$Register;
8803 Register shamt = $shift$$Register;
8804 __ sllv(dst, src, shamt);
8805 %}
8806 ins_pipe( ialu_regI_regI );
8807 %}
8810 // Shift Left Long
8811 instruct salL_Reg_imm(mRegL dst, mRegL src, immI8 shift) %{
8812 //predicate(UseNewLongLShift);
8813 match(Set dst (LShiftL src shift));
8814 ins_cost(100);
8815 format %{ "salL $dst, $src, $shift @ salL_Reg_imm" %}
8816 ins_encode %{
8817 Register src_reg = as_Register($src$$reg);
8818 Register dst_reg = as_Register($dst$$reg);
8819 int shamt = $shift$$constant;
8821 if (__ is_simm(shamt, 5))
8822 __ dsll(dst_reg, src_reg, shamt);
8823 else
8824 {
8825 __ move(AT, shamt);
8826 __ dsllv(dst_reg, src_reg, AT);
8827 }
8828 %}
8829 ins_pipe( ialu_regL_regL );
8830 %}
8833 // Shift Left Long
8834 instruct salL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
8835 //predicate(UseNewLongLShift);
8836 match(Set dst (LShiftL src shift));
8837 ins_cost(100);
8838 format %{ "salL $dst, $src, $shift @ salL_Reg_Reg" %}
8839 ins_encode %{
8840 Register creg = T9;
8841 Register src_reg = as_Register($src$$reg);
8842 Register dst_reg = as_Register($dst$$reg);
8844 __ move(creg, $shift$$Register);
8845 __ andi(creg, creg, 0x3f);
8846 __ dsllv(dst_reg, src_reg, creg);
8847 %}
8848 ins_pipe( ialu_regL_regL );
8849 %}
8851 // Shift Right Long
8852 instruct sarL_Reg_imm(mRegL dst, mRegL src, immI8 shift) %{
8853 //predicate(UseNewLongLShift);
8854 match(Set dst (RShiftL src shift));
8855 ins_cost(100);
8856 format %{ "sarL $dst, $src, $shift @ sarL_Reg_imm" %}
8857 ins_encode %{
8858 Register src_reg = as_Register($src$$reg);
8859 Register dst_reg = as_Register($dst$$reg);
8860 int shamt = ($shift$$constant & 0x3f);
8861 if (__ is_simm(shamt, 5))
8862 __ dsra(dst_reg, src_reg, shamt);
8863 else
8864 {
8865 __ move(AT, shamt);
8866 __ dsrav(dst_reg, src_reg, AT);
8867 }
8868 %}
8869 ins_pipe( ialu_regL_regL );
8870 %}
8872 // Shift Right Long arithmetically
8873 instruct sarL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
8874 //predicate(UseNewLongLShift);
8875 match(Set dst (RShiftL src shift));
8876 ins_cost(100);
8877 format %{ "sarL $dst, $src, $shift @ sarL_Reg_Reg" %}
8878 ins_encode %{
8879 Register creg = T9;
8880 Register src_reg = as_Register($src$$reg);
8881 Register dst_reg = as_Register($dst$$reg);
8883 __ move(creg, $shift$$Register);
8884 __ andi(creg, creg, 0x3f);
8885 __ dsrav(dst_reg, src_reg, creg);
8886 %}
8887 ins_pipe( ialu_regL_regL );
8888 %}
8890 // Shift Right Long logically
8891 instruct slrL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
8892 match(Set dst (URShiftL src shift));
8893 ins_cost(100);
8894 format %{ "slrL $dst, $src, $shift @ slrL_Reg_Reg" %}
8895 ins_encode %{
8896 Register creg = T9;
8897 Register src_reg = as_Register($src$$reg);
8898 Register dst_reg = as_Register($dst$$reg);
8899 Label normal, done, notZero;
8901 __ move(creg, $shift$$Register);
8902 __ andi(creg, creg, 0x3f);
8903 __ dsrlv(dst_reg, src_reg, creg);
8904 %}
8905 ins_pipe( ialu_regL_regL );
8906 %}
8909 // Xor Instructions
8910 // Xor Register with Register
8911 instruct xorI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
8912 match(Set dst (XorI src1 src2));
8914 format %{ "XOR $dst, $src1, $src2 #@xorI_Reg_Reg" %}
8916 ins_encode %{
8917 Register dst = $dst$$Register;
8918 Register src1 = $src1$$Register;
8919 Register src2 = $src2$$Register;
8920 __ xorr(dst, src1, src2);
8921 __ sll(dst, dst, 0); /* long -> int */
8922 %}
8924 ins_pipe( ialu_regI_regI );
8925 %}
8927 // Or Instructions
8928 // Or Register with Register
8929 instruct orI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
8930 match(Set dst (OrI src1 src2));
8932 format %{ "OR $dst, $src1, $src2 #@orI_Reg_Reg" %}
8933 ins_encode %{
8934 Register dst = $dst$$Register;
8935 Register src1 = $src1$$Register;
8936 Register src2 = $src2$$Register;
8937 __ orr(dst, src1, src2);
8938 %}
8940 ins_pipe( ialu_regI_regI );
8941 %}
8943 instruct orI_Reg_castP2X(mRegL dst, mRegL src1, mRegP src2) %{
8944 match(Set dst (OrI src1 (CastP2X src2)));
8946 format %{ "OR $dst, $src1, $src2 #@orI_Reg_castP2X" %}
8947 ins_encode %{
8948 Register dst = $dst$$Register;
8949 Register src1 = $src1$$Register;
8950 Register src2 = $src2$$Register;
8951 __ orr(dst, src1, src2);
8952 %}
8954 ins_pipe( ialu_regI_regI );
8955 %}
8957 // Logical Shift Right by 8-bit immediate
8958 instruct shr_logical_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
8959 match(Set dst (URShiftI src shift));
8960 // effect(KILL cr);
8962 format %{ "SRL $dst, $src, $shift #@shr_logical_Reg_imm" %}
8963 ins_encode %{
8964 Register src = $src$$Register;
8965 Register dst = $dst$$Register;
8966 int shift = $shift$$constant;
8967 if (shift > 0)
8968 __ srl(dst, src, shift);
8969 else
8970 {
8971 __ move(AT, shift);
8972 __ srlv(dst, src, AT);
8973 }
8974 %}
8975 ins_pipe( ialu_regI_regI );
8976 %}
8978 // Logical Shift Right
8979 instruct shr_logical_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
8980 match(Set dst (URShiftI src shift));
8982 format %{ "SRL $dst, $src, $shift #@shr_logical_Reg_Reg" %}
8983 ins_encode %{
8984 Register src = $src$$Register;
8985 Register dst = $dst$$Register;
8986 Register shift = $shift$$Register;
8987 __ srlv(dst, src, shift);
8988 %}
8989 ins_pipe( ialu_regI_regI );
8990 %}
8993 instruct shr_arith_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
8994 match(Set dst (RShiftI src shift));
8995 // effect(KILL cr);
8997 format %{ "SRA $dst, $src, $shift #@shr_arith_Reg_imm" %}
8998 ins_encode %{
8999 Register src = $src$$Register;
9000 Register dst = $dst$$Register;
9001 int shift = $shift$$constant;
9002 __ sra(dst, src, shift);
9003 %}
9004 ins_pipe( ialu_regI_regI );
9005 %}
9007 instruct shr_arith_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
9008 match(Set dst (RShiftI src shift));
9009 // effect(KILL cr);
9011 format %{ "SRA $dst, $src, $shift #@shr_arith_Reg_Reg" %}
9012 ins_encode %{
9013 Register src = $src$$Register;
9014 Register dst = $dst$$Register;
9015 Register shift = $shift$$Register;
9016 __ srav(dst, src, shift);
9017 %}
9018 ins_pipe( ialu_regI_regI );
9019 %}
9021 //----------Convert Int to Boolean---------------------------------------------
9023 instruct movI_nocopy(mRegI dst, mRegI src) %{
9024 effect( DEF dst, USE src );
9025 format %{ "MOV $dst, $src @ movI_nocopy" %}
9026 ins_encode %{
9027 Register dst = $dst$$Register;
9028 Register src = $src$$Register;
9029 __ move(dst, src);
9030 %}
9031 ins_pipe( ialu_regI_regI );
9032 %}
9034 instruct ci2b(mRegI dst, mRegI src) %{
9035 effect( USE_DEF dst, USE src );
9037 format %{ "NEG $dst @ ci2b\n\t"
9038 "ADC $dst,$src @ ci2b" %}
9039 ins_encode %{
9040 Register dst = $dst$$Register;
9041 Register src = $src$$Register;
9042 Label L;
9043 //If ( dst != 0 ) CF = 1;
9044 guarantee(dst != src, "in ci2b");
9045 __ move(AT, src);
9046 __ beq(dst, R0, L);
9047 __ nop();
9048 __ addiu(AT, AT, 1);
9049 __ bind(L);
9050 __ neg(dst);
9051 __ addu(dst, dst, AT);
9052 %}
9054 ins_pipe( ialu_regL_regL );
9055 %}
9058 instruct convI2B(mRegI dst, mRegI src) %{
9059 match(Set dst (Conv2B src));
9061 expand %{
9062 movI_nocopy(dst,src);
9063 ci2b(dst,src);
9064 %}
9065 %}
9067 instruct convI2L_reg( mRegL dst, mRegI src) %{
9068 match(Set dst (ConvI2L src));
9070 ins_cost(50);
9071 format %{ "SLL $dst, $src @ convI2L_reg\t" %}
9072 ins_encode %{
9073 Register dst = as_Register($dst$$reg);
9074 Register src = as_Register($src$$reg);
9076 if(dst != src) __ sll(dst, src, 0);
9077 %}
9078 ins_pipe( ialu_regL_regL );
9079 %}
9082 instruct convL2I_reg( mRegI dst, mRegL src ) %{
9083 match(Set dst (ConvL2I src));
9084 effect( DEF dst, USE src );
9085 format %{ "MOV $dst, $src @ convL2I_reg" %}
9086 ins_encode %{
9087 Register dst = as_Register($dst$$reg);
9088 Register src = as_Register($src$$reg);
9090 __ dsll32(dst, src, 0);
9091 __ dsra32(dst, dst, 0);
9092 %}
9094 ins_pipe( ialu_regI_regI );
9095 %}
9097 instruct convL2D_reg( regD dst, mRegL src ) %{
9098 match(Set dst (ConvL2D src));
9099 effect( DEF dst, USE src );
9100 format %{ "convL2D $dst, $src @ convL2D_reg" %}
9101 ins_encode %{
9102 Register src = as_Register($src$$reg);
9103 FloatRegister dst = as_FloatRegister($dst$$reg);
9105 __ dmtc1(src, dst);
9106 __ cvt_d_l(dst, dst);
9107 %}
9109 ins_pipe( pipe_slow );
9110 %}
9112 instruct convD2L_reg( mRegL dst, regD src ) %{
9113 match(Set dst (ConvD2L src));
9114 effect( DEF dst, USE src );
9115 format %{ "convD2L $dst, $src @ convD2L_reg" %}
9116 ins_encode %{
9117 Register dst = as_Register($dst$$reg);
9118 FloatRegister src = as_FloatRegister($src$$reg);
9120 Label L;
9122 __ c_un_d(src, src); //NaN?
9123 __ bc1t(L);
9124 __ delayed();
9125 __ move(dst, R0);
9127 __ trunc_l_d(F30, src);
9128 __ cfc1(AT, 31);
9129 __ li(T9, 0x10000);
9130 __ andr(AT, AT, T9);
9131 __ beq(AT, R0, L);
9132 __ delayed()->dmfc1(dst, F30);
9134 __ mov_d(F12, src);
9135 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2l), 1);
9136 __ move(dst, V0);
9137 __ bind(L);
9138 %}
9140 ins_pipe( pipe_slow );
9141 %}
9143 instruct convF2I_reg( mRegI dst, regF src ) %{
9144 match(Set dst (ConvF2I src));
9145 effect( DEF dst, USE src );
9146 format %{ "convf2i $dst, $src @ convF2I_reg" %}
9147 ins_encode %{
9148 Register dreg = $dst$$Register;
9149 FloatRegister fval = $src$$FloatRegister;
9150 Label L;
9152 __ c_un_s(fval, fval); //NaN?
9153 __ bc1t(L);
9154 __ delayed();
9155 __ move(dreg, R0);
9157 __ trunc_w_s(F30, fval);
9159 /* Call SharedRuntime:f2i() to do valid convention */
9160 __ cfc1(AT, 31);
9161 __ li(T9, 0x10000);
9162 __ andr(AT, AT, T9);
9163 __ beq(AT, R0, L);
9164 __ delayed()->mfc1(dreg, F30);
9166 __ mov_s(F12, fval);
9168 /* 2014/01/08 Fu : This bug was found when running ezDS's control-panel.
9169 * J 982 C2 javax.swing.text.BoxView.layoutMajorAxis(II[I[I)V (283 bytes) @ 0x000000555c46aa74
9170 *
9171 * An interger array index has been assigned to V0, and then changed from 1 to Integer.MAX_VALUE.
9172 * V0 is corrupted during call_VM_leaf(), and should be preserved.
9173 */
9174 if(dreg != V0) {
9175 __ push(V0);
9176 }
9177 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2i), 1);
9178 if(dreg != V0) {
9179 __ move(dreg, V0);
9180 __ pop(V0);
9181 }
9182 __ bind(L);
9183 %}
9185 ins_pipe( pipe_slow );
9186 %}
9188 instruct convF2L_reg( mRegL dst, regF src ) %{
9189 match(Set dst (ConvF2L src));
9190 effect( DEF dst, USE src );
9191 format %{ "convf2l $dst, $src @ convF2L_reg" %}
9192 ins_encode %{
9193 Register dst = as_Register($dst$$reg);
9194 FloatRegister fval = $src$$FloatRegister;
9195 Label L;
9197 __ c_un_s(fval, fval); //NaN?
9198 __ bc1t(L);
9199 __ delayed();
9200 __ move(dst, R0);
9202 __ trunc_l_s(F30, fval);
9203 __ cfc1(AT, 31);
9204 __ li(T9, 0x10000);
9205 __ andr(AT, AT, T9);
9206 __ beq(AT, R0, L);
9207 __ delayed()->dmfc1(dst, F30);
9209 __ mov_s(F12, fval);
9210 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2l), 1);
9211 __ move(dst, V0);
9212 __ bind(L);
9213 %}
9215 ins_pipe( pipe_slow );
9216 %}
9218 instruct convL2F_reg( regF dst, mRegL src ) %{
9219 match(Set dst (ConvL2F src));
9220 effect( DEF dst, USE src );
9221 format %{ "convl2f $dst, $src @ convL2F_reg" %}
9222 ins_encode %{
9223 FloatRegister dst = $dst$$FloatRegister;
9224 Register src = as_Register($src$$reg);
9225 Label L;
9227 __ dmtc1(src, dst);
9228 __ cvt_s_l(dst, dst);
9229 %}
9231 ins_pipe( pipe_slow );
9232 %}
9234 instruct convI2F_reg( regF dst, mRegI src ) %{
9235 match(Set dst (ConvI2F src));
9236 effect( DEF dst, USE src );
9237 format %{ "convi2f $dst, $src @ convI2F_reg" %}
9238 ins_encode %{
9239 Register src = $src$$Register;
9240 FloatRegister dst = $dst$$FloatRegister;
9242 __ mtc1(src, dst);
9243 __ cvt_s_w(dst, dst);
9244 %}
9246 ins_pipe( fpu_regF_regF );
9247 %}
9249 instruct cmpLTMask( mRegI dst, mRegI p, mRegI q ) %{
9250 match(Set dst (CmpLTMask p q));
9251 ins_cost(400);
9253 format %{ "cmpLTMask $dst, $p, $q @ cmpLTMask" %}
9254 ins_encode %{
9255 Register p = $p$$Register;
9256 Register q = $q$$Register;
9257 Register dst = $dst$$Register;
9259 __ slt(dst, p, q);
9260 __ subu(dst, R0, dst);
9261 %}
9262 ins_pipe( pipe_slow );
9263 %}
9265 instruct movP_nocopy(mRegI dst, mRegP src) %{
9266 effect( DEF dst, USE src );
9267 format %{ "MOV $dst,$src @ movP_nocopy" %}
9268 ins_encode %{
9269 Register dst = $dst$$Register;
9270 Register src = $src$$Register;
9271 __ addu(dst, src, R0);
9272 %}
9273 // ins_encode( enc_Copy( dst, src) );
9274 ins_pipe( ialu_regI_regI );
9275 %}
9277 //FIXME
9278 //instruct cp2b( mRegI dst, mRegP src, eFlagsReg cr ) %{
9279 instruct cp2b( mRegI dst, mRegP src ) %{
9280 effect( USE_DEF dst, USE src );
9281 format %{ "NEG $dst\n\t @cp2b"
9282 "ADC $dst,$src @cp2b" %}
9283 ins_encode %{
9284 Register dst = $dst$$Register;
9285 Register src = $src$$Register;
9286 Label L;
9287 //If ( dst != 0 ) CF = 1;
9288 __ move(AT, src);
9289 __ beq(dst, R0, L);
9290 __ nop();
9291 __ addiu(AT, AT, 1);
9292 __ bind(L);
9293 __ neg(dst);
9294 __ addu(dst, dst, AT);
9295 %}
9297 ins_pipe( ialu_regL_regL );
9298 %}
9300 instruct convP2B( mRegI dst, mRegP src ) %{
9301 match(Set dst (Conv2B src));
9303 expand %{
9304 movP_nocopy(dst,src);
9305 cp2b(dst,src);
9306 %}
9307 %}
9309 instruct convI2D_reg_reg(regD dst, mRegI src) %{
9310 match(Set dst (ConvI2D src));
9311 format %{ "conI2D $dst, $src @convI2D_reg" %}
9312 ins_encode %{
9313 Register src = $src$$Register;
9314 FloatRegister dst = $dst$$FloatRegister;
9315 __ mtc1(src, dst);
9316 __ cvt_d_w(dst, dst);
9317 %}
9318 ins_pipe( fpu_regF_regF );
9319 %}
9321 instruct convF2I_reg_reg(mRegI dst, regF src) %{
9322 match(Set dst (ConvF2I src));
9323 format %{ "convF2I $dst, $src\t# @convF2D_reg_reg" %}
9324 ins_encode %{
9325 FloatRegister dst = $dst$$FloatRegister;
9326 FloatRegister src = $src$$FloatRegister;
9328 __ cvt_d_s(dst, src);
9329 %}
9330 ins_pipe( fpu_regF_regF );
9331 %}
9333 instruct convF2D_reg_reg(regD dst, regF src) %{
9334 match(Set dst (ConvF2D src));
9335 format %{ "convF2D $dst, $src\t# @convF2D_reg_reg" %}
9336 ins_encode %{
9337 FloatRegister dst = $dst$$FloatRegister;
9338 FloatRegister src = $src$$FloatRegister;
9340 __ cvt_d_s(dst, src);
9341 %}
9342 ins_pipe( fpu_regF_regF );
9343 %}
9345 instruct convD2F_reg_reg(regF dst, regD src) %{
9346 match(Set dst (ConvD2F src));
9347 format %{ "convD2F $dst, $src\t# @convD2F_reg_reg" %}
9348 ins_encode %{
9349 FloatRegister dst = $dst$$FloatRegister;
9350 FloatRegister src = $src$$FloatRegister;
9352 __ cvt_s_d(dst, src);
9353 %}
9354 ins_pipe( fpu_regF_regF );
9355 %}
9357 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
9358 instruct convD2I_reg_reg( mRegI dst, regD src ) %{
9359 match(Set dst (ConvD2I src));
9360 // effect( KILL tmp, KILL cr );//after this instruction, it will release register tmp and cr
9362 format %{ "convD2I $dst, $src\t# @ convD2I_reg_reg \n\t" %}
9364 ins_encode %{
9365 FloatRegister src = $src$$FloatRegister;
9366 Register dst = $dst$$Register;
9367 Label L;
9369 __ trunc_w_d(F30, src);
9370 __ cfc1(AT, 31);
9371 __ li(T9, 0x10000);
9372 __ andr(AT, AT, T9);
9373 __ beq(AT, R0, L);
9374 __ delayed()->mfc1(dst, F30);
9376 __ mov_d(F12, src);
9377 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2i), 1);
9378 __ move(dst, V0);
9379 __ bind(L);
9381 %}
9382 ins_pipe( pipe_slow );
9383 %}
9385 // Convert oop pointer into compressed form
9386 instruct encodeHeapOop(mRegN dst, mRegP src, FlagsReg cr) %{
9387 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
9388 match(Set dst (EncodeP src));
9389 effect(KILL cr);
9390 format %{ "encode_heap_oop $dst,$src" %}
9391 ins_encode %{
9392 Register src = $src$$Register;
9393 Register dst = $dst$$Register;
9394 if (src != dst) {
9395 __ move(dst, src);
9396 }
9397 __ encode_heap_oop(dst);
9398 %}
9399 ins_pipe( ialu_regL_regL );
9400 %}
9402 instruct encodeHeapOop_not_null(mRegN dst, mRegP src, FlagsReg cr) %{
9403 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
9404 match(Set dst (EncodeP src));
9405 effect(KILL cr);
9406 format %{ "encode_heap_oop_not_null $dst,$src @ encodeHeapOop_not_null" %}
9407 ins_encode %{
9408 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
9409 %}
9410 ins_pipe( ialu_regL_regL );
9411 %}
9413 instruct decodeHeapOop(mRegP dst, mRegN src) %{
9414 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
9415 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
9416 match(Set dst (DecodeN src));
9417 format %{ "decode_heap_oop $dst,$src @ decodeHeapOop" %}
9418 ins_encode %{
9419 Register s = $src$$Register;
9420 Register d = $dst$$Register;
9421 if (s != d) {
9422 __ move(d, s);
9423 }
9424 __ decode_heap_oop(d);
9425 %}
9426 ins_pipe( ialu_regL_regL );
9427 %}
9429 instruct decodeHeapOop_not_null(mRegP dst, mRegN src) %{
9430 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
9431 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
9432 match(Set dst (DecodeN src));
9433 format %{ "decode_heap_oop_not_null $dst,$src @ decodeHeapOop_not_null" %}
9434 ins_encode %{
9435 Register s = $src$$Register;
9436 Register d = $dst$$Register;
9437 if (s != d) {
9438 __ decode_heap_oop_not_null(d, s);
9439 } else {
9440 __ decode_heap_oop_not_null(d);
9441 }
9442 %}
9443 ins_pipe( ialu_regL_regL );
9444 %}
9446 instruct encodeKlass_not_null(mRegN dst, mRegP src, FlagsReg cr) %{
9447 match(Set dst (EncodePKlass src));
9448 effect(KILL cr);
9449 format %{ "encode_heap_oop_not_null $dst,$src @ encodeKlass_not_null" %}
9450 ins_encode %{
9451 __ encode_klass_not_null($dst$$Register, $src$$Register);
9452 %}
9453 ins_pipe( ialu_regL_regL );
9454 %}
9456 instruct decodeKlass_not_null(mRegP dst, mRegN src, FlagsReg cr) %{
9457 match(Set dst (DecodeNKlass src));
9458 effect(KILL cr);
9459 format %{ "decode_heap_klass_not_null $dst,$src" %}
9460 ins_encode %{
9461 Register s = $src$$Register;
9462 Register d = $dst$$Register;
9463 if (s != d) {
9464 __ decode_klass_not_null(d, s);
9465 } else {
9466 __ decode_klass_not_null(d);
9467 }
9468 %}
9469 ins_pipe( ialu_regL_regL );
9470 %}
9472 //FIXME
9473 instruct tlsLoadP(mRegP dst) %{
9474 match(Set dst (ThreadLocal));
9476 ins_cost(0);
9477 format %{ " get_thread in $dst #@tlsLoadP" %}
9478 ins_encode %{
9479 Register dst = $dst$$Register;
9480 #ifdef OPT_THREAD
9481 __ move(dst, TREG);
9482 #else
9483 __ get_thread(dst);
9484 #endif
9485 %}
9487 ins_pipe( ialu_loadI );
9488 %}
9491 instruct checkCastPP( mRegP dst ) %{
9492 match(Set dst (CheckCastPP dst));
9494 format %{ "#checkcastPP of $dst (empty encoding) #@chekCastPP" %}
9495 ins_encode( /*empty encoding*/ );
9496 ins_pipe( empty );
9497 %}
9499 instruct castPP(mRegP dst)
9500 %{
9501 match(Set dst (CastPP dst));
9503 size(0);
9504 format %{ "# castPP of $dst" %}
9505 ins_encode(/* empty encoding */);
9506 ins_pipe(empty);
9507 %}
9509 instruct castII( mRegI dst ) %{
9510 match(Set dst (CastII dst));
9511 format %{ "#castII of $dst empty encoding" %}
9512 ins_encode( /*empty encoding*/ );
9513 ins_cost(0);
9514 ins_pipe( empty );
9515 %}
9517 // Return Instruction
9518 // Remove the return address & jump to it.
9519 instruct Ret() %{
9520 match(Return);
9521 format %{ "RET #@Ret" %}
9523 ins_encode %{
9524 __ jr(RA);
9525 __ nop();
9526 %}
9528 ins_pipe( pipe_jump );
9529 %}
9532 // Jump Direct - Label defines a relative address from JMP
9533 instruct jmpDir(label labl) %{
9534 match(Goto);
9535 effect(USE labl);
9537 ins_cost(300);
9538 format %{ "JMP $labl #@jmpDir" %}
9540 ins_encode %{
9541 Label &L = *($labl$$label);
9542 if(&L)
9543 __ b(L);
9544 else
9545 __ b(int(0));
9546 __ nop();
9547 %}
9549 ins_pipe( pipe_jump );
9550 ins_pc_relative(1);
9551 %}
9555 // Tail Jump; remove the return address; jump to target.
9556 // TailCall above leaves the return address around.
9557 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9558 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9559 // "restore" before this instruction (in Epilogue), we need to materialize it
9560 // in %i0.
9561 //FIXME
9562 instruct tailjmpInd(mRegP jump_target,mRegP ex_oop) %{
9563 match( TailJump jump_target ex_oop );
9564 ins_cost(200);
9565 format %{ "Jmp $jump_target ; ex_oop = $ex_oop #@tailjmpInd" %}
9566 ins_encode %{
9567 Register target = $jump_target$$Register;
9569 /* 2012/9/14 Jin: V0, V1 are indicated in:
9570 * [stubGenerator_mips.cpp] generate_forward_exception()
9571 * [runtime_mips.cpp] OptoRuntime::generate_exception_blob()
9572 */
9573 Register oop = $ex_oop$$Register;
9574 Register exception_oop = V0;
9575 Register exception_pc = V1;
9577 __ move(exception_pc, RA);
9578 __ move(exception_oop, oop);
9580 __ jr(target);
9581 __ nop();
9582 %}
9583 ins_pipe( pipe_jump );
9584 %}
9586 // ============================================================================
9587 // Procedure Call/Return Instructions
9588 // Call Java Static Instruction
9589 // Note: If this code changes, the corresponding ret_addr_offset() and
9590 // compute_padding() functions will have to be adjusted.
9591 instruct CallStaticJavaDirect(method meth) %{
9592 match(CallStaticJava);
9593 effect(USE meth);
9595 ins_cost(300);
9596 format %{ "CALL,static #@CallStaticJavaDirect " %}
9597 ins_encode( Java_Static_Call( meth ) );
9598 ins_pipe( pipe_slow );
9599 ins_pc_relative(1);
9600 ins_alignment(16);
9601 %}
9603 // Call Java Dynamic Instruction
9604 // Note: If this code changes, the corresponding ret_addr_offset() and
9605 // compute_padding() functions will have to be adjusted.
9606 instruct CallDynamicJavaDirect(method meth) %{
9607 match(CallDynamicJava);
9608 effect(USE meth);
9610 ins_cost(300);
9611 format %{"MOV IC_Klass, (oop)-1 @ CallDynamicJavaDirect\n\t"
9612 "CallDynamic @ CallDynamicJavaDirect" %}
9613 ins_encode( Java_Dynamic_Call( meth ) );
9614 ins_pipe( pipe_slow );
9615 ins_pc_relative(1);
9616 ins_alignment(16);
9617 %}
9619 instruct CallLeafNoFPDirect(method meth) %{
9620 match(CallLeafNoFP);
9621 effect(USE meth);
9623 ins_cost(300);
9624 format %{ "CALL_LEAF_NOFP,runtime " %}
9625 ins_encode(Java_To_Runtime(meth));
9626 ins_pipe( pipe_slow );
9627 ins_pc_relative(1);
9628 ins_alignment(16);
9629 %}
9632 instruct prefetchw0( memory mem ) %{
9633 // predicate(UseSSE==0 && !VM_Version::supports_3dnow());
9634 match(PrefetchWrite mem);
9635 format %{ "Prefetch (sync) #@prefetchw0" %}
9636 ins_encode %{
9637 __ sync();
9638 %}
9639 ins_pipe(pipe_slow);
9640 %}
9643 // Call runtime without safepoint
9644 instruct CallLeafDirect(method meth) %{
9645 match(CallLeaf);
9646 effect(USE meth);
9648 ins_cost(300);
9649 format %{ "CALL_LEAF,runtime #@CallLeafDirect " %}
9650 ins_encode(Java_To_Runtime(meth));
9651 ins_pipe( pipe_slow );
9652 ins_pc_relative(1);
9653 ins_alignment(16);
9654 %}
9656 // Load Char (16bit unsigned)
9657 instruct loadUS(mRegI dst, memory mem) %{
9658 match(Set dst (LoadUS mem));
9660 ins_cost(125);
9661 format %{ "loadUS $dst,$mem @ loadC" %}
9662 // opcode(0xB7, 0x0F);
9663 // ins_encode( OpcS, OpcP, RegMem(dst,mem));
9664 ins_encode(load_C_enc(dst, mem));
9665 ins_pipe( ialu_loadI );
9666 %}
9668 // Store Char (16bit unsigned)
9669 instruct storeC(memory mem, mRegI src) %{
9670 match(Set mem (StoreC mem src));
9672 ins_cost(125);
9673 format %{ "storeC $src,$mem @ storeC" %}
9674 ins_encode(store_C_reg_enc(mem, src));
9675 ins_pipe( ialu_loadI );
9676 %}
9679 instruct loadConF0(regF dst, immF0 zero) %{
9680 match(Set dst zero);
9681 ins_cost(100);
9683 format %{ "mov $dst, zero @ loadConF0\n"%}
9684 ins_encode %{
9685 FloatRegister dst = $dst$$FloatRegister;
9687 __ mtc1(R0, dst);
9688 %}
9689 ins_pipe( fpu_loadF );
9690 %}
9693 instruct loadConF(regF dst, immF src) %{
9694 match(Set dst src);
9695 ins_cost(125);
9697 format %{ "mov $dst, $src @ loadConF"%}
9698 ins_encode %{
9699 FloatRegister dst = $dst$$FloatRegister;
9700 jfloat jf = $src$$constant;
9701 address const_addr = __ float_constant(jf);
9702 assert (const_addr != NULL, "must create float constant in the constant table");
9704 __ relocate(relocInfo::internal_pc_type);
9705 __ li(AT, const_addr);
9706 __ lwc1(dst, AT, 0);
9707 %}
9708 ins_pipe( fpu_loadF );
9709 %}
9712 instruct loadConD0(regD dst, immD0 zero) %{
9713 match(Set dst zero);
9714 ins_cost(100);
9716 format %{ "mov $dst, zero @ loadConD0\n"%}
9717 ins_encode %{
9718 FloatRegister dst = as_FloatRegister($dst$$reg);
9720 __ dmtc1(R0, dst);
9721 %}
9722 ins_pipe( fpu_loadF );
9723 %}
9725 instruct loadConD(regD dst, immD src) %{
9726 match(Set dst src);
9727 ins_cost(125);
9729 format %{ "mov $dst, $src @ loadConD\n"%}
9730 ins_encode %{
9731 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
9733 jdouble jd = $src$$constant;
9734 address const_addr = __ double_constant(jd);
9735 assert (const_addr != NULL, "must create double constant in the constant table");
9737 __ relocate(relocInfo::internal_pc_type);
9738 __ li(AT, const_addr);
9739 __ ldc1(dst_reg, AT, 0);
9740 %}
9741 ins_pipe( fpu_loadF );
9742 %}
9744 // Store register Float value (it is faster than store from FPU register)
9745 instruct storeF_reg( memory mem, regF src) %{
9746 match(Set mem (StoreF mem src));
9748 ins_cost(50);
9749 format %{ "store $mem, $src\t# store float @ storeF_reg" %}
9750 ins_encode(store_F_reg_enc(mem, src));
9751 ins_pipe( fpu_storeF );
9752 %}
9755 // Store immediate Float value (it is faster than store from FPU register)
9756 // The instruction usage is guarded by predicate in operand immF().
9757 instruct storeF_imm( memory mem, immF src) %{
9758 match(Set mem (StoreF mem src));
9760 ins_cost(50);
9761 format %{ "store $mem, $src\t# store float @ storeF_imm" %}
9762 ins_encode %{
9763 jfloat jf = $src$$constant;
9764 int base = $mem$$base;
9765 int index = $mem$$index;
9766 int scale = $mem$$scale;
9767 int disp = $mem$$disp;
9768 address const_addr = __ float_constant(jf);
9769 assert (const_addr != NULL, "must create float constant in the constant table");
9771 __ relocate(relocInfo::internal_pc_type);
9772 __ li(AT, const_addr);
9773 __ lwc1(F30, AT, 0);
9775 if( scale != 0 ) Unimplemented();
9776 if( index != 0 ) {
9777 if( Assembler::is_simm16(disp) ) {
9778 __ addu(AT, as_Register(base), as_Register(index));
9779 __ swc1(F30, AT, disp);
9780 } else {
9781 __ addu(AT, as_Register(base), as_Register(index));
9782 __ move(T9, disp);
9783 __ addu(AT, AT, T9);
9784 __ swc1(F30, AT, 0);
9785 }
9787 } else {
9788 if( Assembler::is_simm16(disp) ) {
9789 __ swc1(F30, as_Register(base), disp);
9790 } else {
9791 __ move(T9, disp);
9792 __ addu(AT, as_Register(base), T9);
9793 __ swc1(F30, AT, 0);
9794 }
9795 }
9796 %}
9797 ins_pipe( ialu_storeI );
9798 %}
9800 instruct storeF_imm0( memory mem, immF0 zero) %{
9801 match(Set mem (StoreF mem zero));
9803 ins_cost(40);
9804 format %{ "store $mem, zero\t# store float @ storeF_imm0" %}
9805 ins_encode %{
9806 int base = $mem$$base;
9807 int index = $mem$$index;
9808 int scale = $mem$$scale;
9809 int disp = $mem$$disp;
9811 if( index != 0 ) {
9812 if(scale != 0) {
9813 __ dsll(T9, as_Register(index), scale);
9814 __ addu(AT, as_Register(base), T9);
9815 } else {
9816 __ daddu(AT, as_Register(base), as_Register(index));
9817 }
9818 if( Assembler::is_simm16(disp) ) {
9819 __ sw(R0, AT, disp);
9820 } else {
9821 __ move(T9, disp);
9822 __ addu(AT, AT, T9);
9823 __ sw(R0, AT, 0);
9824 }
9826 } else {
9827 if( Assembler::is_simm16(disp) ) {
9828 __ sw(R0, as_Register(base), disp);
9829 } else {
9830 __ move(T9, disp);
9831 __ addu(AT, as_Register(base), T9);
9832 __ sw(R0, AT, 0);
9833 }
9834 }
9835 %}
9836 ins_pipe( ialu_storeI );
9837 %}
9839 // Load Double
9840 instruct loadD(regD dst, memory mem) %{
9841 match(Set dst (LoadD mem));
9843 ins_cost(150);
9844 format %{ "loadD $dst, $mem #@loadD" %}
9845 ins_encode(load_D_enc(dst, mem));
9846 ins_pipe( ialu_loadI );
9847 %}
9849 // Load Double - UNaligned
9850 instruct loadD_unaligned(regD dst, memory mem ) %{
9851 match(Set dst (LoadD_unaligned mem));
9852 ins_cost(250);
9853 // FIXME: Jin: Need more effective ldl/ldr
9854 format %{ "loadD_unaligned $dst, $mem #@loadD_unaligned" %}
9855 ins_encode(load_D_enc(dst, mem));
9856 ins_pipe( ialu_loadI );
9857 %}
9859 instruct storeD_reg( memory mem, regD src) %{
9860 match(Set mem (StoreD mem src));
9862 ins_cost(50);
9863 format %{ "store $mem, $src\t# store float @ storeD_reg" %}
9864 ins_encode(store_D_reg_enc(mem, src));
9865 ins_pipe( fpu_storeF );
9866 %}
9868 instruct storeD_imm0( memory mem, immD0 zero) %{
9869 match(Set mem (StoreD mem zero));
9871 ins_cost(40);
9872 format %{ "store $mem, zero\t# store float @ storeD_imm0" %}
9873 ins_encode %{
9874 int base = $mem$$base;
9875 int index = $mem$$index;
9876 int scale = $mem$$scale;
9877 int disp = $mem$$disp;
9879 __ mtc1(R0, F30);
9880 __ cvt_d_w(F30, F30);
9882 if( index != 0 ) {
9883 if(scale != 0) {
9884 __ dsll(T9, as_Register(index), scale);
9885 __ addu(AT, as_Register(base), T9);
9886 } else {
9887 __ daddu(AT, as_Register(base), as_Register(index));
9888 }
9889 if( Assembler::is_simm16(disp) ) {
9890 __ sdc1(F30, AT, disp);
9891 } else {
9892 __ move(T9, disp);
9893 __ addu(AT, AT, T9);
9894 __ sdc1(F30, AT, 0);
9895 }
9897 } else {
9898 if( Assembler::is_simm16(disp) ) {
9899 __ sdc1(F30, as_Register(base), disp);
9900 } else {
9901 __ move(T9, disp);
9902 __ addu(AT, as_Register(base), T9);
9903 __ sdc1(F30, AT, 0);
9904 }
9905 }
9906 %}
9907 ins_pipe( ialu_storeI );
9908 %}
9910 instruct cmpFastLock( FlagsReg cr, mRegP object, mRegP box, mRegI tmp, mRegP scr) %{
9911 match( Set cr (FastLock object box) );
9912 effect( TEMP tmp, TEMP scr );
9913 ins_cost(300);
9914 format %{ "FASTLOCK $cr $object, $box, $tmp #@ cmpFastLock" %}
9915 ins_encode %{
9916 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, $scr$$Register);
9917 %}
9919 ins_pipe( pipe_slow );
9920 ins_pc_relative(1);
9921 %}
9923 instruct cmpFastUnlock( FlagsReg cr, mRegP object, mRegP box, mRegP tmp ) %{
9924 match( Set cr (FastUnlock object box) );
9925 effect( TEMP tmp );
9926 ins_cost(300);
9927 format %{ "FASTUNLOCK $object, $box, $tmp #@cmpFastUnlock" %}
9928 ins_encode %{
9929 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register);
9930 %}
9932 ins_pipe( pipe_slow );
9933 ins_pc_relative(1);
9934 %}
9936 // Store CMS card-mark Immediate
9937 instruct storeImmCM(memory mem, immI8 src) %{
9938 match(Set mem (StoreCM mem src));
9940 ins_cost(150);
9941 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
9942 // opcode(0xC6);
9943 ins_encode(store_B_immI_enc(mem, src));
9944 ins_pipe( ialu_storeI );
9945 %}
9947 // Die now
9948 instruct ShouldNotReachHere( )
9949 %{
9950 match(Halt);
9951 ins_cost(300);
9953 // Use the following format syntax
9954 format %{ "ILLTRAP ;#@ShouldNotReachHere" %}
9955 ins_encode %{
9956 // Here we should emit illtrap !
9958 __ stop("in ShoudNotReachHere");
9960 %}
9961 ins_pipe( pipe_jump );
9962 %}
9965 // Jump Direct Conditional - Label defines a relative address from Jcc+1
9966 instruct jmpLoopEnd(cmpOp cop, mRegI src1, mRegI src2, label labl) %{
9967 match(CountedLoopEnd cop (CmpI src1 src2));
9968 effect(USE labl);
9970 ins_cost(300);
9971 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd" %}
9972 ins_encode %{
9973 Register op1 = $src1$$Register;
9974 Register op2 = $src2$$Register;
9975 Label &L = *($labl$$label);
9976 int flag = $cop$$cmpcode;
9978 switch(flag)
9979 {
9980 case 0x01: //equal
9981 if (&L)
9982 __ beq(op1, op2, L);
9983 else
9984 __ beq(op1, op2, (int)0);
9985 break;
9986 case 0x02: //not_equal
9987 if (&L)
9988 __ bne(op1, op2, L);
9989 else
9990 __ bne(op1, op2, (int)0);
9991 break;
9992 case 0x03: //above
9993 __ slt(AT, op2, op1);
9994 if(&L)
9995 __ bne(AT, R0, L);
9996 else
9997 __ bne(AT, R0, (int)0);
9998 break;
9999 case 0x04: //above_equal
10000 __ slt(AT, op1, op2);
10001 if(&L)
10002 __ beq(AT, R0, L);
10003 else
10004 __ beq(AT, R0, (int)0);
10005 break;
10006 case 0x05: //below
10007 __ slt(AT, op1, op2);
10008 if(&L)
10009 __ bne(AT, R0, L);
10010 else
10011 __ bne(AT, R0, (int)0);
10012 break;
10013 case 0x06: //below_equal
10014 __ slt(AT, op2, op1);
10015 if(&L)
10016 __ beq(AT, R0, L);
10017 else
10018 __ beq(AT, R0, (int)0);
10019 break;
10020 default:
10021 Unimplemented();
10022 }
10023 __ nop();
10024 %}
10025 ins_pipe( pipe_jump );
10026 ins_pc_relative(1);
10027 %}
10030 instruct jmpLoopEnd_reg_imm16_sub(cmpOp cop, mRegI src1, immI16_sub src2, label labl) %{
10031 match(CountedLoopEnd cop (CmpI src1 src2));
10032 effect(USE labl);
10034 ins_cost(250);
10035 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd_reg_imm16_sub" %}
10036 ins_encode %{
10037 Register op1 = $src1$$Register;
10038 int op2 = $src2$$constant;
10039 Label &L = *($labl$$label);
10040 int flag = $cop$$cmpcode;
10042 __ addiu32(AT, op1, -1 * op2);
10044 switch(flag)
10045 {
10046 case 0x01: //equal
10047 if (&L)
10048 __ beq(AT, R0, L);
10049 else
10050 __ beq(AT, R0, (int)0);
10051 break;
10052 case 0x02: //not_equal
10053 if (&L)
10054 __ bne(AT, R0, L);
10055 else
10056 __ bne(AT, R0, (int)0);
10057 break;
10058 case 0x03: //above
10059 if(&L)
10060 __ bgtz(AT, L);
10061 else
10062 __ bgtz(AT, (int)0);
10063 break;
10064 case 0x04: //above_equal
10065 if(&L)
10066 __ bgez(AT, L);
10067 else
10068 __ bgez(AT,(int)0);
10069 break;
10070 case 0x05: //below
10071 if(&L)
10072 __ bltz(AT, L);
10073 else
10074 __ bltz(AT, (int)0);
10075 break;
10076 case 0x06: //below_equal
10077 if(&L)
10078 __ blez(AT, L);
10079 else
10080 __ blez(AT, (int)0);
10081 break;
10082 default:
10083 Unimplemented();
10084 }
10085 __ nop();
10086 %}
10087 ins_pipe( pipe_jump );
10088 ins_pc_relative(1);
10089 %}
10092 /*
10093 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10094 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
10095 match(CountedLoopEnd cop cmp);
10096 effect(USE labl);
10098 ins_cost(300);
10099 format %{ "J$cop,u $labl\t# Loop end" %}
10100 size(6);
10101 opcode(0x0F, 0x80);
10102 ins_encode( Jcc( cop, labl) );
10103 ins_pipe( pipe_jump );
10104 ins_pc_relative(1);
10105 %}
10107 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
10108 match(CountedLoopEnd cop cmp);
10109 effect(USE labl);
10111 ins_cost(200);
10112 format %{ "J$cop,u $labl\t# Loop end" %}
10113 opcode(0x0F, 0x80);
10114 ins_encode( Jcc( cop, labl) );
10115 ins_pipe( pipe_jump );
10116 ins_pc_relative(1);
10117 %}
10118 */
10120 // This match pattern is created for StoreIConditional since I cannot match IfNode without a RegFlags! fujie 2012/07/17
10121 instruct jmpCon_flags(cmpOp cop, FlagsReg cr, label labl) %{
10122 match(If cop cr);
10123 effect(USE labl);
10125 ins_cost(300);
10126 format %{ "J$cop $labl #mips uses AT as eflag @jmpCon_flags" %}
10128 ins_encode %{
10129 Label &L = *($labl$$label);
10130 switch($cop$$cmpcode)
10131 {
10132 case 0x01: //equal
10133 if (&L)
10134 __ bne(AT, R0, L);
10135 else
10136 __ bne(AT, R0, (int)0);
10137 break;
10138 case 0x02: //not equal
10139 if (&L)
10140 __ beq(AT, R0, L);
10141 else
10142 __ beq(AT, R0, (int)0);
10143 break;
10144 default:
10145 Unimplemented();
10146 }
10147 __ nop();
10148 %}
10150 ins_pipe( pipe_jump );
10151 ins_pc_relative(1);
10152 %}
10155 // ============================================================================
10156 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10157 // array for an instance of the superklass. Set a hidden internal cache on a
10158 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10159 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
10160 instruct partialSubtypeCheck( mRegP result, mRegP sub, mRegP super ) %{
10161 match(Set result (PartialSubtypeCheck sub super));
10162 ins_cost(1100); // slightly larger than the next version
10163 format %{ "partialSubtypeCheck result=$result, sub=$sub, super=$super " %}
10165 ins_encode( enc_PartialSubtypeCheck(result, sub, super) );
10166 ins_pipe( pipe_slow );
10167 %}
10170 // Conditional-store of an int value.
10171 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
10172 instruct storeIConditional( memory mem, mRegI oldval, mRegI newval, FlagsReg cr ) %{
10173 match(Set cr (StoreIConditional mem (Binary oldval newval)));
10174 // effect(KILL oldval);
10175 format %{ "CMPXCHG $newval, $mem, $oldval \t# @storeIConditional" %}
10177 ins_encode %{
10178 Register oldval = $oldval$$Register;
10179 Register newval = $newval$$Register;
10180 Address addr(as_Register($mem$$base), $mem$$disp);
10181 Label again, failure;
10183 // int base = $mem$$base;
10184 int index = $mem$$index;
10185 int scale = $mem$$scale;
10186 int disp = $mem$$disp;
10188 guarantee(Assembler::is_simm16(disp), "");
10190 if( scale != 0 ) Unimplemented();
10191 if( index != 0 ) {
10192 __ stop("in storeIConditional: index != 0");
10193 } else {
10194 __ bind(again);
10195 __ sync();
10196 __ ll(AT, addr);
10197 __ bne(AT, oldval, failure);
10198 __ delayed()->addu(AT, R0, R0);
10200 __ addu(AT, newval, R0);
10201 __ sc(AT, addr);
10202 __ beq(AT, R0, again);
10203 __ delayed()->addiu(AT, R0, 0xFF);
10204 __ bind(failure);
10205 __ sync();
10206 }
10207 %}
10209 ins_pipe( long_memory_op );
10210 %}
10212 // Conditional-store of a long value.
10213 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
10214 instruct storeLConditional(memory mem, t2RegL oldval, mRegL newval, FlagsReg cr )
10215 %{
10216 match(Set cr (StoreLConditional mem (Binary oldval newval)));
10217 effect(KILL oldval);
10219 format %{ "cmpxchg $mem, $newval\t# If $oldval == $mem then store $newval into $mem" %}
10220 ins_encode%{
10221 Register oldval = $oldval$$Register;
10222 Register newval = $newval$$Register;
10223 Address addr((Register)$mem$$base, $mem$$disp);
10225 int index = $mem$$index;
10226 int scale = $mem$$scale;
10227 int disp = $mem$$disp;
10229 guarantee(Assembler::is_simm16(disp), "");
10231 if( scale != 0 ) Unimplemented();
10232 if( index != 0 ) {
10233 __ stop("in storeIConditional: index != 0");
10234 } else {
10235 __ cmpxchg(newval, addr, oldval);
10236 }
10237 %}
10238 ins_pipe( long_memory_op );
10239 %}
10242 instruct compareAndSwapI( mRegI res, mRegP mem_ptr, mS2RegI oldval, mRegI newval) %{
10243 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
10244 effect(KILL oldval);
10245 // match(CompareAndSwapI mem_ptr (Binary oldval newval));
10246 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapI\n\t"
10247 "MOV $res, 1 @ compareAndSwapI\n\t"
10248 "BNE AT, R0 @ compareAndSwapI\n\t"
10249 "MOV $res, 0 @ compareAndSwapI\n"
10250 "L:" %}
10251 ins_encode %{
10252 Register newval = $newval$$Register;
10253 Register oldval = $oldval$$Register;
10254 Register res = $res$$Register;
10255 Address addr($mem_ptr$$Register, 0);
10256 Label L;
10258 __ cmpxchg32(newval, addr, oldval);
10259 __ move(res, AT);
10260 %}
10261 ins_pipe( long_memory_op );
10262 %}
10264 //FIXME:
10265 instruct compareAndSwapP( mRegI res, mRegP mem_ptr, s2_RegP oldval, mRegP newval) %{
10266 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
10267 effect(KILL oldval);
10268 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapP\n\t"
10269 "MOV $res, AT @ compareAndSwapP\n\t"
10270 "L:" %}
10271 ins_encode %{
10272 Register newval = $newval$$Register;
10273 Register oldval = $oldval$$Register;
10274 Register res = $res$$Register;
10275 Address addr($mem_ptr$$Register, 0);
10276 Label L;
10278 __ cmpxchg(newval, addr, oldval);
10279 __ move(res, AT);
10280 %}
10281 ins_pipe( long_memory_op );
10282 %}
10284 instruct compareAndSwapN( mRegI res, mRegP mem_ptr, t2_RegN oldval, mRegN newval) %{
10285 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
10286 effect(KILL oldval);
10287 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapN\n\t"
10288 "MOV $res, AT @ compareAndSwapN\n\t"
10289 "L:" %}
10290 ins_encode %{
10291 Register newval = $newval$$Register;
10292 Register oldval = $oldval$$Register;
10293 Register res = $res$$Register;
10294 Address addr($mem_ptr$$Register, 0);
10295 Label L;
10297 /* 2013/7/19 Jin: cmpxchg32 is implemented with ll/sc, which will do sign extension.
10298 * Thus, we should extend oldval's sign for correct comparision.
10299 */
10300 __ sll(oldval, oldval, 0);
10302 __ cmpxchg32(newval, addr, oldval);
10303 __ move(res, AT);
10304 %}
10305 ins_pipe( long_memory_op );
10306 %}
10308 //----------Max and Min--------------------------------------------------------
10309 // Min Instructions
10310 ////
10311 // *** Min and Max using the conditional move are slower than the
10312 // *** branch version on a Pentium III.
10313 // // Conditional move for min
10314 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
10315 // effect( USE_DEF op2, USE op1, USE cr );
10316 // format %{ "CMOVlt $op2,$op1\t! min" %}
10317 // opcode(0x4C,0x0F);
10318 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
10319 // ins_pipe( pipe_cmov_reg );
10320 //%}
10321 //
10322 //// Min Register with Register (P6 version)
10323 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
10324 // predicate(VM_Version::supports_cmov() );
10325 // match(Set op2 (MinI op1 op2));
10326 // ins_cost(200);
10327 // expand %{
10328 // eFlagsReg cr;
10329 // compI_eReg(cr,op1,op2);
10330 // cmovI_reg_lt(op2,op1,cr);
10331 // %}
10332 //%}
10334 // Min Register with Register (generic version)
10335 instruct minI_Reg_Reg(mRegI dst, mRegI src) %{
10336 match(Set dst (MinI dst src));
10337 //effect(KILL flags);
10338 ins_cost(80);
10340 format %{ "MIN $dst, $src @minI_Reg_Reg" %}
10341 ins_encode %{
10342 Register dst = $dst$$Register;
10343 Register src = $src$$Register;
10345 __ slt(AT, src, dst);
10346 __ movn(dst, src, AT);
10348 %}
10350 ins_pipe( pipe_slow );
10351 %}
10353 // Max Register with Register
10354 // *** Min and Max using the conditional move are slower than the
10355 // *** branch version on a Pentium III.
10356 // // Conditional move for max
10357 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
10358 // effect( USE_DEF op2, USE op1, USE cr );
10359 // format %{ "CMOVgt $op2,$op1\t! max" %}
10360 // opcode(0x4F,0x0F);
10361 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
10362 // ins_pipe( pipe_cmov_reg );
10363 //%}
10364 //
10365 // // Max Register with Register (P6 version)
10366 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
10367 // predicate(VM_Version::supports_cmov() );
10368 // match(Set op2 (MaxI op1 op2));
10369 // ins_cost(200);
10370 // expand %{
10371 // eFlagsReg cr;
10372 // compI_eReg(cr,op1,op2);
10373 // cmovI_reg_gt(op2,op1,cr);
10374 // %}
10375 //%}
10377 // Max Register with Register (generic version)
10378 instruct maxI_Reg_Reg(mRegI dst, mRegI src) %{
10379 match(Set dst (MaxI dst src));
10380 ins_cost(80);
10382 format %{ "MAX $dst, $src @maxI_Reg_Reg" %}
10384 ins_encode %{
10385 Register dst = $dst$$Register;
10386 Register src = $src$$Register;
10388 __ slt(AT, dst, src);
10389 __ movn(dst, src, AT);
10391 %}
10393 ins_pipe( pipe_slow );
10394 %}
10397 // ============================================================================
10398 // Safepoint Instruction
10399 instruct safePoint_poll() %{
10400 match(SafePoint);
10402 ins_cost(125);
10403 format %{ "lui at, HI(polling_page)]\t! Safepoint: poll for GC @ safePoint_poll \n\t"
10404 "lw at, LO(polling_page)]\n " %}
10406 ins_encode %{
10407 __ block_comment("Safepoint:");
10408 #ifndef OPT_SAFEPOINT
10409 __ li48(S7, (long)os::get_polling_page());
10410 __ relocate(relocInfo::poll_type);
10411 __ lw(AT, S7, 0);
10412 #else
10413 __ lui(S7, Assembler::split_high((intptr_t)os::get_polling_page()));
10414 __ relocate(relocInfo::poll_type);
10415 __ lw(AT, S7, Assembler::split_low((intptr_t)os::get_polling_page()));
10416 #endif
10417 %}
10419 ins_pipe( ialu_storeI );
10420 %}
10422 //----------PEEPHOLE RULES-----------------------------------------------------
10423 // These must follow all instruction definitions as they use the names
10424 // defined in the instructions definitions.
10425 //
10426 // peepmatch ( root_instr_name [preceeding_instruction]* );
10427 //
10428 // peepconstraint %{
10429 // (instruction_number.operand_name relational_op instruction_number.operand_name
10430 // [, ...] );
10431 // // instruction numbers are zero-based using left to right order in peepmatch
10432 //
10433 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10434 // // provide an instruction_number.operand_name for each operand that appears
10435 // // in the replacement instruction's match rule
10436 //
10437 // ---------VM FLAGS---------------------------------------------------------
10438 //
10439 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10440 //
10441 // Each peephole rule is given an identifying number starting with zero and
10442 // increasing by one in the order seen by the parser. An individual peephole
10443 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10444 // on the command-line.
10445 //
10446 // ---------CURRENT LIMITATIONS----------------------------------------------
10447 //
10448 // Only match adjacent instructions in same basic block
10449 // Only equality constraints
10450 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10451 // Only one replacement instruction
10452 //
10453 // ---------EXAMPLE----------------------------------------------------------
10454 //
10455 // // pertinent parts of existing instructions in architecture description
10456 // instruct movI(eRegI dst, eRegI src) %{
10457 // match(Set dst (CopyI src));
10458 // %}
10459 //
10460 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10461 // match(Set dst (AddI dst src));
10462 // effect(KILL cr);
10463 // %}
10464 //
10465 // // Change (inc mov) to lea
10466 // peephole %{
10467 // // increment preceeded by register-register move
10468 // peepmatch ( incI_eReg movI );
10469 // // require that the destination register of the increment
10470 // // match the destination register of the move
10471 // peepconstraint ( 0.dst == 1.dst );
10472 // // construct a replacement instruction that sets
10473 // // the destination to ( move's source register + one )
10474 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
10475 // %}
10476 //
10477 // Implementation no longer uses movX instructions since
10478 // machine-independent system no longer uses CopyX nodes.
10479 //
10480 // peephole %{
10481 // peepmatch ( incI_eReg movI );
10482 // peepconstraint ( 0.dst == 1.dst );
10483 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
10484 // %}
10485 //
10486 // peephole %{
10487 // peepmatch ( decI_eReg movI );
10488 // peepconstraint ( 0.dst == 1.dst );
10489 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
10490 // %}
10491 //
10492 // peephole %{
10493 // peepmatch ( addI_eReg_imm movI );
10494 // peepconstraint ( 0.dst == 1.dst );
10495 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
10496 // %}
10497 //
10498 // peephole %{
10499 // peepmatch ( addP_eReg_imm movP );
10500 // peepconstraint ( 0.dst == 1.dst );
10501 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
10502 // %}
10504 // // Change load of spilled value to only a spill
10505 // instruct storeI(memory mem, eRegI src) %{
10506 // match(Set mem (StoreI mem src));
10507 // %}
10508 //
10509 // instruct loadI(eRegI dst, memory mem) %{
10510 // match(Set dst (LoadI mem));
10511 // %}
10512 //
10513 //peephole %{
10514 // peepmatch ( loadI storeI );
10515 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10516 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10517 //%}
10519 //----------SMARTSPILL RULES---------------------------------------------------
10520 // These must follow all instruction definitions as they use the names
10521 // defined in the instructions definitions.
