1.1 --- a/src/cpu/mips/vm/mips_64.ad Wed Aug 10 17:54:14 2016 +0800 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Thu Aug 11 09:27:28 2016 +0800 1.3 @@ -8365,8 +8365,12 @@ 1.4 Register op1 = as_Register($src1$$reg); 1.5 Register op2 = as_Register($src2$$reg); 1.6 1.7 - __ ddiv(op1, op2); 1.8 - __ mfhi(dst); 1.9 + if (UseLoongsonISA) { 1.10 + __ gsdmod(dst, op1, op2); 1.11 + } else { 1.12 + __ ddiv(op1, op2); 1.13 + __ mfhi(dst); 1.14 + } 1.15 %} 1.16 ins_pipe( pipe_slow ); 1.17 %}