src/cpu/mips/vm/mips_64.ad

changeset 60
c9917fbd0a31
parent 59
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child 61
17f070949775
equal deleted inserted replaced
59:2dcecbdfda11 60:c9917fbd0a31
8363 ins_encode %{ 8363 ins_encode %{
8364 Register dst = as_Register($dst$$reg); 8364 Register dst = as_Register($dst$$reg);
8365 Register op1 = as_Register($src1$$reg); 8365 Register op1 = as_Register($src1$$reg);
8366 Register op2 = as_Register($src2$$reg); 8366 Register op2 = as_Register($src2$$reg);
8367 8367
8368 __ ddiv(op1, op2); 8368 if (UseLoongsonISA) {
8369 __ mfhi(dst); 8369 __ gsdmod(dst, op1, op2);
8370 } else {
8371 __ ddiv(op1, op2);
8372 __ mfhi(dst);
8373 }
8370 %} 8374 %}
8371 ins_pipe( pipe_slow ); 8375 ins_pipe( pipe_slow );
8372 %} 8376 %}
8373 8377
8374 instruct mulI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{ 8378 instruct mulI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{

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