Tue, 12 Jun 2012 14:31:44 -0700
7174218: remove AtomicLongCSImpl intrinsics
Reviewed-by: kvn, twisti
Contributed-by: Krystal Mok <sajia@taobao.com>
1 //
2 // Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
25 // X86 Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source_hpp %{
239 // Must be visible to the DFA in dfa_x86_32.cpp
240 extern bool is_operand_hi32_zero(Node* n);
241 %}
243 source %{
244 #define RELOC_IMM32 Assembler::imm_operand
245 #define RELOC_DISP32 Assembler::disp32_operand
247 #define __ _masm.
249 // How to find the high register of a Long pair, given the low register
250 #define HIGH_FROM_LOW(x) ((x)+2)
252 // These masks are used to provide 128-bit aligned bitmasks to the XMM
253 // instructions, to allow sign-masking or sign-bit flipping. They allow
254 // fast versions of NegF/NegD and AbsF/AbsD.
256 // Note: 'double' and 'long long' have 32-bits alignment on x86.
257 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
258 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
259 // of 128-bits operands for SSE instructions.
260 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
261 // Store the value to a 128-bits operand.
262 operand[0] = lo;
263 operand[1] = hi;
264 return operand;
265 }
267 // Buffer for 128-bits masks used by SSE instructions.
268 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
270 // Static initialization during VM startup.
271 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
272 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
273 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
274 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
276 // Offset hacking within calls.
277 static int pre_call_FPU_size() {
278 if (Compile::current()->in_24_bit_fp_mode())
279 return 6; // fldcw
280 return 0;
281 }
283 static int preserve_SP_size() {
284 return 2; // op, rm(reg/reg)
285 }
287 // !!!!! Special hack to get all type of calls to specify the byte offset
288 // from the start of the call to the point where the return address
289 // will point.
290 int MachCallStaticJavaNode::ret_addr_offset() {
291 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
292 if (_method_handle_invoke)
293 offset += preserve_SP_size();
294 return offset;
295 }
297 int MachCallDynamicJavaNode::ret_addr_offset() {
298 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
299 }
301 static int sizeof_FFree_Float_Stack_All = -1;
303 int MachCallRuntimeNode::ret_addr_offset() {
304 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
305 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
306 }
308 // Indicate if the safepoint node needs the polling page as an input.
309 // Since x86 does have absolute addressing, it doesn't.
310 bool SafePointNode::needs_polling_address_input() {
311 return false;
312 }
314 //
315 // Compute padding required for nodes which need alignment
316 //
318 // The address of the call instruction needs to be 4-byte aligned to
319 // ensure that it does not span a cache line so that it can be patched.
320 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
321 current_offset += pre_call_FPU_size(); // skip fldcw, if any
322 current_offset += 1; // skip call opcode byte
323 return round_to(current_offset, alignment_required()) - current_offset;
324 }
326 // The address of the call instruction needs to be 4-byte aligned to
327 // ensure that it does not span a cache line so that it can be patched.
328 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
329 current_offset += pre_call_FPU_size(); // skip fldcw, if any
330 current_offset += preserve_SP_size(); // skip mov rbp, rsp
331 current_offset += 1; // skip call opcode byte
332 return round_to(current_offset, alignment_required()) - current_offset;
333 }
335 // The address of the call instruction needs to be 4-byte aligned to
336 // ensure that it does not span a cache line so that it can be patched.
337 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
338 current_offset += pre_call_FPU_size(); // skip fldcw, if any
339 current_offset += 5; // skip MOV instruction
340 current_offset += 1; // skip call opcode byte
341 return round_to(current_offset, alignment_required()) - current_offset;
342 }
344 // EMIT_RM()
345 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
346 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
347 cbuf.insts()->emit_int8(c);
348 }
350 // EMIT_CC()
351 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
352 unsigned char c = (unsigned char)( f1 | f2 );
353 cbuf.insts()->emit_int8(c);
354 }
356 // EMIT_OPCODE()
357 void emit_opcode(CodeBuffer &cbuf, int code) {
358 cbuf.insts()->emit_int8((unsigned char) code);
359 }
361 // EMIT_OPCODE() w/ relocation information
362 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
363 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
364 emit_opcode(cbuf, code);
365 }
367 // EMIT_D8()
368 void emit_d8(CodeBuffer &cbuf, int d8) {
369 cbuf.insts()->emit_int8((unsigned char) d8);
370 }
372 // EMIT_D16()
373 void emit_d16(CodeBuffer &cbuf, int d16) {
374 cbuf.insts()->emit_int16(d16);
375 }
377 // EMIT_D32()
378 void emit_d32(CodeBuffer &cbuf, int d32) {
379 cbuf.insts()->emit_int32(d32);
380 }
382 // emit 32 bit value and construct relocation entry from relocInfo::relocType
383 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
384 int format) {
385 cbuf.relocate(cbuf.insts_mark(), reloc, format);
386 cbuf.insts()->emit_int32(d32);
387 }
389 // emit 32 bit value and construct relocation entry from RelocationHolder
390 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
391 int format) {
392 #ifdef ASSERT
393 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
394 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
395 }
396 #endif
397 cbuf.relocate(cbuf.insts_mark(), rspec, format);
398 cbuf.insts()->emit_int32(d32);
399 }
401 // Access stack slot for load or store
402 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
403 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
404 if( -128 <= disp && disp <= 127 ) {
405 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
406 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
407 emit_d8 (cbuf, disp); // Displacement // R/M byte
408 } else {
409 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
410 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
411 emit_d32(cbuf, disp); // Displacement // R/M byte
412 }
413 }
415 // eRegI ereg, memory mem) %{ // emit_reg_mem
416 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
417 // There is no index & no scale, use form without SIB byte
418 if ((index == 0x4) &&
419 (scale == 0) && (base != ESP_enc)) {
420 // If no displacement, mode is 0x0; unless base is [EBP]
421 if ( (displace == 0) && (base != EBP_enc) ) {
422 emit_rm(cbuf, 0x0, reg_encoding, base);
423 }
424 else { // If 8-bit displacement, mode 0x1
425 if ((displace >= -128) && (displace <= 127)
426 && !(displace_is_oop) ) {
427 emit_rm(cbuf, 0x1, reg_encoding, base);
428 emit_d8(cbuf, displace);
429 }
430 else { // If 32-bit displacement
431 if (base == -1) { // Special flag for absolute address
432 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
433 // (manual lies; no SIB needed here)
434 if ( displace_is_oop ) {
435 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
436 } else {
437 emit_d32 (cbuf, displace);
438 }
439 }
440 else { // Normal base + offset
441 emit_rm(cbuf, 0x2, reg_encoding, base);
442 if ( displace_is_oop ) {
443 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
444 } else {
445 emit_d32 (cbuf, displace);
446 }
447 }
448 }
449 }
450 }
451 else { // Else, encode with the SIB byte
452 // If no displacement, mode is 0x0; unless base is [EBP]
453 if (displace == 0 && (base != EBP_enc)) { // If no displacement
454 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
455 emit_rm(cbuf, scale, index, base);
456 }
457 else { // If 8-bit displacement, mode 0x1
458 if ((displace >= -128) && (displace <= 127)
459 && !(displace_is_oop) ) {
460 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
461 emit_rm(cbuf, scale, index, base);
462 emit_d8(cbuf, displace);
463 }
464 else { // If 32-bit displacement
465 if (base == 0x04 ) {
466 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
467 emit_rm(cbuf, scale, index, 0x04);
468 } else {
469 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
470 emit_rm(cbuf, scale, index, base);
471 }
472 if ( displace_is_oop ) {
473 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
474 } else {
475 emit_d32 (cbuf, displace);
476 }
477 }
478 }
479 }
480 }
483 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
484 if( dst_encoding == src_encoding ) {
485 // reg-reg copy, use an empty encoding
486 } else {
487 emit_opcode( cbuf, 0x8B );
488 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
489 }
490 }
492 void emit_cmpfp_fixup(MacroAssembler& _masm) {
493 Label exit;
494 __ jccb(Assembler::noParity, exit);
495 __ pushf();
496 //
497 // comiss/ucomiss instructions set ZF,PF,CF flags and
498 // zero OF,AF,SF for NaN values.
499 // Fixup flags by zeroing ZF,PF so that compare of NaN
500 // values returns 'less than' result (CF is set).
501 // Leave the rest of flags unchanged.
502 //
503 // 7 6 5 4 3 2 1 0
504 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
505 // 0 0 1 0 1 0 1 1 (0x2B)
506 //
507 __ andl(Address(rsp, 0), 0xffffff2b);
508 __ popf();
509 __ bind(exit);
510 }
512 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
513 Label done;
514 __ movl(dst, -1);
515 __ jcc(Assembler::parity, done);
516 __ jcc(Assembler::below, done);
517 __ setb(Assembler::notEqual, dst);
518 __ movzbl(dst, dst);
519 __ bind(done);
520 }
523 //=============================================================================
524 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
526 int Compile::ConstantTable::calculate_table_base_offset() const {
527 return 0; // absolute addressing, no offset
528 }
530 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
531 // Empty encoding
532 }
534 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
535 return 0;
536 }
538 #ifndef PRODUCT
539 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
540 st->print("# MachConstantBaseNode (empty encoding)");
541 }
542 #endif
545 //=============================================================================
546 #ifndef PRODUCT
547 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
548 Compile* C = ra_->C;
550 int framesize = C->frame_slots() << LogBytesPerInt;
551 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
552 // Remove wordSize for return addr which is already pushed.
553 framesize -= wordSize;
555 if (C->need_stack_bang(framesize)) {
556 framesize -= wordSize;
557 st->print("# stack bang");
558 st->print("\n\t");
559 st->print("PUSH EBP\t# Save EBP");
560 if (framesize) {
561 st->print("\n\t");
562 st->print("SUB ESP, #%d\t# Create frame",framesize);
563 }
564 } else {
565 st->print("SUB ESP, #%d\t# Create frame",framesize);
566 st->print("\n\t");
567 framesize -= wordSize;
568 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
569 }
571 if (VerifyStackAtCalls) {
572 st->print("\n\t");
573 framesize -= wordSize;
574 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
575 }
577 if( C->in_24_bit_fp_mode() ) {
578 st->print("\n\t");
579 st->print("FLDCW \t# load 24 bit fpu control word");
580 }
581 if (UseSSE >= 2 && VerifyFPU) {
582 st->print("\n\t");
583 st->print("# verify FPU stack (must be clean on entry)");
584 }
586 #ifdef ASSERT
587 if (VerifyStackAtCalls) {
588 st->print("\n\t");
589 st->print("# stack alignment check");
590 }
591 #endif
592 st->cr();
593 }
594 #endif
597 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
598 Compile* C = ra_->C;
599 MacroAssembler _masm(&cbuf);
601 int framesize = C->frame_slots() << LogBytesPerInt;
603 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
605 C->set_frame_complete(cbuf.insts_size());
607 if (C->has_mach_constant_base_node()) {
608 // NOTE: We set the table base offset here because users might be
609 // emitted before MachConstantBaseNode.
610 Compile::ConstantTable& constant_table = C->constant_table();
611 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
612 }
613 }
615 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
616 return MachNode::size(ra_); // too many variables; just compute it the hard way
617 }
619 int MachPrologNode::reloc() const {
620 return 0; // a large enough number
621 }
623 //=============================================================================
624 #ifndef PRODUCT
625 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
626 Compile *C = ra_->C;
627 int framesize = C->frame_slots() << LogBytesPerInt;
628 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
629 // Remove two words for return addr and rbp,
630 framesize -= 2*wordSize;
632 if( C->in_24_bit_fp_mode() ) {
633 st->print("FLDCW standard control word");
634 st->cr(); st->print("\t");
635 }
636 if( framesize ) {
637 st->print("ADD ESP,%d\t# Destroy frame",framesize);
638 st->cr(); st->print("\t");
639 }
640 st->print_cr("POPL EBP"); st->print("\t");
641 if( do_polling() && C->is_method_compilation() ) {
642 st->print("TEST PollPage,EAX\t! Poll Safepoint");
643 st->cr(); st->print("\t");
644 }
645 }
646 #endif
648 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
649 Compile *C = ra_->C;
651 // If method set FPU control word, restore to standard control word
652 if( C->in_24_bit_fp_mode() ) {
653 MacroAssembler masm(&cbuf);
654 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
655 }
657 int framesize = C->frame_slots() << LogBytesPerInt;
658 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
659 // Remove two words for return addr and rbp,
660 framesize -= 2*wordSize;
662 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
664 if( framesize >= 128 ) {
665 emit_opcode(cbuf, 0x81); // add SP, #framesize
666 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
667 emit_d32(cbuf, framesize);
668 }
669 else if( framesize ) {
670 emit_opcode(cbuf, 0x83); // add SP, #framesize
671 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
672 emit_d8(cbuf, framesize);
673 }
675 emit_opcode(cbuf, 0x58 | EBP_enc);
677 if( do_polling() && C->is_method_compilation() ) {
678 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
679 emit_opcode(cbuf,0x85);
680 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
681 emit_d32(cbuf, (intptr_t)os::get_polling_page());
682 }
683 }
685 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
686 Compile *C = ra_->C;
687 // If method set FPU control word, restore to standard control word
688 int size = C->in_24_bit_fp_mode() ? 6 : 0;
689 if( do_polling() && C->is_method_compilation() ) size += 6;
691 int framesize = C->frame_slots() << LogBytesPerInt;
692 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
693 // Remove two words for return addr and rbp,
694 framesize -= 2*wordSize;
696 size++; // popl rbp,
698 if( framesize >= 128 ) {
699 size += 6;
700 } else {
701 size += framesize ? 3 : 0;
702 }
703 return size;
704 }
706 int MachEpilogNode::reloc() const {
707 return 0; // a large enough number
708 }
710 const Pipeline * MachEpilogNode::pipeline() const {
711 return MachNode::pipeline_class();
712 }
714 int MachEpilogNode::safepoint_offset() const { return 0; }
716 //=============================================================================
718 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
719 static enum RC rc_class( OptoReg::Name reg ) {
721 if( !OptoReg::is_valid(reg) ) return rc_bad;
722 if (OptoReg::is_stack(reg)) return rc_stack;
724 VMReg r = OptoReg::as_VMReg(reg);
725 if (r->is_Register()) return rc_int;
726 if (r->is_FloatRegister()) {
727 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
728 return rc_float;
729 }
730 assert(r->is_XMMRegister(), "must be");
731 return rc_xmm;
732 }
734 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
735 int opcode, const char *op_str, int size, outputStream* st ) {
736 if( cbuf ) {
737 emit_opcode (*cbuf, opcode );
738 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
739 #ifndef PRODUCT
740 } else if( !do_size ) {
741 if( size != 0 ) st->print("\n\t");
742 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
743 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
744 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
745 } else { // FLD, FST, PUSH, POP
746 st->print("%s [ESP + #%d]",op_str,offset);
747 }
748 #endif
749 }
750 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
751 return size+3+offset_size;
752 }
754 // Helper for XMM registers. Extra opcode bits, limited syntax.
755 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
756 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
757 if (cbuf) {
758 MacroAssembler _masm(cbuf);
759 if (reg_lo+1 == reg_hi) { // double move?
760 if (is_load) {
761 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
762 } else {
763 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
764 }
765 } else {
766 if (is_load) {
767 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
768 } else {
769 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
770 }
771 }
772 #ifndef PRODUCT
773 } else if (!do_size) {
774 if (size != 0) st->print("\n\t");
775 if (reg_lo+1 == reg_hi) { // double move?
776 if (is_load) st->print("%s %s,[ESP + #%d]",
777 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
778 Matcher::regName[reg_lo], offset);
779 else st->print("MOVSD [ESP + #%d],%s",
780 offset, Matcher::regName[reg_lo]);
781 } else {
782 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
783 Matcher::regName[reg_lo], offset);
784 else st->print("MOVSS [ESP + #%d],%s",
785 offset, Matcher::regName[reg_lo]);
786 }
787 #endif
788 }
789 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
790 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes.
791 return size+5+offset_size;
792 }
795 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
796 int src_hi, int dst_hi, int size, outputStream* st ) {
797 if (cbuf) {
798 MacroAssembler _masm(cbuf);
799 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
800 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
801 as_XMMRegister(Matcher::_regEncode[src_lo]));
802 } else {
803 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
804 as_XMMRegister(Matcher::_regEncode[src_lo]));
805 }
806 #ifndef PRODUCT
807 } else if (!do_size) {
808 if (size != 0) st->print("\n\t");
809 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
810 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
811 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
812 } else {
813 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
814 }
815 } else {
816 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
817 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
818 } else {
819 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
820 }
821 }
822 #endif
823 }
824 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes.
825 // Only MOVAPS SSE prefix uses 1 byte.
826 int sz = 4;
827 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
828 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
829 return size + sz;
830 }
832 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
833 int src_hi, int dst_hi, int size, outputStream* st ) {
834 // 32-bit
835 if (cbuf) {
836 MacroAssembler _masm(cbuf);
837 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
838 as_Register(Matcher::_regEncode[src_lo]));
839 #ifndef PRODUCT
840 } else if (!do_size) {
841 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
842 #endif
843 }
844 return 4;
845 }
848 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
849 int src_hi, int dst_hi, int size, outputStream* st ) {
850 // 32-bit
851 if (cbuf) {
852 MacroAssembler _masm(cbuf);
853 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
854 as_XMMRegister(Matcher::_regEncode[src_lo]));
855 #ifndef PRODUCT
856 } else if (!do_size) {
857 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
858 #endif
859 }
860 return 4;
861 }
863 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
864 if( cbuf ) {
865 emit_opcode(*cbuf, 0x8B );
866 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
867 #ifndef PRODUCT
868 } else if( !do_size ) {
869 if( size != 0 ) st->print("\n\t");
870 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
871 #endif
872 }
873 return size+2;
874 }
876 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
877 int offset, int size, outputStream* st ) {
878 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
879 if( cbuf ) {
880 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
881 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
882 #ifndef PRODUCT
883 } else if( !do_size ) {
884 if( size != 0 ) st->print("\n\t");
885 st->print("FLD %s",Matcher::regName[src_lo]);
886 #endif
887 }
888 size += 2;
889 }
891 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
892 const char *op_str;
893 int op;
894 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
895 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
896 op = 0xDD;
897 } else { // 32-bit store
898 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
899 op = 0xD9;
900 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
901 }
903 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
904 }
906 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
907 // Get registers to move
908 OptoReg::Name src_second = ra_->get_reg_second(in(1));
909 OptoReg::Name src_first = ra_->get_reg_first(in(1));
910 OptoReg::Name dst_second = ra_->get_reg_second(this );
911 OptoReg::Name dst_first = ra_->get_reg_first(this );
913 enum RC src_second_rc = rc_class(src_second);
914 enum RC src_first_rc = rc_class(src_first);
915 enum RC dst_second_rc = rc_class(dst_second);
916 enum RC dst_first_rc = rc_class(dst_first);
918 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
920 // Generate spill code!
921 int size = 0;
923 if( src_first == dst_first && src_second == dst_second )
924 return size; // Self copy, no move
926 // --------------------------------------
927 // Check for mem-mem move. push/pop to move.
928 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
929 if( src_second == dst_first ) { // overlapping stack copy ranges
930 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
931 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
932 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
933 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
934 }
935 // move low bits
936 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
937 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
938 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
939 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
940 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
941 }
942 return size;
943 }
945 // --------------------------------------
946 // Check for integer reg-reg copy
947 if( src_first_rc == rc_int && dst_first_rc == rc_int )
948 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
950 // Check for integer store
951 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
952 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
954 // Check for integer load
955 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
956 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
958 // Check for integer reg-xmm reg copy
959 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
960 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
961 "no 64 bit integer-float reg moves" );
962 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
963 }
964 // --------------------------------------
965 // Check for float reg-reg copy
966 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
967 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
968 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
969 if( cbuf ) {
971 // Note the mucking with the register encode to compensate for the 0/1
972 // indexing issue mentioned in a comment in the reg_def sections
973 // for FPR registers many lines above here.
975 if( src_first != FPR1L_num ) {
976 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
977 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
978 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
979 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
980 } else {
981 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
982 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
983 }
984 #ifndef PRODUCT
985 } else if( !do_size ) {
986 if( size != 0 ) st->print("\n\t");
987 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
988 else st->print( "FST %s", Matcher::regName[dst_first]);
989 #endif
990 }
991 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
992 }
994 // Check for float store
995 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
996 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
997 }
999 // Check for float load
1000 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1001 int offset = ra_->reg2offset(src_first);
1002 const char *op_str;
1003 int op;
1004 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1005 op_str = "FLD_D";
1006 op = 0xDD;
1007 } else { // 32-bit load
1008 op_str = "FLD_S";
1009 op = 0xD9;
1010 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1011 }
1012 if( cbuf ) {
1013 emit_opcode (*cbuf, op );
1014 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
1015 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1016 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1017 #ifndef PRODUCT
1018 } else if( !do_size ) {
1019 if( size != 0 ) st->print("\n\t");
1020 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1021 #endif
1022 }
1023 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1024 return size + 3+offset_size+2;
1025 }
1027 // Check for xmm reg-reg copy
1028 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1029 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1030 (src_first+1 == src_second && dst_first+1 == dst_second),
1031 "no non-adjacent float-moves" );
1032 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1033 }
1035 // Check for xmm reg-integer reg copy
1036 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1037 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1038 "no 64 bit float-integer reg moves" );
1039 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1040 }
1042 // Check for xmm store
1043 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1044 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1045 }
1047 // Check for float xmm load
1048 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1049 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1050 }
1052 // Copy from float reg to xmm reg
1053 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1054 // copy to the top of stack from floating point reg
1055 // and use LEA to preserve flags
1056 if( cbuf ) {
1057 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1058 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1059 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1060 emit_d8(*cbuf,0xF8);
1061 #ifndef PRODUCT
1062 } else if( !do_size ) {
1063 if( size != 0 ) st->print("\n\t");
1064 st->print("LEA ESP,[ESP-8]");
1065 #endif
1066 }
1067 size += 4;
1069 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1071 // Copy from the temp memory to the xmm reg.
1072 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1074 if( cbuf ) {
1075 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1076 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1077 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1078 emit_d8(*cbuf,0x08);
1079 #ifndef PRODUCT
1080 } else if( !do_size ) {
1081 if( size != 0 ) st->print("\n\t");
1082 st->print("LEA ESP,[ESP+8]");
1083 #endif
1084 }
1085 size += 4;
1086 return size;
1087 }
1089 assert( size > 0, "missed a case" );
1091 // --------------------------------------------------------------------
1092 // Check for second bits still needing moving.
1093 if( src_second == dst_second )
1094 return size; // Self copy; no move
1095 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1097 // Check for second word int-int move
1098 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1099 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1101 // Check for second word integer store
1102 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1103 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1105 // Check for second word integer load
1106 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1107 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1110 Unimplemented();
1111 }
1113 #ifndef PRODUCT
1114 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1115 implementation( NULL, ra_, false, st );
1116 }
1117 #endif
1119 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1120 implementation( &cbuf, ra_, false, NULL );
1121 }
1123 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1124 return implementation( NULL, ra_, true, NULL );
1125 }
1128 //=============================================================================
1129 #ifndef PRODUCT
1130 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1131 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1132 int reg = ra_->get_reg_first(this);
1133 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1134 }
1135 #endif
1137 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1138 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1139 int reg = ra_->get_encode(this);
1140 if( offset >= 128 ) {
1141 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1142 emit_rm(cbuf, 0x2, reg, 0x04);
1143 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1144 emit_d32(cbuf, offset);
1145 }
1146 else {
1147 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1148 emit_rm(cbuf, 0x1, reg, 0x04);
1149 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1150 emit_d8(cbuf, offset);
1151 }
1152 }
1154 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1155 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1156 if( offset >= 128 ) {
1157 return 7;
1158 }
1159 else {
1160 return 4;
1161 }
1162 }
1164 //=============================================================================
1166 // emit call stub, compiled java to interpreter
1167 void emit_java_to_interp(CodeBuffer &cbuf ) {
1168 // Stub is fixed up when the corresponding call is converted from calling
1169 // compiled code to calling interpreted code.
1170 // mov rbx,0
1171 // jmp -1
1173 address mark = cbuf.insts_mark(); // get mark within main instrs section
1175 // Note that the code buffer's insts_mark is always relative to insts.
1176 // That's why we must use the macroassembler to generate a stub.
1177 MacroAssembler _masm(&cbuf);
1179 address base =
1180 __ start_a_stub(Compile::MAX_stubs_size);
1181 if (base == NULL) return; // CodeBuffer::expand failed
1182 // static stub relocation stores the instruction address of the call
1183 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1184 // static stub relocation also tags the methodOop in the code-stream.
1185 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1186 // This is recognized as unresolved by relocs/nativeInst/ic code
1187 __ jump(RuntimeAddress(__ pc()));
1189 __ end_a_stub();
1190 // Update current stubs pointer and restore insts_end.
1191 }
1192 // size of call stub, compiled java to interpretor
1193 uint size_java_to_interp() {
1194 return 10; // movl; jmp
1195 }
1196 // relocation entries for call stub, compiled java to interpretor
1197 uint reloc_java_to_interp() {
1198 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1199 }
1201 //=============================================================================
1202 #ifndef PRODUCT
1203 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1204 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1205 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1206 st->print_cr("\tNOP");
1207 st->print_cr("\tNOP");
1208 if( !OptoBreakpoint )
1209 st->print_cr("\tNOP");
1210 }
1211 #endif
1213 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1214 MacroAssembler masm(&cbuf);
1215 #ifdef ASSERT
1216 uint insts_size = cbuf.insts_size();
1217 #endif
1218 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1219 masm.jump_cc(Assembler::notEqual,
1220 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1221 /* WARNING these NOPs are critical so that verified entry point is properly
1222 aligned for patching by NativeJump::patch_verified_entry() */
1223 int nops_cnt = 2;
1224 if( !OptoBreakpoint ) // Leave space for int3
1225 nops_cnt += 1;
1226 masm.nop(nops_cnt);
1228 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1229 }
1231 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1232 return OptoBreakpoint ? 11 : 12;
1233 }
1236 //=============================================================================
1237 uint size_exception_handler() {
1238 // NativeCall instruction size is the same as NativeJump.
1239 // exception handler starts out as jump and can be patched to
1240 // a call be deoptimization. (4932387)
1241 // Note that this value is also credited (in output.cpp) to
1242 // the size of the code section.
1243 return NativeJump::instruction_size;
1244 }
1246 // Emit exception handler code. Stuff framesize into a register
1247 // and call a VM stub routine.
1248 int emit_exception_handler(CodeBuffer& cbuf) {
1250 // Note that the code buffer's insts_mark is always relative to insts.
1251 // That's why we must use the macroassembler to generate a handler.
1252 MacroAssembler _masm(&cbuf);
1253 address base =
1254 __ start_a_stub(size_exception_handler());
1255 if (base == NULL) return 0; // CodeBuffer::expand failed
1256 int offset = __ offset();
1257 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1258 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1259 __ end_a_stub();
1260 return offset;
1261 }
1263 uint size_deopt_handler() {
1264 // NativeCall instruction size is the same as NativeJump.
1265 // exception handler starts out as jump and can be patched to
1266 // a call be deoptimization. (4932387)
1267 // Note that this value is also credited (in output.cpp) to
1268 // the size of the code section.
1269 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1270 }
1272 // Emit deopt handler code.
1273 int emit_deopt_handler(CodeBuffer& cbuf) {
1275 // Note that the code buffer's insts_mark is always relative to insts.
1276 // That's why we must use the macroassembler to generate a handler.
1277 MacroAssembler _masm(&cbuf);
1278 address base =
1279 __ start_a_stub(size_exception_handler());
1280 if (base == NULL) return 0; // CodeBuffer::expand failed
1281 int offset = __ offset();
1282 InternalAddress here(__ pc());
1283 __ pushptr(here.addr());
1285 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1286 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1287 __ end_a_stub();
1288 return offset;
1289 }
1292 const bool Matcher::match_rule_supported(int opcode) {
1293 if (!has_match_rule(opcode))
1294 return false;
1296 switch (opcode) {
1297 case Op_PopCountI:
1298 case Op_PopCountL:
1299 if (!UsePopCountInstruction)
1300 return false;
1301 break;
1302 }
1304 return true; // Per default match rules are supported.
1305 }
1307 int Matcher::regnum_to_fpu_offset(int regnum) {
1308 return regnum - 32; // The FP registers are in the second chunk
1309 }
1311 // This is UltraSparc specific, true just means we have fast l2f conversion
1312 const bool Matcher::convL2FSupported(void) {
1313 return true;
1314 }
1316 // Vector width in bytes
1317 const uint Matcher::vector_width_in_bytes(void) {
1318 return UseSSE >= 2 ? 8 : 0;
1319 }
1321 // Vector ideal reg
1322 const uint Matcher::vector_ideal_reg(void) {
1323 return Op_RegD;
1324 }
1326 // Is this branch offset short enough that a short branch can be used?
1327 //
1328 // NOTE: If the platform does not provide any short branch variants, then
1329 // this method should return false for offset 0.
1330 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1331 // The passed offset is relative to address of the branch.
1332 // On 86 a branch displacement is calculated relative to address
1333 // of a next instruction.
1334 offset -= br_size;
1336 // the short version of jmpConUCF2 contains multiple branches,
1337 // making the reach slightly less
1338 if (rule == jmpConUCF2_rule)
1339 return (-126 <= offset && offset <= 125);
1340 return (-128 <= offset && offset <= 127);
1341 }
1343 const bool Matcher::isSimpleConstant64(jlong value) {
1344 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1345 return false;
1346 }
1348 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1349 const bool Matcher::init_array_count_is_in_bytes = false;
1351 // Threshold size for cleararray.
1352 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1354 // Needs 2 CMOV's for longs.
1355 const int Matcher::long_cmove_cost() { return 1; }
1357 // No CMOVF/CMOVD with SSE/SSE2
1358 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1360 // Should the Matcher clone shifts on addressing modes, expecting them to
1361 // be subsumed into complex addressing expressions or compute them into
1362 // registers? True for Intel but false for most RISCs
1363 const bool Matcher::clone_shift_expressions = true;
1365 // Do we need to mask the count passed to shift instructions or does
1366 // the cpu only look at the lower 5/6 bits anyway?
1367 const bool Matcher::need_masked_shift_count = false;
1369 bool Matcher::narrow_oop_use_complex_address() {
1370 ShouldNotCallThis();
1371 return true;
1372 }
1375 // Is it better to copy float constants, or load them directly from memory?
1376 // Intel can load a float constant from a direct address, requiring no
1377 // extra registers. Most RISCs will have to materialize an address into a
1378 // register first, so they would do better to copy the constant from stack.
1379 const bool Matcher::rematerialize_float_constants = true;
1381 // If CPU can load and store mis-aligned doubles directly then no fixup is
1382 // needed. Else we split the double into 2 integer pieces and move it
1383 // piece-by-piece. Only happens when passing doubles into C code as the
1384 // Java calling convention forces doubles to be aligned.
1385 const bool Matcher::misaligned_doubles_ok = true;
1388 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1389 // Get the memory operand from the node
1390 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1391 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1392 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1393 uint opcnt = 1; // First operand
1394 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1395 while( idx >= skipped+num_edges ) {
1396 skipped += num_edges;
1397 opcnt++; // Bump operand count
1398 assert( opcnt < numopnds, "Accessing non-existent operand" );
1399 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1400 }
1402 MachOper *memory = node->_opnds[opcnt];
1403 MachOper *new_memory = NULL;
1404 switch (memory->opcode()) {
1405 case DIRECT:
1406 case INDOFFSET32X:
1407 // No transformation necessary.
1408 return;
1409 case INDIRECT:
1410 new_memory = new (C) indirect_win95_safeOper( );
1411 break;
1412 case INDOFFSET8:
1413 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1414 break;
1415 case INDOFFSET32:
1416 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1417 break;
1418 case INDINDEXOFFSET:
1419 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1420 break;
1421 case INDINDEXSCALE:
1422 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1423 break;
1424 case INDINDEXSCALEOFFSET:
1425 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1426 break;
1427 case LOAD_LONG_INDIRECT:
1428 case LOAD_LONG_INDOFFSET32:
1429 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1430 return;
1431 default:
1432 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1433 return;
1434 }
1435 node->_opnds[opcnt] = new_memory;
1436 }
1438 // Advertise here if the CPU requires explicit rounding operations
1439 // to implement the UseStrictFP mode.
1440 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1442 // Are floats conerted to double when stored to stack during deoptimization?
1443 // On x32 it is stored with convertion only when FPU is used for floats.
1444 bool Matcher::float_in_double() { return (UseSSE == 0); }
1446 // Do ints take an entire long register or just half?
1447 const bool Matcher::int_in_long = false;
1449 // Return whether or not this register is ever used as an argument. This
1450 // function is used on startup to build the trampoline stubs in generateOptoStub.
1451 // Registers not mentioned will be killed by the VM call in the trampoline, and
1452 // arguments in those registers not be available to the callee.
1453 bool Matcher::can_be_java_arg( int reg ) {
1454 if( reg == ECX_num || reg == EDX_num ) return true;
1455 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1456 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1457 return false;
1458 }
1460 bool Matcher::is_spillable_arg( int reg ) {
1461 return can_be_java_arg(reg);
1462 }
1464 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1465 // Use hardware integer DIV instruction when
1466 // it is faster than a code which use multiply.
1467 // Only when constant divisor fits into 32 bit
1468 // (min_jint is excluded to get only correct
1469 // positive 32 bit values from negative).
1470 return VM_Version::has_fast_idiv() &&
1471 (divisor == (int)divisor && divisor != min_jint);
1472 }
1474 // Register for DIVI projection of divmodI
1475 RegMask Matcher::divI_proj_mask() {
1476 return EAX_REG_mask();
1477 }
1479 // Register for MODI projection of divmodI
1480 RegMask Matcher::modI_proj_mask() {
1481 return EDX_REG_mask();
1482 }
1484 // Register for DIVL projection of divmodL
1485 RegMask Matcher::divL_proj_mask() {
1486 ShouldNotReachHere();
1487 return RegMask();
1488 }
1490 // Register for MODL projection of divmodL
1491 RegMask Matcher::modL_proj_mask() {
1492 ShouldNotReachHere();
1493 return RegMask();
1494 }
1496 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1497 return EBP_REG_mask();
1498 }
1500 // Returns true if the high 32 bits of the value is known to be zero.
1501 bool is_operand_hi32_zero(Node* n) {
1502 int opc = n->Opcode();
1503 if (opc == Op_LoadUI2L) {
1504 return true;
1505 }
1506 if (opc == Op_AndL) {
1507 Node* o2 = n->in(2);
1508 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1509 return true;
1510 }
1511 }
1512 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1513 return true;
1514 }
1515 return false;
1516 }
1518 %}
1520 //----------ENCODING BLOCK-----------------------------------------------------
1521 // This block specifies the encoding classes used by the compiler to output
1522 // byte streams. Encoding classes generate functions which are called by
1523 // Machine Instruction Nodes in order to generate the bit encoding of the
1524 // instruction. Operands specify their base encoding interface with the
1525 // interface keyword. There are currently supported four interfaces,
1526 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1527 // operand to generate a function which returns its register number when
1528 // queried. CONST_INTER causes an operand to generate a function which
1529 // returns the value of the constant when queried. MEMORY_INTER causes an
1530 // operand to generate four functions which return the Base Register, the
1531 // Index Register, the Scale Value, and the Offset Value of the operand when
1532 // queried. COND_INTER causes an operand to generate six functions which
1533 // return the encoding code (ie - encoding bits for the instruction)
1534 // associated with each basic boolean condition for a conditional instruction.
1535 // Instructions specify two basic values for encoding. They use the
1536 // ins_encode keyword to specify their encoding class (which must be one of
1537 // the class names specified in the encoding block), and they use the
1538 // opcode keyword to specify, in order, their primary, secondary, and
1539 // tertiary opcode. Only the opcode sections which a particular instruction
1540 // needs for encoding need to be specified.
1541 encode %{
1542 // Build emit functions for each basic byte or larger field in the intel
1543 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1544 // code in the enc_class source block. Emit functions will live in the
1545 // main source block for now. In future, we can generalize this by
1546 // adding a syntax that specifies the sizes of fields in an order,
1547 // so that the adlc can build the emit functions automagically
1549 // Emit primary opcode
1550 enc_class OpcP %{
1551 emit_opcode(cbuf, $primary);
1552 %}
1554 // Emit secondary opcode
1555 enc_class OpcS %{
1556 emit_opcode(cbuf, $secondary);
1557 %}
1559 // Emit opcode directly
1560 enc_class Opcode(immI d8) %{
1561 emit_opcode(cbuf, $d8$$constant);
1562 %}
1564 enc_class SizePrefix %{
1565 emit_opcode(cbuf,0x66);
1566 %}
1568 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1569 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1570 %}
1572 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1573 emit_opcode(cbuf,$opcode$$constant);
1574 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1575 %}
1577 enc_class mov_r32_imm0( eRegI dst ) %{
1578 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1579 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1580 %}
1582 enc_class cdq_enc %{
1583 // Full implementation of Java idiv and irem; checks for
1584 // special case as described in JVM spec., p.243 & p.271.
1585 //
1586 // normal case special case
1587 //
1588 // input : rax,: dividend min_int
1589 // reg: divisor -1
1590 //
1591 // output: rax,: quotient (= rax, idiv reg) min_int
1592 // rdx: remainder (= rax, irem reg) 0
1593 //
1594 // Code sequnce:
1595 //
1596 // 81 F8 00 00 00 80 cmp rax,80000000h
1597 // 0F 85 0B 00 00 00 jne normal_case
1598 // 33 D2 xor rdx,edx
1599 // 83 F9 FF cmp rcx,0FFh
1600 // 0F 84 03 00 00 00 je done
1601 // normal_case:
1602 // 99 cdq
1603 // F7 F9 idiv rax,ecx
1604 // done:
1605 //
1606 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1607 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1608 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1609 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1610 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1611 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1612 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1613 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1614 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1615 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1616 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1617 // normal_case:
1618 emit_opcode(cbuf,0x99); // cdq
1619 // idiv (note: must be emitted by the user of this rule)
1620 // normal:
1621 %}
1623 // Dense encoding for older common ops
1624 enc_class Opc_plus(immI opcode, eRegI reg) %{
1625 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1626 %}
1629 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1630 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1631 // Check for 8-bit immediate, and set sign extend bit in opcode
1632 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1633 emit_opcode(cbuf, $primary | 0x02);
1634 }
1635 else { // If 32-bit immediate
1636 emit_opcode(cbuf, $primary);
1637 }
1638 %}
1640 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1641 // Emit primary opcode and set sign-extend bit
1642 // Check for 8-bit immediate, and set sign extend bit in opcode
1643 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1644 emit_opcode(cbuf, $primary | 0x02); }
1645 else { // If 32-bit immediate
1646 emit_opcode(cbuf, $primary);
1647 }
1648 // Emit r/m byte with secondary opcode, after primary opcode.
1649 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1650 %}
1652 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1653 // Check for 8-bit immediate, and set sign extend bit in opcode
1654 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1655 $$$emit8$imm$$constant;
1656 }
1657 else { // If 32-bit immediate
1658 // Output immediate
1659 $$$emit32$imm$$constant;
1660 }
1661 %}
1663 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1664 // Emit primary opcode and set sign-extend bit
1665 // Check for 8-bit immediate, and set sign extend bit in opcode
1666 int con = (int)$imm$$constant; // Throw away top bits
1667 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1668 // Emit r/m byte with secondary opcode, after primary opcode.
1669 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1670 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1671 else emit_d32(cbuf,con);
1672 %}
1674 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1675 // Emit primary opcode and set sign-extend bit
1676 // Check for 8-bit immediate, and set sign extend bit in opcode
1677 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1678 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1679 // Emit r/m byte with tertiary opcode, after primary opcode.
1680 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1681 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1682 else emit_d32(cbuf,con);
1683 %}
1685 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1686 emit_cc(cbuf, $secondary, $dst$$reg );
1687 %}
1689 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1690 int destlo = $dst$$reg;
1691 int desthi = HIGH_FROM_LOW(destlo);
1692 // bswap lo
1693 emit_opcode(cbuf, 0x0F);
1694 emit_cc(cbuf, 0xC8, destlo);
1695 // bswap hi
1696 emit_opcode(cbuf, 0x0F);
1697 emit_cc(cbuf, 0xC8, desthi);
1698 // xchg lo and hi
1699 emit_opcode(cbuf, 0x87);
1700 emit_rm(cbuf, 0x3, destlo, desthi);
1701 %}
1703 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1704 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1705 %}
1707 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1708 $$$emit8$primary;
1709 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1710 %}
1712 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1713 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1714 emit_d8(cbuf, op >> 8 );
1715 emit_d8(cbuf, op & 255);
1716 %}
1718 // emulate a CMOV with a conditional branch around a MOV
1719 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1720 // Invert sense of branch from sense of CMOV
1721 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1722 emit_d8( cbuf, $brOffs$$constant );
1723 %}
1725 enc_class enc_PartialSubtypeCheck( ) %{
1726 Register Redi = as_Register(EDI_enc); // result register
1727 Register Reax = as_Register(EAX_enc); // super class
1728 Register Recx = as_Register(ECX_enc); // killed
1729 Register Resi = as_Register(ESI_enc); // sub class
1730 Label miss;
1732 MacroAssembler _masm(&cbuf);
1733 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1734 NULL, &miss,
1735 /*set_cond_codes:*/ true);
1736 if ($primary) {
1737 __ xorptr(Redi, Redi);
1738 }
1739 __ bind(miss);
1740 %}
1742 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1743 MacroAssembler masm(&cbuf);
1744 int start = masm.offset();
1745 if (UseSSE >= 2) {
1746 if (VerifyFPU) {
1747 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1748 }
1749 } else {
1750 // External c_calling_convention expects the FPU stack to be 'clean'.
1751 // Compiled code leaves it dirty. Do cleanup now.
1752 masm.empty_FPU_stack();
1753 }
1754 if (sizeof_FFree_Float_Stack_All == -1) {
1755 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1756 } else {
1757 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1758 }
1759 %}
1761 enc_class Verify_FPU_For_Leaf %{
1762 if( VerifyFPU ) {
1763 MacroAssembler masm(&cbuf);
1764 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1765 }
1766 %}
1768 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1769 // This is the instruction starting address for relocation info.
1770 cbuf.set_insts_mark();
1771 $$$emit8$primary;
1772 // CALL directly to the runtime
1773 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1774 runtime_call_Relocation::spec(), RELOC_IMM32 );
1776 if (UseSSE >= 2) {
1777 MacroAssembler _masm(&cbuf);
1778 BasicType rt = tf()->return_type();
1780 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1781 // A C runtime call where the return value is unused. In SSE2+
1782 // mode the result needs to be removed from the FPU stack. It's
1783 // likely that this function call could be removed by the
1784 // optimizer if the C function is a pure function.
1785 __ ffree(0);
1786 } else if (rt == T_FLOAT) {
1787 __ lea(rsp, Address(rsp, -4));
1788 __ fstp_s(Address(rsp, 0));
1789 __ movflt(xmm0, Address(rsp, 0));
1790 __ lea(rsp, Address(rsp, 4));
1791 } else if (rt == T_DOUBLE) {
1792 __ lea(rsp, Address(rsp, -8));
1793 __ fstp_d(Address(rsp, 0));
1794 __ movdbl(xmm0, Address(rsp, 0));
1795 __ lea(rsp, Address(rsp, 8));
1796 }
1797 }
1798 %}
1801 enc_class pre_call_FPU %{
1802 // If method sets FPU control word restore it here
1803 debug_only(int off0 = cbuf.insts_size());
1804 if( Compile::current()->in_24_bit_fp_mode() ) {
1805 MacroAssembler masm(&cbuf);
1806 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1807 }
1808 debug_only(int off1 = cbuf.insts_size());
1809 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1810 %}
1812 enc_class post_call_FPU %{
1813 // If method sets FPU control word do it here also
1814 if( Compile::current()->in_24_bit_fp_mode() ) {
1815 MacroAssembler masm(&cbuf);
1816 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1817 }
1818 %}
1820 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1821 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1822 // who we intended to call.
1823 cbuf.set_insts_mark();
1824 $$$emit8$primary;
1825 if ( !_method ) {
1826 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1827 runtime_call_Relocation::spec(), RELOC_IMM32 );
1828 } else if(_optimized_virtual) {
1829 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1830 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1831 } else {
1832 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1833 static_call_Relocation::spec(), RELOC_IMM32 );
1834 }
1835 if( _method ) { // Emit stub for static call
1836 emit_java_to_interp(cbuf);
1837 }
1838 %}
1840 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1841 // !!!!!
1842 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1843 // emit_call_dynamic_prologue( cbuf );
1844 cbuf.set_insts_mark();
1845 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1846 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1847 address virtual_call_oop_addr = cbuf.insts_mark();
1848 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1849 // who we intended to call.
1850 cbuf.set_insts_mark();
1851 $$$emit8$primary;
1852 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1853 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1854 %}
1856 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1857 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1858 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1860 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1861 cbuf.set_insts_mark();
1862 $$$emit8$primary;
1863 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1864 emit_d8(cbuf, disp); // Displacement
1866 %}
1868 // Following encoding is no longer used, but may be restored if calling
1869 // convention changes significantly.
1870 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1871 //
1872 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1873 // // int ic_reg = Matcher::inline_cache_reg();
1874 // // int ic_encode = Matcher::_regEncode[ic_reg];
1875 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1876 // // int imo_encode = Matcher::_regEncode[imo_reg];
1877 //
1878 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1879 // // // so we load it immediately before the call
1880 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1881 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1882 //
1883 // // xor rbp,ebp
1884 // emit_opcode(cbuf, 0x33);
1885 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1886 //
1887 // // CALL to interpreter.
1888 // cbuf.set_insts_mark();
1889 // $$$emit8$primary;
1890 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1891 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1892 // %}
1894 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1895 $$$emit8$primary;
1896 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1897 $$$emit8$shift$$constant;
1898 %}
1900 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1901 // Load immediate does not have a zero or sign extended version
1902 // for 8-bit immediates
1903 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1904 $$$emit32$src$$constant;
1905 %}
1907 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1908 // Load immediate does not have a zero or sign extended version
1909 // for 8-bit immediates
1910 emit_opcode(cbuf, $primary + $dst$$reg);
1911 $$$emit32$src$$constant;
1912 %}
1914 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1915 // Load immediate does not have a zero or sign extended version
1916 // for 8-bit immediates
1917 int dst_enc = $dst$$reg;
1918 int src_con = $src$$constant & 0x0FFFFFFFFL;
1919 if (src_con == 0) {
1920 // xor dst, dst
1921 emit_opcode(cbuf, 0x33);
1922 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1923 } else {
1924 emit_opcode(cbuf, $primary + dst_enc);
1925 emit_d32(cbuf, src_con);
1926 }
1927 %}
1929 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1930 // Load immediate does not have a zero or sign extended version
1931 // for 8-bit immediates
1932 int dst_enc = $dst$$reg + 2;
1933 int src_con = ((julong)($src$$constant)) >> 32;
1934 if (src_con == 0) {
1935 // xor dst, dst
1936 emit_opcode(cbuf, 0x33);
1937 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1938 } else {
1939 emit_opcode(cbuf, $primary + dst_enc);
1940 emit_d32(cbuf, src_con);
1941 }
1942 %}
1945 // Encode a reg-reg copy. If it is useless, then empty encoding.
1946 enc_class enc_Copy( eRegI dst, eRegI src ) %{
1947 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1948 %}
1950 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
1951 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1952 %}
1954 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1955 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1956 %}
1958 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
1959 $$$emit8$primary;
1960 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1961 %}
1963 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
1964 $$$emit8$secondary;
1965 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1966 %}
1968 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
1969 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1970 %}
1972 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
1973 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1974 %}
1976 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
1977 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
1978 %}
1980 enc_class Con32 (immI src) %{ // Con32(storeImmI)
1981 // Output immediate
1982 $$$emit32$src$$constant;
1983 %}
1985 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
1986 // Output Float immediate bits
1987 jfloat jf = $src$$constant;
1988 int jf_as_bits = jint_cast( jf );
1989 emit_d32(cbuf, jf_as_bits);
1990 %}
1992 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
1993 // Output Float immediate bits
1994 jfloat jf = $src$$constant;
1995 int jf_as_bits = jint_cast( jf );
1996 emit_d32(cbuf, jf_as_bits);
1997 %}
1999 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2000 // Output immediate
2001 $$$emit16$src$$constant;
2002 %}
2004 enc_class Con_d32(immI src) %{
2005 emit_d32(cbuf,$src$$constant);
2006 %}
2008 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2009 // Output immediate memory reference
2010 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2011 emit_d32(cbuf, 0x00);
2012 %}
2014 enc_class lock_prefix( ) %{
2015 if( os::is_MP() )
2016 emit_opcode(cbuf,0xF0); // [Lock]
2017 %}
2019 // Cmp-xchg long value.
2020 // Note: we need to swap rbx, and rcx before and after the
2021 // cmpxchg8 instruction because the instruction uses
2022 // rcx as the high order word of the new value to store but
2023 // our register encoding uses rbx,.
2024 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2026 // XCHG rbx,ecx
2027 emit_opcode(cbuf,0x87);
2028 emit_opcode(cbuf,0xD9);
2029 // [Lock]
2030 if( os::is_MP() )
2031 emit_opcode(cbuf,0xF0);
2032 // CMPXCHG8 [Eptr]
2033 emit_opcode(cbuf,0x0F);
2034 emit_opcode(cbuf,0xC7);
2035 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2036 // XCHG rbx,ecx
2037 emit_opcode(cbuf,0x87);
2038 emit_opcode(cbuf,0xD9);
2039 %}
2041 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2042 // [Lock]
2043 if( os::is_MP() )
2044 emit_opcode(cbuf,0xF0);
2046 // CMPXCHG [Eptr]
2047 emit_opcode(cbuf,0x0F);
2048 emit_opcode(cbuf,0xB1);
2049 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2050 %}
2052 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2053 int res_encoding = $res$$reg;
2055 // MOV res,0
2056 emit_opcode( cbuf, 0xB8 + res_encoding);
2057 emit_d32( cbuf, 0 );
2058 // JNE,s fail
2059 emit_opcode(cbuf,0x75);
2060 emit_d8(cbuf, 5 );
2061 // MOV res,1
2062 emit_opcode( cbuf, 0xB8 + res_encoding);
2063 emit_d32( cbuf, 1 );
2064 // fail:
2065 %}
2067 enc_class set_instruction_start( ) %{
2068 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2069 %}
2071 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2072 int reg_encoding = $ereg$$reg;
2073 int base = $mem$$base;
2074 int index = $mem$$index;
2075 int scale = $mem$$scale;
2076 int displace = $mem$$disp;
2077 bool disp_is_oop = $mem->disp_is_oop();
2078 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2079 %}
2081 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2082 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2083 int base = $mem$$base;
2084 int index = $mem$$index;
2085 int scale = $mem$$scale;
2086 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2087 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2088 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2089 %}
2091 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2092 int r1, r2;
2093 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2094 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2095 emit_opcode(cbuf,0x0F);
2096 emit_opcode(cbuf,$tertiary);
2097 emit_rm(cbuf, 0x3, r1, r2);
2098 emit_d8(cbuf,$cnt$$constant);
2099 emit_d8(cbuf,$primary);
2100 emit_rm(cbuf, 0x3, $secondary, r1);
2101 emit_d8(cbuf,$cnt$$constant);
2102 %}
2104 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2105 emit_opcode( cbuf, 0x8B ); // Move
2106 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2107 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2108 emit_d8(cbuf,$primary);
2109 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2110 emit_d8(cbuf,$cnt$$constant-32);
2111 }
2112 emit_d8(cbuf,$primary);
2113 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2114 emit_d8(cbuf,31);
2115 %}
2117 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2118 int r1, r2;
2119 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2120 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2122 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2123 emit_rm(cbuf, 0x3, r1, r2);
2124 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2125 emit_opcode(cbuf,$primary);
2126 emit_rm(cbuf, 0x3, $secondary, r1);
2127 emit_d8(cbuf,$cnt$$constant-32);
2128 }
2129 emit_opcode(cbuf,0x33); // XOR r2,r2
2130 emit_rm(cbuf, 0x3, r2, r2);
2131 %}
2133 // Clone of RegMem but accepts an extra parameter to access each
2134 // half of a double in memory; it never needs relocation info.
2135 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2136 emit_opcode(cbuf,$opcode$$constant);
2137 int reg_encoding = $rm_reg$$reg;
2138 int base = $mem$$base;
2139 int index = $mem$$index;
2140 int scale = $mem$$scale;
2141 int displace = $mem$$disp + $disp_for_half$$constant;
2142 bool disp_is_oop = false;
2143 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2144 %}
2146 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2147 //
2148 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2149 // and it never needs relocation information.
2150 // Frequently used to move data between FPU's Stack Top and memory.
2151 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2152 int rm_byte_opcode = $rm_opcode$$constant;
2153 int base = $mem$$base;
2154 int index = $mem$$index;
2155 int scale = $mem$$scale;
2156 int displace = $mem$$disp;
2157 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2158 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2159 %}
2161 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2162 int rm_byte_opcode = $rm_opcode$$constant;
2163 int base = $mem$$base;
2164 int index = $mem$$index;
2165 int scale = $mem$$scale;
2166 int displace = $mem$$disp;
2167 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2168 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2169 %}
2171 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2172 int reg_encoding = $dst$$reg;
2173 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2174 int index = 0x04; // 0x04 indicates no index
2175 int scale = 0x00; // 0x00 indicates no scale
2176 int displace = $src1$$constant; // 0x00 indicates no displacement
2177 bool disp_is_oop = false;
2178 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2179 %}
2181 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2182 // Compare dst,src
2183 emit_opcode(cbuf,0x3B);
2184 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2185 // jmp dst < src around move
2186 emit_opcode(cbuf,0x7C);
2187 emit_d8(cbuf,2);
2188 // move dst,src
2189 emit_opcode(cbuf,0x8B);
2190 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2191 %}
2193 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2194 // Compare dst,src
2195 emit_opcode(cbuf,0x3B);
2196 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2197 // jmp dst > src around move
2198 emit_opcode(cbuf,0x7F);
2199 emit_d8(cbuf,2);
2200 // move dst,src
2201 emit_opcode(cbuf,0x8B);
2202 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2203 %}
2205 enc_class enc_FPR_store(memory mem, regDPR src) %{
2206 // If src is FPR1, we can just FST to store it.
2207 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2208 int reg_encoding = 0x2; // Just store
2209 int base = $mem$$base;
2210 int index = $mem$$index;
2211 int scale = $mem$$scale;
2212 int displace = $mem$$disp;
2213 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2214 if( $src$$reg != FPR1L_enc ) {
2215 reg_encoding = 0x3; // Store & pop
2216 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2217 emit_d8( cbuf, 0xC0-1+$src$$reg );
2218 }
2219 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2220 emit_opcode(cbuf,$primary);
2221 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2222 %}
2224 enc_class neg_reg(eRegI dst) %{
2225 // NEG $dst
2226 emit_opcode(cbuf,0xF7);
2227 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2228 %}
2230 enc_class setLT_reg(eCXRegI dst) %{
2231 // SETLT $dst
2232 emit_opcode(cbuf,0x0F);
2233 emit_opcode(cbuf,0x9C);
2234 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2235 %}
2237 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2238 int tmpReg = $tmp$$reg;
2240 // SUB $p,$q
2241 emit_opcode(cbuf,0x2B);
2242 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2243 // SBB $tmp,$tmp
2244 emit_opcode(cbuf,0x1B);
2245 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2246 // AND $tmp,$y
2247 emit_opcode(cbuf,0x23);
2248 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2249 // ADD $p,$tmp
2250 emit_opcode(cbuf,0x03);
2251 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2252 %}
2254 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2255 int tmpReg = $tmp$$reg;
2257 // SUB $p,$q
2258 emit_opcode(cbuf,0x2B);
2259 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2260 // SBB $tmp,$tmp
2261 emit_opcode(cbuf,0x1B);
2262 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2263 // AND $tmp,$y
2264 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2265 emit_opcode(cbuf,0x23);
2266 int reg_encoding = tmpReg;
2267 int base = $mem$$base;
2268 int index = $mem$$index;
2269 int scale = $mem$$scale;
2270 int displace = $mem$$disp;
2271 bool disp_is_oop = $mem->disp_is_oop();
2272 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2273 // ADD $p,$tmp
2274 emit_opcode(cbuf,0x03);
2275 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2276 %}
2278 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2279 // TEST shift,32
2280 emit_opcode(cbuf,0xF7);
2281 emit_rm(cbuf, 0x3, 0, ECX_enc);
2282 emit_d32(cbuf,0x20);
2283 // JEQ,s small
2284 emit_opcode(cbuf, 0x74);
2285 emit_d8(cbuf, 0x04);
2286 // MOV $dst.hi,$dst.lo
2287 emit_opcode( cbuf, 0x8B );
2288 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2289 // CLR $dst.lo
2290 emit_opcode(cbuf, 0x33);
2291 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2292 // small:
2293 // SHLD $dst.hi,$dst.lo,$shift
2294 emit_opcode(cbuf,0x0F);
2295 emit_opcode(cbuf,0xA5);
2296 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2297 // SHL $dst.lo,$shift"
2298 emit_opcode(cbuf,0xD3);
2299 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2300 %}
2302 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2303 // TEST shift,32
2304 emit_opcode(cbuf,0xF7);
2305 emit_rm(cbuf, 0x3, 0, ECX_enc);
2306 emit_d32(cbuf,0x20);
2307 // JEQ,s small
2308 emit_opcode(cbuf, 0x74);
2309 emit_d8(cbuf, 0x04);
2310 // MOV $dst.lo,$dst.hi
2311 emit_opcode( cbuf, 0x8B );
2312 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2313 // CLR $dst.hi
2314 emit_opcode(cbuf, 0x33);
2315 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2316 // small:
2317 // SHRD $dst.lo,$dst.hi,$shift
2318 emit_opcode(cbuf,0x0F);
2319 emit_opcode(cbuf,0xAD);
2320 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2321 // SHR $dst.hi,$shift"
2322 emit_opcode(cbuf,0xD3);
2323 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2324 %}
2326 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2327 // TEST shift,32
2328 emit_opcode(cbuf,0xF7);
2329 emit_rm(cbuf, 0x3, 0, ECX_enc);
2330 emit_d32(cbuf,0x20);
2331 // JEQ,s small
2332 emit_opcode(cbuf, 0x74);
2333 emit_d8(cbuf, 0x05);
2334 // MOV $dst.lo,$dst.hi
2335 emit_opcode( cbuf, 0x8B );
2336 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2337 // SAR $dst.hi,31
2338 emit_opcode(cbuf, 0xC1);
2339 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2340 emit_d8(cbuf, 0x1F );
2341 // small:
2342 // SHRD $dst.lo,$dst.hi,$shift
2343 emit_opcode(cbuf,0x0F);
2344 emit_opcode(cbuf,0xAD);
2345 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2346 // SAR $dst.hi,$shift"
2347 emit_opcode(cbuf,0xD3);
2348 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2349 %}
2352 // ----------------- Encodings for floating point unit -----------------
2353 // May leave result in FPU-TOS or FPU reg depending on opcodes
2354 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2355 $$$emit8$primary;
2356 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2357 %}
2359 // Pop argument in FPR0 with FSTP ST(0)
2360 enc_class PopFPU() %{
2361 emit_opcode( cbuf, 0xDD );
2362 emit_d8( cbuf, 0xD8 );
2363 %}
2365 // !!!!! equivalent to Pop_Reg_F
2366 enc_class Pop_Reg_DPR( regDPR dst ) %{
2367 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2368 emit_d8( cbuf, 0xD8+$dst$$reg );
2369 %}
2371 enc_class Push_Reg_DPR( regDPR dst ) %{
2372 emit_opcode( cbuf, 0xD9 );
2373 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2374 %}
2376 enc_class strictfp_bias1( regDPR dst ) %{
2377 emit_opcode( cbuf, 0xDB ); // FLD m80real
2378 emit_opcode( cbuf, 0x2D );
2379 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2380 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2381 emit_opcode( cbuf, 0xC8+$dst$$reg );
2382 %}
2384 enc_class strictfp_bias2( regDPR dst ) %{
2385 emit_opcode( cbuf, 0xDB ); // FLD m80real
2386 emit_opcode( cbuf, 0x2D );
2387 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2388 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2389 emit_opcode( cbuf, 0xC8+$dst$$reg );
2390 %}
2392 // Special case for moving an integer register to a stack slot.
2393 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2394 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2395 %}
2397 // Special case for moving a register to a stack slot.
2398 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2399 // Opcode already emitted
2400 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2401 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2402 emit_d32(cbuf, $dst$$disp); // Displacement
2403 %}
2405 // Push the integer in stackSlot 'src' onto FP-stack
2406 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2407 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2408 %}
2410 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2411 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2412 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2413 %}
2415 // Same as Pop_Mem_F except for opcode
2416 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2417 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2418 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2419 %}
2421 enc_class Pop_Reg_FPR( regFPR dst ) %{
2422 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2423 emit_d8( cbuf, 0xD8+$dst$$reg );
2424 %}
2426 enc_class Push_Reg_FPR( regFPR dst ) %{
2427 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2428 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2429 %}
2431 // Push FPU's float to a stack-slot, and pop FPU-stack
2432 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2433 int pop = 0x02;
2434 if ($src$$reg != FPR1L_enc) {
2435 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2436 emit_d8( cbuf, 0xC0-1+$src$$reg );
2437 pop = 0x03;
2438 }
2439 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2440 %}
2442 // Push FPU's double to a stack-slot, and pop FPU-stack
2443 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2444 int pop = 0x02;
2445 if ($src$$reg != FPR1L_enc) {
2446 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2447 emit_d8( cbuf, 0xC0-1+$src$$reg );
2448 pop = 0x03;
2449 }
2450 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2451 %}
2453 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2454 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2455 int pop = 0xD0 - 1; // -1 since we skip FLD
2456 if ($src$$reg != FPR1L_enc) {
2457 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2458 emit_d8( cbuf, 0xC0-1+$src$$reg );
2459 pop = 0xD8;
2460 }
2461 emit_opcode( cbuf, 0xDD );
2462 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2463 %}
2466 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2467 // load dst in FPR0
2468 emit_opcode( cbuf, 0xD9 );
2469 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2470 if ($src$$reg != FPR1L_enc) {
2471 // fincstp
2472 emit_opcode (cbuf, 0xD9);
2473 emit_opcode (cbuf, 0xF7);
2474 // swap src with FPR1:
2475 // FXCH FPR1 with src
2476 emit_opcode(cbuf, 0xD9);
2477 emit_d8(cbuf, 0xC8-1+$src$$reg );
2478 // fdecstp
2479 emit_opcode (cbuf, 0xD9);
2480 emit_opcode (cbuf, 0xF6);
2481 }
2482 %}
2484 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2485 MacroAssembler _masm(&cbuf);
2486 __ subptr(rsp, 8);
2487 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2488 __ fld_d(Address(rsp, 0));
2489 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2490 __ fld_d(Address(rsp, 0));
2491 %}
2493 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2494 MacroAssembler _masm(&cbuf);
2495 __ subptr(rsp, 4);
2496 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2497 __ fld_s(Address(rsp, 0));
2498 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2499 __ fld_s(Address(rsp, 0));
2500 %}
2502 enc_class Push_ResultD(regD dst) %{
2503 MacroAssembler _masm(&cbuf);
2504 __ fstp_d(Address(rsp, 0));
2505 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2506 __ addptr(rsp, 8);
2507 %}
2509 enc_class Push_ResultF(regF dst, immI d8) %{
2510 MacroAssembler _masm(&cbuf);
2511 __ fstp_s(Address(rsp, 0));
2512 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2513 __ addptr(rsp, $d8$$constant);
2514 %}
2516 enc_class Push_SrcD(regD src) %{
2517 MacroAssembler _masm(&cbuf);
2518 __ subptr(rsp, 8);
2519 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2520 __ fld_d(Address(rsp, 0));
2521 %}
2523 enc_class push_stack_temp_qword() %{
2524 MacroAssembler _masm(&cbuf);
2525 __ subptr(rsp, 8);
2526 %}
2528 enc_class pop_stack_temp_qword() %{
2529 MacroAssembler _masm(&cbuf);
2530 __ addptr(rsp, 8);
2531 %}
2533 enc_class push_xmm_to_fpr1(regD src) %{
2534 MacroAssembler _masm(&cbuf);
2535 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2536 __ fld_d(Address(rsp, 0));
2537 %}
2539 enc_class Push_Result_Mod_DPR( regDPR src) %{
2540 if ($src$$reg != FPR1L_enc) {
2541 // fincstp
2542 emit_opcode (cbuf, 0xD9);
2543 emit_opcode (cbuf, 0xF7);
2544 // FXCH FPR1 with src
2545 emit_opcode(cbuf, 0xD9);
2546 emit_d8(cbuf, 0xC8-1+$src$$reg );
2547 // fdecstp
2548 emit_opcode (cbuf, 0xD9);
2549 emit_opcode (cbuf, 0xF6);
2550 }
2551 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2552 // // FSTP FPR$dst$$reg
2553 // emit_opcode( cbuf, 0xDD );
2554 // emit_d8( cbuf, 0xD8+$dst$$reg );
2555 %}
2557 enc_class fnstsw_sahf_skip_parity() %{
2558 // fnstsw ax
2559 emit_opcode( cbuf, 0xDF );
2560 emit_opcode( cbuf, 0xE0 );
2561 // sahf
2562 emit_opcode( cbuf, 0x9E );
2563 // jnp ::skip
2564 emit_opcode( cbuf, 0x7B );
2565 emit_opcode( cbuf, 0x05 );
2566 %}
2568 enc_class emitModDPR() %{
2569 // fprem must be iterative
2570 // :: loop
2571 // fprem
2572 emit_opcode( cbuf, 0xD9 );
2573 emit_opcode( cbuf, 0xF8 );
2574 // wait
2575 emit_opcode( cbuf, 0x9b );
2576 // fnstsw ax
2577 emit_opcode( cbuf, 0xDF );
2578 emit_opcode( cbuf, 0xE0 );
2579 // sahf
2580 emit_opcode( cbuf, 0x9E );
2581 // jp ::loop
2582 emit_opcode( cbuf, 0x0F );
2583 emit_opcode( cbuf, 0x8A );
2584 emit_opcode( cbuf, 0xF4 );
2585 emit_opcode( cbuf, 0xFF );
2586 emit_opcode( cbuf, 0xFF );
2587 emit_opcode( cbuf, 0xFF );
2588 %}
2590 enc_class fpu_flags() %{
2591 // fnstsw_ax
2592 emit_opcode( cbuf, 0xDF);
2593 emit_opcode( cbuf, 0xE0);
2594 // test ax,0x0400
2595 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2596 emit_opcode( cbuf, 0xA9 );
2597 emit_d16 ( cbuf, 0x0400 );
2598 // // // This sequence works, but stalls for 12-16 cycles on PPro
2599 // // test rax,0x0400
2600 // emit_opcode( cbuf, 0xA9 );
2601 // emit_d32 ( cbuf, 0x00000400 );
2602 //
2603 // jz exit (no unordered comparison)
2604 emit_opcode( cbuf, 0x74 );
2605 emit_d8 ( cbuf, 0x02 );
2606 // mov ah,1 - treat as LT case (set carry flag)
2607 emit_opcode( cbuf, 0xB4 );
2608 emit_d8 ( cbuf, 0x01 );
2609 // sahf
2610 emit_opcode( cbuf, 0x9E);
2611 %}
2613 enc_class cmpF_P6_fixup() %{
2614 // Fixup the integer flags in case comparison involved a NaN
2615 //
2616 // JNP exit (no unordered comparison, P-flag is set by NaN)
2617 emit_opcode( cbuf, 0x7B );
2618 emit_d8 ( cbuf, 0x03 );
2619 // MOV AH,1 - treat as LT case (set carry flag)
2620 emit_opcode( cbuf, 0xB4 );
2621 emit_d8 ( cbuf, 0x01 );
2622 // SAHF
2623 emit_opcode( cbuf, 0x9E);
2624 // NOP // target for branch to avoid branch to branch
2625 emit_opcode( cbuf, 0x90);
2626 %}
2628 // fnstsw_ax();
2629 // sahf();
2630 // movl(dst, nan_result);
2631 // jcc(Assembler::parity, exit);
2632 // movl(dst, less_result);
2633 // jcc(Assembler::below, exit);
2634 // movl(dst, equal_result);
2635 // jcc(Assembler::equal, exit);
2636 // movl(dst, greater_result);
2638 // less_result = 1;
2639 // greater_result = -1;
2640 // equal_result = 0;
2641 // nan_result = -1;
2643 enc_class CmpF_Result(eRegI dst) %{
2644 // fnstsw_ax();
2645 emit_opcode( cbuf, 0xDF);
2646 emit_opcode( cbuf, 0xE0);
2647 // sahf
2648 emit_opcode( cbuf, 0x9E);
2649 // movl(dst, nan_result);
2650 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2651 emit_d32( cbuf, -1 );
2652 // jcc(Assembler::parity, exit);
2653 emit_opcode( cbuf, 0x7A );
2654 emit_d8 ( cbuf, 0x13 );
2655 // movl(dst, less_result);
2656 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2657 emit_d32( cbuf, -1 );
2658 // jcc(Assembler::below, exit);
2659 emit_opcode( cbuf, 0x72 );
2660 emit_d8 ( cbuf, 0x0C );
2661 // movl(dst, equal_result);
2662 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2663 emit_d32( cbuf, 0 );
2664 // jcc(Assembler::equal, exit);
2665 emit_opcode( cbuf, 0x74 );
2666 emit_d8 ( cbuf, 0x05 );
2667 // movl(dst, greater_result);
2668 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2669 emit_d32( cbuf, 1 );
2670 %}
2673 // Compare the longs and set flags
2674 // BROKEN! Do Not use as-is
2675 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2676 // CMP $src1.hi,$src2.hi
2677 emit_opcode( cbuf, 0x3B );
2678 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2679 // JNE,s done
2680 emit_opcode(cbuf,0x75);
2681 emit_d8(cbuf, 2 );
2682 // CMP $src1.lo,$src2.lo
2683 emit_opcode( cbuf, 0x3B );
2684 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2685 // done:
2686 %}
2688 enc_class convert_int_long( regL dst, eRegI src ) %{
2689 // mov $dst.lo,$src
2690 int dst_encoding = $dst$$reg;
2691 int src_encoding = $src$$reg;
2692 encode_Copy( cbuf, dst_encoding , src_encoding );
2693 // mov $dst.hi,$src
2694 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2695 // sar $dst.hi,31
2696 emit_opcode( cbuf, 0xC1 );
2697 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2698 emit_d8(cbuf, 0x1F );
2699 %}
2701 enc_class convert_long_double( eRegL src ) %{
2702 // push $src.hi
2703 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2704 // push $src.lo
2705 emit_opcode(cbuf, 0x50+$src$$reg );
2706 // fild 64-bits at [SP]
2707 emit_opcode(cbuf,0xdf);
2708 emit_d8(cbuf, 0x6C);
2709 emit_d8(cbuf, 0x24);
2710 emit_d8(cbuf, 0x00);
2711 // pop stack
2712 emit_opcode(cbuf, 0x83); // add SP, #8
2713 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2714 emit_d8(cbuf, 0x8);
2715 %}
2717 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2718 // IMUL EDX:EAX,$src1
2719 emit_opcode( cbuf, 0xF7 );
2720 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2721 // SAR EDX,$cnt-32
2722 int shift_count = ((int)$cnt$$constant) - 32;
2723 if (shift_count > 0) {
2724 emit_opcode(cbuf, 0xC1);
2725 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2726 emit_d8(cbuf, shift_count);
2727 }
2728 %}
2730 // this version doesn't have add sp, 8
2731 enc_class convert_long_double2( eRegL src ) %{
2732 // push $src.hi
2733 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2734 // push $src.lo
2735 emit_opcode(cbuf, 0x50+$src$$reg );
2736 // fild 64-bits at [SP]
2737 emit_opcode(cbuf,0xdf);
2738 emit_d8(cbuf, 0x6C);
2739 emit_d8(cbuf, 0x24);
2740 emit_d8(cbuf, 0x00);
2741 %}
2743 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2744 // Basic idea: long = (long)int * (long)int
2745 // IMUL EDX:EAX, src
2746 emit_opcode( cbuf, 0xF7 );
2747 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2748 %}
2750 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2751 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2752 // MUL EDX:EAX, src
2753 emit_opcode( cbuf, 0xF7 );
2754 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2755 %}
2757 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
2758 // Basic idea: lo(result) = lo(x_lo * y_lo)
2759 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2760 // MOV $tmp,$src.lo
2761 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2762 // IMUL $tmp,EDX
2763 emit_opcode( cbuf, 0x0F );
2764 emit_opcode( cbuf, 0xAF );
2765 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2766 // MOV EDX,$src.hi
2767 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2768 // IMUL EDX,EAX
2769 emit_opcode( cbuf, 0x0F );
2770 emit_opcode( cbuf, 0xAF );
2771 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2772 // ADD $tmp,EDX
2773 emit_opcode( cbuf, 0x03 );
2774 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2775 // MUL EDX:EAX,$src.lo
2776 emit_opcode( cbuf, 0xF7 );
2777 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2778 // ADD EDX,ESI
2779 emit_opcode( cbuf, 0x03 );
2780 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2781 %}
2783 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
2784 // Basic idea: lo(result) = lo(src * y_lo)
2785 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2786 // IMUL $tmp,EDX,$src
2787 emit_opcode( cbuf, 0x6B );
2788 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2789 emit_d8( cbuf, (int)$src$$constant );
2790 // MOV EDX,$src
2791 emit_opcode(cbuf, 0xB8 + EDX_enc);
2792 emit_d32( cbuf, (int)$src$$constant );
2793 // MUL EDX:EAX,EDX
2794 emit_opcode( cbuf, 0xF7 );
2795 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2796 // ADD EDX,ESI
2797 emit_opcode( cbuf, 0x03 );
2798 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2799 %}
2801 enc_class long_div( eRegL src1, eRegL src2 ) %{
2802 // PUSH src1.hi
2803 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2804 // PUSH src1.lo
2805 emit_opcode(cbuf, 0x50+$src1$$reg );
2806 // PUSH src2.hi
2807 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2808 // PUSH src2.lo
2809 emit_opcode(cbuf, 0x50+$src2$$reg );
2810 // CALL directly to the runtime
2811 cbuf.set_insts_mark();
2812 emit_opcode(cbuf,0xE8); // Call into runtime
2813 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2814 // Restore stack
2815 emit_opcode(cbuf, 0x83); // add SP, #framesize
2816 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2817 emit_d8(cbuf, 4*4);
2818 %}
2820 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2821 // PUSH src1.hi
2822 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2823 // PUSH src1.lo
2824 emit_opcode(cbuf, 0x50+$src1$$reg );
2825 // PUSH src2.hi
2826 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2827 // PUSH src2.lo
2828 emit_opcode(cbuf, 0x50+$src2$$reg );
2829 // CALL directly to the runtime
2830 cbuf.set_insts_mark();
2831 emit_opcode(cbuf,0xE8); // Call into runtime
2832 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2833 // Restore stack
2834 emit_opcode(cbuf, 0x83); // add SP, #framesize
2835 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2836 emit_d8(cbuf, 4*4);
2837 %}
2839 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
2840 // MOV $tmp,$src.lo
2841 emit_opcode(cbuf, 0x8B);
2842 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2843 // OR $tmp,$src.hi
2844 emit_opcode(cbuf, 0x0B);
2845 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2846 %}
2848 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2849 // CMP $src1.lo,$src2.lo
2850 emit_opcode( cbuf, 0x3B );
2851 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2852 // JNE,s skip
2853 emit_cc(cbuf, 0x70, 0x5);
2854 emit_d8(cbuf,2);
2855 // CMP $src1.hi,$src2.hi
2856 emit_opcode( cbuf, 0x3B );
2857 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2858 %}
2860 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
2861 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2862 emit_opcode( cbuf, 0x3B );
2863 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2864 // MOV $tmp,$src1.hi
2865 emit_opcode( cbuf, 0x8B );
2866 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2867 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2868 emit_opcode( cbuf, 0x1B );
2869 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2870 %}
2872 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
2873 // XOR $tmp,$tmp
2874 emit_opcode(cbuf,0x33); // XOR
2875 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2876 // CMP $tmp,$src.lo
2877 emit_opcode( cbuf, 0x3B );
2878 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2879 // SBB $tmp,$src.hi
2880 emit_opcode( cbuf, 0x1B );
2881 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2882 %}
2884 // Sniff, sniff... smells like Gnu Superoptimizer
2885 enc_class neg_long( eRegL dst ) %{
2886 emit_opcode(cbuf,0xF7); // NEG hi
2887 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2888 emit_opcode(cbuf,0xF7); // NEG lo
2889 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2890 emit_opcode(cbuf,0x83); // SBB hi,0
2891 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2892 emit_d8 (cbuf,0 );
2893 %}
2896 // Because the transitions from emitted code to the runtime
2897 // monitorenter/exit helper stubs are so slow it's critical that
2898 // we inline both the stack-locking fast-path and the inflated fast path.
2899 //
2900 // See also: cmpFastLock and cmpFastUnlock.
2901 //
2902 // What follows is a specialized inline transliteration of the code
2903 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2904 // another option would be to emit TrySlowEnter and TrySlowExit methods
2905 // at startup-time. These methods would accept arguments as
2906 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2907 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2908 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2909 // In practice, however, the # of lock sites is bounded and is usually small.
2910 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2911 // if the processor uses simple bimodal branch predictors keyed by EIP
2912 // Since the helper routines would be called from multiple synchronization
2913 // sites.
2914 //
2915 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2916 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2917 // to those specialized methods. That'd give us a mostly platform-independent
2918 // implementation that the JITs could optimize and inline at their pleasure.
2919 // Done correctly, the only time we'd need to cross to native could would be
2920 // to park() or unpark() threads. We'd also need a few more unsafe operators
2921 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2922 // (b) explicit barriers or fence operations.
2923 //
2924 // TODO:
2925 //
2926 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2927 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2928 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2929 // the lock operators would typically be faster than reifying Self.
2930 //
2931 // * Ideally I'd define the primitives as:
2932 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2933 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2934 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2935 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2936 // Furthermore the register assignments are overconstrained, possibly resulting in
2937 // sub-optimal code near the synchronization site.
2938 //
2939 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2940 // Alternately, use a better sp-proximity test.
2941 //
2942 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2943 // Either one is sufficient to uniquely identify a thread.
2944 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2945 //
2946 // * Intrinsify notify() and notifyAll() for the common cases where the
2947 // object is locked by the calling thread but the waitlist is empty.
2948 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2949 //
2950 // * use jccb and jmpb instead of jcc and jmp to improve code density.
2951 // But beware of excessive branch density on AMD Opterons.
2952 //
2953 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
2954 // or failure of the fast-path. If the fast-path fails then we pass
2955 // control to the slow-path, typically in C. In Fast_Lock and
2956 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
2957 // will emit a conditional branch immediately after the node.
2958 // So we have branches to branches and lots of ICC.ZF games.
2959 // Instead, it might be better to have C2 pass a "FailureLabel"
2960 // into Fast_Lock and Fast_Unlock. In the case of success, control
2961 // will drop through the node. ICC.ZF is undefined at exit.
2962 // In the case of failure, the node will branch directly to the
2963 // FailureLabel
2966 // obj: object to lock
2967 // box: on-stack box address (displaced header location) - KILLED
2968 // rax,: tmp -- KILLED
2969 // scr: tmp -- KILLED
2970 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
2972 Register objReg = as_Register($obj$$reg);
2973 Register boxReg = as_Register($box$$reg);
2974 Register tmpReg = as_Register($tmp$$reg);
2975 Register scrReg = as_Register($scr$$reg);
2977 // Ensure the register assignents are disjoint
2978 guarantee (objReg != boxReg, "") ;
2979 guarantee (objReg != tmpReg, "") ;
2980 guarantee (objReg != scrReg, "") ;
2981 guarantee (boxReg != tmpReg, "") ;
2982 guarantee (boxReg != scrReg, "") ;
2983 guarantee (tmpReg == as_Register(EAX_enc), "") ;
2985 MacroAssembler masm(&cbuf);
2987 if (_counters != NULL) {
2988 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
2989 }
2990 if (EmitSync & 1) {
2991 // set box->dhw = unused_mark (3)
2992 // Force all sync thru slow-path: slow_enter() and slow_exit()
2993 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
2994 masm.cmpptr (rsp, (int32_t)0) ;
2995 } else
2996 if (EmitSync & 2) {
2997 Label DONE_LABEL ;
2998 if (UseBiasedLocking) {
2999 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3000 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3001 }
3003 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3004 masm.orptr (tmpReg, 0x1);
3005 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3006 if (os::is_MP()) { masm.lock(); }
3007 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3008 masm.jcc(Assembler::equal, DONE_LABEL);
3009 // Recursive locking
3010 masm.subptr(tmpReg, rsp);
3011 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3012 masm.movptr(Address(boxReg, 0), tmpReg);
3013 masm.bind(DONE_LABEL) ;
3014 } else {
3015 // Possible cases that we'll encounter in fast_lock
3016 // ------------------------------------------------
3017 // * Inflated
3018 // -- unlocked
3019 // -- Locked
3020 // = by self
3021 // = by other
3022 // * biased
3023 // -- by Self
3024 // -- by other
3025 // * neutral
3026 // * stack-locked
3027 // -- by self
3028 // = sp-proximity test hits
3029 // = sp-proximity test generates false-negative
3030 // -- by other
3031 //
3033 Label IsInflated, DONE_LABEL, PopDone ;
3035 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3036 // order to reduce the number of conditional branches in the most common cases.
3037 // Beware -- there's a subtle invariant that fetch of the markword
3038 // at [FETCH], below, will never observe a biased encoding (*101b).
3039 // If this invariant is not held we risk exclusion (safety) failure.
3040 if (UseBiasedLocking && !UseOptoBiasInlining) {
3041 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3042 }
3044 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3045 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3046 masm.jccb (Assembler::notZero, IsInflated) ;
3048 // Attempt stack-locking ...
3049 masm.orptr (tmpReg, 0x1);
3050 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3051 if (os::is_MP()) { masm.lock(); }
3052 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3053 if (_counters != NULL) {
3054 masm.cond_inc32(Assembler::equal,
3055 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3056 }
3057 masm.jccb (Assembler::equal, DONE_LABEL);
3059 // Recursive locking
3060 masm.subptr(tmpReg, rsp);
3061 masm.andptr(tmpReg, 0xFFFFF003 );
3062 masm.movptr(Address(boxReg, 0), tmpReg);
3063 if (_counters != NULL) {
3064 masm.cond_inc32(Assembler::equal,
3065 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3066 }
3067 masm.jmp (DONE_LABEL) ;
3069 masm.bind (IsInflated) ;
3071 // The object is inflated.
3072 //
3073 // TODO-FIXME: eliminate the ugly use of manifest constants:
3074 // Use markOopDesc::monitor_value instead of "2".
3075 // use markOop::unused_mark() instead of "3".
3076 // The tmpReg value is an objectMonitor reference ORed with
3077 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3078 // objectmonitor pointer by masking off the "2" bit or we can just
3079 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3080 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3081 //
3082 // I use the latter as it avoids AGI stalls.
3083 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3084 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3085 //
3086 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3088 // boxReg refers to the on-stack BasicLock in the current frame.
3089 // We'd like to write:
3090 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3091 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3092 // additional latency as we have another ST in the store buffer that must drain.
3094 if (EmitSync & 8192) {
3095 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3096 masm.get_thread (scrReg) ;
3097 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3098 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3099 if (os::is_MP()) { masm.lock(); }
3100 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3101 } else
3102 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3103 masm.movptr(scrReg, boxReg) ;
3104 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3106 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3107 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3108 // prefetchw [eax + Offset(_owner)-2]
3109 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3110 }
3112 if ((EmitSync & 64) == 0) {
3113 // Optimistic form: consider XORL tmpReg,tmpReg
3114 masm.movptr(tmpReg, NULL_WORD) ;
3115 } else {
3116 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3117 // Test-And-CAS instead of CAS
3118 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3119 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3120 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3121 }
3123 // Appears unlocked - try to swing _owner from null to non-null.
3124 // Ideally, I'd manifest "Self" with get_thread and then attempt
3125 // to CAS the register containing Self into m->Owner.
3126 // But we don't have enough registers, so instead we can either try to CAS
3127 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3128 // we later store "Self" into m->Owner. Transiently storing a stack address
3129 // (rsp or the address of the box) into m->owner is harmless.
3130 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3131 if (os::is_MP()) { masm.lock(); }
3132 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3133 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3134 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3135 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3136 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3137 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3139 // If the CAS fails we can either retry or pass control to the slow-path.
3140 // We use the latter tactic.
3141 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3142 // If the CAS was successful ...
3143 // Self has acquired the lock
3144 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3145 // Intentional fall-through into DONE_LABEL ...
3146 } else {
3147 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3148 masm.movptr(boxReg, tmpReg) ;
3150 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3151 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3152 // prefetchw [eax + Offset(_owner)-2]
3153 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3154 }
3156 if ((EmitSync & 64) == 0) {
3157 // Optimistic form
3158 masm.xorptr (tmpReg, tmpReg) ;
3159 } else {
3160 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3161 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3162 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3163 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3164 }
3166 // Appears unlocked - try to swing _owner from null to non-null.
3167 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3168 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3169 masm.get_thread (scrReg) ;
3170 if (os::is_MP()) { masm.lock(); }
3171 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3173 // If the CAS fails we can either retry or pass control to the slow-path.
3174 // We use the latter tactic.
3175 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3176 // If the CAS was successful ...
3177 // Self has acquired the lock
3178 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3179 // Intentional fall-through into DONE_LABEL ...
3180 }
3182 // DONE_LABEL is a hot target - we'd really like to place it at the
3183 // start of cache line by padding with NOPs.
3184 // See the AMD and Intel software optimization manuals for the
3185 // most efficient "long" NOP encodings.
3186 // Unfortunately none of our alignment mechanisms suffice.
3187 masm.bind(DONE_LABEL);
3189 // Avoid branch-to-branch on AMD processors
3190 // This appears to be superstition.
3191 if (EmitSync & 32) masm.nop() ;
3194 // At DONE_LABEL the icc ZFlag is set as follows ...
3195 // Fast_Unlock uses the same protocol.
3196 // ZFlag == 1 -> Success
3197 // ZFlag == 0 -> Failure - force control through the slow-path
3198 }
3199 %}
3201 // obj: object to unlock
3202 // box: box address (displaced header location), killed. Must be EAX.
3203 // rbx,: killed tmp; cannot be obj nor box.
3204 //
3205 // Some commentary on balanced locking:
3206 //
3207 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3208 // Methods that don't have provably balanced locking are forced to run in the
3209 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3210 // The interpreter provides two properties:
3211 // I1: At return-time the interpreter automatically and quietly unlocks any
3212 // objects acquired the current activation (frame). Recall that the
3213 // interpreter maintains an on-stack list of locks currently held by
3214 // a frame.
3215 // I2: If a method attempts to unlock an object that is not held by the
3216 // the frame the interpreter throws IMSX.
3217 //
3218 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3219 // B() doesn't have provably balanced locking so it runs in the interpreter.
3220 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3221 // is still locked by A().
3222 //
3223 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3224 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3225 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3226 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3228 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3230 Register objReg = as_Register($obj$$reg);
3231 Register boxReg = as_Register($box$$reg);
3232 Register tmpReg = as_Register($tmp$$reg);
3234 guarantee (objReg != boxReg, "") ;
3235 guarantee (objReg != tmpReg, "") ;
3236 guarantee (boxReg != tmpReg, "") ;
3237 guarantee (boxReg == as_Register(EAX_enc), "") ;
3238 MacroAssembler masm(&cbuf);
3240 if (EmitSync & 4) {
3241 // Disable - inhibit all inlining. Force control through the slow-path
3242 masm.cmpptr (rsp, 0) ;
3243 } else
3244 if (EmitSync & 8) {
3245 Label DONE_LABEL ;
3246 if (UseBiasedLocking) {
3247 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3248 }
3249 // classic stack-locking code ...
3250 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3251 masm.testptr(tmpReg, tmpReg) ;
3252 masm.jcc (Assembler::zero, DONE_LABEL) ;
3253 if (os::is_MP()) { masm.lock(); }
3254 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3255 masm.bind(DONE_LABEL);
3256 } else {
3257 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3259 // Critically, the biased locking test must have precedence over
3260 // and appear before the (box->dhw == 0) recursive stack-lock test.
3261 if (UseBiasedLocking && !UseOptoBiasInlining) {
3262 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3263 }
3265 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3266 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3267 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3269 masm.testptr(tmpReg, 0x02) ; // Inflated?
3270 masm.jccb (Assembler::zero, Stacked) ;
3272 masm.bind (Inflated) ;
3273 // It's inflated.
3274 // Despite our balanced locking property we still check that m->_owner == Self
3275 // as java routines or native JNI code called by this thread might
3276 // have released the lock.
3277 // Refer to the comments in synchronizer.cpp for how we might encode extra
3278 // state in _succ so we can avoid fetching EntryList|cxq.
3279 //
3280 // I'd like to add more cases in fast_lock() and fast_unlock() --
3281 // such as recursive enter and exit -- but we have to be wary of
3282 // I$ bloat, T$ effects and BP$ effects.
3283 //
3284 // If there's no contention try a 1-0 exit. That is, exit without
3285 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3286 // we detect and recover from the race that the 1-0 exit admits.
3287 //
3288 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3289 // before it STs null into _owner, releasing the lock. Updates
3290 // to data protected by the critical section must be visible before
3291 // we drop the lock (and thus before any other thread could acquire
3292 // the lock and observe the fields protected by the lock).
3293 // IA32's memory-model is SPO, so STs are ordered with respect to
3294 // each other and there's no need for an explicit barrier (fence).
3295 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3297 masm.get_thread (boxReg) ;
3298 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3299 // prefetchw [ebx + Offset(_owner)-2]
3300 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3301 }
3303 // Note that we could employ various encoding schemes to reduce
3304 // the number of loads below (currently 4) to just 2 or 3.
3305 // Refer to the comments in synchronizer.cpp.
3306 // In practice the chain of fetches doesn't seem to impact performance, however.
3307 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3308 // Attempt to reduce branch density - AMD's branch predictor.
3309 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3310 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3311 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3312 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3313 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3314 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3315 masm.jmpb (DONE_LABEL) ;
3316 } else {
3317 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3318 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3319 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3320 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3321 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3322 masm.jccb (Assembler::notZero, CheckSucc) ;
3323 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3324 masm.jmpb (DONE_LABEL) ;
3325 }
3327 // The Following code fragment (EmitSync & 65536) improves the performance of
3328 // contended applications and contended synchronization microbenchmarks.
3329 // Unfortunately the emission of the code - even though not executed - causes regressions
3330 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3331 // with an equal number of never-executed NOPs results in the same regression.
3332 // We leave it off by default.
3334 if ((EmitSync & 65536) != 0) {
3335 Label LSuccess, LGoSlowPath ;
3337 masm.bind (CheckSucc) ;
3339 // Optional pre-test ... it's safe to elide this
3340 if ((EmitSync & 16) == 0) {
3341 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3342 masm.jccb (Assembler::zero, LGoSlowPath) ;
3343 }
3345 // We have a classic Dekker-style idiom:
3346 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3347 // There are a number of ways to implement the barrier:
3348 // (1) lock:andl &m->_owner, 0
3349 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3350 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3351 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3352 // (2) If supported, an explicit MFENCE is appealing.
3353 // In older IA32 processors MFENCE is slower than lock:add or xchg
3354 // particularly if the write-buffer is full as might be the case if
3355 // if stores closely precede the fence or fence-equivalent instruction.
3356 // In more modern implementations MFENCE appears faster, however.
3357 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3358 // The $lines underlying the top-of-stack should be in M-state.
3359 // The locked add instruction is serializing, of course.
3360 // (4) Use xchg, which is serializing
3361 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3362 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3363 // The integer condition codes will tell us if succ was 0.
3364 // Since _succ and _owner should reside in the same $line and
3365 // we just stored into _owner, it's likely that the $line
3366 // remains in M-state for the lock:orl.
3367 //
3368 // We currently use (3), although it's likely that switching to (2)
3369 // is correct for the future.
3371 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3372 if (os::is_MP()) {
3373 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3374 masm.mfence();
3375 } else {
3376 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3377 }
3378 }
3379 // Ratify _succ remains non-null
3380 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3381 masm.jccb (Assembler::notZero, LSuccess) ;
3383 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3384 if (os::is_MP()) { masm.lock(); }
3385 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3386 masm.jccb (Assembler::notEqual, LSuccess) ;
3387 // Since we're low on registers we installed rsp as a placeholding in _owner.
3388 // Now install Self over rsp. This is safe as we're transitioning from
3389 // non-null to non=null
3390 masm.get_thread (boxReg) ;
3391 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3392 // Intentional fall-through into LGoSlowPath ...
3394 masm.bind (LGoSlowPath) ;
3395 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3396 masm.jmpb (DONE_LABEL) ;
3398 masm.bind (LSuccess) ;
3399 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3400 masm.jmpb (DONE_LABEL) ;
3401 }
3403 masm.bind (Stacked) ;
3404 // It's not inflated and it's not recursively stack-locked and it's not biased.
3405 // It must be stack-locked.
3406 // Try to reset the header to displaced header.
3407 // The "box" value on the stack is stable, so we can reload
3408 // and be assured we observe the same value as above.
3409 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3410 if (os::is_MP()) { masm.lock(); }
3411 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3412 // Intention fall-thru into DONE_LABEL
3415 // DONE_LABEL is a hot target - we'd really like to place it at the
3416 // start of cache line by padding with NOPs.
3417 // See the AMD and Intel software optimization manuals for the
3418 // most efficient "long" NOP encodings.
3419 // Unfortunately none of our alignment mechanisms suffice.
3420 if ((EmitSync & 65536) == 0) {
3421 masm.bind (CheckSucc) ;
3422 }
3423 masm.bind(DONE_LABEL);
3425 // Avoid branch to branch on AMD processors
3426 if (EmitSync & 32768) { masm.nop() ; }
3427 }
3428 %}
3431 enc_class enc_pop_rdx() %{
3432 emit_opcode(cbuf,0x5A);
3433 %}
3435 enc_class enc_rethrow() %{
3436 cbuf.set_insts_mark();
3437 emit_opcode(cbuf, 0xE9); // jmp entry
3438 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3439 runtime_call_Relocation::spec(), RELOC_IMM32 );
3440 %}
3443 // Convert a double to an int. Java semantics require we do complex
3444 // manglelations in the corner cases. So we set the rounding mode to
3445 // 'zero', store the darned double down as an int, and reset the
3446 // rounding mode to 'nearest'. The hardware throws an exception which
3447 // patches up the correct value directly to the stack.
3448 enc_class DPR2I_encoding( regDPR src ) %{
3449 // Flip to round-to-zero mode. We attempted to allow invalid-op
3450 // exceptions here, so that a NAN or other corner-case value will
3451 // thrown an exception (but normal values get converted at full speed).
3452 // However, I2C adapters and other float-stack manglers leave pending
3453 // invalid-op exceptions hanging. We would have to clear them before
3454 // enabling them and that is more expensive than just testing for the
3455 // invalid value Intel stores down in the corner cases.
3456 emit_opcode(cbuf,0xD9); // FLDCW trunc
3457 emit_opcode(cbuf,0x2D);
3458 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3459 // Allocate a word
3460 emit_opcode(cbuf,0x83); // SUB ESP,4
3461 emit_opcode(cbuf,0xEC);
3462 emit_d8(cbuf,0x04);
3463 // Encoding assumes a double has been pushed into FPR0.
3464 // Store down the double as an int, popping the FPU stack
3465 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3466 emit_opcode(cbuf,0x1C);
3467 emit_d8(cbuf,0x24);
3468 // Restore the rounding mode; mask the exception
3469 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3470 emit_opcode(cbuf,0x2D);
3471 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3472 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3473 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3475 // Load the converted int; adjust CPU stack
3476 emit_opcode(cbuf,0x58); // POP EAX
3477 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3478 emit_d32 (cbuf,0x80000000); // 0x80000000
3479 emit_opcode(cbuf,0x75); // JNE around_slow_call
3480 emit_d8 (cbuf,0x07); // Size of slow_call
3481 // Push src onto stack slow-path
3482 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3483 emit_d8 (cbuf,0xC0-1+$src$$reg );
3484 // CALL directly to the runtime
3485 cbuf.set_insts_mark();
3486 emit_opcode(cbuf,0xE8); // Call into runtime
3487 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3488 // Carry on here...
3489 %}
3491 enc_class DPR2L_encoding( regDPR src ) %{
3492 emit_opcode(cbuf,0xD9); // FLDCW trunc
3493 emit_opcode(cbuf,0x2D);
3494 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3495 // Allocate a word
3496 emit_opcode(cbuf,0x83); // SUB ESP,8
3497 emit_opcode(cbuf,0xEC);
3498 emit_d8(cbuf,0x08);
3499 // Encoding assumes a double has been pushed into FPR0.
3500 // Store down the double as a long, popping the FPU stack
3501 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3502 emit_opcode(cbuf,0x3C);
3503 emit_d8(cbuf,0x24);
3504 // Restore the rounding mode; mask the exception
3505 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3506 emit_opcode(cbuf,0x2D);
3507 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3508 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3509 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3511 // Load the converted int; adjust CPU stack
3512 emit_opcode(cbuf,0x58); // POP EAX
3513 emit_opcode(cbuf,0x5A); // POP EDX
3514 emit_opcode(cbuf,0x81); // CMP EDX,imm
3515 emit_d8 (cbuf,0xFA); // rdx
3516 emit_d32 (cbuf,0x80000000); // 0x80000000
3517 emit_opcode(cbuf,0x75); // JNE around_slow_call
3518 emit_d8 (cbuf,0x07+4); // Size of slow_call
3519 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3520 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3521 emit_opcode(cbuf,0x75); // JNE around_slow_call
3522 emit_d8 (cbuf,0x07); // Size of slow_call
3523 // Push src onto stack slow-path
3524 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3525 emit_d8 (cbuf,0xC0-1+$src$$reg );
3526 // CALL directly to the runtime
3527 cbuf.set_insts_mark();
3528 emit_opcode(cbuf,0xE8); // Call into runtime
3529 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3530 // Carry on here...
3531 %}
3533 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3534 // Operand was loaded from memory into fp ST (stack top)
3535 // FMUL ST,$src /* D8 C8+i */
3536 emit_opcode(cbuf, 0xD8);
3537 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3538 %}
3540 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3541 // FADDP ST,src2 /* D8 C0+i */
3542 emit_opcode(cbuf, 0xD8);
3543 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3544 //could use FADDP src2,fpST /* DE C0+i */
3545 %}
3547 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3548 // FADDP src2,ST /* DE C0+i */
3549 emit_opcode(cbuf, 0xDE);
3550 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3551 %}
3553 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3554 // Operand has been loaded into fp ST (stack top)
3555 // FSUB ST,$src1
3556 emit_opcode(cbuf, 0xD8);
3557 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3559 // FDIV
3560 emit_opcode(cbuf, 0xD8);
3561 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3562 %}
3564 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3565 // Operand was loaded from memory into fp ST (stack top)
3566 // FADD ST,$src /* D8 C0+i */
3567 emit_opcode(cbuf, 0xD8);
3568 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3570 // FMUL ST,src2 /* D8 C*+i */
3571 emit_opcode(cbuf, 0xD8);
3572 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3573 %}
3576 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3577 // Operand was loaded from memory into fp ST (stack top)
3578 // FADD ST,$src /* D8 C0+i */
3579 emit_opcode(cbuf, 0xD8);
3580 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3582 // FMULP src2,ST /* DE C8+i */
3583 emit_opcode(cbuf, 0xDE);
3584 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3585 %}
3587 // Atomically load the volatile long
3588 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3589 emit_opcode(cbuf,0xDF);
3590 int rm_byte_opcode = 0x05;
3591 int base = $mem$$base;
3592 int index = $mem$$index;
3593 int scale = $mem$$scale;
3594 int displace = $mem$$disp;
3595 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3596 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3597 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3598 %}
3600 // Volatile Store Long. Must be atomic, so move it into
3601 // the FP TOS and then do a 64-bit FIST. Has to probe the
3602 // target address before the store (for null-ptr checks)
3603 // so the memory operand is used twice in the encoding.
3604 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3605 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3606 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3607 emit_opcode(cbuf,0xDF);
3608 int rm_byte_opcode = 0x07;
3609 int base = $mem$$base;
3610 int index = $mem$$index;
3611 int scale = $mem$$scale;
3612 int displace = $mem$$disp;
3613 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3614 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3615 %}
3617 // Safepoint Poll. This polls the safepoint page, and causes an
3618 // exception if it is not readable. Unfortunately, it kills the condition code
3619 // in the process
3620 // We current use TESTL [spp],EDI
3621 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3623 enc_class Safepoint_Poll() %{
3624 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3625 emit_opcode(cbuf,0x85);
3626 emit_rm (cbuf, 0x0, 0x7, 0x5);
3627 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3628 %}
3629 %}
3632 //----------FRAME--------------------------------------------------------------
3633 // Definition of frame structure and management information.
3634 //
3635 // S T A C K L A Y O U T Allocators stack-slot number
3636 // | (to get allocators register number
3637 // G Owned by | | v add OptoReg::stack0())
3638 // r CALLER | |
3639 // o | +--------+ pad to even-align allocators stack-slot
3640 // w V | pad0 | numbers; owned by CALLER
3641 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3642 // h ^ | in | 5
3643 // | | args | 4 Holes in incoming args owned by SELF
3644 // | | | | 3
3645 // | | +--------+
3646 // V | | old out| Empty on Intel, window on Sparc
3647 // | old |preserve| Must be even aligned.
3648 // | SP-+--------+----> Matcher::_old_SP, even aligned
3649 // | | in | 3 area for Intel ret address
3650 // Owned by |preserve| Empty on Sparc.
3651 // SELF +--------+
3652 // | | pad2 | 2 pad to align old SP
3653 // | +--------+ 1
3654 // | | locks | 0
3655 // | +--------+----> OptoReg::stack0(), even aligned
3656 // | | pad1 | 11 pad to align new SP
3657 // | +--------+
3658 // | | | 10
3659 // | | spills | 9 spills
3660 // V | | 8 (pad0 slot for callee)
3661 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3662 // ^ | out | 7
3663 // | | args | 6 Holes in outgoing args owned by CALLEE
3664 // Owned by +--------+
3665 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3666 // | new |preserve| Must be even-aligned.
3667 // | SP-+--------+----> Matcher::_new_SP, even aligned
3668 // | | |
3669 //
3670 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3671 // known from SELF's arguments and the Java calling convention.
3672 // Region 6-7 is determined per call site.
3673 // Note 2: If the calling convention leaves holes in the incoming argument
3674 // area, those holes are owned by SELF. Holes in the outgoing area
3675 // are owned by the CALLEE. Holes should not be nessecary in the
3676 // incoming area, as the Java calling convention is completely under
3677 // the control of the AD file. Doubles can be sorted and packed to
3678 // avoid holes. Holes in the outgoing arguments may be nessecary for
3679 // varargs C calling conventions.
3680 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3681 // even aligned with pad0 as needed.
3682 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3683 // region 6-11 is even aligned; it may be padded out more so that
3684 // the region from SP to FP meets the minimum stack alignment.
3686 frame %{
3687 // What direction does stack grow in (assumed to be same for C & Java)
3688 stack_direction(TOWARDS_LOW);
3690 // These three registers define part of the calling convention
3691 // between compiled code and the interpreter.
3692 inline_cache_reg(EAX); // Inline Cache Register
3693 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3695 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3696 cisc_spilling_operand_name(indOffset32);
3698 // Number of stack slots consumed by locking an object
3699 sync_stack_slots(1);
3701 // Compiled code's Frame Pointer
3702 frame_pointer(ESP);
3703 // Interpreter stores its frame pointer in a register which is
3704 // stored to the stack by I2CAdaptors.
3705 // I2CAdaptors convert from interpreted java to compiled java.
3706 interpreter_frame_pointer(EBP);
3708 // Stack alignment requirement
3709 // Alignment size in bytes (128-bit -> 16 bytes)
3710 stack_alignment(StackAlignmentInBytes);
3712 // Number of stack slots between incoming argument block and the start of
3713 // a new frame. The PROLOG must add this many slots to the stack. The
3714 // EPILOG must remove this many slots. Intel needs one slot for
3715 // return address and one for rbp, (must save rbp)
3716 in_preserve_stack_slots(2+VerifyStackAtCalls);
3718 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3719 // for calls to C. Supports the var-args backing area for register parms.
3720 varargs_C_out_slots_killed(0);
3722 // The after-PROLOG location of the return address. Location of
3723 // return address specifies a type (REG or STACK) and a number
3724 // representing the register number (i.e. - use a register name) or
3725 // stack slot.
3726 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3727 // Otherwise, it is above the locks and verification slot and alignment word
3728 return_addr(STACK - 1 +
3729 round_to((Compile::current()->in_preserve_stack_slots() +
3730 Compile::current()->fixed_slots()),
3731 stack_alignment_in_slots()));
3733 // Body of function which returns an integer array locating
3734 // arguments either in registers or in stack slots. Passed an array
3735 // of ideal registers called "sig" and a "length" count. Stack-slot
3736 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3737 // arguments for a CALLEE. Incoming stack arguments are
3738 // automatically biased by the preserve_stack_slots field above.
3739 calling_convention %{
3740 // No difference between ingoing/outgoing just pass false
3741 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3742 %}
3745 // Body of function which returns an integer array locating
3746 // arguments either in registers or in stack slots. Passed an array
3747 // of ideal registers called "sig" and a "length" count. Stack-slot
3748 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3749 // arguments for a CALLEE. Incoming stack arguments are
3750 // automatically biased by the preserve_stack_slots field above.
3751 c_calling_convention %{
3752 // This is obviously always outgoing
3753 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3754 %}
3756 // Location of C & interpreter return values
3757 c_return_value %{
3758 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3759 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3760 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3762 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3763 // that C functions return float and double results in XMM0.
3764 if( ideal_reg == Op_RegD && UseSSE>=2 )
3765 return OptoRegPair(XMM0b_num,XMM0a_num);
3766 if( ideal_reg == Op_RegF && UseSSE>=2 )
3767 return OptoRegPair(OptoReg::Bad,XMM0a_num);
3769 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3770 %}
3772 // Location of return values
3773 return_value %{
3774 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3775 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3776 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3777 if( ideal_reg == Op_RegD && UseSSE>=2 )
3778 return OptoRegPair(XMM0b_num,XMM0a_num);
3779 if( ideal_reg == Op_RegF && UseSSE>=1 )
3780 return OptoRegPair(OptoReg::Bad,XMM0a_num);
3781 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3782 %}
3784 %}
3786 //----------ATTRIBUTES---------------------------------------------------------
3787 //----------Operand Attributes-------------------------------------------------
3788 op_attrib op_cost(0); // Required cost attribute
3790 //----------Instruction Attributes---------------------------------------------
3791 ins_attrib ins_cost(100); // Required cost attribute
3792 ins_attrib ins_size(8); // Required size attribute (in bits)
3793 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3794 // non-matching short branch variant of some
3795 // long branch?
3796 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3797 // specifies the alignment that some part of the instruction (not
3798 // necessarily the start) requires. If > 1, a compute_padding()
3799 // function must be provided for the instruction
3801 //----------OPERANDS-----------------------------------------------------------
3802 // Operand definitions must precede instruction definitions for correct parsing
3803 // in the ADLC because operands constitute user defined types which are used in
3804 // instruction definitions.
3806 //----------Simple Operands----------------------------------------------------
3807 // Immediate Operands
3808 // Integer Immediate
3809 operand immI() %{
3810 match(ConI);
3812 op_cost(10);
3813 format %{ %}
3814 interface(CONST_INTER);
3815 %}
3817 // Constant for test vs zero
3818 operand immI0() %{
3819 predicate(n->get_int() == 0);
3820 match(ConI);
3822 op_cost(0);
3823 format %{ %}
3824 interface(CONST_INTER);
3825 %}
3827 // Constant for increment
3828 operand immI1() %{
3829 predicate(n->get_int() == 1);
3830 match(ConI);
3832 op_cost(0);
3833 format %{ %}
3834 interface(CONST_INTER);
3835 %}
3837 // Constant for decrement
3838 operand immI_M1() %{
3839 predicate(n->get_int() == -1);
3840 match(ConI);
3842 op_cost(0);
3843 format %{ %}
3844 interface(CONST_INTER);
3845 %}
3847 // Valid scale values for addressing modes
3848 operand immI2() %{
3849 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3850 match(ConI);
3852 format %{ %}
3853 interface(CONST_INTER);
3854 %}
3856 operand immI8() %{
3857 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3858 match(ConI);
3860 op_cost(5);
3861 format %{ %}
3862 interface(CONST_INTER);
3863 %}
3865 operand immI16() %{
3866 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3867 match(ConI);
3869 op_cost(10);
3870 format %{ %}
3871 interface(CONST_INTER);
3872 %}
3874 // Constant for long shifts
3875 operand immI_32() %{
3876 predicate( n->get_int() == 32 );
3877 match(ConI);
3879 op_cost(0);
3880 format %{ %}
3881 interface(CONST_INTER);
3882 %}
3884 operand immI_1_31() %{
3885 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3886 match(ConI);
3888 op_cost(0);
3889 format %{ %}
3890 interface(CONST_INTER);
3891 %}
3893 operand immI_32_63() %{
3894 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3895 match(ConI);
3896 op_cost(0);
3898 format %{ %}
3899 interface(CONST_INTER);
3900 %}
3902 operand immI_1() %{
3903 predicate( n->get_int() == 1 );
3904 match(ConI);
3906 op_cost(0);
3907 format %{ %}
3908 interface(CONST_INTER);
3909 %}
3911 operand immI_2() %{
3912 predicate( n->get_int() == 2 );
3913 match(ConI);
3915 op_cost(0);
3916 format %{ %}
3917 interface(CONST_INTER);
3918 %}
3920 operand immI_3() %{
3921 predicate( n->get_int() == 3 );
3922 match(ConI);
3924 op_cost(0);
3925 format %{ %}
3926 interface(CONST_INTER);
3927 %}
3929 // Pointer Immediate
3930 operand immP() %{
3931 match(ConP);
3933 op_cost(10);
3934 format %{ %}
3935 interface(CONST_INTER);
3936 %}
3938 // NULL Pointer Immediate
3939 operand immP0() %{
3940 predicate( n->get_ptr() == 0 );
3941 match(ConP);
3942 op_cost(0);
3944 format %{ %}
3945 interface(CONST_INTER);
3946 %}
3948 // Long Immediate
3949 operand immL() %{
3950 match(ConL);
3952 op_cost(20);
3953 format %{ %}
3954 interface(CONST_INTER);
3955 %}
3957 // Long Immediate zero
3958 operand immL0() %{
3959 predicate( n->get_long() == 0L );
3960 match(ConL);
3961 op_cost(0);
3963 format %{ %}
3964 interface(CONST_INTER);
3965 %}
3967 // Long Immediate zero
3968 operand immL_M1() %{
3969 predicate( n->get_long() == -1L );
3970 match(ConL);
3971 op_cost(0);
3973 format %{ %}
3974 interface(CONST_INTER);
3975 %}
3977 // Long immediate from 0 to 127.
3978 // Used for a shorter form of long mul by 10.
3979 operand immL_127() %{
3980 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
3981 match(ConL);
3982 op_cost(0);
3984 format %{ %}
3985 interface(CONST_INTER);
3986 %}
3988 // Long Immediate: low 32-bit mask
3989 operand immL_32bits() %{
3990 predicate(n->get_long() == 0xFFFFFFFFL);
3991 match(ConL);
3992 op_cost(0);
3994 format %{ %}
3995 interface(CONST_INTER);
3996 %}
3998 // Long Immediate: low 32-bit mask
3999 operand immL32() %{
4000 predicate(n->get_long() == (int)(n->get_long()));
4001 match(ConL);
4002 op_cost(20);
4004 format %{ %}
4005 interface(CONST_INTER);
4006 %}
4008 //Double Immediate zero
4009 operand immDPR0() %{
4010 // Do additional (and counter-intuitive) test against NaN to work around VC++
4011 // bug that generates code such that NaNs compare equal to 0.0
4012 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4013 match(ConD);
4015 op_cost(5);
4016 format %{ %}
4017 interface(CONST_INTER);
4018 %}
4020 // Double Immediate one
4021 operand immDPR1() %{
4022 predicate( UseSSE<=1 && n->getd() == 1.0 );
4023 match(ConD);
4025 op_cost(5);
4026 format %{ %}
4027 interface(CONST_INTER);
4028 %}
4030 // Double Immediate
4031 operand immDPR() %{
4032 predicate(UseSSE<=1);
4033 match(ConD);
4035 op_cost(5);
4036 format %{ %}
4037 interface(CONST_INTER);
4038 %}
4040 operand immD() %{
4041 predicate(UseSSE>=2);
4042 match(ConD);
4044 op_cost(5);
4045 format %{ %}
4046 interface(CONST_INTER);
4047 %}
4049 // Double Immediate zero
4050 operand immD0() %{
4051 // Do additional (and counter-intuitive) test against NaN to work around VC++
4052 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4053 // compare equal to -0.0.
4054 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4055 match(ConD);
4057 format %{ %}
4058 interface(CONST_INTER);
4059 %}
4061 // Float Immediate zero
4062 operand immFPR0() %{
4063 predicate(UseSSE == 0 && n->getf() == 0.0F);
4064 match(ConF);
4066 op_cost(5);
4067 format %{ %}
4068 interface(CONST_INTER);
4069 %}
4071 // Float Immediate one
4072 operand immFPR1() %{
4073 predicate(UseSSE == 0 && n->getf() == 1.0F);
4074 match(ConF);
4076 op_cost(5);
4077 format %{ %}
4078 interface(CONST_INTER);
4079 %}
4081 // Float Immediate
4082 operand immFPR() %{
4083 predicate( UseSSE == 0 );
4084 match(ConF);
4086 op_cost(5);
4087 format %{ %}
4088 interface(CONST_INTER);
4089 %}
4091 // Float Immediate
4092 operand immF() %{
4093 predicate(UseSSE >= 1);
4094 match(ConF);
4096 op_cost(5);
4097 format %{ %}
4098 interface(CONST_INTER);
4099 %}
4101 // Float Immediate zero. Zero and not -0.0
4102 operand immF0() %{
4103 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4104 match(ConF);
4106 op_cost(5);
4107 format %{ %}
4108 interface(CONST_INTER);
4109 %}
4111 // Immediates for special shifts (sign extend)
4113 // Constants for increment
4114 operand immI_16() %{
4115 predicate( n->get_int() == 16 );
4116 match(ConI);
4118 format %{ %}
4119 interface(CONST_INTER);
4120 %}
4122 operand immI_24() %{
4123 predicate( n->get_int() == 24 );
4124 match(ConI);
4126 format %{ %}
4127 interface(CONST_INTER);
4128 %}
4130 // Constant for byte-wide masking
4131 operand immI_255() %{
4132 predicate( n->get_int() == 255 );
4133 match(ConI);
4135 format %{ %}
4136 interface(CONST_INTER);
4137 %}
4139 // Constant for short-wide masking
4140 operand immI_65535() %{
4141 predicate(n->get_int() == 65535);
4142 match(ConI);
4144 format %{ %}
4145 interface(CONST_INTER);
4146 %}
4148 // Register Operands
4149 // Integer Register
4150 operand eRegI() %{
4151 constraint(ALLOC_IN_RC(e_reg));
4152 match(RegI);
4153 match(xRegI);
4154 match(eAXRegI);
4155 match(eBXRegI);
4156 match(eCXRegI);
4157 match(eDXRegI);
4158 match(eDIRegI);
4159 match(eSIRegI);
4161 format %{ %}
4162 interface(REG_INTER);
4163 %}
4165 // Subset of Integer Register
4166 operand xRegI(eRegI reg) %{
4167 constraint(ALLOC_IN_RC(x_reg));
4168 match(reg);
4169 match(eAXRegI);
4170 match(eBXRegI);
4171 match(eCXRegI);
4172 match(eDXRegI);
4174 format %{ %}
4175 interface(REG_INTER);
4176 %}
4178 // Special Registers
4179 operand eAXRegI(xRegI reg) %{
4180 constraint(ALLOC_IN_RC(eax_reg));
4181 match(reg);
4182 match(eRegI);
4184 format %{ "EAX" %}
4185 interface(REG_INTER);
4186 %}
4188 // Special Registers
4189 operand eBXRegI(xRegI reg) %{
4190 constraint(ALLOC_IN_RC(ebx_reg));
4191 match(reg);
4192 match(eRegI);
4194 format %{ "EBX" %}
4195 interface(REG_INTER);
4196 %}
4198 operand eCXRegI(xRegI reg) %{
4199 constraint(ALLOC_IN_RC(ecx_reg));
4200 match(reg);
4201 match(eRegI);
4203 format %{ "ECX" %}
4204 interface(REG_INTER);
4205 %}
4207 operand eDXRegI(xRegI reg) %{
4208 constraint(ALLOC_IN_RC(edx_reg));
4209 match(reg);
4210 match(eRegI);
4212 format %{ "EDX" %}
4213 interface(REG_INTER);
4214 %}
4216 operand eDIRegI(xRegI reg) %{
4217 constraint(ALLOC_IN_RC(edi_reg));
4218 match(reg);
4219 match(eRegI);
4221 format %{ "EDI" %}
4222 interface(REG_INTER);
4223 %}
4225 operand naxRegI() %{
4226 constraint(ALLOC_IN_RC(nax_reg));
4227 match(RegI);
4228 match(eCXRegI);
4229 match(eDXRegI);
4230 match(eSIRegI);
4231 match(eDIRegI);
4233 format %{ %}
4234 interface(REG_INTER);
4235 %}
4237 operand nadxRegI() %{
4238 constraint(ALLOC_IN_RC(nadx_reg));
4239 match(RegI);
4240 match(eBXRegI);
4241 match(eCXRegI);
4242 match(eSIRegI);
4243 match(eDIRegI);
4245 format %{ %}
4246 interface(REG_INTER);
4247 %}
4249 operand ncxRegI() %{
4250 constraint(ALLOC_IN_RC(ncx_reg));
4251 match(RegI);
4252 match(eAXRegI);
4253 match(eDXRegI);
4254 match(eSIRegI);
4255 match(eDIRegI);
4257 format %{ %}
4258 interface(REG_INTER);
4259 %}
4261 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4262 // //
4263 operand eSIRegI(xRegI reg) %{
4264 constraint(ALLOC_IN_RC(esi_reg));
4265 match(reg);
4266 match(eRegI);
4268 format %{ "ESI" %}
4269 interface(REG_INTER);
4270 %}
4272 // Pointer Register
4273 operand anyRegP() %{
4274 constraint(ALLOC_IN_RC(any_reg));
4275 match(RegP);
4276 match(eAXRegP);
4277 match(eBXRegP);
4278 match(eCXRegP);
4279 match(eDIRegP);
4280 match(eRegP);
4282 format %{ %}
4283 interface(REG_INTER);
4284 %}
4286 operand eRegP() %{
4287 constraint(ALLOC_IN_RC(e_reg));
4288 match(RegP);
4289 match(eAXRegP);
4290 match(eBXRegP);
4291 match(eCXRegP);
4292 match(eDIRegP);
4294 format %{ %}
4295 interface(REG_INTER);
4296 %}
4298 // On windows95, EBP is not safe to use for implicit null tests.
4299 operand eRegP_no_EBP() %{
4300 constraint(ALLOC_IN_RC(e_reg_no_rbp));
4301 match(RegP);
4302 match(eAXRegP);
4303 match(eBXRegP);
4304 match(eCXRegP);
4305 match(eDIRegP);
4307 op_cost(100);
4308 format %{ %}
4309 interface(REG_INTER);
4310 %}
4312 operand naxRegP() %{
4313 constraint(ALLOC_IN_RC(nax_reg));
4314 match(RegP);
4315 match(eBXRegP);
4316 match(eDXRegP);
4317 match(eCXRegP);
4318 match(eSIRegP);
4319 match(eDIRegP);
4321 format %{ %}
4322 interface(REG_INTER);
4323 %}
4325 operand nabxRegP() %{
4326 constraint(ALLOC_IN_RC(nabx_reg));
4327 match(RegP);
4328 match(eCXRegP);
4329 match(eDXRegP);
4330 match(eSIRegP);
4331 match(eDIRegP);
4333 format %{ %}
4334 interface(REG_INTER);
4335 %}
4337 operand pRegP() %{
4338 constraint(ALLOC_IN_RC(p_reg));
4339 match(RegP);
4340 match(eBXRegP);
4341 match(eDXRegP);
4342 match(eSIRegP);
4343 match(eDIRegP);
4345 format %{ %}
4346 interface(REG_INTER);
4347 %}
4349 // Special Registers
4350 // Return a pointer value
4351 operand eAXRegP(eRegP reg) %{
4352 constraint(ALLOC_IN_RC(eax_reg));
4353 match(reg);
4354 format %{ "EAX" %}
4355 interface(REG_INTER);
4356 %}
4358 // Used in AtomicAdd
4359 operand eBXRegP(eRegP reg) %{
4360 constraint(ALLOC_IN_RC(ebx_reg));
4361 match(reg);
4362 format %{ "EBX" %}
4363 interface(REG_INTER);
4364 %}
4366 // Tail-call (interprocedural jump) to interpreter
4367 operand eCXRegP(eRegP reg) %{
4368 constraint(ALLOC_IN_RC(ecx_reg));
4369 match(reg);
4370 format %{ "ECX" %}
4371 interface(REG_INTER);
4372 %}
4374 operand eSIRegP(eRegP reg) %{
4375 constraint(ALLOC_IN_RC(esi_reg));
4376 match(reg);
4377 format %{ "ESI" %}
4378 interface(REG_INTER);
4379 %}
4381 // Used in rep stosw
4382 operand eDIRegP(eRegP reg) %{
4383 constraint(ALLOC_IN_RC(edi_reg));
4384 match(reg);
4385 format %{ "EDI" %}
4386 interface(REG_INTER);
4387 %}
4389 operand eBPRegP() %{
4390 constraint(ALLOC_IN_RC(ebp_reg));
4391 match(RegP);
4392 format %{ "EBP" %}
4393 interface(REG_INTER);
4394 %}
4396 operand eRegL() %{
4397 constraint(ALLOC_IN_RC(long_reg));
4398 match(RegL);
4399 match(eADXRegL);
4401 format %{ %}
4402 interface(REG_INTER);
4403 %}
4405 operand eADXRegL( eRegL reg ) %{
4406 constraint(ALLOC_IN_RC(eadx_reg));
4407 match(reg);
4409 format %{ "EDX:EAX" %}
4410 interface(REG_INTER);
4411 %}
4413 operand eBCXRegL( eRegL reg ) %{
4414 constraint(ALLOC_IN_RC(ebcx_reg));
4415 match(reg);
4417 format %{ "EBX:ECX" %}
4418 interface(REG_INTER);
4419 %}
4421 // Special case for integer high multiply
4422 operand eADXRegL_low_only() %{
4423 constraint(ALLOC_IN_RC(eadx_reg));
4424 match(RegL);
4426 format %{ "EAX" %}
4427 interface(REG_INTER);
4428 %}
4430 // Flags register, used as output of compare instructions
4431 operand eFlagsReg() %{
4432 constraint(ALLOC_IN_RC(int_flags));
4433 match(RegFlags);
4435 format %{ "EFLAGS" %}
4436 interface(REG_INTER);
4437 %}
4439 // Flags register, used as output of FLOATING POINT compare instructions
4440 operand eFlagsRegU() %{
4441 constraint(ALLOC_IN_RC(int_flags));
4442 match(RegFlags);
4444 format %{ "EFLAGS_U" %}
4445 interface(REG_INTER);
4446 %}
4448 operand eFlagsRegUCF() %{
4449 constraint(ALLOC_IN_RC(int_flags));
4450 match(RegFlags);
4451 predicate(false);
4453 format %{ "EFLAGS_U_CF" %}
4454 interface(REG_INTER);
4455 %}
4457 // Condition Code Register used by long compare
4458 operand flagsReg_long_LTGE() %{
4459 constraint(ALLOC_IN_RC(int_flags));
4460 match(RegFlags);
4461 format %{ "FLAGS_LTGE" %}
4462 interface(REG_INTER);
4463 %}
4464 operand flagsReg_long_EQNE() %{
4465 constraint(ALLOC_IN_RC(int_flags));
4466 match(RegFlags);
4467 format %{ "FLAGS_EQNE" %}
4468 interface(REG_INTER);
4469 %}
4470 operand flagsReg_long_LEGT() %{
4471 constraint(ALLOC_IN_RC(int_flags));
4472 match(RegFlags);
4473 format %{ "FLAGS_LEGT" %}
4474 interface(REG_INTER);
4475 %}
4477 // Float register operands
4478 operand regDPR() %{
4479 predicate( UseSSE < 2 );
4480 constraint(ALLOC_IN_RC(dbl_reg));
4481 match(RegD);
4482 match(regDPR1);
4483 match(regDPR2);
4484 format %{ %}
4485 interface(REG_INTER);
4486 %}
4488 operand regDPR1(regDPR reg) %{
4489 predicate( UseSSE < 2 );
4490 constraint(ALLOC_IN_RC(dbl_reg0));
4491 match(reg);
4492 format %{ "FPR1" %}
4493 interface(REG_INTER);
4494 %}
4496 operand regDPR2(regDPR reg) %{
4497 predicate( UseSSE < 2 );
4498 constraint(ALLOC_IN_RC(dbl_reg1));
4499 match(reg);
4500 format %{ "FPR2" %}
4501 interface(REG_INTER);
4502 %}
4504 operand regnotDPR1(regDPR reg) %{
4505 predicate( UseSSE < 2 );
4506 constraint(ALLOC_IN_RC(dbl_notreg0));
4507 match(reg);
4508 format %{ %}
4509 interface(REG_INTER);
4510 %}
4512 // XMM Double register operands
4513 operand regD() %{
4514 predicate( UseSSE>=2 );
4515 constraint(ALLOC_IN_RC(xdb_reg));
4516 match(RegD);
4517 match(regD6);
4518 match(regD7);
4519 format %{ %}
4520 interface(REG_INTER);
4521 %}
4523 // XMM6 double register operands
4524 operand regD6(regD reg) %{
4525 predicate( UseSSE>=2 );
4526 constraint(ALLOC_IN_RC(xdb_reg6));
4527 match(reg);
4528 format %{ "XMM6" %}
4529 interface(REG_INTER);
4530 %}
4532 // XMM7 double register operands
4533 operand regD7(regD reg) %{
4534 predicate( UseSSE>=2 );
4535 constraint(ALLOC_IN_RC(xdb_reg7));
4536 match(reg);
4537 format %{ "XMM7" %}
4538 interface(REG_INTER);
4539 %}
4541 // Float register operands
4542 operand regFPR() %{
4543 predicate( UseSSE < 2 );
4544 constraint(ALLOC_IN_RC(flt_reg));
4545 match(RegF);
4546 match(regFPR1);
4547 format %{ %}
4548 interface(REG_INTER);
4549 %}
4551 // Float register operands
4552 operand regFPR1(regFPR reg) %{
4553 predicate( UseSSE < 2 );
4554 constraint(ALLOC_IN_RC(flt_reg0));
4555 match(reg);
4556 format %{ "FPR1" %}
4557 interface(REG_INTER);
4558 %}
4560 // XMM register operands
4561 operand regF() %{
4562 predicate( UseSSE>=1 );
4563 constraint(ALLOC_IN_RC(xmm_reg));
4564 match(RegF);
4565 format %{ %}
4566 interface(REG_INTER);
4567 %}
4570 //----------Memory Operands----------------------------------------------------
4571 // Direct Memory Operand
4572 operand direct(immP addr) %{
4573 match(addr);
4575 format %{ "[$addr]" %}
4576 interface(MEMORY_INTER) %{
4577 base(0xFFFFFFFF);
4578 index(0x4);
4579 scale(0x0);
4580 disp($addr);
4581 %}
4582 %}
4584 // Indirect Memory Operand
4585 operand indirect(eRegP reg) %{
4586 constraint(ALLOC_IN_RC(e_reg));
4587 match(reg);
4589 format %{ "[$reg]" %}
4590 interface(MEMORY_INTER) %{
4591 base($reg);
4592 index(0x4);
4593 scale(0x0);
4594 disp(0x0);
4595 %}
4596 %}
4598 // Indirect Memory Plus Short Offset Operand
4599 operand indOffset8(eRegP reg, immI8 off) %{
4600 match(AddP reg off);
4602 format %{ "[$reg + $off]" %}
4603 interface(MEMORY_INTER) %{
4604 base($reg);
4605 index(0x4);
4606 scale(0x0);
4607 disp($off);
4608 %}
4609 %}
4611 // Indirect Memory Plus Long Offset Operand
4612 operand indOffset32(eRegP reg, immI off) %{
4613 match(AddP reg off);
4615 format %{ "[$reg + $off]" %}
4616 interface(MEMORY_INTER) %{
4617 base($reg);
4618 index(0x4);
4619 scale(0x0);
4620 disp($off);
4621 %}
4622 %}
4624 // Indirect Memory Plus Long Offset Operand
4625 operand indOffset32X(eRegI reg, immP off) %{
4626 match(AddP off reg);
4628 format %{ "[$reg + $off]" %}
4629 interface(MEMORY_INTER) %{
4630 base($reg);
4631 index(0x4);
4632 scale(0x0);
4633 disp($off);
4634 %}
4635 %}
4637 // Indirect Memory Plus Index Register Plus Offset Operand
4638 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
4639 match(AddP (AddP reg ireg) off);
4641 op_cost(10);
4642 format %{"[$reg + $off + $ireg]" %}
4643 interface(MEMORY_INTER) %{
4644 base($reg);
4645 index($ireg);
4646 scale(0x0);
4647 disp($off);
4648 %}
4649 %}
4651 // Indirect Memory Plus Index Register Plus Offset Operand
4652 operand indIndex(eRegP reg, eRegI ireg) %{
4653 match(AddP reg ireg);
4655 op_cost(10);
4656 format %{"[$reg + $ireg]" %}
4657 interface(MEMORY_INTER) %{
4658 base($reg);
4659 index($ireg);
4660 scale(0x0);
4661 disp(0x0);
4662 %}
4663 %}
4665 // // -------------------------------------------------------------------------
4666 // // 486 architecture doesn't support "scale * index + offset" with out a base
4667 // // -------------------------------------------------------------------------
4668 // // Scaled Memory Operands
4669 // // Indirect Memory Times Scale Plus Offset Operand
4670 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
4671 // match(AddP off (LShiftI ireg scale));
4672 //
4673 // op_cost(10);
4674 // format %{"[$off + $ireg << $scale]" %}
4675 // interface(MEMORY_INTER) %{
4676 // base(0x4);
4677 // index($ireg);
4678 // scale($scale);
4679 // disp($off);
4680 // %}
4681 // %}
4683 // Indirect Memory Times Scale Plus Index Register
4684 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
4685 match(AddP reg (LShiftI ireg scale));
4687 op_cost(10);
4688 format %{"[$reg + $ireg << $scale]" %}
4689 interface(MEMORY_INTER) %{
4690 base($reg);
4691 index($ireg);
4692 scale($scale);
4693 disp(0x0);
4694 %}
4695 %}
4697 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4698 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
4699 match(AddP (AddP reg (LShiftI ireg scale)) off);
4701 op_cost(10);
4702 format %{"[$reg + $off + $ireg << $scale]" %}
4703 interface(MEMORY_INTER) %{
4704 base($reg);
4705 index($ireg);
4706 scale($scale);
4707 disp($off);
4708 %}
4709 %}
4711 //----------Load Long Memory Operands------------------------------------------
4712 // The load-long idiom will use it's address expression again after loading
4713 // the first word of the long. If the load-long destination overlaps with
4714 // registers used in the addressing expression, the 2nd half will be loaded
4715 // from a clobbered address. Fix this by requiring that load-long use
4716 // address registers that do not overlap with the load-long target.
4718 // load-long support
4719 operand load_long_RegP() %{
4720 constraint(ALLOC_IN_RC(esi_reg));
4721 match(RegP);
4722 match(eSIRegP);
4723 op_cost(100);
4724 format %{ %}
4725 interface(REG_INTER);
4726 %}
4728 // Indirect Memory Operand Long
4729 operand load_long_indirect(load_long_RegP reg) %{
4730 constraint(ALLOC_IN_RC(esi_reg));
4731 match(reg);
4733 format %{ "[$reg]" %}
4734 interface(MEMORY_INTER) %{
4735 base($reg);
4736 index(0x4);
4737 scale(0x0);
4738 disp(0x0);
4739 %}
4740 %}
4742 // Indirect Memory Plus Long Offset Operand
4743 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4744 match(AddP reg off);
4746 format %{ "[$reg + $off]" %}
4747 interface(MEMORY_INTER) %{
4748 base($reg);
4749 index(0x4);
4750 scale(0x0);
4751 disp($off);
4752 %}
4753 %}
4755 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4758 //----------Special Memory Operands--------------------------------------------
4759 // Stack Slot Operand - This operand is used for loading and storing temporary
4760 // values on the stack where a match requires a value to
4761 // flow through memory.
4762 operand stackSlotP(sRegP reg) %{
4763 constraint(ALLOC_IN_RC(stack_slots));
4764 // No match rule because this operand is only generated in matching
4765 format %{ "[$reg]" %}
4766 interface(MEMORY_INTER) %{
4767 base(0x4); // ESP
4768 index(0x4); // No Index
4769 scale(0x0); // No Scale
4770 disp($reg); // Stack Offset
4771 %}
4772 %}
4774 operand stackSlotI(sRegI reg) %{
4775 constraint(ALLOC_IN_RC(stack_slots));
4776 // No match rule because this operand is only generated in matching
4777 format %{ "[$reg]" %}
4778 interface(MEMORY_INTER) %{
4779 base(0x4); // ESP
4780 index(0x4); // No Index
4781 scale(0x0); // No Scale
4782 disp($reg); // Stack Offset
4783 %}
4784 %}
4786 operand stackSlotF(sRegF reg) %{
4787 constraint(ALLOC_IN_RC(stack_slots));
4788 // No match rule because this operand is only generated in matching
4789 format %{ "[$reg]" %}
4790 interface(MEMORY_INTER) %{
4791 base(0x4); // ESP
4792 index(0x4); // No Index
4793 scale(0x0); // No Scale
4794 disp($reg); // Stack Offset
4795 %}
4796 %}
4798 operand stackSlotD(sRegD reg) %{
4799 constraint(ALLOC_IN_RC(stack_slots));
4800 // No match rule because this operand is only generated in matching
4801 format %{ "[$reg]" %}
4802 interface(MEMORY_INTER) %{
4803 base(0x4); // ESP
4804 index(0x4); // No Index
4805 scale(0x0); // No Scale
4806 disp($reg); // Stack Offset
4807 %}
4808 %}
4810 operand stackSlotL(sRegL reg) %{
4811 constraint(ALLOC_IN_RC(stack_slots));
4812 // No match rule because this operand is only generated in matching
4813 format %{ "[$reg]" %}
4814 interface(MEMORY_INTER) %{
4815 base(0x4); // ESP
4816 index(0x4); // No Index
4817 scale(0x0); // No Scale
4818 disp($reg); // Stack Offset
4819 %}
4820 %}
4822 //----------Memory Operands - Win95 Implicit Null Variants----------------
4823 // Indirect Memory Operand
4824 operand indirect_win95_safe(eRegP_no_EBP reg)
4825 %{
4826 constraint(ALLOC_IN_RC(e_reg));
4827 match(reg);
4829 op_cost(100);
4830 format %{ "[$reg]" %}
4831 interface(MEMORY_INTER) %{
4832 base($reg);
4833 index(0x4);
4834 scale(0x0);
4835 disp(0x0);
4836 %}
4837 %}
4839 // Indirect Memory Plus Short Offset Operand
4840 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4841 %{
4842 match(AddP reg off);
4844 op_cost(100);
4845 format %{ "[$reg + $off]" %}
4846 interface(MEMORY_INTER) %{
4847 base($reg);
4848 index(0x4);
4849 scale(0x0);
4850 disp($off);
4851 %}
4852 %}
4854 // Indirect Memory Plus Long Offset Operand
4855 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4856 %{
4857 match(AddP reg off);
4859 op_cost(100);
4860 format %{ "[$reg + $off]" %}
4861 interface(MEMORY_INTER) %{
4862 base($reg);
4863 index(0x4);
4864 scale(0x0);
4865 disp($off);
4866 %}
4867 %}
4869 // Indirect Memory Plus Index Register Plus Offset Operand
4870 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
4871 %{
4872 match(AddP (AddP reg ireg) off);
4874 op_cost(100);
4875 format %{"[$reg + $off + $ireg]" %}
4876 interface(MEMORY_INTER) %{
4877 base($reg);
4878 index($ireg);
4879 scale(0x0);
4880 disp($off);
4881 %}
4882 %}
4884 // Indirect Memory Times Scale Plus Index Register
4885 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
4886 %{
4887 match(AddP reg (LShiftI ireg scale));
4889 op_cost(100);
4890 format %{"[$reg + $ireg << $scale]" %}
4891 interface(MEMORY_INTER) %{
4892 base($reg);
4893 index($ireg);
4894 scale($scale);
4895 disp(0x0);
4896 %}
4897 %}
4899 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4900 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
4901 %{
4902 match(AddP (AddP reg (LShiftI ireg scale)) off);
4904 op_cost(100);
4905 format %{"[$reg + $off + $ireg << $scale]" %}
4906 interface(MEMORY_INTER) %{
4907 base($reg);
4908 index($ireg);
4909 scale($scale);
4910 disp($off);
4911 %}
4912 %}
4914 //----------Conditional Branch Operands----------------------------------------
4915 // Comparison Op - This is the operation of the comparison, and is limited to
4916 // the following set of codes:
4917 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4918 //
4919 // Other attributes of the comparison, such as unsignedness, are specified
4920 // by the comparison instruction that sets a condition code flags register.
4921 // That result is represented by a flags operand whose subtype is appropriate
4922 // to the unsignedness (etc.) of the comparison.
4923 //
4924 // Later, the instruction which matches both the Comparison Op (a Bool) and
4925 // the flags (produced by the Cmp) specifies the coding of the comparison op
4926 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4928 // Comparision Code
4929 operand cmpOp() %{
4930 match(Bool);
4932 format %{ "" %}
4933 interface(COND_INTER) %{
4934 equal(0x4, "e");
4935 not_equal(0x5, "ne");
4936 less(0xC, "l");
4937 greater_equal(0xD, "ge");
4938 less_equal(0xE, "le");
4939 greater(0xF, "g");
4940 %}
4941 %}
4943 // Comparison Code, unsigned compare. Used by FP also, with
4944 // C2 (unordered) turned into GT or LT already. The other bits
4945 // C0 and C3 are turned into Carry & Zero flags.
4946 operand cmpOpU() %{
4947 match(Bool);
4949 format %{ "" %}
4950 interface(COND_INTER) %{
4951 equal(0x4, "e");
4952 not_equal(0x5, "ne");
4953 less(0x2, "b");
4954 greater_equal(0x3, "nb");
4955 less_equal(0x6, "be");
4956 greater(0x7, "nbe");
4957 %}
4958 %}
4960 // Floating comparisons that don't require any fixup for the unordered case
4961 operand cmpOpUCF() %{
4962 match(Bool);
4963 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4964 n->as_Bool()->_test._test == BoolTest::ge ||
4965 n->as_Bool()->_test._test == BoolTest::le ||
4966 n->as_Bool()->_test._test == BoolTest::gt);
4967 format %{ "" %}
4968 interface(COND_INTER) %{
4969 equal(0x4, "e");
4970 not_equal(0x5, "ne");
4971 less(0x2, "b");
4972 greater_equal(0x3, "nb");
4973 less_equal(0x6, "be");
4974 greater(0x7, "nbe");
4975 %}
4976 %}
4979 // Floating comparisons that can be fixed up with extra conditional jumps
4980 operand cmpOpUCF2() %{
4981 match(Bool);
4982 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4983 n->as_Bool()->_test._test == BoolTest::eq);
4984 format %{ "" %}
4985 interface(COND_INTER) %{
4986 equal(0x4, "e");
4987 not_equal(0x5, "ne");
4988 less(0x2, "b");
4989 greater_equal(0x3, "nb");
4990 less_equal(0x6, "be");
4991 greater(0x7, "nbe");
4992 %}
4993 %}
4995 // Comparison Code for FP conditional move
4996 operand cmpOp_fcmov() %{
4997 match(Bool);
4999 format %{ "" %}
5000 interface(COND_INTER) %{
5001 equal (0x0C8);
5002 not_equal (0x1C8);
5003 less (0x0C0);
5004 greater_equal(0x1C0);
5005 less_equal (0x0D0);
5006 greater (0x1D0);
5007 %}
5008 %}
5010 // Comparision Code used in long compares
5011 operand cmpOp_commute() %{
5012 match(Bool);
5014 format %{ "" %}
5015 interface(COND_INTER) %{
5016 equal(0x4, "e");
5017 not_equal(0x5, "ne");
5018 less(0xF, "g");
5019 greater_equal(0xE, "le");
5020 less_equal(0xD, "ge");
5021 greater(0xC, "l");
5022 %}
5023 %}
5025 //----------OPERAND CLASSES----------------------------------------------------
5026 // Operand Classes are groups of operands that are used as to simplify
5027 // instruction definitions by not requiring the AD writer to specify separate
5028 // instructions for every form of operand when the instruction accepts
5029 // multiple operand types with the same basic encoding and format. The classic
5030 // case of this is memory operands.
5032 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5033 indIndex, indIndexScale, indIndexScaleOffset);
5035 // Long memory operations are encoded in 2 instructions and a +4 offset.
5036 // This means some kind of offset is always required and you cannot use
5037 // an oop as the offset (done when working on static globals).
5038 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5039 indIndex, indIndexScale, indIndexScaleOffset);
5042 //----------PIPELINE-----------------------------------------------------------
5043 // Rules which define the behavior of the target architectures pipeline.
5044 pipeline %{
5046 //----------ATTRIBUTES---------------------------------------------------------
5047 attributes %{
5048 variable_size_instructions; // Fixed size instructions
5049 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5050 instruction_unit_size = 1; // An instruction is 1 bytes long
5051 instruction_fetch_unit_size = 16; // The processor fetches one line
5052 instruction_fetch_units = 1; // of 16 bytes
5054 // List of nop instructions
5055 nops( MachNop );
5056 %}
5058 //----------RESOURCES----------------------------------------------------------
5059 // Resources are the functional units available to the machine
5061 // Generic P2/P3 pipeline
5062 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5063 // 3 instructions decoded per cycle.
5064 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5065 // 2 ALU op, only ALU0 handles mul/div instructions.
5066 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5067 MS0, MS1, MEM = MS0 | MS1,
5068 BR, FPU,
5069 ALU0, ALU1, ALU = ALU0 | ALU1 );
5071 //----------PIPELINE DESCRIPTION-----------------------------------------------
5072 // Pipeline Description specifies the stages in the machine's pipeline
5074 // Generic P2/P3 pipeline
5075 pipe_desc(S0, S1, S2, S3, S4, S5);
5077 //----------PIPELINE CLASSES---------------------------------------------------
5078 // Pipeline Classes describe the stages in which input and output are
5079 // referenced by the hardware pipeline.
5081 // Naming convention: ialu or fpu
5082 // Then: _reg
5083 // Then: _reg if there is a 2nd register
5084 // Then: _long if it's a pair of instructions implementing a long
5085 // Then: _fat if it requires the big decoder
5086 // Or: _mem if it requires the big decoder and a memory unit.
5088 // Integer ALU reg operation
5089 pipe_class ialu_reg(eRegI dst) %{
5090 single_instruction;
5091 dst : S4(write);
5092 dst : S3(read);
5093 DECODE : S0; // any decoder
5094 ALU : S3; // any alu
5095 %}
5097 // Long ALU reg operation
5098 pipe_class ialu_reg_long(eRegL dst) %{
5099 instruction_count(2);
5100 dst : S4(write);
5101 dst : S3(read);
5102 DECODE : S0(2); // any 2 decoders
5103 ALU : S3(2); // both alus
5104 %}
5106 // Integer ALU reg operation using big decoder
5107 pipe_class ialu_reg_fat(eRegI dst) %{
5108 single_instruction;
5109 dst : S4(write);
5110 dst : S3(read);
5111 D0 : S0; // big decoder only
5112 ALU : S3; // any alu
5113 %}
5115 // Long ALU reg operation using big decoder
5116 pipe_class ialu_reg_long_fat(eRegL dst) %{
5117 instruction_count(2);
5118 dst : S4(write);
5119 dst : S3(read);
5120 D0 : S0(2); // big decoder only; twice
5121 ALU : S3(2); // any 2 alus
5122 %}
5124 // Integer ALU reg-reg operation
5125 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
5126 single_instruction;
5127 dst : S4(write);
5128 src : S3(read);
5129 DECODE : S0; // any decoder
5130 ALU : S3; // any alu
5131 %}
5133 // Long ALU reg-reg operation
5134 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5135 instruction_count(2);
5136 dst : S4(write);
5137 src : S3(read);
5138 DECODE : S0(2); // any 2 decoders
5139 ALU : S3(2); // both alus
5140 %}
5142 // Integer ALU reg-reg operation
5143 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
5144 single_instruction;
5145 dst : S4(write);
5146 src : S3(read);
5147 D0 : S0; // big decoder only
5148 ALU : S3; // any alu
5149 %}
5151 // Long ALU reg-reg operation
5152 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5153 instruction_count(2);
5154 dst : S4(write);
5155 src : S3(read);
5156 D0 : S0(2); // big decoder only; twice
5157 ALU : S3(2); // both alus
5158 %}
5160 // Integer ALU reg-mem operation
5161 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
5162 single_instruction;
5163 dst : S5(write);
5164 mem : S3(read);
5165 D0 : S0; // big decoder only
5166 ALU : S4; // any alu
5167 MEM : S3; // any mem
5168 %}
5170 // Long ALU reg-mem operation
5171 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5172 instruction_count(2);
5173 dst : S5(write);
5174 mem : S3(read);
5175 D0 : S0(2); // big decoder only; twice
5176 ALU : S4(2); // any 2 alus
5177 MEM : S3(2); // both mems
5178 %}
5180 // Integer mem operation (prefetch)
5181 pipe_class ialu_mem(memory mem)
5182 %{
5183 single_instruction;
5184 mem : S3(read);
5185 D0 : S0; // big decoder only
5186 MEM : S3; // any mem
5187 %}
5189 // Integer Store to Memory
5190 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
5191 single_instruction;
5192 mem : S3(read);
5193 src : S5(read);
5194 D0 : S0; // big decoder only
5195 ALU : S4; // any alu
5196 MEM : S3;
5197 %}
5199 // Long Store to Memory
5200 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5201 instruction_count(2);
5202 mem : S3(read);
5203 src : S5(read);
5204 D0 : S0(2); // big decoder only; twice
5205 ALU : S4(2); // any 2 alus
5206 MEM : S3(2); // Both mems
5207 %}
5209 // Integer Store to Memory
5210 pipe_class ialu_mem_imm(memory mem) %{
5211 single_instruction;
5212 mem : S3(read);
5213 D0 : S0; // big decoder only
5214 ALU : S4; // any alu
5215 MEM : S3;
5216 %}
5218 // Integer ALU0 reg-reg operation
5219 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
5220 single_instruction;
5221 dst : S4(write);
5222 src : S3(read);
5223 D0 : S0; // Big decoder only
5224 ALU0 : S3; // only alu0
5225 %}
5227 // Integer ALU0 reg-mem operation
5228 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
5229 single_instruction;
5230 dst : S5(write);
5231 mem : S3(read);
5232 D0 : S0; // big decoder only
5233 ALU0 : S4; // ALU0 only
5234 MEM : S3; // any mem
5235 %}
5237 // Integer ALU reg-reg operation
5238 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
5239 single_instruction;
5240 cr : S4(write);
5241 src1 : S3(read);
5242 src2 : S3(read);
5243 DECODE : S0; // any decoder
5244 ALU : S3; // any alu
5245 %}
5247 // Integer ALU reg-imm operation
5248 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
5249 single_instruction;
5250 cr : S4(write);
5251 src1 : S3(read);
5252 DECODE : S0; // any decoder
5253 ALU : S3; // any alu
5254 %}
5256 // Integer ALU reg-mem operation
5257 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
5258 single_instruction;
5259 cr : S4(write);
5260 src1 : S3(read);
5261 src2 : S3(read);
5262 D0 : S0; // big decoder only
5263 ALU : S4; // any alu
5264 MEM : S3;
5265 %}
5267 // Conditional move reg-reg
5268 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
5269 instruction_count(4);
5270 y : S4(read);
5271 q : S3(read);
5272 p : S3(read);
5273 DECODE : S0(4); // any decoder
5274 %}
5276 // Conditional move reg-reg
5277 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
5278 single_instruction;
5279 dst : S4(write);
5280 src : S3(read);
5281 cr : S3(read);
5282 DECODE : S0; // any decoder
5283 %}
5285 // Conditional move reg-mem
5286 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
5287 single_instruction;
5288 dst : S4(write);
5289 src : S3(read);
5290 cr : S3(read);
5291 DECODE : S0; // any decoder
5292 MEM : S3;
5293 %}
5295 // Conditional move reg-reg long
5296 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5297 single_instruction;
5298 dst : S4(write);
5299 src : S3(read);
5300 cr : S3(read);
5301 DECODE : S0(2); // any 2 decoders
5302 %}
5304 // Conditional move double reg-reg
5305 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5306 single_instruction;
5307 dst : S4(write);
5308 src : S3(read);
5309 cr : S3(read);
5310 DECODE : S0; // any decoder
5311 %}
5313 // Float reg-reg operation
5314 pipe_class fpu_reg(regDPR dst) %{
5315 instruction_count(2);
5316 dst : S3(read);
5317 DECODE : S0(2); // any 2 decoders
5318 FPU : S3;
5319 %}
5321 // Float reg-reg operation
5322 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5323 instruction_count(2);
5324 dst : S4(write);
5325 src : S3(read);
5326 DECODE : S0(2); // any 2 decoders
5327 FPU : S3;
5328 %}
5330 // Float reg-reg operation
5331 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5332 instruction_count(3);
5333 dst : S4(write);
5334 src1 : S3(read);
5335 src2 : S3(read);
5336 DECODE : S0(3); // any 3 decoders
5337 FPU : S3(2);
5338 %}
5340 // Float reg-reg operation
5341 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5342 instruction_count(4);
5343 dst : S4(write);
5344 src1 : S3(read);
5345 src2 : S3(read);
5346 src3 : S3(read);
5347 DECODE : S0(4); // any 3 decoders
5348 FPU : S3(2);
5349 %}
5351 // Float reg-reg operation
5352 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5353 instruction_count(4);
5354 dst : S4(write);
5355 src1 : S3(read);
5356 src2 : S3(read);
5357 src3 : S3(read);
5358 DECODE : S1(3); // any 3 decoders
5359 D0 : S0; // Big decoder only
5360 FPU : S3(2);
5361 MEM : S3;
5362 %}
5364 // Float reg-mem operation
5365 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5366 instruction_count(2);
5367 dst : S5(write);
5368 mem : S3(read);
5369 D0 : S0; // big decoder only
5370 DECODE : S1; // any decoder for FPU POP
5371 FPU : S4;
5372 MEM : S3; // any mem
5373 %}
5375 // Float reg-mem operation
5376 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5377 instruction_count(3);
5378 dst : S5(write);
5379 src1 : S3(read);
5380 mem : S3(read);
5381 D0 : S0; // big decoder only
5382 DECODE : S1(2); // any decoder for FPU POP
5383 FPU : S4;
5384 MEM : S3; // any mem
5385 %}
5387 // Float mem-reg operation
5388 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5389 instruction_count(2);
5390 src : S5(read);
5391 mem : S3(read);
5392 DECODE : S0; // any decoder for FPU PUSH
5393 D0 : S1; // big decoder only
5394 FPU : S4;
5395 MEM : S3; // any mem
5396 %}
5398 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5399 instruction_count(3);
5400 src1 : S3(read);
5401 src2 : S3(read);
5402 mem : S3(read);
5403 DECODE : S0(2); // any decoder for FPU PUSH
5404 D0 : S1; // big decoder only
5405 FPU : S4;
5406 MEM : S3; // any mem
5407 %}
5409 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5410 instruction_count(3);
5411 src1 : S3(read);
5412 src2 : S3(read);
5413 mem : S4(read);
5414 DECODE : S0; // any decoder for FPU PUSH
5415 D0 : S0(2); // big decoder only
5416 FPU : S4;
5417 MEM : S3(2); // any mem
5418 %}
5420 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5421 instruction_count(2);
5422 src1 : S3(read);
5423 dst : S4(read);
5424 D0 : S0(2); // big decoder only
5425 MEM : S3(2); // any mem
5426 %}
5428 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5429 instruction_count(3);
5430 src1 : S3(read);
5431 src2 : S3(read);
5432 dst : S4(read);
5433 D0 : S0(3); // big decoder only
5434 FPU : S4;
5435 MEM : S3(3); // any mem
5436 %}
5438 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5439 instruction_count(3);
5440 src1 : S4(read);
5441 mem : S4(read);
5442 DECODE : S0; // any decoder for FPU PUSH
5443 D0 : S0(2); // big decoder only
5444 FPU : S4;
5445 MEM : S3(2); // any mem
5446 %}
5448 // Float load constant
5449 pipe_class fpu_reg_con(regDPR dst) %{
5450 instruction_count(2);
5451 dst : S5(write);
5452 D0 : S0; // big decoder only for the load
5453 DECODE : S1; // any decoder for FPU POP
5454 FPU : S4;
5455 MEM : S3; // any mem
5456 %}
5458 // Float load constant
5459 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5460 instruction_count(3);
5461 dst : S5(write);
5462 src : S3(read);
5463 D0 : S0; // big decoder only for the load
5464 DECODE : S1(2); // any decoder for FPU POP
5465 FPU : S4;
5466 MEM : S3; // any mem
5467 %}
5469 // UnConditional branch
5470 pipe_class pipe_jmp( label labl ) %{
5471 single_instruction;
5472 BR : S3;
5473 %}
5475 // Conditional branch
5476 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5477 single_instruction;
5478 cr : S1(read);
5479 BR : S3;
5480 %}
5482 // Allocation idiom
5483 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5484 instruction_count(1); force_serialization;
5485 fixed_latency(6);
5486 heap_ptr : S3(read);
5487 DECODE : S0(3);
5488 D0 : S2;
5489 MEM : S3;
5490 ALU : S3(2);
5491 dst : S5(write);
5492 BR : S5;
5493 %}
5495 // Generic big/slow expanded idiom
5496 pipe_class pipe_slow( ) %{
5497 instruction_count(10); multiple_bundles; force_serialization;
5498 fixed_latency(100);
5499 D0 : S0(2);
5500 MEM : S3(2);
5501 %}
5503 // The real do-nothing guy
5504 pipe_class empty( ) %{
5505 instruction_count(0);
5506 %}
5508 // Define the class for the Nop node
5509 define %{
5510 MachNop = empty;
5511 %}
5513 %}
5515 //----------INSTRUCTIONS-------------------------------------------------------
5516 //
5517 // match -- States which machine-independent subtree may be replaced
5518 // by this instruction.
5519 // ins_cost -- The estimated cost of this instruction is used by instruction
5520 // selection to identify a minimum cost tree of machine
5521 // instructions that matches a tree of machine-independent
5522 // instructions.
5523 // format -- A string providing the disassembly for this instruction.
5524 // The value of an instruction's operand may be inserted
5525 // by referring to it with a '$' prefix.
5526 // opcode -- Three instruction opcodes may be provided. These are referred
5527 // to within an encode class as $primary, $secondary, and $tertiary
5528 // respectively. The primary opcode is commonly used to
5529 // indicate the type of machine instruction, while secondary
5530 // and tertiary are often used for prefix options or addressing
5531 // modes.
5532 // ins_encode -- A list of encode classes with parameters. The encode class
5533 // name must have been defined in an 'enc_class' specification
5534 // in the encode section of the architecture description.
5536 //----------BSWAP-Instruction--------------------------------------------------
5537 instruct bytes_reverse_int(eRegI dst) %{
5538 match(Set dst (ReverseBytesI dst));
5540 format %{ "BSWAP $dst" %}
5541 opcode(0x0F, 0xC8);
5542 ins_encode( OpcP, OpcSReg(dst) );
5543 ins_pipe( ialu_reg );
5544 %}
5546 instruct bytes_reverse_long(eRegL dst) %{
5547 match(Set dst (ReverseBytesL dst));
5549 format %{ "BSWAP $dst.lo\n\t"
5550 "BSWAP $dst.hi\n\t"
5551 "XCHG $dst.lo $dst.hi" %}
5553 ins_cost(125);
5554 ins_encode( bswap_long_bytes(dst) );
5555 ins_pipe( ialu_reg_reg);
5556 %}
5558 instruct bytes_reverse_unsigned_short(eRegI dst, eFlagsReg cr) %{
5559 match(Set dst (ReverseBytesUS dst));
5560 effect(KILL cr);
5562 format %{ "BSWAP $dst\n\t"
5563 "SHR $dst,16\n\t" %}
5564 ins_encode %{
5565 __ bswapl($dst$$Register);
5566 __ shrl($dst$$Register, 16);
5567 %}
5568 ins_pipe( ialu_reg );
5569 %}
5571 instruct bytes_reverse_short(eRegI dst, eFlagsReg cr) %{
5572 match(Set dst (ReverseBytesS dst));
5573 effect(KILL cr);
5575 format %{ "BSWAP $dst\n\t"
5576 "SAR $dst,16\n\t" %}
5577 ins_encode %{
5578 __ bswapl($dst$$Register);
5579 __ sarl($dst$$Register, 16);
5580 %}
5581 ins_pipe( ialu_reg );
5582 %}
5585 //---------- Zeros Count Instructions ------------------------------------------
5587 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
5588 predicate(UseCountLeadingZerosInstruction);
5589 match(Set dst (CountLeadingZerosI src));
5590 effect(KILL cr);
5592 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5593 ins_encode %{
5594 __ lzcntl($dst$$Register, $src$$Register);
5595 %}
5596 ins_pipe(ialu_reg);
5597 %}
5599 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
5600 predicate(!UseCountLeadingZerosInstruction);
5601 match(Set dst (CountLeadingZerosI src));
5602 effect(KILL cr);
5604 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5605 "JNZ skip\n\t"
5606 "MOV $dst, -1\n"
5607 "skip:\n\t"
5608 "NEG $dst\n\t"
5609 "ADD $dst, 31" %}
5610 ins_encode %{
5611 Register Rdst = $dst$$Register;
5612 Register Rsrc = $src$$Register;
5613 Label skip;
5614 __ bsrl(Rdst, Rsrc);
5615 __ jccb(Assembler::notZero, skip);
5616 __ movl(Rdst, -1);
5617 __ bind(skip);
5618 __ negl(Rdst);
5619 __ addl(Rdst, BitsPerInt - 1);
5620 %}
5621 ins_pipe(ialu_reg);
5622 %}
5624 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
5625 predicate(UseCountLeadingZerosInstruction);
5626 match(Set dst (CountLeadingZerosL src));
5627 effect(TEMP dst, KILL cr);
5629 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5630 "JNC done\n\t"
5631 "LZCNT $dst, $src.lo\n\t"
5632 "ADD $dst, 32\n"
5633 "done:" %}
5634 ins_encode %{
5635 Register Rdst = $dst$$Register;
5636 Register Rsrc = $src$$Register;
5637 Label done;
5638 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5639 __ jccb(Assembler::carryClear, done);
5640 __ lzcntl(Rdst, Rsrc);
5641 __ addl(Rdst, BitsPerInt);
5642 __ bind(done);
5643 %}
5644 ins_pipe(ialu_reg);
5645 %}
5647 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
5648 predicate(!UseCountLeadingZerosInstruction);
5649 match(Set dst (CountLeadingZerosL src));
5650 effect(TEMP dst, KILL cr);
5652 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5653 "JZ msw_is_zero\n\t"
5654 "ADD $dst, 32\n\t"
5655 "JMP not_zero\n"
5656 "msw_is_zero:\n\t"
5657 "BSR $dst, $src.lo\n\t"
5658 "JNZ not_zero\n\t"
5659 "MOV $dst, -1\n"
5660 "not_zero:\n\t"
5661 "NEG $dst\n\t"
5662 "ADD $dst, 63\n" %}
5663 ins_encode %{
5664 Register Rdst = $dst$$Register;
5665 Register Rsrc = $src$$Register;
5666 Label msw_is_zero;
5667 Label not_zero;
5668 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5669 __ jccb(Assembler::zero, msw_is_zero);
5670 __ addl(Rdst, BitsPerInt);
5671 __ jmpb(not_zero);
5672 __ bind(msw_is_zero);
5673 __ bsrl(Rdst, Rsrc);
5674 __ jccb(Assembler::notZero, not_zero);
5675 __ movl(Rdst, -1);
5676 __ bind(not_zero);
5677 __ negl(Rdst);
5678 __ addl(Rdst, BitsPerLong - 1);
5679 %}
5680 ins_pipe(ialu_reg);
5681 %}
5683 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
5684 match(Set dst (CountTrailingZerosI src));
5685 effect(KILL cr);
5687 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5688 "JNZ done\n\t"
5689 "MOV $dst, 32\n"
5690 "done:" %}
5691 ins_encode %{
5692 Register Rdst = $dst$$Register;
5693 Label done;
5694 __ bsfl(Rdst, $src$$Register);
5695 __ jccb(Assembler::notZero, done);
5696 __ movl(Rdst, BitsPerInt);
5697 __ bind(done);
5698 %}
5699 ins_pipe(ialu_reg);
5700 %}
5702 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
5703 match(Set dst (CountTrailingZerosL src));
5704 effect(TEMP dst, KILL cr);
5706 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5707 "JNZ done\n\t"
5708 "BSF $dst, $src.hi\n\t"
5709 "JNZ msw_not_zero\n\t"
5710 "MOV $dst, 32\n"
5711 "msw_not_zero:\n\t"
5712 "ADD $dst, 32\n"
5713 "done:" %}
5714 ins_encode %{
5715 Register Rdst = $dst$$Register;
5716 Register Rsrc = $src$$Register;
5717 Label msw_not_zero;
5718 Label done;
5719 __ bsfl(Rdst, Rsrc);
5720 __ jccb(Assembler::notZero, done);
5721 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5722 __ jccb(Assembler::notZero, msw_not_zero);
5723 __ movl(Rdst, BitsPerInt);
5724 __ bind(msw_not_zero);
5725 __ addl(Rdst, BitsPerInt);
5726 __ bind(done);
5727 %}
5728 ins_pipe(ialu_reg);
5729 %}
5732 //---------- Population Count Instructions -------------------------------------
5734 instruct popCountI(eRegI dst, eRegI src, eFlagsReg cr) %{
5735 predicate(UsePopCountInstruction);
5736 match(Set dst (PopCountI src));
5737 effect(KILL cr);
5739 format %{ "POPCNT $dst, $src" %}
5740 ins_encode %{
5741 __ popcntl($dst$$Register, $src$$Register);
5742 %}
5743 ins_pipe(ialu_reg);
5744 %}
5746 instruct popCountI_mem(eRegI dst, memory mem, eFlagsReg cr) %{
5747 predicate(UsePopCountInstruction);
5748 match(Set dst (PopCountI (LoadI mem)));
5749 effect(KILL cr);
5751 format %{ "POPCNT $dst, $mem" %}
5752 ins_encode %{
5753 __ popcntl($dst$$Register, $mem$$Address);
5754 %}
5755 ins_pipe(ialu_reg);
5756 %}
5758 // Note: Long.bitCount(long) returns an int.
5759 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
5760 predicate(UsePopCountInstruction);
5761 match(Set dst (PopCountL src));
5762 effect(KILL cr, TEMP tmp, TEMP dst);
5764 format %{ "POPCNT $dst, $src.lo\n\t"
5765 "POPCNT $tmp, $src.hi\n\t"
5766 "ADD $dst, $tmp" %}
5767 ins_encode %{
5768 __ popcntl($dst$$Register, $src$$Register);
5769 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5770 __ addl($dst$$Register, $tmp$$Register);
5771 %}
5772 ins_pipe(ialu_reg);
5773 %}
5775 // Note: Long.bitCount(long) returns an int.
5776 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
5777 predicate(UsePopCountInstruction);
5778 match(Set dst (PopCountL (LoadL mem)));
5779 effect(KILL cr, TEMP tmp, TEMP dst);
5781 format %{ "POPCNT $dst, $mem\n\t"
5782 "POPCNT $tmp, $mem+4\n\t"
5783 "ADD $dst, $tmp" %}
5784 ins_encode %{
5785 //__ popcntl($dst$$Register, $mem$$Address$$first);
5786 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5787 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
5788 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
5789 __ addl($dst$$Register, $tmp$$Register);
5790 %}
5791 ins_pipe(ialu_reg);
5792 %}
5795 //----------Load/Store/Move Instructions---------------------------------------
5796 //----------Load Instructions--------------------------------------------------
5797 // Load Byte (8bit signed)
5798 instruct loadB(xRegI dst, memory mem) %{
5799 match(Set dst (LoadB mem));
5801 ins_cost(125);
5802 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5804 ins_encode %{
5805 __ movsbl($dst$$Register, $mem$$Address);
5806 %}
5808 ins_pipe(ialu_reg_mem);
5809 %}
5811 // Load Byte (8bit signed) into Long Register
5812 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5813 match(Set dst (ConvI2L (LoadB mem)));
5814 effect(KILL cr);
5816 ins_cost(375);
5817 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5818 "MOV $dst.hi,$dst.lo\n\t"
5819 "SAR $dst.hi,7" %}
5821 ins_encode %{
5822 __ movsbl($dst$$Register, $mem$$Address);
5823 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5824 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5825 %}
5827 ins_pipe(ialu_reg_mem);
5828 %}
5830 // Load Unsigned Byte (8bit UNsigned)
5831 instruct loadUB(xRegI dst, memory mem) %{
5832 match(Set dst (LoadUB mem));
5834 ins_cost(125);
5835 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5837 ins_encode %{
5838 __ movzbl($dst$$Register, $mem$$Address);
5839 %}
5841 ins_pipe(ialu_reg_mem);
5842 %}
5844 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5845 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5846 match(Set dst (ConvI2L (LoadUB mem)));
5847 effect(KILL cr);
5849 ins_cost(250);
5850 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5851 "XOR $dst.hi,$dst.hi" %}
5853 ins_encode %{
5854 Register Rdst = $dst$$Register;
5855 __ movzbl(Rdst, $mem$$Address);
5856 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5857 %}
5859 ins_pipe(ialu_reg_mem);
5860 %}
5862 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5863 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5864 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5865 effect(KILL cr);
5867 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5868 "XOR $dst.hi,$dst.hi\n\t"
5869 "AND $dst.lo,$mask" %}
5870 ins_encode %{
5871 Register Rdst = $dst$$Register;
5872 __ movzbl(Rdst, $mem$$Address);
5873 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5874 __ andl(Rdst, $mask$$constant);
5875 %}
5876 ins_pipe(ialu_reg_mem);
5877 %}
5879 // Load Short (16bit signed)
5880 instruct loadS(eRegI dst, memory mem) %{
5881 match(Set dst (LoadS mem));
5883 ins_cost(125);
5884 format %{ "MOVSX $dst,$mem\t# short" %}
5886 ins_encode %{
5887 __ movswl($dst$$Register, $mem$$Address);
5888 %}
5890 ins_pipe(ialu_reg_mem);
5891 %}
5893 // Load Short (16 bit signed) to Byte (8 bit signed)
5894 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
5895 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5897 ins_cost(125);
5898 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5899 ins_encode %{
5900 __ movsbl($dst$$Register, $mem$$Address);
5901 %}
5902 ins_pipe(ialu_reg_mem);
5903 %}
5905 // Load Short (16bit signed) into Long Register
5906 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5907 match(Set dst (ConvI2L (LoadS mem)));
5908 effect(KILL cr);
5910 ins_cost(375);
5911 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5912 "MOV $dst.hi,$dst.lo\n\t"
5913 "SAR $dst.hi,15" %}
5915 ins_encode %{
5916 __ movswl($dst$$Register, $mem$$Address);
5917 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5918 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5919 %}
5921 ins_pipe(ialu_reg_mem);
5922 %}
5924 // Load Unsigned Short/Char (16bit unsigned)
5925 instruct loadUS(eRegI dst, memory mem) %{
5926 match(Set dst (LoadUS mem));
5928 ins_cost(125);
5929 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5931 ins_encode %{
5932 __ movzwl($dst$$Register, $mem$$Address);
5933 %}
5935 ins_pipe(ialu_reg_mem);
5936 %}
5938 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5939 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
5940 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5942 ins_cost(125);
5943 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5944 ins_encode %{
5945 __ movsbl($dst$$Register, $mem$$Address);
5946 %}
5947 ins_pipe(ialu_reg_mem);
5948 %}
5950 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5951 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5952 match(Set dst (ConvI2L (LoadUS mem)));
5953 effect(KILL cr);
5955 ins_cost(250);
5956 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5957 "XOR $dst.hi,$dst.hi" %}
5959 ins_encode %{
5960 __ movzwl($dst$$Register, $mem$$Address);
5961 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5962 %}
5964 ins_pipe(ialu_reg_mem);
5965 %}
5967 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5968 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5969 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5970 effect(KILL cr);
5972 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5973 "XOR $dst.hi,$dst.hi" %}
5974 ins_encode %{
5975 Register Rdst = $dst$$Register;
5976 __ movzbl(Rdst, $mem$$Address);
5977 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5978 %}
5979 ins_pipe(ialu_reg_mem);
5980 %}
5982 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
5983 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
5984 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5985 effect(KILL cr);
5987 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
5988 "XOR $dst.hi,$dst.hi\n\t"
5989 "AND $dst.lo,$mask" %}
5990 ins_encode %{
5991 Register Rdst = $dst$$Register;
5992 __ movzwl(Rdst, $mem$$Address);
5993 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5994 __ andl(Rdst, $mask$$constant);
5995 %}
5996 ins_pipe(ialu_reg_mem);
5997 %}
5999 // Load Integer
6000 instruct loadI(eRegI dst, memory mem) %{
6001 match(Set dst (LoadI mem));
6003 ins_cost(125);
6004 format %{ "MOV $dst,$mem\t# int" %}
6006 ins_encode %{
6007 __ movl($dst$$Register, $mem$$Address);
6008 %}
6010 ins_pipe(ialu_reg_mem);
6011 %}
6013 // Load Integer (32 bit signed) to Byte (8 bit signed)
6014 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6015 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6017 ins_cost(125);
6018 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6019 ins_encode %{
6020 __ movsbl($dst$$Register, $mem$$Address);
6021 %}
6022 ins_pipe(ialu_reg_mem);
6023 %}
6025 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6026 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{
6027 match(Set dst (AndI (LoadI mem) mask));
6029 ins_cost(125);
6030 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6031 ins_encode %{
6032 __ movzbl($dst$$Register, $mem$$Address);
6033 %}
6034 ins_pipe(ialu_reg_mem);
6035 %}
6037 // Load Integer (32 bit signed) to Short (16 bit signed)
6038 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{
6039 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6041 ins_cost(125);
6042 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6043 ins_encode %{
6044 __ movswl($dst$$Register, $mem$$Address);
6045 %}
6046 ins_pipe(ialu_reg_mem);
6047 %}
6049 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6050 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{
6051 match(Set dst (AndI (LoadI mem) mask));
6053 ins_cost(125);
6054 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6055 ins_encode %{
6056 __ movzwl($dst$$Register, $mem$$Address);
6057 %}
6058 ins_pipe(ialu_reg_mem);
6059 %}
6061 // Load Integer into Long Register
6062 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6063 match(Set dst (ConvI2L (LoadI mem)));
6064 effect(KILL cr);
6066 ins_cost(375);
6067 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6068 "MOV $dst.hi,$dst.lo\n\t"
6069 "SAR $dst.hi,31" %}
6071 ins_encode %{
6072 __ movl($dst$$Register, $mem$$Address);
6073 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6074 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6075 %}
6077 ins_pipe(ialu_reg_mem);
6078 %}
6080 // Load Integer with mask 0xFF into Long Register
6081 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6082 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6083 effect(KILL cr);
6085 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6086 "XOR $dst.hi,$dst.hi" %}
6087 ins_encode %{
6088 Register Rdst = $dst$$Register;
6089 __ movzbl(Rdst, $mem$$Address);
6090 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6091 %}
6092 ins_pipe(ialu_reg_mem);
6093 %}
6095 // Load Integer with mask 0xFFFF into Long Register
6096 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6097 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6098 effect(KILL cr);
6100 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6101 "XOR $dst.hi,$dst.hi" %}
6102 ins_encode %{
6103 Register Rdst = $dst$$Register;
6104 __ movzwl(Rdst, $mem$$Address);
6105 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6106 %}
6107 ins_pipe(ialu_reg_mem);
6108 %}
6110 // Load Integer with 32-bit mask into Long Register
6111 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6112 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6113 effect(KILL cr);
6115 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6116 "XOR $dst.hi,$dst.hi\n\t"
6117 "AND $dst.lo,$mask" %}
6118 ins_encode %{
6119 Register Rdst = $dst$$Register;
6120 __ movl(Rdst, $mem$$Address);
6121 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6122 __ andl(Rdst, $mask$$constant);
6123 %}
6124 ins_pipe(ialu_reg_mem);
6125 %}
6127 // Load Unsigned Integer into Long Register
6128 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6129 match(Set dst (LoadUI2L mem));
6130 effect(KILL cr);
6132 ins_cost(250);
6133 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6134 "XOR $dst.hi,$dst.hi" %}
6136 ins_encode %{
6137 __ movl($dst$$Register, $mem$$Address);
6138 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6139 %}
6141 ins_pipe(ialu_reg_mem);
6142 %}
6144 // Load Long. Cannot clobber address while loading, so restrict address
6145 // register to ESI
6146 instruct loadL(eRegL dst, load_long_memory mem) %{
6147 predicate(!((LoadLNode*)n)->require_atomic_access());
6148 match(Set dst (LoadL mem));
6150 ins_cost(250);
6151 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6152 "MOV $dst.hi,$mem+4" %}
6154 ins_encode %{
6155 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6156 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6157 __ movl($dst$$Register, Amemlo);
6158 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6159 %}
6161 ins_pipe(ialu_reg_long_mem);
6162 %}
6164 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6165 // then store it down to the stack and reload on the int
6166 // side.
6167 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6168 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6169 match(Set dst (LoadL mem));
6171 ins_cost(200);
6172 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6173 "FISTp $dst" %}
6174 ins_encode(enc_loadL_volatile(mem,dst));
6175 ins_pipe( fpu_reg_mem );
6176 %}
6178 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6179 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6180 match(Set dst (LoadL mem));
6181 effect(TEMP tmp);
6182 ins_cost(180);
6183 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6184 "MOVSD $dst,$tmp" %}
6185 ins_encode %{
6186 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6187 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6188 %}
6189 ins_pipe( pipe_slow );
6190 %}
6192 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6193 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6194 match(Set dst (LoadL mem));
6195 effect(TEMP tmp);
6196 ins_cost(160);
6197 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6198 "MOVD $dst.lo,$tmp\n\t"
6199 "PSRLQ $tmp,32\n\t"
6200 "MOVD $dst.hi,$tmp" %}
6201 ins_encode %{
6202 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6203 __ movdl($dst$$Register, $tmp$$XMMRegister);
6204 __ psrlq($tmp$$XMMRegister, 32);
6205 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6206 %}
6207 ins_pipe( pipe_slow );
6208 %}
6210 // Load Range
6211 instruct loadRange(eRegI dst, memory mem) %{
6212 match(Set dst (LoadRange mem));
6214 ins_cost(125);
6215 format %{ "MOV $dst,$mem" %}
6216 opcode(0x8B);
6217 ins_encode( OpcP, RegMem(dst,mem));
6218 ins_pipe( ialu_reg_mem );
6219 %}
6222 // Load Pointer
6223 instruct loadP(eRegP dst, memory mem) %{
6224 match(Set dst (LoadP mem));
6226 ins_cost(125);
6227 format %{ "MOV $dst,$mem" %}
6228 opcode(0x8B);
6229 ins_encode( OpcP, RegMem(dst,mem));
6230 ins_pipe( ialu_reg_mem );
6231 %}
6233 // Load Klass Pointer
6234 instruct loadKlass(eRegP dst, memory mem) %{
6235 match(Set dst (LoadKlass mem));
6237 ins_cost(125);
6238 format %{ "MOV $dst,$mem" %}
6239 opcode(0x8B);
6240 ins_encode( OpcP, RegMem(dst,mem));
6241 ins_pipe( ialu_reg_mem );
6242 %}
6244 // Load Double
6245 instruct loadDPR(regDPR dst, memory mem) %{
6246 predicate(UseSSE<=1);
6247 match(Set dst (LoadD mem));
6249 ins_cost(150);
6250 format %{ "FLD_D ST,$mem\n\t"
6251 "FSTP $dst" %}
6252 opcode(0xDD); /* DD /0 */
6253 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6254 Pop_Reg_DPR(dst) );
6255 ins_pipe( fpu_reg_mem );
6256 %}
6258 // Load Double to XMM
6259 instruct loadD(regD dst, memory mem) %{
6260 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6261 match(Set dst (LoadD mem));
6262 ins_cost(145);
6263 format %{ "MOVSD $dst,$mem" %}
6264 ins_encode %{
6265 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6266 %}
6267 ins_pipe( pipe_slow );
6268 %}
6270 instruct loadD_partial(regD dst, memory mem) %{
6271 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6272 match(Set dst (LoadD mem));
6273 ins_cost(145);
6274 format %{ "MOVLPD $dst,$mem" %}
6275 ins_encode %{
6276 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6277 %}
6278 ins_pipe( pipe_slow );
6279 %}
6281 // Load to XMM register (single-precision floating point)
6282 // MOVSS instruction
6283 instruct loadF(regF dst, memory mem) %{
6284 predicate(UseSSE>=1);
6285 match(Set dst (LoadF mem));
6286 ins_cost(145);
6287 format %{ "MOVSS $dst,$mem" %}
6288 ins_encode %{
6289 __ movflt ($dst$$XMMRegister, $mem$$Address);
6290 %}
6291 ins_pipe( pipe_slow );
6292 %}
6294 // Load Float
6295 instruct loadFPR(regFPR dst, memory mem) %{
6296 predicate(UseSSE==0);
6297 match(Set dst (LoadF mem));
6299 ins_cost(150);
6300 format %{ "FLD_S ST,$mem\n\t"
6301 "FSTP $dst" %}
6302 opcode(0xD9); /* D9 /0 */
6303 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6304 Pop_Reg_FPR(dst) );
6305 ins_pipe( fpu_reg_mem );
6306 %}
6308 // Load Aligned Packed Byte to XMM register
6309 instruct loadA8B(regD dst, memory mem) %{
6310 predicate(UseSSE>=1);
6311 match(Set dst (Load8B mem));
6312 ins_cost(125);
6313 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6314 ins_encode %{
6315 __ movq($dst$$XMMRegister, $mem$$Address);
6316 %}
6317 ins_pipe( pipe_slow );
6318 %}
6320 // Load Aligned Packed Short to XMM register
6321 instruct loadA4S(regD dst, memory mem) %{
6322 predicate(UseSSE>=1);
6323 match(Set dst (Load4S mem));
6324 ins_cost(125);
6325 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6326 ins_encode %{
6327 __ movq($dst$$XMMRegister, $mem$$Address);
6328 %}
6329 ins_pipe( pipe_slow );
6330 %}
6332 // Load Aligned Packed Char to XMM register
6333 instruct loadA4C(regD dst, memory mem) %{
6334 predicate(UseSSE>=1);
6335 match(Set dst (Load4C mem));
6336 ins_cost(125);
6337 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6338 ins_encode %{
6339 __ movq($dst$$XMMRegister, $mem$$Address);
6340 %}
6341 ins_pipe( pipe_slow );
6342 %}
6344 // Load Aligned Packed Integer to XMM register
6345 instruct load2IU(regD dst, memory mem) %{
6346 predicate(UseSSE>=1);
6347 match(Set dst (Load2I mem));
6348 ins_cost(125);
6349 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6350 ins_encode %{
6351 __ movq($dst$$XMMRegister, $mem$$Address);
6352 %}
6353 ins_pipe( pipe_slow );
6354 %}
6356 // Load Aligned Packed Single to XMM
6357 instruct loadA2F(regD dst, memory mem) %{
6358 predicate(UseSSE>=1);
6359 match(Set dst (Load2F mem));
6360 ins_cost(145);
6361 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6362 ins_encode %{
6363 __ movq($dst$$XMMRegister, $mem$$Address);
6364 %}
6365 ins_pipe( pipe_slow );
6366 %}
6368 // Load Effective Address
6369 instruct leaP8(eRegP dst, indOffset8 mem) %{
6370 match(Set dst mem);
6372 ins_cost(110);
6373 format %{ "LEA $dst,$mem" %}
6374 opcode(0x8D);
6375 ins_encode( OpcP, RegMem(dst,mem));
6376 ins_pipe( ialu_reg_reg_fat );
6377 %}
6379 instruct leaP32(eRegP dst, indOffset32 mem) %{
6380 match(Set dst mem);
6382 ins_cost(110);
6383 format %{ "LEA $dst,$mem" %}
6384 opcode(0x8D);
6385 ins_encode( OpcP, RegMem(dst,mem));
6386 ins_pipe( ialu_reg_reg_fat );
6387 %}
6389 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6390 match(Set dst mem);
6392 ins_cost(110);
6393 format %{ "LEA $dst,$mem" %}
6394 opcode(0x8D);
6395 ins_encode( OpcP, RegMem(dst,mem));
6396 ins_pipe( ialu_reg_reg_fat );
6397 %}
6399 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6400 match(Set dst mem);
6402 ins_cost(110);
6403 format %{ "LEA $dst,$mem" %}
6404 opcode(0x8D);
6405 ins_encode( OpcP, RegMem(dst,mem));
6406 ins_pipe( ialu_reg_reg_fat );
6407 %}
6409 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6410 match(Set dst mem);
6412 ins_cost(110);
6413 format %{ "LEA $dst,$mem" %}
6414 opcode(0x8D);
6415 ins_encode( OpcP, RegMem(dst,mem));
6416 ins_pipe( ialu_reg_reg_fat );
6417 %}
6419 // Load Constant
6420 instruct loadConI(eRegI dst, immI src) %{
6421 match(Set dst src);
6423 format %{ "MOV $dst,$src" %}
6424 ins_encode( LdImmI(dst, src) );
6425 ins_pipe( ialu_reg_fat );
6426 %}
6428 // Load Constant zero
6429 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
6430 match(Set dst src);
6431 effect(KILL cr);
6433 ins_cost(50);
6434 format %{ "XOR $dst,$dst" %}
6435 opcode(0x33); /* + rd */
6436 ins_encode( OpcP, RegReg( dst, dst ) );
6437 ins_pipe( ialu_reg );
6438 %}
6440 instruct loadConP(eRegP dst, immP src) %{
6441 match(Set dst src);
6443 format %{ "MOV $dst,$src" %}
6444 opcode(0xB8); /* + rd */
6445 ins_encode( LdImmP(dst, src) );
6446 ins_pipe( ialu_reg_fat );
6447 %}
6449 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6450 match(Set dst src);
6451 effect(KILL cr);
6452 ins_cost(200);
6453 format %{ "MOV $dst.lo,$src.lo\n\t"
6454 "MOV $dst.hi,$src.hi" %}
6455 opcode(0xB8);
6456 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6457 ins_pipe( ialu_reg_long_fat );
6458 %}
6460 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6461 match(Set dst src);
6462 effect(KILL cr);
6463 ins_cost(150);
6464 format %{ "XOR $dst.lo,$dst.lo\n\t"
6465 "XOR $dst.hi,$dst.hi" %}
6466 opcode(0x33,0x33);
6467 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6468 ins_pipe( ialu_reg_long );
6469 %}
6471 // The instruction usage is guarded by predicate in operand immFPR().
6472 instruct loadConFPR(regFPR dst, immFPR con) %{
6473 match(Set dst con);
6474 ins_cost(125);
6475 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6476 "FSTP $dst" %}
6477 ins_encode %{
6478 __ fld_s($constantaddress($con));
6479 __ fstp_d($dst$$reg);
6480 %}
6481 ins_pipe(fpu_reg_con);
6482 %}
6484 // The instruction usage is guarded by predicate in operand immFPR0().
6485 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6486 match(Set dst con);
6487 ins_cost(125);
6488 format %{ "FLDZ ST\n\t"
6489 "FSTP $dst" %}
6490 ins_encode %{
6491 __ fldz();
6492 __ fstp_d($dst$$reg);
6493 %}
6494 ins_pipe(fpu_reg_con);
6495 %}
6497 // The instruction usage is guarded by predicate in operand immFPR1().
6498 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6499 match(Set dst con);
6500 ins_cost(125);
6501 format %{ "FLD1 ST\n\t"
6502 "FSTP $dst" %}
6503 ins_encode %{
6504 __ fld1();
6505 __ fstp_d($dst$$reg);
6506 %}
6507 ins_pipe(fpu_reg_con);
6508 %}
6510 // The instruction usage is guarded by predicate in operand immF().
6511 instruct loadConF(regF dst, immF con) %{
6512 match(Set dst con);
6513 ins_cost(125);
6514 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6515 ins_encode %{
6516 __ movflt($dst$$XMMRegister, $constantaddress($con));
6517 %}
6518 ins_pipe(pipe_slow);
6519 %}
6521 // The instruction usage is guarded by predicate in operand immF0().
6522 instruct loadConF0(regF dst, immF0 src) %{
6523 match(Set dst src);
6524 ins_cost(100);
6525 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6526 ins_encode %{
6527 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6528 %}
6529 ins_pipe(pipe_slow);
6530 %}
6532 // The instruction usage is guarded by predicate in operand immDPR().
6533 instruct loadConDPR(regDPR dst, immDPR con) %{
6534 match(Set dst con);
6535 ins_cost(125);
6537 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6538 "FSTP $dst" %}
6539 ins_encode %{
6540 __ fld_d($constantaddress($con));
6541 __ fstp_d($dst$$reg);
6542 %}
6543 ins_pipe(fpu_reg_con);
6544 %}
6546 // The instruction usage is guarded by predicate in operand immDPR0().
6547 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6548 match(Set dst con);
6549 ins_cost(125);
6551 format %{ "FLDZ ST\n\t"
6552 "FSTP $dst" %}
6553 ins_encode %{
6554 __ fldz();
6555 __ fstp_d($dst$$reg);
6556 %}
6557 ins_pipe(fpu_reg_con);
6558 %}
6560 // The instruction usage is guarded by predicate in operand immDPR1().
6561 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6562 match(Set dst con);
6563 ins_cost(125);
6565 format %{ "FLD1 ST\n\t"
6566 "FSTP $dst" %}
6567 ins_encode %{
6568 __ fld1();
6569 __ fstp_d($dst$$reg);
6570 %}
6571 ins_pipe(fpu_reg_con);
6572 %}
6574 // The instruction usage is guarded by predicate in operand immD().
6575 instruct loadConD(regD dst, immD con) %{
6576 match(Set dst con);
6577 ins_cost(125);
6578 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6579 ins_encode %{
6580 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6581 %}
6582 ins_pipe(pipe_slow);
6583 %}
6585 // The instruction usage is guarded by predicate in operand immD0().
6586 instruct loadConD0(regD dst, immD0 src) %{
6587 match(Set dst src);
6588 ins_cost(100);
6589 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6590 ins_encode %{
6591 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6592 %}
6593 ins_pipe( pipe_slow );
6594 %}
6596 // Load Stack Slot
6597 instruct loadSSI(eRegI dst, stackSlotI src) %{
6598 match(Set dst src);
6599 ins_cost(125);
6601 format %{ "MOV $dst,$src" %}
6602 opcode(0x8B);
6603 ins_encode( OpcP, RegMem(dst,src));
6604 ins_pipe( ialu_reg_mem );
6605 %}
6607 instruct loadSSL(eRegL dst, stackSlotL src) %{
6608 match(Set dst src);
6610 ins_cost(200);
6611 format %{ "MOV $dst,$src.lo\n\t"
6612 "MOV $dst+4,$src.hi" %}
6613 opcode(0x8B, 0x8B);
6614 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6615 ins_pipe( ialu_mem_long_reg );
6616 %}
6618 // Load Stack Slot
6619 instruct loadSSP(eRegP dst, stackSlotP src) %{
6620 match(Set dst src);
6621 ins_cost(125);
6623 format %{ "MOV $dst,$src" %}
6624 opcode(0x8B);
6625 ins_encode( OpcP, RegMem(dst,src));
6626 ins_pipe( ialu_reg_mem );
6627 %}
6629 // Load Stack Slot
6630 instruct loadSSF(regFPR dst, stackSlotF src) %{
6631 match(Set dst src);
6632 ins_cost(125);
6634 format %{ "FLD_S $src\n\t"
6635 "FSTP $dst" %}
6636 opcode(0xD9); /* D9 /0, FLD m32real */
6637 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6638 Pop_Reg_FPR(dst) );
6639 ins_pipe( fpu_reg_mem );
6640 %}
6642 // Load Stack Slot
6643 instruct loadSSD(regDPR dst, stackSlotD src) %{
6644 match(Set dst src);
6645 ins_cost(125);
6647 format %{ "FLD_D $src\n\t"
6648 "FSTP $dst" %}
6649 opcode(0xDD); /* DD /0, FLD m64real */
6650 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6651 Pop_Reg_DPR(dst) );
6652 ins_pipe( fpu_reg_mem );
6653 %}
6655 // Prefetch instructions.
6656 // Must be safe to execute with invalid address (cannot fault).
6658 instruct prefetchr0( memory mem ) %{
6659 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6660 match(PrefetchRead mem);
6661 ins_cost(0);
6662 size(0);
6663 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6664 ins_encode();
6665 ins_pipe(empty);
6666 %}
6668 instruct prefetchr( memory mem ) %{
6669 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6670 match(PrefetchRead mem);
6671 ins_cost(100);
6673 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6674 ins_encode %{
6675 __ prefetchr($mem$$Address);
6676 %}
6677 ins_pipe(ialu_mem);
6678 %}
6680 instruct prefetchrNTA( memory mem ) %{
6681 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6682 match(PrefetchRead mem);
6683 ins_cost(100);
6685 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6686 ins_encode %{
6687 __ prefetchnta($mem$$Address);
6688 %}
6689 ins_pipe(ialu_mem);
6690 %}
6692 instruct prefetchrT0( memory mem ) %{
6693 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6694 match(PrefetchRead mem);
6695 ins_cost(100);
6697 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6698 ins_encode %{
6699 __ prefetcht0($mem$$Address);
6700 %}
6701 ins_pipe(ialu_mem);
6702 %}
6704 instruct prefetchrT2( memory mem ) %{
6705 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6706 match(PrefetchRead mem);
6707 ins_cost(100);
6709 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6710 ins_encode %{
6711 __ prefetcht2($mem$$Address);
6712 %}
6713 ins_pipe(ialu_mem);
6714 %}
6716 instruct prefetchw0( memory mem ) %{
6717 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6718 match(PrefetchWrite mem);
6719 ins_cost(0);
6720 size(0);
6721 format %{ "Prefetch (non-SSE is empty encoding)" %}
6722 ins_encode();
6723 ins_pipe(empty);
6724 %}
6726 instruct prefetchw( memory mem ) %{
6727 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6728 match( PrefetchWrite mem );
6729 ins_cost(100);
6731 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6732 ins_encode %{
6733 __ prefetchw($mem$$Address);
6734 %}
6735 ins_pipe(ialu_mem);
6736 %}
6738 instruct prefetchwNTA( memory mem ) %{
6739 predicate(UseSSE>=1);
6740 match(PrefetchWrite mem);
6741 ins_cost(100);
6743 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6744 ins_encode %{
6745 __ prefetchnta($mem$$Address);
6746 %}
6747 ins_pipe(ialu_mem);
6748 %}
6750 // Prefetch instructions for allocation.
6752 instruct prefetchAlloc0( memory mem ) %{
6753 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6754 match(PrefetchAllocation mem);
6755 ins_cost(0);
6756 size(0);
6757 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6758 ins_encode();
6759 ins_pipe(empty);
6760 %}
6762 instruct prefetchAlloc( memory mem ) %{
6763 predicate(AllocatePrefetchInstr==3);
6764 match( PrefetchAllocation mem );
6765 ins_cost(100);
6767 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6768 ins_encode %{
6769 __ prefetchw($mem$$Address);
6770 %}
6771 ins_pipe(ialu_mem);
6772 %}
6774 instruct prefetchAllocNTA( memory mem ) %{
6775 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6776 match(PrefetchAllocation mem);
6777 ins_cost(100);
6779 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6780 ins_encode %{
6781 __ prefetchnta($mem$$Address);
6782 %}
6783 ins_pipe(ialu_mem);
6784 %}
6786 instruct prefetchAllocT0( memory mem ) %{
6787 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6788 match(PrefetchAllocation mem);
6789 ins_cost(100);
6791 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6792 ins_encode %{
6793 __ prefetcht0($mem$$Address);
6794 %}
6795 ins_pipe(ialu_mem);
6796 %}
6798 instruct prefetchAllocT2( memory mem ) %{
6799 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6800 match(PrefetchAllocation mem);
6801 ins_cost(100);
6803 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6804 ins_encode %{
6805 __ prefetcht2($mem$$Address);
6806 %}
6807 ins_pipe(ialu_mem);
6808 %}
6810 //----------Store Instructions-------------------------------------------------
6812 // Store Byte
6813 instruct storeB(memory mem, xRegI src) %{
6814 match(Set mem (StoreB mem src));
6816 ins_cost(125);
6817 format %{ "MOV8 $mem,$src" %}
6818 opcode(0x88);
6819 ins_encode( OpcP, RegMem( src, mem ) );
6820 ins_pipe( ialu_mem_reg );
6821 %}
6823 // Store Char/Short
6824 instruct storeC(memory mem, eRegI src) %{
6825 match(Set mem (StoreC mem src));
6827 ins_cost(125);
6828 format %{ "MOV16 $mem,$src" %}
6829 opcode(0x89, 0x66);
6830 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6831 ins_pipe( ialu_mem_reg );
6832 %}
6834 // Store Integer
6835 instruct storeI(memory mem, eRegI src) %{
6836 match(Set mem (StoreI mem src));
6838 ins_cost(125);
6839 format %{ "MOV $mem,$src" %}
6840 opcode(0x89);
6841 ins_encode( OpcP, RegMem( src, mem ) );
6842 ins_pipe( ialu_mem_reg );
6843 %}
6845 // Store Long
6846 instruct storeL(long_memory mem, eRegL src) %{
6847 predicate(!((StoreLNode*)n)->require_atomic_access());
6848 match(Set mem (StoreL mem src));
6850 ins_cost(200);
6851 format %{ "MOV $mem,$src.lo\n\t"
6852 "MOV $mem+4,$src.hi" %}
6853 opcode(0x89, 0x89);
6854 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6855 ins_pipe( ialu_mem_long_reg );
6856 %}
6858 // Store Long to Integer
6859 instruct storeL2I(memory mem, eRegL src) %{
6860 match(Set mem (StoreI mem (ConvL2I src)));
6862 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6863 ins_encode %{
6864 __ movl($mem$$Address, $src$$Register);
6865 %}
6866 ins_pipe(ialu_mem_reg);
6867 %}
6869 // Volatile Store Long. Must be atomic, so move it into
6870 // the FP TOS and then do a 64-bit FIST. Has to probe the
6871 // target address before the store (for null-ptr checks)
6872 // so the memory operand is used twice in the encoding.
6873 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6874 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6875 match(Set mem (StoreL mem src));
6876 effect( KILL cr );
6877 ins_cost(400);
6878 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6879 "FILD $src\n\t"
6880 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6881 opcode(0x3B);
6882 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6883 ins_pipe( fpu_reg_mem );
6884 %}
6886 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6887 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6888 match(Set mem (StoreL mem src));
6889 effect( TEMP tmp, KILL cr );
6890 ins_cost(380);
6891 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6892 "MOVSD $tmp,$src\n\t"
6893 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6894 ins_encode %{
6895 __ cmpl(rax, $mem$$Address);
6896 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6897 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6898 %}
6899 ins_pipe( pipe_slow );
6900 %}
6902 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6903 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6904 match(Set mem (StoreL mem src));
6905 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6906 ins_cost(360);
6907 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6908 "MOVD $tmp,$src.lo\n\t"
6909 "MOVD $tmp2,$src.hi\n\t"
6910 "PUNPCKLDQ $tmp,$tmp2\n\t"
6911 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6912 ins_encode %{
6913 __ cmpl(rax, $mem$$Address);
6914 __ movdl($tmp$$XMMRegister, $src$$Register);
6915 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6916 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6917 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6918 %}
6919 ins_pipe( pipe_slow );
6920 %}
6922 // Store Pointer; for storing unknown oops and raw pointers
6923 instruct storeP(memory mem, anyRegP src) %{
6924 match(Set mem (StoreP mem src));
6926 ins_cost(125);
6927 format %{ "MOV $mem,$src" %}
6928 opcode(0x89);
6929 ins_encode( OpcP, RegMem( src, mem ) );
6930 ins_pipe( ialu_mem_reg );
6931 %}
6933 // Store Integer Immediate
6934 instruct storeImmI(memory mem, immI src) %{
6935 match(Set mem (StoreI mem src));
6937 ins_cost(150);
6938 format %{ "MOV $mem,$src" %}
6939 opcode(0xC7); /* C7 /0 */
6940 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6941 ins_pipe( ialu_mem_imm );
6942 %}
6944 // Store Short/Char Immediate
6945 instruct storeImmI16(memory mem, immI16 src) %{
6946 predicate(UseStoreImmI16);
6947 match(Set mem (StoreC mem src));
6949 ins_cost(150);
6950 format %{ "MOV16 $mem,$src" %}
6951 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6952 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6953 ins_pipe( ialu_mem_imm );
6954 %}
6956 // Store Pointer Immediate; null pointers or constant oops that do not
6957 // need card-mark barriers.
6958 instruct storeImmP(memory mem, immP src) %{
6959 match(Set mem (StoreP mem src));
6961 ins_cost(150);
6962 format %{ "MOV $mem,$src" %}
6963 opcode(0xC7); /* C7 /0 */
6964 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6965 ins_pipe( ialu_mem_imm );
6966 %}
6968 // Store Byte Immediate
6969 instruct storeImmB(memory mem, immI8 src) %{
6970 match(Set mem (StoreB mem src));
6972 ins_cost(150);
6973 format %{ "MOV8 $mem,$src" %}
6974 opcode(0xC6); /* C6 /0 */
6975 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6976 ins_pipe( ialu_mem_imm );
6977 %}
6979 // Store Aligned Packed Byte XMM register to memory
6980 instruct storeA8B(memory mem, regD src) %{
6981 predicate(UseSSE>=1);
6982 match(Set mem (Store8B mem src));
6983 ins_cost(145);
6984 format %{ "MOVQ $mem,$src\t! packed8B" %}
6985 ins_encode %{
6986 __ movq($mem$$Address, $src$$XMMRegister);
6987 %}
6988 ins_pipe( pipe_slow );
6989 %}
6991 // Store Aligned Packed Char/Short XMM register to memory
6992 instruct storeA4C(memory mem, regD src) %{
6993 predicate(UseSSE>=1);
6994 match(Set mem (Store4C mem src));
6995 ins_cost(145);
6996 format %{ "MOVQ $mem,$src\t! packed4C" %}
6997 ins_encode %{
6998 __ movq($mem$$Address, $src$$XMMRegister);
6999 %}
7000 ins_pipe( pipe_slow );
7001 %}
7003 // Store Aligned Packed Integer XMM register to memory
7004 instruct storeA2I(memory mem, regD src) %{
7005 predicate(UseSSE>=1);
7006 match(Set mem (Store2I mem src));
7007 ins_cost(145);
7008 format %{ "MOVQ $mem,$src\t! packed2I" %}
7009 ins_encode %{
7010 __ movq($mem$$Address, $src$$XMMRegister);
7011 %}
7012 ins_pipe( pipe_slow );
7013 %}
7015 // Store CMS card-mark Immediate
7016 instruct storeImmCM(memory mem, immI8 src) %{
7017 match(Set mem (StoreCM mem src));
7019 ins_cost(150);
7020 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7021 opcode(0xC6); /* C6 /0 */
7022 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7023 ins_pipe( ialu_mem_imm );
7024 %}
7026 // Store Double
7027 instruct storeDPR( memory mem, regDPR1 src) %{
7028 predicate(UseSSE<=1);
7029 match(Set mem (StoreD mem src));
7031 ins_cost(100);
7032 format %{ "FST_D $mem,$src" %}
7033 opcode(0xDD); /* DD /2 */
7034 ins_encode( enc_FPR_store(mem,src) );
7035 ins_pipe( fpu_mem_reg );
7036 %}
7038 // Store double does rounding on x86
7039 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
7040 predicate(UseSSE<=1);
7041 match(Set mem (StoreD mem (RoundDouble src)));
7043 ins_cost(100);
7044 format %{ "FST_D $mem,$src\t# round" %}
7045 opcode(0xDD); /* DD /2 */
7046 ins_encode( enc_FPR_store(mem,src) );
7047 ins_pipe( fpu_mem_reg );
7048 %}
7050 // Store XMM register to memory (double-precision floating points)
7051 // MOVSD instruction
7052 instruct storeD(memory mem, regD src) %{
7053 predicate(UseSSE>=2);
7054 match(Set mem (StoreD mem src));
7055 ins_cost(95);
7056 format %{ "MOVSD $mem,$src" %}
7057 ins_encode %{
7058 __ movdbl($mem$$Address, $src$$XMMRegister);
7059 %}
7060 ins_pipe( pipe_slow );
7061 %}
7063 // Store XMM register to memory (single-precision floating point)
7064 // MOVSS instruction
7065 instruct storeF(memory mem, regF src) %{
7066 predicate(UseSSE>=1);
7067 match(Set mem (StoreF mem src));
7068 ins_cost(95);
7069 format %{ "MOVSS $mem,$src" %}
7070 ins_encode %{
7071 __ movflt($mem$$Address, $src$$XMMRegister);
7072 %}
7073 ins_pipe( pipe_slow );
7074 %}
7076 // Store Aligned Packed Single Float XMM register to memory
7077 instruct storeA2F(memory mem, regD src) %{
7078 predicate(UseSSE>=1);
7079 match(Set mem (Store2F mem src));
7080 ins_cost(145);
7081 format %{ "MOVQ $mem,$src\t! packed2F" %}
7082 ins_encode %{
7083 __ movq($mem$$Address, $src$$XMMRegister);
7084 %}
7085 ins_pipe( pipe_slow );
7086 %}
7088 // Store Float
7089 instruct storeFPR( memory mem, regFPR1 src) %{
7090 predicate(UseSSE==0);
7091 match(Set mem (StoreF mem src));
7093 ins_cost(100);
7094 format %{ "FST_S $mem,$src" %}
7095 opcode(0xD9); /* D9 /2 */
7096 ins_encode( enc_FPR_store(mem,src) );
7097 ins_pipe( fpu_mem_reg );
7098 %}
7100 // Store Float does rounding on x86
7101 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7102 predicate(UseSSE==0);
7103 match(Set mem (StoreF mem (RoundFloat src)));
7105 ins_cost(100);
7106 format %{ "FST_S $mem,$src\t# round" %}
7107 opcode(0xD9); /* D9 /2 */
7108 ins_encode( enc_FPR_store(mem,src) );
7109 ins_pipe( fpu_mem_reg );
7110 %}
7112 // Store Float does rounding on x86
7113 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7114 predicate(UseSSE<=1);
7115 match(Set mem (StoreF mem (ConvD2F src)));
7117 ins_cost(100);
7118 format %{ "FST_S $mem,$src\t# D-round" %}
7119 opcode(0xD9); /* D9 /2 */
7120 ins_encode( enc_FPR_store(mem,src) );
7121 ins_pipe( fpu_mem_reg );
7122 %}
7124 // Store immediate Float value (it is faster than store from FPU register)
7125 // The instruction usage is guarded by predicate in operand immFPR().
7126 instruct storeFPR_imm( memory mem, immFPR src) %{
7127 match(Set mem (StoreF mem src));
7129 ins_cost(50);
7130 format %{ "MOV $mem,$src\t# store float" %}
7131 opcode(0xC7); /* C7 /0 */
7132 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7133 ins_pipe( ialu_mem_imm );
7134 %}
7136 // Store immediate Float value (it is faster than store from XMM register)
7137 // The instruction usage is guarded by predicate in operand immF().
7138 instruct storeF_imm( memory mem, immF src) %{
7139 match(Set mem (StoreF mem src));
7141 ins_cost(50);
7142 format %{ "MOV $mem,$src\t# store float" %}
7143 opcode(0xC7); /* C7 /0 */
7144 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7145 ins_pipe( ialu_mem_imm );
7146 %}
7148 // Store Integer to stack slot
7149 instruct storeSSI(stackSlotI dst, eRegI src) %{
7150 match(Set dst src);
7152 ins_cost(100);
7153 format %{ "MOV $dst,$src" %}
7154 opcode(0x89);
7155 ins_encode( OpcPRegSS( dst, src ) );
7156 ins_pipe( ialu_mem_reg );
7157 %}
7159 // Store Integer to stack slot
7160 instruct storeSSP(stackSlotP dst, eRegP src) %{
7161 match(Set dst src);
7163 ins_cost(100);
7164 format %{ "MOV $dst,$src" %}
7165 opcode(0x89);
7166 ins_encode( OpcPRegSS( dst, src ) );
7167 ins_pipe( ialu_mem_reg );
7168 %}
7170 // Store Long to stack slot
7171 instruct storeSSL(stackSlotL dst, eRegL src) %{
7172 match(Set dst src);
7174 ins_cost(200);
7175 format %{ "MOV $dst,$src.lo\n\t"
7176 "MOV $dst+4,$src.hi" %}
7177 opcode(0x89, 0x89);
7178 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7179 ins_pipe( ialu_mem_long_reg );
7180 %}
7182 //----------MemBar Instructions-----------------------------------------------
7183 // Memory barrier flavors
7185 instruct membar_acquire() %{
7186 match(MemBarAcquire);
7187 ins_cost(400);
7189 size(0);
7190 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7191 ins_encode();
7192 ins_pipe(empty);
7193 %}
7195 instruct membar_acquire_lock() %{
7196 match(MemBarAcquireLock);
7197 ins_cost(0);
7199 size(0);
7200 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7201 ins_encode( );
7202 ins_pipe(empty);
7203 %}
7205 instruct membar_release() %{
7206 match(MemBarRelease);
7207 ins_cost(400);
7209 size(0);
7210 format %{ "MEMBAR-release ! (empty encoding)" %}
7211 ins_encode( );
7212 ins_pipe(empty);
7213 %}
7215 instruct membar_release_lock() %{
7216 match(MemBarReleaseLock);
7217 ins_cost(0);
7219 size(0);
7220 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7221 ins_encode( );
7222 ins_pipe(empty);
7223 %}
7225 instruct membar_volatile(eFlagsReg cr) %{
7226 match(MemBarVolatile);
7227 effect(KILL cr);
7228 ins_cost(400);
7230 format %{
7231 $$template
7232 if (os::is_MP()) {
7233 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7234 } else {
7235 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7236 }
7237 %}
7238 ins_encode %{
7239 __ membar(Assembler::StoreLoad);
7240 %}
7241 ins_pipe(pipe_slow);
7242 %}
7244 instruct unnecessary_membar_volatile() %{
7245 match(MemBarVolatile);
7246 predicate(Matcher::post_store_load_barrier(n));
7247 ins_cost(0);
7249 size(0);
7250 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7251 ins_encode( );
7252 ins_pipe(empty);
7253 %}
7255 instruct membar_storestore() %{
7256 match(MemBarStoreStore);
7257 ins_cost(0);
7259 size(0);
7260 format %{ "MEMBAR-storestore (empty encoding)" %}
7261 ins_encode( );
7262 ins_pipe(empty);
7263 %}
7265 //----------Move Instructions--------------------------------------------------
7266 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7267 match(Set dst (CastX2P src));
7268 format %{ "# X2P $dst, $src" %}
7269 ins_encode( /*empty encoding*/ );
7270 ins_cost(0);
7271 ins_pipe(empty);
7272 %}
7274 instruct castP2X(eRegI dst, eRegP src ) %{
7275 match(Set dst (CastP2X src));
7276 ins_cost(50);
7277 format %{ "MOV $dst, $src\t# CastP2X" %}
7278 ins_encode( enc_Copy( dst, src) );
7279 ins_pipe( ialu_reg_reg );
7280 %}
7282 //----------Conditional Move---------------------------------------------------
7283 // Conditional move
7284 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, eRegI dst, eRegI src) %{
7285 predicate(!VM_Version::supports_cmov() );
7286 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7287 ins_cost(200);
7288 format %{ "J$cop,us skip\t# signed cmove\n\t"
7289 "MOV $dst,$src\n"
7290 "skip:" %}
7291 ins_encode %{
7292 Label Lskip;
7293 // Invert sense of branch from sense of CMOV
7294 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7295 __ movl($dst$$Register, $src$$Register);
7296 __ bind(Lskip);
7297 %}
7298 ins_pipe( pipe_cmov_reg );
7299 %}
7301 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src) %{
7302 predicate(!VM_Version::supports_cmov() );
7303 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7304 ins_cost(200);
7305 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7306 "MOV $dst,$src\n"
7307 "skip:" %}
7308 ins_encode %{
7309 Label Lskip;
7310 // Invert sense of branch from sense of CMOV
7311 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7312 __ movl($dst$$Register, $src$$Register);
7313 __ bind(Lskip);
7314 %}
7315 ins_pipe( pipe_cmov_reg );
7316 %}
7318 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7319 predicate(VM_Version::supports_cmov() );
7320 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7321 ins_cost(200);
7322 format %{ "CMOV$cop $dst,$src" %}
7323 opcode(0x0F,0x40);
7324 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7325 ins_pipe( pipe_cmov_reg );
7326 %}
7328 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
7329 predicate(VM_Version::supports_cmov() );
7330 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7331 ins_cost(200);
7332 format %{ "CMOV$cop $dst,$src" %}
7333 opcode(0x0F,0x40);
7334 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7335 ins_pipe( pipe_cmov_reg );
7336 %}
7338 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
7339 predicate(VM_Version::supports_cmov() );
7340 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7341 ins_cost(200);
7342 expand %{
7343 cmovI_regU(cop, cr, dst, src);
7344 %}
7345 %}
7347 // Conditional move
7348 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7349 predicate(VM_Version::supports_cmov() );
7350 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7351 ins_cost(250);
7352 format %{ "CMOV$cop $dst,$src" %}
7353 opcode(0x0F,0x40);
7354 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7355 ins_pipe( pipe_cmov_mem );
7356 %}
7358 // Conditional move
7359 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7360 predicate(VM_Version::supports_cmov() );
7361 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7362 ins_cost(250);
7363 format %{ "CMOV$cop $dst,$src" %}
7364 opcode(0x0F,0x40);
7365 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7366 ins_pipe( pipe_cmov_mem );
7367 %}
7369 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
7370 predicate(VM_Version::supports_cmov() );
7371 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7372 ins_cost(250);
7373 expand %{
7374 cmovI_memU(cop, cr, dst, src);
7375 %}
7376 %}
7378 // Conditional move
7379 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7380 predicate(VM_Version::supports_cmov() );
7381 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7382 ins_cost(200);
7383 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7384 opcode(0x0F,0x40);
7385 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7386 ins_pipe( pipe_cmov_reg );
7387 %}
7389 // Conditional move (non-P6 version)
7390 // Note: a CMoveP is generated for stubs and native wrappers
7391 // regardless of whether we are on a P6, so we
7392 // emulate a cmov here
7393 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7394 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7395 ins_cost(300);
7396 format %{ "Jn$cop skip\n\t"
7397 "MOV $dst,$src\t# pointer\n"
7398 "skip:" %}
7399 opcode(0x8b);
7400 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7401 ins_pipe( pipe_cmov_reg );
7402 %}
7404 // Conditional move
7405 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7406 predicate(VM_Version::supports_cmov() );
7407 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7408 ins_cost(200);
7409 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7410 opcode(0x0F,0x40);
7411 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7412 ins_pipe( pipe_cmov_reg );
7413 %}
7415 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7416 predicate(VM_Version::supports_cmov() );
7417 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7418 ins_cost(200);
7419 expand %{
7420 cmovP_regU(cop, cr, dst, src);
7421 %}
7422 %}
7424 // DISABLED: Requires the ADLC to emit a bottom_type call that
7425 // correctly meets the two pointer arguments; one is an incoming
7426 // register but the other is a memory operand. ALSO appears to
7427 // be buggy with implicit null checks.
7428 //
7429 //// Conditional move
7430 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7431 // predicate(VM_Version::supports_cmov() );
7432 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7433 // ins_cost(250);
7434 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7435 // opcode(0x0F,0x40);
7436 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7437 // ins_pipe( pipe_cmov_mem );
7438 //%}
7439 //
7440 //// Conditional move
7441 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7442 // predicate(VM_Version::supports_cmov() );
7443 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7444 // ins_cost(250);
7445 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7446 // opcode(0x0F,0x40);
7447 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7448 // ins_pipe( pipe_cmov_mem );
7449 //%}
7451 // Conditional move
7452 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7453 predicate(UseSSE<=1);
7454 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7455 ins_cost(200);
7456 format %{ "FCMOV$cop $dst,$src\t# double" %}
7457 opcode(0xDA);
7458 ins_encode( enc_cmov_dpr(cop,src) );
7459 ins_pipe( pipe_cmovDPR_reg );
7460 %}
7462 // Conditional move
7463 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7464 predicate(UseSSE==0);
7465 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7466 ins_cost(200);
7467 format %{ "FCMOV$cop $dst,$src\t# float" %}
7468 opcode(0xDA);
7469 ins_encode( enc_cmov_dpr(cop,src) );
7470 ins_pipe( pipe_cmovDPR_reg );
7471 %}
7473 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7474 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7475 predicate(UseSSE<=1);
7476 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7477 ins_cost(200);
7478 format %{ "Jn$cop skip\n\t"
7479 "MOV $dst,$src\t# double\n"
7480 "skip:" %}
7481 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7482 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7483 ins_pipe( pipe_cmovDPR_reg );
7484 %}
7486 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7487 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7488 predicate(UseSSE==0);
7489 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7490 ins_cost(200);
7491 format %{ "Jn$cop skip\n\t"
7492 "MOV $dst,$src\t# float\n"
7493 "skip:" %}
7494 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7495 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7496 ins_pipe( pipe_cmovDPR_reg );
7497 %}
7499 // No CMOVE with SSE/SSE2
7500 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7501 predicate (UseSSE>=1);
7502 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7503 ins_cost(200);
7504 format %{ "Jn$cop skip\n\t"
7505 "MOVSS $dst,$src\t# float\n"
7506 "skip:" %}
7507 ins_encode %{
7508 Label skip;
7509 // Invert sense of branch from sense of CMOV
7510 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7511 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7512 __ bind(skip);
7513 %}
7514 ins_pipe( pipe_slow );
7515 %}
7517 // No CMOVE with SSE/SSE2
7518 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7519 predicate (UseSSE>=2);
7520 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7521 ins_cost(200);
7522 format %{ "Jn$cop skip\n\t"
7523 "MOVSD $dst,$src\t# float\n"
7524 "skip:" %}
7525 ins_encode %{
7526 Label skip;
7527 // Invert sense of branch from sense of CMOV
7528 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7529 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7530 __ bind(skip);
7531 %}
7532 ins_pipe( pipe_slow );
7533 %}
7535 // unsigned version
7536 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7537 predicate (UseSSE>=1);
7538 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7539 ins_cost(200);
7540 format %{ "Jn$cop skip\n\t"
7541 "MOVSS $dst,$src\t# float\n"
7542 "skip:" %}
7543 ins_encode %{
7544 Label skip;
7545 // Invert sense of branch from sense of CMOV
7546 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7547 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7548 __ bind(skip);
7549 %}
7550 ins_pipe( pipe_slow );
7551 %}
7553 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7554 predicate (UseSSE>=1);
7555 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7556 ins_cost(200);
7557 expand %{
7558 fcmovF_regU(cop, cr, dst, src);
7559 %}
7560 %}
7562 // unsigned version
7563 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7564 predicate (UseSSE>=2);
7565 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7566 ins_cost(200);
7567 format %{ "Jn$cop skip\n\t"
7568 "MOVSD $dst,$src\t# float\n"
7569 "skip:" %}
7570 ins_encode %{
7571 Label skip;
7572 // Invert sense of branch from sense of CMOV
7573 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7574 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7575 __ bind(skip);
7576 %}
7577 ins_pipe( pipe_slow );
7578 %}
7580 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7581 predicate (UseSSE>=2);
7582 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7583 ins_cost(200);
7584 expand %{
7585 fcmovD_regU(cop, cr, dst, src);
7586 %}
7587 %}
7589 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7590 predicate(VM_Version::supports_cmov() );
7591 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7592 ins_cost(200);
7593 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7594 "CMOV$cop $dst.hi,$src.hi" %}
7595 opcode(0x0F,0x40);
7596 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7597 ins_pipe( pipe_cmov_reg_long );
7598 %}
7600 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7601 predicate(VM_Version::supports_cmov() );
7602 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7603 ins_cost(200);
7604 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7605 "CMOV$cop $dst.hi,$src.hi" %}
7606 opcode(0x0F,0x40);
7607 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7608 ins_pipe( pipe_cmov_reg_long );
7609 %}
7611 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7612 predicate(VM_Version::supports_cmov() );
7613 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7614 ins_cost(200);
7615 expand %{
7616 cmovL_regU(cop, cr, dst, src);
7617 %}
7618 %}
7620 //----------Arithmetic Instructions--------------------------------------------
7621 //----------Addition Instructions----------------------------------------------
7622 // Integer Addition Instructions
7623 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7624 match(Set dst (AddI dst src));
7625 effect(KILL cr);
7627 size(2);
7628 format %{ "ADD $dst,$src" %}
7629 opcode(0x03);
7630 ins_encode( OpcP, RegReg( dst, src) );
7631 ins_pipe( ialu_reg_reg );
7632 %}
7634 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
7635 match(Set dst (AddI dst src));
7636 effect(KILL cr);
7638 format %{ "ADD $dst,$src" %}
7639 opcode(0x81, 0x00); /* /0 id */
7640 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7641 ins_pipe( ialu_reg );
7642 %}
7644 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
7645 predicate(UseIncDec);
7646 match(Set dst (AddI dst src));
7647 effect(KILL cr);
7649 size(1);
7650 format %{ "INC $dst" %}
7651 opcode(0x40); /* */
7652 ins_encode( Opc_plus( primary, dst ) );
7653 ins_pipe( ialu_reg );
7654 %}
7656 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
7657 match(Set dst (AddI src0 src1));
7658 ins_cost(110);
7660 format %{ "LEA $dst,[$src0 + $src1]" %}
7661 opcode(0x8D); /* 0x8D /r */
7662 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7663 ins_pipe( ialu_reg_reg );
7664 %}
7666 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7667 match(Set dst (AddP src0 src1));
7668 ins_cost(110);
7670 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7671 opcode(0x8D); /* 0x8D /r */
7672 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7673 ins_pipe( ialu_reg_reg );
7674 %}
7676 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
7677 predicate(UseIncDec);
7678 match(Set dst (AddI dst src));
7679 effect(KILL cr);
7681 size(1);
7682 format %{ "DEC $dst" %}
7683 opcode(0x48); /* */
7684 ins_encode( Opc_plus( primary, dst ) );
7685 ins_pipe( ialu_reg );
7686 %}
7688 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
7689 match(Set dst (AddP dst src));
7690 effect(KILL cr);
7692 size(2);
7693 format %{ "ADD $dst,$src" %}
7694 opcode(0x03);
7695 ins_encode( OpcP, RegReg( dst, src) );
7696 ins_pipe( ialu_reg_reg );
7697 %}
7699 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7700 match(Set dst (AddP dst src));
7701 effect(KILL cr);
7703 format %{ "ADD $dst,$src" %}
7704 opcode(0x81,0x00); /* Opcode 81 /0 id */
7705 // ins_encode( RegImm( dst, src) );
7706 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7707 ins_pipe( ialu_reg );
7708 %}
7710 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
7711 match(Set dst (AddI dst (LoadI src)));
7712 effect(KILL cr);
7714 ins_cost(125);
7715 format %{ "ADD $dst,$src" %}
7716 opcode(0x03);
7717 ins_encode( OpcP, RegMem( dst, src) );
7718 ins_pipe( ialu_reg_mem );
7719 %}
7721 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
7722 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7723 effect(KILL cr);
7725 ins_cost(150);
7726 format %{ "ADD $dst,$src" %}
7727 opcode(0x01); /* Opcode 01 /r */
7728 ins_encode( OpcP, RegMem( src, dst ) );
7729 ins_pipe( ialu_mem_reg );
7730 %}
7732 // Add Memory with Immediate
7733 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7734 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7735 effect(KILL cr);
7737 ins_cost(125);
7738 format %{ "ADD $dst,$src" %}
7739 opcode(0x81); /* Opcode 81 /0 id */
7740 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7741 ins_pipe( ialu_mem_imm );
7742 %}
7744 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7745 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7746 effect(KILL cr);
7748 ins_cost(125);
7749 format %{ "INC $dst" %}
7750 opcode(0xFF); /* Opcode FF /0 */
7751 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7752 ins_pipe( ialu_mem_imm );
7753 %}
7755 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7756 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7757 effect(KILL cr);
7759 ins_cost(125);
7760 format %{ "DEC $dst" %}
7761 opcode(0xFF); /* Opcode FF /1 */
7762 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7763 ins_pipe( ialu_mem_imm );
7764 %}
7767 instruct checkCastPP( eRegP dst ) %{
7768 match(Set dst (CheckCastPP dst));
7770 size(0);
7771 format %{ "#checkcastPP of $dst" %}
7772 ins_encode( /*empty encoding*/ );
7773 ins_pipe( empty );
7774 %}
7776 instruct castPP( eRegP dst ) %{
7777 match(Set dst (CastPP dst));
7778 format %{ "#castPP of $dst" %}
7779 ins_encode( /*empty encoding*/ );
7780 ins_pipe( empty );
7781 %}
7783 instruct castII( eRegI dst ) %{
7784 match(Set dst (CastII dst));
7785 format %{ "#castII of $dst" %}
7786 ins_encode( /*empty encoding*/ );
7787 ins_cost(0);
7788 ins_pipe( empty );
7789 %}
7792 // Load-locked - same as a regular pointer load when used with compare-swap
7793 instruct loadPLocked(eRegP dst, memory mem) %{
7794 match(Set dst (LoadPLocked mem));
7796 ins_cost(125);
7797 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7798 opcode(0x8B);
7799 ins_encode( OpcP, RegMem(dst,mem));
7800 ins_pipe( ialu_reg_mem );
7801 %}
7803 // Conditional-store of the updated heap-top.
7804 // Used during allocation of the shared heap.
7805 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7806 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7807 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7808 // EAX is killed if there is contention, but then it's also unused.
7809 // In the common case of no contention, EAX holds the new oop address.
7810 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7811 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7812 ins_pipe( pipe_cmpxchg );
7813 %}
7815 // Conditional-store of an int value.
7816 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7817 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
7818 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7819 effect(KILL oldval);
7820 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7821 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7822 ins_pipe( pipe_cmpxchg );
7823 %}
7825 // Conditional-store of a long value.
7826 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7827 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7828 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7829 effect(KILL oldval);
7830 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7831 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7832 "XCHG EBX,ECX"
7833 %}
7834 ins_encode %{
7835 // Note: we need to swap rbx, and rcx before and after the
7836 // cmpxchg8 instruction because the instruction uses
7837 // rcx as the high order word of the new value to store but
7838 // our register encoding uses rbx.
7839 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7840 if( os::is_MP() )
7841 __ lock();
7842 __ cmpxchg8($mem$$Address);
7843 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7844 %}
7845 ins_pipe( pipe_cmpxchg );
7846 %}
7848 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7850 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7851 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7852 effect(KILL cr, KILL oldval);
7853 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7854 "MOV $res,0\n\t"
7855 "JNE,s fail\n\t"
7856 "MOV $res,1\n"
7857 "fail:" %}
7858 ins_encode( enc_cmpxchg8(mem_ptr),
7859 enc_flags_ne_to_boolean(res) );
7860 ins_pipe( pipe_cmpxchg );
7861 %}
7863 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7864 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7865 effect(KILL cr, KILL oldval);
7866 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7867 "MOV $res,0\n\t"
7868 "JNE,s fail\n\t"
7869 "MOV $res,1\n"
7870 "fail:" %}
7871 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7872 ins_pipe( pipe_cmpxchg );
7873 %}
7875 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7876 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7877 effect(KILL cr, KILL oldval);
7878 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7879 "MOV $res,0\n\t"
7880 "JNE,s fail\n\t"
7881 "MOV $res,1\n"
7882 "fail:" %}
7883 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7884 ins_pipe( pipe_cmpxchg );
7885 %}
7887 //----------Subtraction Instructions-------------------------------------------
7888 // Integer Subtraction Instructions
7889 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7890 match(Set dst (SubI dst src));
7891 effect(KILL cr);
7893 size(2);
7894 format %{ "SUB $dst,$src" %}
7895 opcode(0x2B);
7896 ins_encode( OpcP, RegReg( dst, src) );
7897 ins_pipe( ialu_reg_reg );
7898 %}
7900 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
7901 match(Set dst (SubI dst src));
7902 effect(KILL cr);
7904 format %{ "SUB $dst,$src" %}
7905 opcode(0x81,0x05); /* Opcode 81 /5 */
7906 // ins_encode( RegImm( dst, src) );
7907 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7908 ins_pipe( ialu_reg );
7909 %}
7911 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
7912 match(Set dst (SubI dst (LoadI src)));
7913 effect(KILL cr);
7915 ins_cost(125);
7916 format %{ "SUB $dst,$src" %}
7917 opcode(0x2B);
7918 ins_encode( OpcP, RegMem( dst, src) );
7919 ins_pipe( ialu_reg_mem );
7920 %}
7922 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
7923 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7924 effect(KILL cr);
7926 ins_cost(150);
7927 format %{ "SUB $dst,$src" %}
7928 opcode(0x29); /* Opcode 29 /r */
7929 ins_encode( OpcP, RegMem( src, dst ) );
7930 ins_pipe( ialu_mem_reg );
7931 %}
7933 // Subtract from a pointer
7934 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
7935 match(Set dst (AddP dst (SubI zero src)));
7936 effect(KILL cr);
7938 size(2);
7939 format %{ "SUB $dst,$src" %}
7940 opcode(0x2B);
7941 ins_encode( OpcP, RegReg( dst, src) );
7942 ins_pipe( ialu_reg_reg );
7943 %}
7945 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
7946 match(Set dst (SubI zero dst));
7947 effect(KILL cr);
7949 size(2);
7950 format %{ "NEG $dst" %}
7951 opcode(0xF7,0x03); // Opcode F7 /3
7952 ins_encode( OpcP, RegOpc( dst ) );
7953 ins_pipe( ialu_reg );
7954 %}
7957 //----------Multiplication/Division Instructions-------------------------------
7958 // Integer Multiplication Instructions
7959 // Multiply Register
7960 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7961 match(Set dst (MulI dst src));
7962 effect(KILL cr);
7964 size(3);
7965 ins_cost(300);
7966 format %{ "IMUL $dst,$src" %}
7967 opcode(0xAF, 0x0F);
7968 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7969 ins_pipe( ialu_reg_reg_alu0 );
7970 %}
7972 // Multiply 32-bit Immediate
7973 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
7974 match(Set dst (MulI src imm));
7975 effect(KILL cr);
7977 ins_cost(300);
7978 format %{ "IMUL $dst,$src,$imm" %}
7979 opcode(0x69); /* 69 /r id */
7980 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7981 ins_pipe( ialu_reg_reg_alu0 );
7982 %}
7984 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7985 match(Set dst src);
7986 effect(KILL cr);
7988 // Note that this is artificially increased to make it more expensive than loadConL
7989 ins_cost(250);
7990 format %{ "MOV EAX,$src\t// low word only" %}
7991 opcode(0xB8);
7992 ins_encode( LdImmL_Lo(dst, src) );
7993 ins_pipe( ialu_reg_fat );
7994 %}
7996 // Multiply by 32-bit Immediate, taking the shifted high order results
7997 // (special case for shift by 32)
7998 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7999 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8000 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8001 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8002 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8003 effect(USE src1, KILL cr);
8005 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8006 ins_cost(0*100 + 1*400 - 150);
8007 format %{ "IMUL EDX:EAX,$src1" %}
8008 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8009 ins_pipe( pipe_slow );
8010 %}
8012 // Multiply by 32-bit Immediate, taking the shifted high order results
8013 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8014 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8015 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8016 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8017 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8018 effect(USE src1, KILL cr);
8020 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8021 ins_cost(1*100 + 1*400 - 150);
8022 format %{ "IMUL EDX:EAX,$src1\n\t"
8023 "SAR EDX,$cnt-32" %}
8024 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8025 ins_pipe( pipe_slow );
8026 %}
8028 // Multiply Memory 32-bit Immediate
8029 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8030 match(Set dst (MulI (LoadI src) imm));
8031 effect(KILL cr);
8033 ins_cost(300);
8034 format %{ "IMUL $dst,$src,$imm" %}
8035 opcode(0x69); /* 69 /r id */
8036 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8037 ins_pipe( ialu_reg_mem_alu0 );
8038 %}
8040 // Multiply Memory
8041 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8042 match(Set dst (MulI dst (LoadI src)));
8043 effect(KILL cr);
8045 ins_cost(350);
8046 format %{ "IMUL $dst,$src" %}
8047 opcode(0xAF, 0x0F);
8048 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8049 ins_pipe( ialu_reg_mem_alu0 );
8050 %}
8052 // Multiply Register Int to Long
8053 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8054 // Basic Idea: long = (long)int * (long)int
8055 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8056 effect(DEF dst, USE src, USE src1, KILL flags);
8058 ins_cost(300);
8059 format %{ "IMUL $dst,$src1" %}
8061 ins_encode( long_int_multiply( dst, src1 ) );
8062 ins_pipe( ialu_reg_reg_alu0 );
8063 %}
8065 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8066 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8067 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8068 effect(KILL flags);
8070 ins_cost(300);
8071 format %{ "MUL $dst,$src1" %}
8073 ins_encode( long_uint_multiply(dst, src1) );
8074 ins_pipe( ialu_reg_reg_alu0 );
8075 %}
8077 // Multiply Register Long
8078 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8079 match(Set dst (MulL dst src));
8080 effect(KILL cr, TEMP tmp);
8081 ins_cost(4*100+3*400);
8082 // Basic idea: lo(result) = lo(x_lo * y_lo)
8083 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8084 format %{ "MOV $tmp,$src.lo\n\t"
8085 "IMUL $tmp,EDX\n\t"
8086 "MOV EDX,$src.hi\n\t"
8087 "IMUL EDX,EAX\n\t"
8088 "ADD $tmp,EDX\n\t"
8089 "MUL EDX:EAX,$src.lo\n\t"
8090 "ADD EDX,$tmp" %}
8091 ins_encode( long_multiply( dst, src, tmp ) );
8092 ins_pipe( pipe_slow );
8093 %}
8095 // Multiply Register Long where the left operand's high 32 bits are zero
8096 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8097 predicate(is_operand_hi32_zero(n->in(1)));
8098 match(Set dst (MulL dst src));
8099 effect(KILL cr, TEMP tmp);
8100 ins_cost(2*100+2*400);
8101 // Basic idea: lo(result) = lo(x_lo * y_lo)
8102 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8103 format %{ "MOV $tmp,$src.hi\n\t"
8104 "IMUL $tmp,EAX\n\t"
8105 "MUL EDX:EAX,$src.lo\n\t"
8106 "ADD EDX,$tmp" %}
8107 ins_encode %{
8108 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8109 __ imull($tmp$$Register, rax);
8110 __ mull($src$$Register);
8111 __ addl(rdx, $tmp$$Register);
8112 %}
8113 ins_pipe( pipe_slow );
8114 %}
8116 // Multiply Register Long where the right operand's high 32 bits are zero
8117 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8118 predicate(is_operand_hi32_zero(n->in(2)));
8119 match(Set dst (MulL dst src));
8120 effect(KILL cr, TEMP tmp);
8121 ins_cost(2*100+2*400);
8122 // Basic idea: lo(result) = lo(x_lo * y_lo)
8123 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8124 format %{ "MOV $tmp,$src.lo\n\t"
8125 "IMUL $tmp,EDX\n\t"
8126 "MUL EDX:EAX,$src.lo\n\t"
8127 "ADD EDX,$tmp" %}
8128 ins_encode %{
8129 __ movl($tmp$$Register, $src$$Register);
8130 __ imull($tmp$$Register, rdx);
8131 __ mull($src$$Register);
8132 __ addl(rdx, $tmp$$Register);
8133 %}
8134 ins_pipe( pipe_slow );
8135 %}
8137 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8138 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8139 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8140 match(Set dst (MulL dst src));
8141 effect(KILL cr);
8142 ins_cost(1*400);
8143 // Basic idea: lo(result) = lo(x_lo * y_lo)
8144 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8145 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8146 ins_encode %{
8147 __ mull($src$$Register);
8148 %}
8149 ins_pipe( pipe_slow );
8150 %}
8152 // Multiply Register Long by small constant
8153 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8154 match(Set dst (MulL dst src));
8155 effect(KILL cr, TEMP tmp);
8156 ins_cost(2*100+2*400);
8157 size(12);
8158 // Basic idea: lo(result) = lo(src * EAX)
8159 // hi(result) = hi(src * EAX) + lo(src * EDX)
8160 format %{ "IMUL $tmp,EDX,$src\n\t"
8161 "MOV EDX,$src\n\t"
8162 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8163 "ADD EDX,$tmp" %}
8164 ins_encode( long_multiply_con( dst, src, tmp ) );
8165 ins_pipe( pipe_slow );
8166 %}
8168 // Integer DIV with Register
8169 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8170 match(Set rax (DivI rax div));
8171 effect(KILL rdx, KILL cr);
8172 size(26);
8173 ins_cost(30*100+10*100);
8174 format %{ "CMP EAX,0x80000000\n\t"
8175 "JNE,s normal\n\t"
8176 "XOR EDX,EDX\n\t"
8177 "CMP ECX,-1\n\t"
8178 "JE,s done\n"
8179 "normal: CDQ\n\t"
8180 "IDIV $div\n\t"
8181 "done:" %}
8182 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8183 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8184 ins_pipe( ialu_reg_reg_alu0 );
8185 %}
8187 // Divide Register Long
8188 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8189 match(Set dst (DivL src1 src2));
8190 effect( KILL cr, KILL cx, KILL bx );
8191 ins_cost(10000);
8192 format %{ "PUSH $src1.hi\n\t"
8193 "PUSH $src1.lo\n\t"
8194 "PUSH $src2.hi\n\t"
8195 "PUSH $src2.lo\n\t"
8196 "CALL SharedRuntime::ldiv\n\t"
8197 "ADD ESP,16" %}
8198 ins_encode( long_div(src1,src2) );
8199 ins_pipe( pipe_slow );
8200 %}
8202 // Integer DIVMOD with Register, both quotient and mod results
8203 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8204 match(DivModI rax div);
8205 effect(KILL cr);
8206 size(26);
8207 ins_cost(30*100+10*100);
8208 format %{ "CMP EAX,0x80000000\n\t"
8209 "JNE,s normal\n\t"
8210 "XOR EDX,EDX\n\t"
8211 "CMP ECX,-1\n\t"
8212 "JE,s done\n"
8213 "normal: CDQ\n\t"
8214 "IDIV $div\n\t"
8215 "done:" %}
8216 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8217 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8218 ins_pipe( pipe_slow );
8219 %}
8221 // Integer MOD with Register
8222 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8223 match(Set rdx (ModI rax div));
8224 effect(KILL rax, KILL cr);
8226 size(26);
8227 ins_cost(300);
8228 format %{ "CDQ\n\t"
8229 "IDIV $div" %}
8230 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8231 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8232 ins_pipe( ialu_reg_reg_alu0 );
8233 %}
8235 // Remainder Register Long
8236 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8237 match(Set dst (ModL src1 src2));
8238 effect( KILL cr, KILL cx, KILL bx );
8239 ins_cost(10000);
8240 format %{ "PUSH $src1.hi\n\t"
8241 "PUSH $src1.lo\n\t"
8242 "PUSH $src2.hi\n\t"
8243 "PUSH $src2.lo\n\t"
8244 "CALL SharedRuntime::lrem\n\t"
8245 "ADD ESP,16" %}
8246 ins_encode( long_mod(src1,src2) );
8247 ins_pipe( pipe_slow );
8248 %}
8250 // Divide Register Long (no special case since divisor != -1)
8251 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
8252 match(Set dst (DivL dst imm));
8253 effect( TEMP tmp, TEMP tmp2, KILL cr );
8254 ins_cost(1000);
8255 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8256 "XOR $tmp2,$tmp2\n\t"
8257 "CMP $tmp,EDX\n\t"
8258 "JA,s fast\n\t"
8259 "MOV $tmp2,EAX\n\t"
8260 "MOV EAX,EDX\n\t"
8261 "MOV EDX,0\n\t"
8262 "JLE,s pos\n\t"
8263 "LNEG EAX : $tmp2\n\t"
8264 "DIV $tmp # unsigned division\n\t"
8265 "XCHG EAX,$tmp2\n\t"
8266 "DIV $tmp\n\t"
8267 "LNEG $tmp2 : EAX\n\t"
8268 "JMP,s done\n"
8269 "pos:\n\t"
8270 "DIV $tmp\n\t"
8271 "XCHG EAX,$tmp2\n"
8272 "fast:\n\t"
8273 "DIV $tmp\n"
8274 "done:\n\t"
8275 "MOV EDX,$tmp2\n\t"
8276 "NEG EDX:EAX # if $imm < 0" %}
8277 ins_encode %{
8278 int con = (int)$imm$$constant;
8279 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8280 int pcon = (con > 0) ? con : -con;
8281 Label Lfast, Lpos, Ldone;
8283 __ movl($tmp$$Register, pcon);
8284 __ xorl($tmp2$$Register,$tmp2$$Register);
8285 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8286 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8288 __ movl($tmp2$$Register, $dst$$Register); // save
8289 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8290 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8291 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8293 // Negative dividend.
8294 // convert value to positive to use unsigned division
8295 __ lneg($dst$$Register, $tmp2$$Register);
8296 __ divl($tmp$$Register);
8297 __ xchgl($dst$$Register, $tmp2$$Register);
8298 __ divl($tmp$$Register);
8299 // revert result back to negative
8300 __ lneg($tmp2$$Register, $dst$$Register);
8301 __ jmpb(Ldone);
8303 __ bind(Lpos);
8304 __ divl($tmp$$Register); // Use unsigned division
8305 __ xchgl($dst$$Register, $tmp2$$Register);
8306 // Fallthrow for final divide, tmp2 has 32 bit hi result
8308 __ bind(Lfast);
8309 // fast path: src is positive
8310 __ divl($tmp$$Register); // Use unsigned division
8312 __ bind(Ldone);
8313 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8314 if (con < 0) {
8315 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8316 }
8317 %}
8318 ins_pipe( pipe_slow );
8319 %}
8321 // Remainder Register Long (remainder fit into 32 bits)
8322 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
8323 match(Set dst (ModL dst imm));
8324 effect( TEMP tmp, TEMP tmp2, KILL cr );
8325 ins_cost(1000);
8326 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8327 "CMP $tmp,EDX\n\t"
8328 "JA,s fast\n\t"
8329 "MOV $tmp2,EAX\n\t"
8330 "MOV EAX,EDX\n\t"
8331 "MOV EDX,0\n\t"
8332 "JLE,s pos\n\t"
8333 "LNEG EAX : $tmp2\n\t"
8334 "DIV $tmp # unsigned division\n\t"
8335 "MOV EAX,$tmp2\n\t"
8336 "DIV $tmp\n\t"
8337 "NEG EDX\n\t"
8338 "JMP,s done\n"
8339 "pos:\n\t"
8340 "DIV $tmp\n\t"
8341 "MOV EAX,$tmp2\n"
8342 "fast:\n\t"
8343 "DIV $tmp\n"
8344 "done:\n\t"
8345 "MOV EAX,EDX\n\t"
8346 "SAR EDX,31\n\t" %}
8347 ins_encode %{
8348 int con = (int)$imm$$constant;
8349 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8350 int pcon = (con > 0) ? con : -con;
8351 Label Lfast, Lpos, Ldone;
8353 __ movl($tmp$$Register, pcon);
8354 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8355 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8357 __ movl($tmp2$$Register, $dst$$Register); // save
8358 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8359 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8360 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8362 // Negative dividend.
8363 // convert value to positive to use unsigned division
8364 __ lneg($dst$$Register, $tmp2$$Register);
8365 __ divl($tmp$$Register);
8366 __ movl($dst$$Register, $tmp2$$Register);
8367 __ divl($tmp$$Register);
8368 // revert remainder back to negative
8369 __ negl(HIGH_FROM_LOW($dst$$Register));
8370 __ jmpb(Ldone);
8372 __ bind(Lpos);
8373 __ divl($tmp$$Register);
8374 __ movl($dst$$Register, $tmp2$$Register);
8376 __ bind(Lfast);
8377 // fast path: src is positive
8378 __ divl($tmp$$Register);
8380 __ bind(Ldone);
8381 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8382 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8384 %}
8385 ins_pipe( pipe_slow );
8386 %}
8388 // Integer Shift Instructions
8389 // Shift Left by one
8390 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8391 match(Set dst (LShiftI dst shift));
8392 effect(KILL cr);
8394 size(2);
8395 format %{ "SHL $dst,$shift" %}
8396 opcode(0xD1, 0x4); /* D1 /4 */
8397 ins_encode( OpcP, RegOpc( dst ) );
8398 ins_pipe( ialu_reg );
8399 %}
8401 // Shift Left by 8-bit immediate
8402 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8403 match(Set dst (LShiftI dst shift));
8404 effect(KILL cr);
8406 size(3);
8407 format %{ "SHL $dst,$shift" %}
8408 opcode(0xC1, 0x4); /* C1 /4 ib */
8409 ins_encode( RegOpcImm( dst, shift) );
8410 ins_pipe( ialu_reg );
8411 %}
8413 // Shift Left by variable
8414 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8415 match(Set dst (LShiftI dst shift));
8416 effect(KILL cr);
8418 size(2);
8419 format %{ "SHL $dst,$shift" %}
8420 opcode(0xD3, 0x4); /* D3 /4 */
8421 ins_encode( OpcP, RegOpc( dst ) );
8422 ins_pipe( ialu_reg_reg );
8423 %}
8425 // Arithmetic shift right by one
8426 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8427 match(Set dst (RShiftI dst shift));
8428 effect(KILL cr);
8430 size(2);
8431 format %{ "SAR $dst,$shift" %}
8432 opcode(0xD1, 0x7); /* D1 /7 */
8433 ins_encode( OpcP, RegOpc( dst ) );
8434 ins_pipe( ialu_reg );
8435 %}
8437 // Arithmetic shift right by one
8438 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8439 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8440 effect(KILL cr);
8441 format %{ "SAR $dst,$shift" %}
8442 opcode(0xD1, 0x7); /* D1 /7 */
8443 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8444 ins_pipe( ialu_mem_imm );
8445 %}
8447 // Arithmetic Shift Right by 8-bit immediate
8448 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8449 match(Set dst (RShiftI dst shift));
8450 effect(KILL cr);
8452 size(3);
8453 format %{ "SAR $dst,$shift" %}
8454 opcode(0xC1, 0x7); /* C1 /7 ib */
8455 ins_encode( RegOpcImm( dst, shift ) );
8456 ins_pipe( ialu_mem_imm );
8457 %}
8459 // Arithmetic Shift Right by 8-bit immediate
8460 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8461 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8462 effect(KILL cr);
8464 format %{ "SAR $dst,$shift" %}
8465 opcode(0xC1, 0x7); /* C1 /7 ib */
8466 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8467 ins_pipe( ialu_mem_imm );
8468 %}
8470 // Arithmetic Shift Right by variable
8471 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8472 match(Set dst (RShiftI dst shift));
8473 effect(KILL cr);
8475 size(2);
8476 format %{ "SAR $dst,$shift" %}
8477 opcode(0xD3, 0x7); /* D3 /7 */
8478 ins_encode( OpcP, RegOpc( dst ) );
8479 ins_pipe( ialu_reg_reg );
8480 %}
8482 // Logical shift right by one
8483 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8484 match(Set dst (URShiftI dst shift));
8485 effect(KILL cr);
8487 size(2);
8488 format %{ "SHR $dst,$shift" %}
8489 opcode(0xD1, 0x5); /* D1 /5 */
8490 ins_encode( OpcP, RegOpc( dst ) );
8491 ins_pipe( ialu_reg );
8492 %}
8494 // Logical Shift Right by 8-bit immediate
8495 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8496 match(Set dst (URShiftI dst shift));
8497 effect(KILL cr);
8499 size(3);
8500 format %{ "SHR $dst,$shift" %}
8501 opcode(0xC1, 0x5); /* C1 /5 ib */
8502 ins_encode( RegOpcImm( dst, shift) );
8503 ins_pipe( ialu_reg );
8504 %}
8507 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8508 // This idiom is used by the compiler for the i2b bytecode.
8509 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{
8510 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8512 size(3);
8513 format %{ "MOVSX $dst,$src :8" %}
8514 ins_encode %{
8515 __ movsbl($dst$$Register, $src$$Register);
8516 %}
8517 ins_pipe(ialu_reg_reg);
8518 %}
8520 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8521 // This idiom is used by the compiler the i2s bytecode.
8522 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{
8523 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8525 size(3);
8526 format %{ "MOVSX $dst,$src :16" %}
8527 ins_encode %{
8528 __ movswl($dst$$Register, $src$$Register);
8529 %}
8530 ins_pipe(ialu_reg_reg);
8531 %}
8534 // Logical Shift Right by variable
8535 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8536 match(Set dst (URShiftI dst shift));
8537 effect(KILL cr);
8539 size(2);
8540 format %{ "SHR $dst,$shift" %}
8541 opcode(0xD3, 0x5); /* D3 /5 */
8542 ins_encode( OpcP, RegOpc( dst ) );
8543 ins_pipe( ialu_reg_reg );
8544 %}
8547 //----------Logical Instructions-----------------------------------------------
8548 //----------Integer Logical Instructions---------------------------------------
8549 // And Instructions
8550 // And Register with Register
8551 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8552 match(Set dst (AndI dst src));
8553 effect(KILL cr);
8555 size(2);
8556 format %{ "AND $dst,$src" %}
8557 opcode(0x23);
8558 ins_encode( OpcP, RegReg( dst, src) );
8559 ins_pipe( ialu_reg_reg );
8560 %}
8562 // And Register with Immediate
8563 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8564 match(Set dst (AndI dst src));
8565 effect(KILL cr);
8567 format %{ "AND $dst,$src" %}
8568 opcode(0x81,0x04); /* Opcode 81 /4 */
8569 // ins_encode( RegImm( dst, src) );
8570 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8571 ins_pipe( ialu_reg );
8572 %}
8574 // And Register with Memory
8575 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8576 match(Set dst (AndI dst (LoadI src)));
8577 effect(KILL cr);
8579 ins_cost(125);
8580 format %{ "AND $dst,$src" %}
8581 opcode(0x23);
8582 ins_encode( OpcP, RegMem( dst, src) );
8583 ins_pipe( ialu_reg_mem );
8584 %}
8586 // And Memory with Register
8587 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8588 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8589 effect(KILL cr);
8591 ins_cost(150);
8592 format %{ "AND $dst,$src" %}
8593 opcode(0x21); /* Opcode 21 /r */
8594 ins_encode( OpcP, RegMem( src, dst ) );
8595 ins_pipe( ialu_mem_reg );
8596 %}
8598 // And Memory with Immediate
8599 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8600 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8601 effect(KILL cr);
8603 ins_cost(125);
8604 format %{ "AND $dst,$src" %}
8605 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8606 // ins_encode( MemImm( dst, src) );
8607 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8608 ins_pipe( ialu_mem_imm );
8609 %}
8611 // Or Instructions
8612 // Or Register with Register
8613 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8614 match(Set dst (OrI dst src));
8615 effect(KILL cr);
8617 size(2);
8618 format %{ "OR $dst,$src" %}
8619 opcode(0x0B);
8620 ins_encode( OpcP, RegReg( dst, src) );
8621 ins_pipe( ialu_reg_reg );
8622 %}
8624 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
8625 match(Set dst (OrI dst (CastP2X src)));
8626 effect(KILL cr);
8628 size(2);
8629 format %{ "OR $dst,$src" %}
8630 opcode(0x0B);
8631 ins_encode( OpcP, RegReg( dst, src) );
8632 ins_pipe( ialu_reg_reg );
8633 %}
8636 // Or Register with Immediate
8637 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8638 match(Set dst (OrI dst src));
8639 effect(KILL cr);
8641 format %{ "OR $dst,$src" %}
8642 opcode(0x81,0x01); /* Opcode 81 /1 id */
8643 // ins_encode( RegImm( dst, src) );
8644 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8645 ins_pipe( ialu_reg );
8646 %}
8648 // Or Register with Memory
8649 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8650 match(Set dst (OrI dst (LoadI src)));
8651 effect(KILL cr);
8653 ins_cost(125);
8654 format %{ "OR $dst,$src" %}
8655 opcode(0x0B);
8656 ins_encode( OpcP, RegMem( dst, src) );
8657 ins_pipe( ialu_reg_mem );
8658 %}
8660 // Or Memory with Register
8661 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8662 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8663 effect(KILL cr);
8665 ins_cost(150);
8666 format %{ "OR $dst,$src" %}
8667 opcode(0x09); /* Opcode 09 /r */
8668 ins_encode( OpcP, RegMem( src, dst ) );
8669 ins_pipe( ialu_mem_reg );
8670 %}
8672 // Or Memory with Immediate
8673 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8674 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8675 effect(KILL cr);
8677 ins_cost(125);
8678 format %{ "OR $dst,$src" %}
8679 opcode(0x81,0x1); /* Opcode 81 /1 id */
8680 // ins_encode( MemImm( dst, src) );
8681 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8682 ins_pipe( ialu_mem_imm );
8683 %}
8685 // ROL/ROR
8686 // ROL expand
8687 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8688 effect(USE_DEF dst, USE shift, KILL cr);
8690 format %{ "ROL $dst, $shift" %}
8691 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8692 ins_encode( OpcP, RegOpc( dst ));
8693 ins_pipe( ialu_reg );
8694 %}
8696 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8697 effect(USE_DEF dst, USE shift, KILL cr);
8699 format %{ "ROL $dst, $shift" %}
8700 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8701 ins_encode( RegOpcImm(dst, shift) );
8702 ins_pipe(ialu_reg);
8703 %}
8705 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8706 effect(USE_DEF dst, USE shift, KILL cr);
8708 format %{ "ROL $dst, $shift" %}
8709 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8710 ins_encode(OpcP, RegOpc(dst));
8711 ins_pipe( ialu_reg_reg );
8712 %}
8713 // end of ROL expand
8715 // ROL 32bit by one once
8716 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8717 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8719 expand %{
8720 rolI_eReg_imm1(dst, lshift, cr);
8721 %}
8722 %}
8724 // ROL 32bit var by imm8 once
8725 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8726 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8727 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8729 expand %{
8730 rolI_eReg_imm8(dst, lshift, cr);
8731 %}
8732 %}
8734 // ROL 32bit var by var once
8735 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8736 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8738 expand %{
8739 rolI_eReg_CL(dst, shift, cr);
8740 %}
8741 %}
8743 // ROL 32bit var by var once
8744 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8745 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8747 expand %{
8748 rolI_eReg_CL(dst, shift, cr);
8749 %}
8750 %}
8752 // ROR expand
8753 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8754 effect(USE_DEF dst, USE shift, KILL cr);
8756 format %{ "ROR $dst, $shift" %}
8757 opcode(0xD1,0x1); /* Opcode D1 /1 */
8758 ins_encode( OpcP, RegOpc( dst ) );
8759 ins_pipe( ialu_reg );
8760 %}
8762 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8763 effect (USE_DEF dst, USE shift, KILL cr);
8765 format %{ "ROR $dst, $shift" %}
8766 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8767 ins_encode( RegOpcImm(dst, shift) );
8768 ins_pipe( ialu_reg );
8769 %}
8771 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8772 effect(USE_DEF dst, USE shift, KILL cr);
8774 format %{ "ROR $dst, $shift" %}
8775 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8776 ins_encode(OpcP, RegOpc(dst));
8777 ins_pipe( ialu_reg_reg );
8778 %}
8779 // end of ROR expand
8781 // ROR right once
8782 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8783 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8785 expand %{
8786 rorI_eReg_imm1(dst, rshift, cr);
8787 %}
8788 %}
8790 // ROR 32bit by immI8 once
8791 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8792 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8793 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8795 expand %{
8796 rorI_eReg_imm8(dst, rshift, cr);
8797 %}
8798 %}
8800 // ROR 32bit var by var once
8801 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8802 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8804 expand %{
8805 rorI_eReg_CL(dst, shift, cr);
8806 %}
8807 %}
8809 // ROR 32bit var by var once
8810 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8811 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8813 expand %{
8814 rorI_eReg_CL(dst, shift, cr);
8815 %}
8816 %}
8818 // Xor Instructions
8819 // Xor Register with Register
8820 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8821 match(Set dst (XorI dst src));
8822 effect(KILL cr);
8824 size(2);
8825 format %{ "XOR $dst,$src" %}
8826 opcode(0x33);
8827 ins_encode( OpcP, RegReg( dst, src) );
8828 ins_pipe( ialu_reg_reg );
8829 %}
8831 // Xor Register with Immediate -1
8832 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
8833 match(Set dst (XorI dst imm));
8835 size(2);
8836 format %{ "NOT $dst" %}
8837 ins_encode %{
8838 __ notl($dst$$Register);
8839 %}
8840 ins_pipe( ialu_reg );
8841 %}
8843 // Xor Register with Immediate
8844 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8845 match(Set dst (XorI dst src));
8846 effect(KILL cr);
8848 format %{ "XOR $dst,$src" %}
8849 opcode(0x81,0x06); /* Opcode 81 /6 id */
8850 // ins_encode( RegImm( dst, src) );
8851 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8852 ins_pipe( ialu_reg );
8853 %}
8855 // Xor Register with Memory
8856 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8857 match(Set dst (XorI dst (LoadI src)));
8858 effect(KILL cr);
8860 ins_cost(125);
8861 format %{ "XOR $dst,$src" %}
8862 opcode(0x33);
8863 ins_encode( OpcP, RegMem(dst, src) );
8864 ins_pipe( ialu_reg_mem );
8865 %}
8867 // Xor Memory with Register
8868 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8869 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8870 effect(KILL cr);
8872 ins_cost(150);
8873 format %{ "XOR $dst,$src" %}
8874 opcode(0x31); /* Opcode 31 /r */
8875 ins_encode( OpcP, RegMem( src, dst ) );
8876 ins_pipe( ialu_mem_reg );
8877 %}
8879 // Xor Memory with Immediate
8880 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8881 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8882 effect(KILL cr);
8884 ins_cost(125);
8885 format %{ "XOR $dst,$src" %}
8886 opcode(0x81,0x6); /* Opcode 81 /6 id */
8887 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8888 ins_pipe( ialu_mem_imm );
8889 %}
8891 //----------Convert Int to Boolean---------------------------------------------
8893 instruct movI_nocopy(eRegI dst, eRegI src) %{
8894 effect( DEF dst, USE src );
8895 format %{ "MOV $dst,$src" %}
8896 ins_encode( enc_Copy( dst, src) );
8897 ins_pipe( ialu_reg_reg );
8898 %}
8900 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
8901 effect( USE_DEF dst, USE src, KILL cr );
8903 size(4);
8904 format %{ "NEG $dst\n\t"
8905 "ADC $dst,$src" %}
8906 ins_encode( neg_reg(dst),
8907 OpcRegReg(0x13,dst,src) );
8908 ins_pipe( ialu_reg_reg_long );
8909 %}
8911 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
8912 match(Set dst (Conv2B src));
8914 expand %{
8915 movI_nocopy(dst,src);
8916 ci2b(dst,src,cr);
8917 %}
8918 %}
8920 instruct movP_nocopy(eRegI dst, eRegP src) %{
8921 effect( DEF dst, USE src );
8922 format %{ "MOV $dst,$src" %}
8923 ins_encode( enc_Copy( dst, src) );
8924 ins_pipe( ialu_reg_reg );
8925 %}
8927 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
8928 effect( USE_DEF dst, USE src, KILL cr );
8929 format %{ "NEG $dst\n\t"
8930 "ADC $dst,$src" %}
8931 ins_encode( neg_reg(dst),
8932 OpcRegReg(0x13,dst,src) );
8933 ins_pipe( ialu_reg_reg_long );
8934 %}
8936 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
8937 match(Set dst (Conv2B src));
8939 expand %{
8940 movP_nocopy(dst,src);
8941 cp2b(dst,src,cr);
8942 %}
8943 %}
8945 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
8946 match(Set dst (CmpLTMask p q));
8947 effect( KILL cr );
8948 ins_cost(400);
8950 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8951 format %{ "XOR $dst,$dst\n\t"
8952 "CMP $p,$q\n\t"
8953 "SETlt $dst\n\t"
8954 "NEG $dst" %}
8955 ins_encode( OpcRegReg(0x33,dst,dst),
8956 OpcRegReg(0x3B,p,q),
8957 setLT_reg(dst), neg_reg(dst) );
8958 ins_pipe( pipe_slow );
8959 %}
8961 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
8962 match(Set dst (CmpLTMask dst zero));
8963 effect( DEF dst, KILL cr );
8964 ins_cost(100);
8966 format %{ "SAR $dst,31" %}
8967 opcode(0xC1, 0x7); /* C1 /7 ib */
8968 ins_encode( RegOpcImm( dst, 0x1F ) );
8969 ins_pipe( ialu_reg );
8970 %}
8973 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
8974 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8975 effect( KILL tmp, KILL cr );
8976 ins_cost(400);
8977 // annoyingly, $tmp has no edges so you cant ask for it in
8978 // any format or encoding
8979 format %{ "SUB $p,$q\n\t"
8980 "SBB ECX,ECX\n\t"
8981 "AND ECX,$y\n\t"
8982 "ADD $p,ECX" %}
8983 ins_encode( enc_cmpLTP(p,q,y,tmp) );
8984 ins_pipe( pipe_cmplt );
8985 %}
8987 /* If I enable this, I encourage spilling in the inner loop of compress.
8988 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
8989 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8990 effect( USE_KILL tmp, KILL cr );
8991 ins_cost(400);
8993 format %{ "SUB $p,$q\n\t"
8994 "SBB ECX,ECX\n\t"
8995 "AND ECX,$y\n\t"
8996 "ADD $p,ECX" %}
8997 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
8998 %}
8999 */
9001 //----------Long Instructions------------------------------------------------
9002 // Add Long Register with Register
9003 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9004 match(Set dst (AddL dst src));
9005 effect(KILL cr);
9006 ins_cost(200);
9007 format %{ "ADD $dst.lo,$src.lo\n\t"
9008 "ADC $dst.hi,$src.hi" %}
9009 opcode(0x03, 0x13);
9010 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9011 ins_pipe( ialu_reg_reg_long );
9012 %}
9014 // Add Long Register with Immediate
9015 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9016 match(Set dst (AddL dst src));
9017 effect(KILL cr);
9018 format %{ "ADD $dst.lo,$src.lo\n\t"
9019 "ADC $dst.hi,$src.hi" %}
9020 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9021 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9022 ins_pipe( ialu_reg_long );
9023 %}
9025 // Add Long Register with Memory
9026 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9027 match(Set dst (AddL dst (LoadL mem)));
9028 effect(KILL cr);
9029 ins_cost(125);
9030 format %{ "ADD $dst.lo,$mem\n\t"
9031 "ADC $dst.hi,$mem+4" %}
9032 opcode(0x03, 0x13);
9033 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9034 ins_pipe( ialu_reg_long_mem );
9035 %}
9037 // Subtract Long Register with Register.
9038 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9039 match(Set dst (SubL dst src));
9040 effect(KILL cr);
9041 ins_cost(200);
9042 format %{ "SUB $dst.lo,$src.lo\n\t"
9043 "SBB $dst.hi,$src.hi" %}
9044 opcode(0x2B, 0x1B);
9045 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9046 ins_pipe( ialu_reg_reg_long );
9047 %}
9049 // Subtract Long Register with Immediate
9050 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9051 match(Set dst (SubL dst src));
9052 effect(KILL cr);
9053 format %{ "SUB $dst.lo,$src.lo\n\t"
9054 "SBB $dst.hi,$src.hi" %}
9055 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9056 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9057 ins_pipe( ialu_reg_long );
9058 %}
9060 // Subtract Long Register with Memory
9061 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9062 match(Set dst (SubL dst (LoadL mem)));
9063 effect(KILL cr);
9064 ins_cost(125);
9065 format %{ "SUB $dst.lo,$mem\n\t"
9066 "SBB $dst.hi,$mem+4" %}
9067 opcode(0x2B, 0x1B);
9068 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9069 ins_pipe( ialu_reg_long_mem );
9070 %}
9072 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9073 match(Set dst (SubL zero dst));
9074 effect(KILL cr);
9075 ins_cost(300);
9076 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9077 ins_encode( neg_long(dst) );
9078 ins_pipe( ialu_reg_reg_long );
9079 %}
9081 // And Long Register with Register
9082 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9083 match(Set dst (AndL dst src));
9084 effect(KILL cr);
9085 format %{ "AND $dst.lo,$src.lo\n\t"
9086 "AND $dst.hi,$src.hi" %}
9087 opcode(0x23,0x23);
9088 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9089 ins_pipe( ialu_reg_reg_long );
9090 %}
9092 // And Long Register with Immediate
9093 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9094 match(Set dst (AndL dst src));
9095 effect(KILL cr);
9096 format %{ "AND $dst.lo,$src.lo\n\t"
9097 "AND $dst.hi,$src.hi" %}
9098 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9099 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9100 ins_pipe( ialu_reg_long );
9101 %}
9103 // And Long Register with Memory
9104 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9105 match(Set dst (AndL dst (LoadL mem)));
9106 effect(KILL cr);
9107 ins_cost(125);
9108 format %{ "AND $dst.lo,$mem\n\t"
9109 "AND $dst.hi,$mem+4" %}
9110 opcode(0x23, 0x23);
9111 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9112 ins_pipe( ialu_reg_long_mem );
9113 %}
9115 // Or Long Register with Register
9116 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9117 match(Set dst (OrL dst src));
9118 effect(KILL cr);
9119 format %{ "OR $dst.lo,$src.lo\n\t"
9120 "OR $dst.hi,$src.hi" %}
9121 opcode(0x0B,0x0B);
9122 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9123 ins_pipe( ialu_reg_reg_long );
9124 %}
9126 // Or Long Register with Immediate
9127 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9128 match(Set dst (OrL dst src));
9129 effect(KILL cr);
9130 format %{ "OR $dst.lo,$src.lo\n\t"
9131 "OR $dst.hi,$src.hi" %}
9132 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9133 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9134 ins_pipe( ialu_reg_long );
9135 %}
9137 // Or Long Register with Memory
9138 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9139 match(Set dst (OrL dst (LoadL mem)));
9140 effect(KILL cr);
9141 ins_cost(125);
9142 format %{ "OR $dst.lo,$mem\n\t"
9143 "OR $dst.hi,$mem+4" %}
9144 opcode(0x0B,0x0B);
9145 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9146 ins_pipe( ialu_reg_long_mem );
9147 %}
9149 // Xor Long Register with Register
9150 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9151 match(Set dst (XorL dst src));
9152 effect(KILL cr);
9153 format %{ "XOR $dst.lo,$src.lo\n\t"
9154 "XOR $dst.hi,$src.hi" %}
9155 opcode(0x33,0x33);
9156 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9157 ins_pipe( ialu_reg_reg_long );
9158 %}
9160 // Xor Long Register with Immediate -1
9161 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9162 match(Set dst (XorL dst imm));
9163 format %{ "NOT $dst.lo\n\t"
9164 "NOT $dst.hi" %}
9165 ins_encode %{
9166 __ notl($dst$$Register);
9167 __ notl(HIGH_FROM_LOW($dst$$Register));
9168 %}
9169 ins_pipe( ialu_reg_long );
9170 %}
9172 // Xor Long Register with Immediate
9173 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9174 match(Set dst (XorL dst src));
9175 effect(KILL cr);
9176 format %{ "XOR $dst.lo,$src.lo\n\t"
9177 "XOR $dst.hi,$src.hi" %}
9178 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9179 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9180 ins_pipe( ialu_reg_long );
9181 %}
9183 // Xor Long Register with Memory
9184 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9185 match(Set dst (XorL dst (LoadL mem)));
9186 effect(KILL cr);
9187 ins_cost(125);
9188 format %{ "XOR $dst.lo,$mem\n\t"
9189 "XOR $dst.hi,$mem+4" %}
9190 opcode(0x33,0x33);
9191 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9192 ins_pipe( ialu_reg_long_mem );
9193 %}
9195 // Shift Left Long by 1
9196 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9197 predicate(UseNewLongLShift);
9198 match(Set dst (LShiftL dst cnt));
9199 effect(KILL cr);
9200 ins_cost(100);
9201 format %{ "ADD $dst.lo,$dst.lo\n\t"
9202 "ADC $dst.hi,$dst.hi" %}
9203 ins_encode %{
9204 __ addl($dst$$Register,$dst$$Register);
9205 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9206 %}
9207 ins_pipe( ialu_reg_long );
9208 %}
9210 // Shift Left Long by 2
9211 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9212 predicate(UseNewLongLShift);
9213 match(Set dst (LShiftL dst cnt));
9214 effect(KILL cr);
9215 ins_cost(100);
9216 format %{ "ADD $dst.lo,$dst.lo\n\t"
9217 "ADC $dst.hi,$dst.hi\n\t"
9218 "ADD $dst.lo,$dst.lo\n\t"
9219 "ADC $dst.hi,$dst.hi" %}
9220 ins_encode %{
9221 __ addl($dst$$Register,$dst$$Register);
9222 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9223 __ addl($dst$$Register,$dst$$Register);
9224 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9225 %}
9226 ins_pipe( ialu_reg_long );
9227 %}
9229 // Shift Left Long by 3
9230 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9231 predicate(UseNewLongLShift);
9232 match(Set dst (LShiftL dst cnt));
9233 effect(KILL cr);
9234 ins_cost(100);
9235 format %{ "ADD $dst.lo,$dst.lo\n\t"
9236 "ADC $dst.hi,$dst.hi\n\t"
9237 "ADD $dst.lo,$dst.lo\n\t"
9238 "ADC $dst.hi,$dst.hi\n\t"
9239 "ADD $dst.lo,$dst.lo\n\t"
9240 "ADC $dst.hi,$dst.hi" %}
9241 ins_encode %{
9242 __ addl($dst$$Register,$dst$$Register);
9243 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9244 __ addl($dst$$Register,$dst$$Register);
9245 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9246 __ addl($dst$$Register,$dst$$Register);
9247 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9248 %}
9249 ins_pipe( ialu_reg_long );
9250 %}
9252 // Shift Left Long by 1-31
9253 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9254 match(Set dst (LShiftL dst cnt));
9255 effect(KILL cr);
9256 ins_cost(200);
9257 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9258 "SHL $dst.lo,$cnt" %}
9259 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9260 ins_encode( move_long_small_shift(dst,cnt) );
9261 ins_pipe( ialu_reg_long );
9262 %}
9264 // Shift Left Long by 32-63
9265 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9266 match(Set dst (LShiftL dst cnt));
9267 effect(KILL cr);
9268 ins_cost(300);
9269 format %{ "MOV $dst.hi,$dst.lo\n"
9270 "\tSHL $dst.hi,$cnt-32\n"
9271 "\tXOR $dst.lo,$dst.lo" %}
9272 opcode(0xC1, 0x4); /* C1 /4 ib */
9273 ins_encode( move_long_big_shift_clr(dst,cnt) );
9274 ins_pipe( ialu_reg_long );
9275 %}
9277 // Shift Left Long by variable
9278 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9279 match(Set dst (LShiftL dst shift));
9280 effect(KILL cr);
9281 ins_cost(500+200);
9282 size(17);
9283 format %{ "TEST $shift,32\n\t"
9284 "JEQ,s small\n\t"
9285 "MOV $dst.hi,$dst.lo\n\t"
9286 "XOR $dst.lo,$dst.lo\n"
9287 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9288 "SHL $dst.lo,$shift" %}
9289 ins_encode( shift_left_long( dst, shift ) );
9290 ins_pipe( pipe_slow );
9291 %}
9293 // Shift Right Long by 1-31
9294 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9295 match(Set dst (URShiftL dst cnt));
9296 effect(KILL cr);
9297 ins_cost(200);
9298 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9299 "SHR $dst.hi,$cnt" %}
9300 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9301 ins_encode( move_long_small_shift(dst,cnt) );
9302 ins_pipe( ialu_reg_long );
9303 %}
9305 // Shift Right Long by 32-63
9306 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9307 match(Set dst (URShiftL dst cnt));
9308 effect(KILL cr);
9309 ins_cost(300);
9310 format %{ "MOV $dst.lo,$dst.hi\n"
9311 "\tSHR $dst.lo,$cnt-32\n"
9312 "\tXOR $dst.hi,$dst.hi" %}
9313 opcode(0xC1, 0x5); /* C1 /5 ib */
9314 ins_encode( move_long_big_shift_clr(dst,cnt) );
9315 ins_pipe( ialu_reg_long );
9316 %}
9318 // Shift Right Long by variable
9319 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9320 match(Set dst (URShiftL dst shift));
9321 effect(KILL cr);
9322 ins_cost(600);
9323 size(17);
9324 format %{ "TEST $shift,32\n\t"
9325 "JEQ,s small\n\t"
9326 "MOV $dst.lo,$dst.hi\n\t"
9327 "XOR $dst.hi,$dst.hi\n"
9328 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9329 "SHR $dst.hi,$shift" %}
9330 ins_encode( shift_right_long( dst, shift ) );
9331 ins_pipe( pipe_slow );
9332 %}
9334 // Shift Right Long by 1-31
9335 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9336 match(Set dst (RShiftL dst cnt));
9337 effect(KILL cr);
9338 ins_cost(200);
9339 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9340 "SAR $dst.hi,$cnt" %}
9341 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9342 ins_encode( move_long_small_shift(dst,cnt) );
9343 ins_pipe( ialu_reg_long );
9344 %}
9346 // Shift Right Long by 32-63
9347 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9348 match(Set dst (RShiftL dst cnt));
9349 effect(KILL cr);
9350 ins_cost(300);
9351 format %{ "MOV $dst.lo,$dst.hi\n"
9352 "\tSAR $dst.lo,$cnt-32\n"
9353 "\tSAR $dst.hi,31" %}
9354 opcode(0xC1, 0x7); /* C1 /7 ib */
9355 ins_encode( move_long_big_shift_sign(dst,cnt) );
9356 ins_pipe( ialu_reg_long );
9357 %}
9359 // Shift Right arithmetic Long by variable
9360 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9361 match(Set dst (RShiftL dst shift));
9362 effect(KILL cr);
9363 ins_cost(600);
9364 size(18);
9365 format %{ "TEST $shift,32\n\t"
9366 "JEQ,s small\n\t"
9367 "MOV $dst.lo,$dst.hi\n\t"
9368 "SAR $dst.hi,31\n"
9369 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9370 "SAR $dst.hi,$shift" %}
9371 ins_encode( shift_right_arith_long( dst, shift ) );
9372 ins_pipe( pipe_slow );
9373 %}
9376 //----------Double Instructions------------------------------------------------
9377 // Double Math
9379 // Compare & branch
9381 // P6 version of float compare, sets condition codes in EFLAGS
9382 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9383 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9384 match(Set cr (CmpD src1 src2));
9385 effect(KILL rax);
9386 ins_cost(150);
9387 format %{ "FLD $src1\n\t"
9388 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9389 "JNP exit\n\t"
9390 "MOV ah,1 // saw a NaN, set CF\n\t"
9391 "SAHF\n"
9392 "exit:\tNOP // avoid branch to branch" %}
9393 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9394 ins_encode( Push_Reg_DPR(src1),
9395 OpcP, RegOpc(src2),
9396 cmpF_P6_fixup );
9397 ins_pipe( pipe_slow );
9398 %}
9400 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9401 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9402 match(Set cr (CmpD src1 src2));
9403 ins_cost(150);
9404 format %{ "FLD $src1\n\t"
9405 "FUCOMIP ST,$src2 // P6 instruction" %}
9406 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9407 ins_encode( Push_Reg_DPR(src1),
9408 OpcP, RegOpc(src2));
9409 ins_pipe( pipe_slow );
9410 %}
9412 // Compare & branch
9413 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9414 predicate(UseSSE<=1);
9415 match(Set cr (CmpD src1 src2));
9416 effect(KILL rax);
9417 ins_cost(200);
9418 format %{ "FLD $src1\n\t"
9419 "FCOMp $src2\n\t"
9420 "FNSTSW AX\n\t"
9421 "TEST AX,0x400\n\t"
9422 "JZ,s flags\n\t"
9423 "MOV AH,1\t# unordered treat as LT\n"
9424 "flags:\tSAHF" %}
9425 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9426 ins_encode( Push_Reg_DPR(src1),
9427 OpcP, RegOpc(src2),
9428 fpu_flags);
9429 ins_pipe( pipe_slow );
9430 %}
9432 // Compare vs zero into -1,0,1
9433 instruct cmpDPR_0(eRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9434 predicate(UseSSE<=1);
9435 match(Set dst (CmpD3 src1 zero));
9436 effect(KILL cr, KILL rax);
9437 ins_cost(280);
9438 format %{ "FTSTD $dst,$src1" %}
9439 opcode(0xE4, 0xD9);
9440 ins_encode( Push_Reg_DPR(src1),
9441 OpcS, OpcP, PopFPU,
9442 CmpF_Result(dst));
9443 ins_pipe( pipe_slow );
9444 %}
9446 // Compare into -1,0,1
9447 instruct cmpDPR_reg(eRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9448 predicate(UseSSE<=1);
9449 match(Set dst (CmpD3 src1 src2));
9450 effect(KILL cr, KILL rax);
9451 ins_cost(300);
9452 format %{ "FCMPD $dst,$src1,$src2" %}
9453 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9454 ins_encode( Push_Reg_DPR(src1),
9455 OpcP, RegOpc(src2),
9456 CmpF_Result(dst));
9457 ins_pipe( pipe_slow );
9458 %}
9460 // float compare and set condition codes in EFLAGS by XMM regs
9461 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9462 predicate(UseSSE>=2);
9463 match(Set cr (CmpD src1 src2));
9464 ins_cost(145);
9465 format %{ "UCOMISD $src1,$src2\n\t"
9466 "JNP,s exit\n\t"
9467 "PUSHF\t# saw NaN, set CF\n\t"
9468 "AND [rsp], #0xffffff2b\n\t"
9469 "POPF\n"
9470 "exit:" %}
9471 ins_encode %{
9472 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9473 emit_cmpfp_fixup(_masm);
9474 %}
9475 ins_pipe( pipe_slow );
9476 %}
9478 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9479 predicate(UseSSE>=2);
9480 match(Set cr (CmpD src1 src2));
9481 ins_cost(100);
9482 format %{ "UCOMISD $src1,$src2" %}
9483 ins_encode %{
9484 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9485 %}
9486 ins_pipe( pipe_slow );
9487 %}
9489 // float compare and set condition codes in EFLAGS by XMM regs
9490 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9491 predicate(UseSSE>=2);
9492 match(Set cr (CmpD src1 (LoadD src2)));
9493 ins_cost(145);
9494 format %{ "UCOMISD $src1,$src2\n\t"
9495 "JNP,s exit\n\t"
9496 "PUSHF\t# saw NaN, set CF\n\t"
9497 "AND [rsp], #0xffffff2b\n\t"
9498 "POPF\n"
9499 "exit:" %}
9500 ins_encode %{
9501 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9502 emit_cmpfp_fixup(_masm);
9503 %}
9504 ins_pipe( pipe_slow );
9505 %}
9507 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9508 predicate(UseSSE>=2);
9509 match(Set cr (CmpD src1 (LoadD src2)));
9510 ins_cost(100);
9511 format %{ "UCOMISD $src1,$src2" %}
9512 ins_encode %{
9513 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9514 %}
9515 ins_pipe( pipe_slow );
9516 %}
9518 // Compare into -1,0,1 in XMM
9519 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9520 predicate(UseSSE>=2);
9521 match(Set dst (CmpD3 src1 src2));
9522 effect(KILL cr);
9523 ins_cost(255);
9524 format %{ "UCOMISD $src1, $src2\n\t"
9525 "MOV $dst, #-1\n\t"
9526 "JP,s done\n\t"
9527 "JB,s done\n\t"
9528 "SETNE $dst\n\t"
9529 "MOVZB $dst, $dst\n"
9530 "done:" %}
9531 ins_encode %{
9532 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9533 emit_cmpfp3(_masm, $dst$$Register);
9534 %}
9535 ins_pipe( pipe_slow );
9536 %}
9538 // Compare into -1,0,1 in XMM and memory
9539 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9540 predicate(UseSSE>=2);
9541 match(Set dst (CmpD3 src1 (LoadD src2)));
9542 effect(KILL cr);
9543 ins_cost(275);
9544 format %{ "UCOMISD $src1, $src2\n\t"
9545 "MOV $dst, #-1\n\t"
9546 "JP,s done\n\t"
9547 "JB,s done\n\t"
9548 "SETNE $dst\n\t"
9549 "MOVZB $dst, $dst\n"
9550 "done:" %}
9551 ins_encode %{
9552 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9553 emit_cmpfp3(_masm, $dst$$Register);
9554 %}
9555 ins_pipe( pipe_slow );
9556 %}
9559 instruct subDPR_reg(regDPR dst, regDPR src) %{
9560 predicate (UseSSE <=1);
9561 match(Set dst (SubD dst src));
9563 format %{ "FLD $src\n\t"
9564 "DSUBp $dst,ST" %}
9565 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9566 ins_cost(150);
9567 ins_encode( Push_Reg_DPR(src),
9568 OpcP, RegOpc(dst) );
9569 ins_pipe( fpu_reg_reg );
9570 %}
9572 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9573 predicate (UseSSE <=1);
9574 match(Set dst (RoundDouble (SubD src1 src2)));
9575 ins_cost(250);
9577 format %{ "FLD $src2\n\t"
9578 "DSUB ST,$src1\n\t"
9579 "FSTP_D $dst\t# D-round" %}
9580 opcode(0xD8, 0x5);
9581 ins_encode( Push_Reg_DPR(src2),
9582 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9583 ins_pipe( fpu_mem_reg_reg );
9584 %}
9587 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9588 predicate (UseSSE <=1);
9589 match(Set dst (SubD dst (LoadD src)));
9590 ins_cost(150);
9592 format %{ "FLD $src\n\t"
9593 "DSUBp $dst,ST" %}
9594 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9595 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9596 OpcP, RegOpc(dst) );
9597 ins_pipe( fpu_reg_mem );
9598 %}
9600 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9601 predicate (UseSSE<=1);
9602 match(Set dst (AbsD src));
9603 ins_cost(100);
9604 format %{ "FABS" %}
9605 opcode(0xE1, 0xD9);
9606 ins_encode( OpcS, OpcP );
9607 ins_pipe( fpu_reg_reg );
9608 %}
9610 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9611 predicate(UseSSE<=1);
9612 match(Set dst (NegD src));
9613 ins_cost(100);
9614 format %{ "FCHS" %}
9615 opcode(0xE0, 0xD9);
9616 ins_encode( OpcS, OpcP );
9617 ins_pipe( fpu_reg_reg );
9618 %}
9620 instruct addDPR_reg(regDPR dst, regDPR src) %{
9621 predicate(UseSSE<=1);
9622 match(Set dst (AddD dst src));
9623 format %{ "FLD $src\n\t"
9624 "DADD $dst,ST" %}
9625 size(4);
9626 ins_cost(150);
9627 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9628 ins_encode( Push_Reg_DPR(src),
9629 OpcP, RegOpc(dst) );
9630 ins_pipe( fpu_reg_reg );
9631 %}
9634 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9635 predicate(UseSSE<=1);
9636 match(Set dst (RoundDouble (AddD src1 src2)));
9637 ins_cost(250);
9639 format %{ "FLD $src2\n\t"
9640 "DADD ST,$src1\n\t"
9641 "FSTP_D $dst\t# D-round" %}
9642 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9643 ins_encode( Push_Reg_DPR(src2),
9644 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9645 ins_pipe( fpu_mem_reg_reg );
9646 %}
9649 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9650 predicate(UseSSE<=1);
9651 match(Set dst (AddD dst (LoadD src)));
9652 ins_cost(150);
9654 format %{ "FLD $src\n\t"
9655 "DADDp $dst,ST" %}
9656 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9657 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9658 OpcP, RegOpc(dst) );
9659 ins_pipe( fpu_reg_mem );
9660 %}
9662 // add-to-memory
9663 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9664 predicate(UseSSE<=1);
9665 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9666 ins_cost(150);
9668 format %{ "FLD_D $dst\n\t"
9669 "DADD ST,$src\n\t"
9670 "FST_D $dst" %}
9671 opcode(0xDD, 0x0);
9672 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9673 Opcode(0xD8), RegOpc(src),
9674 set_instruction_start,
9675 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9676 ins_pipe( fpu_reg_mem );
9677 %}
9679 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9680 predicate(UseSSE<=1);
9681 match(Set dst (AddD dst con));
9682 ins_cost(125);
9683 format %{ "FLD1\n\t"
9684 "DADDp $dst,ST" %}
9685 ins_encode %{
9686 __ fld1();
9687 __ faddp($dst$$reg);
9688 %}
9689 ins_pipe(fpu_reg);
9690 %}
9692 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9693 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9694 match(Set dst (AddD dst con));
9695 ins_cost(200);
9696 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9697 "DADDp $dst,ST" %}
9698 ins_encode %{
9699 __ fld_d($constantaddress($con));
9700 __ faddp($dst$$reg);
9701 %}
9702 ins_pipe(fpu_reg_mem);
9703 %}
9705 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9706 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9707 match(Set dst (RoundDouble (AddD src con)));
9708 ins_cost(200);
9709 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9710 "DADD ST,$src\n\t"
9711 "FSTP_D $dst\t# D-round" %}
9712 ins_encode %{
9713 __ fld_d($constantaddress($con));
9714 __ fadd($src$$reg);
9715 __ fstp_d(Address(rsp, $dst$$disp));
9716 %}
9717 ins_pipe(fpu_mem_reg_con);
9718 %}
9720 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9721 predicate(UseSSE<=1);
9722 match(Set dst (MulD dst src));
9723 format %{ "FLD $src\n\t"
9724 "DMULp $dst,ST" %}
9725 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9726 ins_cost(150);
9727 ins_encode( Push_Reg_DPR(src),
9728 OpcP, RegOpc(dst) );
9729 ins_pipe( fpu_reg_reg );
9730 %}
9732 // Strict FP instruction biases argument before multiply then
9733 // biases result to avoid double rounding of subnormals.
9734 //
9735 // scale arg1 by multiplying arg1 by 2^(-15360)
9736 // load arg2
9737 // multiply scaled arg1 by arg2
9738 // rescale product by 2^(15360)
9739 //
9740 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9741 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9742 match(Set dst (MulD dst src));
9743 ins_cost(1); // Select this instruction for all strict FP double multiplies
9745 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9746 "DMULp $dst,ST\n\t"
9747 "FLD $src\n\t"
9748 "DMULp $dst,ST\n\t"
9749 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9750 "DMULp $dst,ST\n\t" %}
9751 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9752 ins_encode( strictfp_bias1(dst),
9753 Push_Reg_DPR(src),
9754 OpcP, RegOpc(dst),
9755 strictfp_bias2(dst) );
9756 ins_pipe( fpu_reg_reg );
9757 %}
9759 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9760 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9761 match(Set dst (MulD dst con));
9762 ins_cost(200);
9763 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9764 "DMULp $dst,ST" %}
9765 ins_encode %{
9766 __ fld_d($constantaddress($con));
9767 __ fmulp($dst$$reg);
9768 %}
9769 ins_pipe(fpu_reg_mem);
9770 %}
9773 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9774 predicate( UseSSE<=1 );
9775 match(Set dst (MulD dst (LoadD src)));
9776 ins_cost(200);
9777 format %{ "FLD_D $src\n\t"
9778 "DMULp $dst,ST" %}
9779 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9780 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9781 OpcP, RegOpc(dst) );
9782 ins_pipe( fpu_reg_mem );
9783 %}
9785 //
9786 // Cisc-alternate to reg-reg multiply
9787 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9788 predicate( UseSSE<=1 );
9789 match(Set dst (MulD src (LoadD mem)));
9790 ins_cost(250);
9791 format %{ "FLD_D $mem\n\t"
9792 "DMUL ST,$src\n\t"
9793 "FSTP_D $dst" %}
9794 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9795 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9796 OpcReg_FPR(src),
9797 Pop_Reg_DPR(dst) );
9798 ins_pipe( fpu_reg_reg_mem );
9799 %}
9802 // MACRO3 -- addDPR a mulDPR
9803 // This instruction is a '2-address' instruction in that the result goes
9804 // back to src2. This eliminates a move from the macro; possibly the
9805 // register allocator will have to add it back (and maybe not).
9806 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9807 predicate( UseSSE<=1 );
9808 match(Set src2 (AddD (MulD src0 src1) src2));
9809 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9810 "DMUL ST,$src1\n\t"
9811 "DADDp $src2,ST" %}
9812 ins_cost(250);
9813 opcode(0xDD); /* LoadD DD /0 */
9814 ins_encode( Push_Reg_FPR(src0),
9815 FMul_ST_reg(src1),
9816 FAddP_reg_ST(src2) );
9817 ins_pipe( fpu_reg_reg_reg );
9818 %}
9821 // MACRO3 -- subDPR a mulDPR
9822 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9823 predicate( UseSSE<=1 );
9824 match(Set src2 (SubD (MulD src0 src1) src2));
9825 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9826 "DMUL ST,$src1\n\t"
9827 "DSUBRp $src2,ST" %}
9828 ins_cost(250);
9829 ins_encode( Push_Reg_FPR(src0),
9830 FMul_ST_reg(src1),
9831 Opcode(0xDE), Opc_plus(0xE0,src2));
9832 ins_pipe( fpu_reg_reg_reg );
9833 %}
9836 instruct divDPR_reg(regDPR dst, regDPR src) %{
9837 predicate( UseSSE<=1 );
9838 match(Set dst (DivD dst src));
9840 format %{ "FLD $src\n\t"
9841 "FDIVp $dst,ST" %}
9842 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9843 ins_cost(150);
9844 ins_encode( Push_Reg_DPR(src),
9845 OpcP, RegOpc(dst) );
9846 ins_pipe( fpu_reg_reg );
9847 %}
9849 // Strict FP instruction biases argument before division then
9850 // biases result, to avoid double rounding of subnormals.
9851 //
9852 // scale dividend by multiplying dividend by 2^(-15360)
9853 // load divisor
9854 // divide scaled dividend by divisor
9855 // rescale quotient by 2^(15360)
9856 //
9857 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9858 predicate (UseSSE<=1);
9859 match(Set dst (DivD dst src));
9860 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9861 ins_cost(01);
9863 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9864 "DMULp $dst,ST\n\t"
9865 "FLD $src\n\t"
9866 "FDIVp $dst,ST\n\t"
9867 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9868 "DMULp $dst,ST\n\t" %}
9869 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9870 ins_encode( strictfp_bias1(dst),
9871 Push_Reg_DPR(src),
9872 OpcP, RegOpc(dst),
9873 strictfp_bias2(dst) );
9874 ins_pipe( fpu_reg_reg );
9875 %}
9877 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9878 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9879 match(Set dst (RoundDouble (DivD src1 src2)));
9881 format %{ "FLD $src1\n\t"
9882 "FDIV ST,$src2\n\t"
9883 "FSTP_D $dst\t# D-round" %}
9884 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9885 ins_encode( Push_Reg_DPR(src1),
9886 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9887 ins_pipe( fpu_mem_reg_reg );
9888 %}
9891 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9892 predicate(UseSSE<=1);
9893 match(Set dst (ModD dst src));
9894 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9896 format %{ "DMOD $dst,$src" %}
9897 ins_cost(250);
9898 ins_encode(Push_Reg_Mod_DPR(dst, src),
9899 emitModDPR(),
9900 Push_Result_Mod_DPR(src),
9901 Pop_Reg_DPR(dst));
9902 ins_pipe( pipe_slow );
9903 %}
9905 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9906 predicate(UseSSE>=2);
9907 match(Set dst (ModD src0 src1));
9908 effect(KILL rax, KILL cr);
9910 format %{ "SUB ESP,8\t # DMOD\n"
9911 "\tMOVSD [ESP+0],$src1\n"
9912 "\tFLD_D [ESP+0]\n"
9913 "\tMOVSD [ESP+0],$src0\n"
9914 "\tFLD_D [ESP+0]\n"
9915 "loop:\tFPREM\n"
9916 "\tFWAIT\n"
9917 "\tFNSTSW AX\n"
9918 "\tSAHF\n"
9919 "\tJP loop\n"
9920 "\tFSTP_D [ESP+0]\n"
9921 "\tMOVSD $dst,[ESP+0]\n"
9922 "\tADD ESP,8\n"
9923 "\tFSTP ST0\t # Restore FPU Stack"
9924 %}
9925 ins_cost(250);
9926 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9927 ins_pipe( pipe_slow );
9928 %}
9930 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9931 predicate (UseSSE<=1);
9932 match(Set dst (SinD src));
9933 ins_cost(1800);
9934 format %{ "DSIN $dst" %}
9935 opcode(0xD9, 0xFE);
9936 ins_encode( OpcP, OpcS );
9937 ins_pipe( pipe_slow );
9938 %}
9940 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9941 predicate (UseSSE>=2);
9942 match(Set dst (SinD dst));
9943 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9944 ins_cost(1800);
9945 format %{ "DSIN $dst" %}
9946 opcode(0xD9, 0xFE);
9947 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9948 ins_pipe( pipe_slow );
9949 %}
9951 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9952 predicate (UseSSE<=1);
9953 match(Set dst (CosD src));
9954 ins_cost(1800);
9955 format %{ "DCOS $dst" %}
9956 opcode(0xD9, 0xFF);
9957 ins_encode( OpcP, OpcS );
9958 ins_pipe( pipe_slow );
9959 %}
9961 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9962 predicate (UseSSE>=2);
9963 match(Set dst (CosD dst));
9964 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9965 ins_cost(1800);
9966 format %{ "DCOS $dst" %}
9967 opcode(0xD9, 0xFF);
9968 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9969 ins_pipe( pipe_slow );
9970 %}
9972 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9973 predicate (UseSSE<=1);
9974 match(Set dst(TanD src));
9975 format %{ "DTAN $dst" %}
9976 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9977 Opcode(0xDD), Opcode(0xD8)); // fstp st
9978 ins_pipe( pipe_slow );
9979 %}
9981 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9982 predicate (UseSSE>=2);
9983 match(Set dst(TanD dst));
9984 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9985 format %{ "DTAN $dst" %}
9986 ins_encode( Push_SrcD(dst),
9987 Opcode(0xD9), Opcode(0xF2), // fptan
9988 Opcode(0xDD), Opcode(0xD8), // fstp st
9989 Push_ResultD(dst) );
9990 ins_pipe( pipe_slow );
9991 %}
9993 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9994 predicate (UseSSE<=1);
9995 match(Set dst(AtanD dst src));
9996 format %{ "DATA $dst,$src" %}
9997 opcode(0xD9, 0xF3);
9998 ins_encode( Push_Reg_DPR(src),
9999 OpcP, OpcS, RegOpc(dst) );
10000 ins_pipe( pipe_slow );
10001 %}
10003 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
10004 predicate (UseSSE>=2);
10005 match(Set dst(AtanD dst src));
10006 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10007 format %{ "DATA $dst,$src" %}
10008 opcode(0xD9, 0xF3);
10009 ins_encode( Push_SrcD(src),
10010 OpcP, OpcS, Push_ResultD(dst) );
10011 ins_pipe( pipe_slow );
10012 %}
10014 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
10015 predicate (UseSSE<=1);
10016 match(Set dst (SqrtD src));
10017 format %{ "DSQRT $dst,$src" %}
10018 opcode(0xFA, 0xD9);
10019 ins_encode( Push_Reg_DPR(src),
10020 OpcS, OpcP, Pop_Reg_DPR(dst) );
10021 ins_pipe( pipe_slow );
10022 %}
10024 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10025 predicate (UseSSE<=1);
10026 match(Set Y (PowD X Y)); // Raise X to the Yth power
10027 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10028 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
10029 ins_encode %{
10030 __ subptr(rsp, 8);
10031 __ fld_s($X$$reg - 1);
10032 __ fast_pow();
10033 __ addptr(rsp, 8);
10034 %}
10035 ins_pipe( pipe_slow );
10036 %}
10038 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10039 predicate (UseSSE>=2);
10040 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10041 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10042 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
10043 ins_encode %{
10044 __ subptr(rsp, 8);
10045 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
10046 __ fld_d(Address(rsp, 0));
10047 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
10048 __ fld_d(Address(rsp, 0));
10049 __ fast_pow();
10050 __ fstp_d(Address(rsp, 0));
10051 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10052 __ addptr(rsp, 8);
10053 %}
10054 ins_pipe( pipe_slow );
10055 %}
10058 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10059 predicate (UseSSE<=1);
10060 match(Set dpr1 (ExpD dpr1));
10061 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10062 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
10063 ins_encode %{
10064 __ fast_exp();
10065 %}
10066 ins_pipe( pipe_slow );
10067 %}
10069 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10070 predicate (UseSSE>=2);
10071 match(Set dst (ExpD src));
10072 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10073 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
10074 ins_encode %{
10075 __ subptr(rsp, 8);
10076 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10077 __ fld_d(Address(rsp, 0));
10078 __ fast_exp();
10079 __ fstp_d(Address(rsp, 0));
10080 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10081 __ addptr(rsp, 8);
10082 %}
10083 ins_pipe( pipe_slow );
10084 %}
10086 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10087 predicate (UseSSE<=1);
10088 // The source Double operand on FPU stack
10089 match(Set dst (Log10D src));
10090 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10091 // fxch ; swap ST(0) with ST(1)
10092 // fyl2x ; compute log_10(2) * log_2(x)
10093 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10094 "FXCH \n\t"
10095 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10096 %}
10097 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10098 Opcode(0xD9), Opcode(0xC9), // fxch
10099 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10101 ins_pipe( pipe_slow );
10102 %}
10104 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10105 predicate (UseSSE>=2);
10106 effect(KILL cr);
10107 match(Set dst (Log10D src));
10108 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10109 // fyl2x ; compute log_10(2) * log_2(x)
10110 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10111 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10112 %}
10113 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10114 Push_SrcD(src),
10115 Opcode(0xD9), Opcode(0xF1), // fyl2x
10116 Push_ResultD(dst));
10118 ins_pipe( pipe_slow );
10119 %}
10121 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10122 predicate (UseSSE<=1);
10123 // The source Double operand on FPU stack
10124 match(Set dst (LogD src));
10125 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10126 // fxch ; swap ST(0) with ST(1)
10127 // fyl2x ; compute log_e(2) * log_2(x)
10128 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10129 "FXCH \n\t"
10130 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10131 %}
10132 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10133 Opcode(0xD9), Opcode(0xC9), // fxch
10134 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10136 ins_pipe( pipe_slow );
10137 %}
10139 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10140 predicate (UseSSE>=2);
10141 effect(KILL cr);
10142 // The source and result Double operands in XMM registers
10143 match(Set dst (LogD src));
10144 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10145 // fyl2x ; compute log_e(2) * log_2(x)
10146 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10147 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10148 %}
10149 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10150 Push_SrcD(src),
10151 Opcode(0xD9), Opcode(0xF1), // fyl2x
10152 Push_ResultD(dst));
10153 ins_pipe( pipe_slow );
10154 %}
10156 //-------------Float Instructions-------------------------------
10157 // Float Math
10159 // Code for float compare:
10160 // fcompp();
10161 // fwait(); fnstsw_ax();
10162 // sahf();
10163 // movl(dst, unordered_result);
10164 // jcc(Assembler::parity, exit);
10165 // movl(dst, less_result);
10166 // jcc(Assembler::below, exit);
10167 // movl(dst, equal_result);
10168 // jcc(Assembler::equal, exit);
10169 // movl(dst, greater_result);
10170 // exit:
10172 // P6 version of float compare, sets condition codes in EFLAGS
10173 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10174 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10175 match(Set cr (CmpF src1 src2));
10176 effect(KILL rax);
10177 ins_cost(150);
10178 format %{ "FLD $src1\n\t"
10179 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10180 "JNP exit\n\t"
10181 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10182 "SAHF\n"
10183 "exit:\tNOP // avoid branch to branch" %}
10184 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10185 ins_encode( Push_Reg_DPR(src1),
10186 OpcP, RegOpc(src2),
10187 cmpF_P6_fixup );
10188 ins_pipe( pipe_slow );
10189 %}
10191 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10192 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10193 match(Set cr (CmpF src1 src2));
10194 ins_cost(100);
10195 format %{ "FLD $src1\n\t"
10196 "FUCOMIP ST,$src2 // P6 instruction" %}
10197 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10198 ins_encode( Push_Reg_DPR(src1),
10199 OpcP, RegOpc(src2));
10200 ins_pipe( pipe_slow );
10201 %}
10204 // Compare & branch
10205 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10206 predicate(UseSSE == 0);
10207 match(Set cr (CmpF src1 src2));
10208 effect(KILL rax);
10209 ins_cost(200);
10210 format %{ "FLD $src1\n\t"
10211 "FCOMp $src2\n\t"
10212 "FNSTSW AX\n\t"
10213 "TEST AX,0x400\n\t"
10214 "JZ,s flags\n\t"
10215 "MOV AH,1\t# unordered treat as LT\n"
10216 "flags:\tSAHF" %}
10217 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10218 ins_encode( Push_Reg_DPR(src1),
10219 OpcP, RegOpc(src2),
10220 fpu_flags);
10221 ins_pipe( pipe_slow );
10222 %}
10224 // Compare vs zero into -1,0,1
10225 instruct cmpFPR_0(eRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10226 predicate(UseSSE == 0);
10227 match(Set dst (CmpF3 src1 zero));
10228 effect(KILL cr, KILL rax);
10229 ins_cost(280);
10230 format %{ "FTSTF $dst,$src1" %}
10231 opcode(0xE4, 0xD9);
10232 ins_encode( Push_Reg_DPR(src1),
10233 OpcS, OpcP, PopFPU,
10234 CmpF_Result(dst));
10235 ins_pipe( pipe_slow );
10236 %}
10238 // Compare into -1,0,1
10239 instruct cmpFPR_reg(eRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10240 predicate(UseSSE == 0);
10241 match(Set dst (CmpF3 src1 src2));
10242 effect(KILL cr, KILL rax);
10243 ins_cost(300);
10244 format %{ "FCMPF $dst,$src1,$src2" %}
10245 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10246 ins_encode( Push_Reg_DPR(src1),
10247 OpcP, RegOpc(src2),
10248 CmpF_Result(dst));
10249 ins_pipe( pipe_slow );
10250 %}
10252 // float compare and set condition codes in EFLAGS by XMM regs
10253 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10254 predicate(UseSSE>=1);
10255 match(Set cr (CmpF src1 src2));
10256 ins_cost(145);
10257 format %{ "UCOMISS $src1,$src2\n\t"
10258 "JNP,s exit\n\t"
10259 "PUSHF\t# saw NaN, set CF\n\t"
10260 "AND [rsp], #0xffffff2b\n\t"
10261 "POPF\n"
10262 "exit:" %}
10263 ins_encode %{
10264 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10265 emit_cmpfp_fixup(_masm);
10266 %}
10267 ins_pipe( pipe_slow );
10268 %}
10270 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10271 predicate(UseSSE>=1);
10272 match(Set cr (CmpF src1 src2));
10273 ins_cost(100);
10274 format %{ "UCOMISS $src1,$src2" %}
10275 ins_encode %{
10276 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10277 %}
10278 ins_pipe( pipe_slow );
10279 %}
10281 // float compare and set condition codes in EFLAGS by XMM regs
10282 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10283 predicate(UseSSE>=1);
10284 match(Set cr (CmpF src1 (LoadF src2)));
10285 ins_cost(165);
10286 format %{ "UCOMISS $src1,$src2\n\t"
10287 "JNP,s exit\n\t"
10288 "PUSHF\t# saw NaN, set CF\n\t"
10289 "AND [rsp], #0xffffff2b\n\t"
10290 "POPF\n"
10291 "exit:" %}
10292 ins_encode %{
10293 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10294 emit_cmpfp_fixup(_masm);
10295 %}
10296 ins_pipe( pipe_slow );
10297 %}
10299 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10300 predicate(UseSSE>=1);
10301 match(Set cr (CmpF src1 (LoadF src2)));
10302 ins_cost(100);
10303 format %{ "UCOMISS $src1,$src2" %}
10304 ins_encode %{
10305 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10306 %}
10307 ins_pipe( pipe_slow );
10308 %}
10310 // Compare into -1,0,1 in XMM
10311 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10312 predicate(UseSSE>=1);
10313 match(Set dst (CmpF3 src1 src2));
10314 effect(KILL cr);
10315 ins_cost(255);
10316 format %{ "UCOMISS $src1, $src2\n\t"
10317 "MOV $dst, #-1\n\t"
10318 "JP,s done\n\t"
10319 "JB,s done\n\t"
10320 "SETNE $dst\n\t"
10321 "MOVZB $dst, $dst\n"
10322 "done:" %}
10323 ins_encode %{
10324 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10325 emit_cmpfp3(_masm, $dst$$Register);
10326 %}
10327 ins_pipe( pipe_slow );
10328 %}
10330 // Compare into -1,0,1 in XMM and memory
10331 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10332 predicate(UseSSE>=1);
10333 match(Set dst (CmpF3 src1 (LoadF src2)));
10334 effect(KILL cr);
10335 ins_cost(275);
10336 format %{ "UCOMISS $src1, $src2\n\t"
10337 "MOV $dst, #-1\n\t"
10338 "JP,s done\n\t"
10339 "JB,s done\n\t"
10340 "SETNE $dst\n\t"
10341 "MOVZB $dst, $dst\n"
10342 "done:" %}
10343 ins_encode %{
10344 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10345 emit_cmpfp3(_masm, $dst$$Register);
10346 %}
10347 ins_pipe( pipe_slow );
10348 %}
10350 // Spill to obtain 24-bit precision
10351 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10352 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10353 match(Set dst (SubF src1 src2));
10355 format %{ "FSUB $dst,$src1 - $src2" %}
10356 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10357 ins_encode( Push_Reg_FPR(src1),
10358 OpcReg_FPR(src2),
10359 Pop_Mem_FPR(dst) );
10360 ins_pipe( fpu_mem_reg_reg );
10361 %}
10362 //
10363 // This instruction does not round to 24-bits
10364 instruct subFPR_reg(regFPR dst, regFPR src) %{
10365 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10366 match(Set dst (SubF dst src));
10368 format %{ "FSUB $dst,$src" %}
10369 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10370 ins_encode( Push_Reg_FPR(src),
10371 OpcP, RegOpc(dst) );
10372 ins_pipe( fpu_reg_reg );
10373 %}
10375 // Spill to obtain 24-bit precision
10376 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10377 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10378 match(Set dst (AddF src1 src2));
10380 format %{ "FADD $dst,$src1,$src2" %}
10381 opcode(0xD8, 0x0); /* D8 C0+i */
10382 ins_encode( Push_Reg_FPR(src2),
10383 OpcReg_FPR(src1),
10384 Pop_Mem_FPR(dst) );
10385 ins_pipe( fpu_mem_reg_reg );
10386 %}
10387 //
10388 // This instruction does not round to 24-bits
10389 instruct addFPR_reg(regFPR dst, regFPR src) %{
10390 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10391 match(Set dst (AddF dst src));
10393 format %{ "FLD $src\n\t"
10394 "FADDp $dst,ST" %}
10395 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10396 ins_encode( Push_Reg_FPR(src),
10397 OpcP, RegOpc(dst) );
10398 ins_pipe( fpu_reg_reg );
10399 %}
10401 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10402 predicate(UseSSE==0);
10403 match(Set dst (AbsF src));
10404 ins_cost(100);
10405 format %{ "FABS" %}
10406 opcode(0xE1, 0xD9);
10407 ins_encode( OpcS, OpcP );
10408 ins_pipe( fpu_reg_reg );
10409 %}
10411 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10412 predicate(UseSSE==0);
10413 match(Set dst (NegF src));
10414 ins_cost(100);
10415 format %{ "FCHS" %}
10416 opcode(0xE0, 0xD9);
10417 ins_encode( OpcS, OpcP );
10418 ins_pipe( fpu_reg_reg );
10419 %}
10421 // Cisc-alternate to addFPR_reg
10422 // Spill to obtain 24-bit precision
10423 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10424 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10425 match(Set dst (AddF src1 (LoadF src2)));
10427 format %{ "FLD $src2\n\t"
10428 "FADD ST,$src1\n\t"
10429 "FSTP_S $dst" %}
10430 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10431 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10432 OpcReg_FPR(src1),
10433 Pop_Mem_FPR(dst) );
10434 ins_pipe( fpu_mem_reg_mem );
10435 %}
10436 //
10437 // Cisc-alternate to addFPR_reg
10438 // This instruction does not round to 24-bits
10439 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10440 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10441 match(Set dst (AddF dst (LoadF src)));
10443 format %{ "FADD $dst,$src" %}
10444 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10445 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10446 OpcP, RegOpc(dst) );
10447 ins_pipe( fpu_reg_mem );
10448 %}
10450 // // Following two instructions for _222_mpegaudio
10451 // Spill to obtain 24-bit precision
10452 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10453 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10454 match(Set dst (AddF src1 src2));
10456 format %{ "FADD $dst,$src1,$src2" %}
10457 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10458 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10459 OpcReg_FPR(src2),
10460 Pop_Mem_FPR(dst) );
10461 ins_pipe( fpu_mem_reg_mem );
10462 %}
10464 // Cisc-spill variant
10465 // Spill to obtain 24-bit precision
10466 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10467 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10468 match(Set dst (AddF src1 (LoadF src2)));
10470 format %{ "FADD $dst,$src1,$src2 cisc" %}
10471 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10472 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10473 set_instruction_start,
10474 OpcP, RMopc_Mem(secondary,src1),
10475 Pop_Mem_FPR(dst) );
10476 ins_pipe( fpu_mem_mem_mem );
10477 %}
10479 // Spill to obtain 24-bit precision
10480 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10481 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10482 match(Set dst (AddF src1 src2));
10484 format %{ "FADD $dst,$src1,$src2" %}
10485 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10486 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10487 set_instruction_start,
10488 OpcP, RMopc_Mem(secondary,src1),
10489 Pop_Mem_FPR(dst) );
10490 ins_pipe( fpu_mem_mem_mem );
10491 %}
10494 // Spill to obtain 24-bit precision
10495 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10496 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10497 match(Set dst (AddF src con));
10498 format %{ "FLD $src\n\t"
10499 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10500 "FSTP_S $dst" %}
10501 ins_encode %{
10502 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10503 __ fadd_s($constantaddress($con));
10504 __ fstp_s(Address(rsp, $dst$$disp));
10505 %}
10506 ins_pipe(fpu_mem_reg_con);
10507 %}
10508 //
10509 // This instruction does not round to 24-bits
10510 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10511 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10512 match(Set dst (AddF src con));
10513 format %{ "FLD $src\n\t"
10514 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10515 "FSTP $dst" %}
10516 ins_encode %{
10517 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10518 __ fadd_s($constantaddress($con));
10519 __ fstp_d($dst$$reg);
10520 %}
10521 ins_pipe(fpu_reg_reg_con);
10522 %}
10524 // Spill to obtain 24-bit precision
10525 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10526 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10527 match(Set dst (MulF src1 src2));
10529 format %{ "FLD $src1\n\t"
10530 "FMUL $src2\n\t"
10531 "FSTP_S $dst" %}
10532 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10533 ins_encode( Push_Reg_FPR(src1),
10534 OpcReg_FPR(src2),
10535 Pop_Mem_FPR(dst) );
10536 ins_pipe( fpu_mem_reg_reg );
10537 %}
10538 //
10539 // This instruction does not round to 24-bits
10540 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10541 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10542 match(Set dst (MulF src1 src2));
10544 format %{ "FLD $src1\n\t"
10545 "FMUL $src2\n\t"
10546 "FSTP_S $dst" %}
10547 opcode(0xD8, 0x1); /* D8 C8+i */
10548 ins_encode( Push_Reg_FPR(src2),
10549 OpcReg_FPR(src1),
10550 Pop_Reg_FPR(dst) );
10551 ins_pipe( fpu_reg_reg_reg );
10552 %}
10555 // Spill to obtain 24-bit precision
10556 // Cisc-alternate to reg-reg multiply
10557 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10558 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10559 match(Set dst (MulF src1 (LoadF src2)));
10561 format %{ "FLD_S $src2\n\t"
10562 "FMUL $src1\n\t"
10563 "FSTP_S $dst" %}
10564 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10565 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10566 OpcReg_FPR(src1),
10567 Pop_Mem_FPR(dst) );
10568 ins_pipe( fpu_mem_reg_mem );
10569 %}
10570 //
10571 // This instruction does not round to 24-bits
10572 // Cisc-alternate to reg-reg multiply
10573 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10574 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10575 match(Set dst (MulF src1 (LoadF src2)));
10577 format %{ "FMUL $dst,$src1,$src2" %}
10578 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10579 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10580 OpcReg_FPR(src1),
10581 Pop_Reg_FPR(dst) );
10582 ins_pipe( fpu_reg_reg_mem );
10583 %}
10585 // Spill to obtain 24-bit precision
10586 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10587 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10588 match(Set dst (MulF src1 src2));
10590 format %{ "FMUL $dst,$src1,$src2" %}
10591 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10592 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10593 set_instruction_start,
10594 OpcP, RMopc_Mem(secondary,src1),
10595 Pop_Mem_FPR(dst) );
10596 ins_pipe( fpu_mem_mem_mem );
10597 %}
10599 // Spill to obtain 24-bit precision
10600 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10601 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10602 match(Set dst (MulF src con));
10604 format %{ "FLD $src\n\t"
10605 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10606 "FSTP_S $dst" %}
10607 ins_encode %{
10608 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10609 __ fmul_s($constantaddress($con));
10610 __ fstp_s(Address(rsp, $dst$$disp));
10611 %}
10612 ins_pipe(fpu_mem_reg_con);
10613 %}
10614 //
10615 // This instruction does not round to 24-bits
10616 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10617 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10618 match(Set dst (MulF src con));
10620 format %{ "FLD $src\n\t"
10621 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10622 "FSTP $dst" %}
10623 ins_encode %{
10624 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10625 __ fmul_s($constantaddress($con));
10626 __ fstp_d($dst$$reg);
10627 %}
10628 ins_pipe(fpu_reg_reg_con);
10629 %}
10632 //
10633 // MACRO1 -- subsume unshared load into mulFPR
10634 // This instruction does not round to 24-bits
10635 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10636 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10637 match(Set dst (MulF (LoadF mem1) src));
10639 format %{ "FLD $mem1 ===MACRO1===\n\t"
10640 "FMUL ST,$src\n\t"
10641 "FSTP $dst" %}
10642 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10643 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10644 OpcReg_FPR(src),
10645 Pop_Reg_FPR(dst) );
10646 ins_pipe( fpu_reg_reg_mem );
10647 %}
10648 //
10649 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10650 // This instruction does not round to 24-bits
10651 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10652 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10653 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10654 ins_cost(95);
10656 format %{ "FLD $mem1 ===MACRO2===\n\t"
10657 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10658 "FADD ST,$src2\n\t"
10659 "FSTP $dst" %}
10660 opcode(0xD9); /* LoadF D9 /0 */
10661 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10662 FMul_ST_reg(src1),
10663 FAdd_ST_reg(src2),
10664 Pop_Reg_FPR(dst) );
10665 ins_pipe( fpu_reg_mem_reg_reg );
10666 %}
10668 // MACRO3 -- addFPR a mulFPR
10669 // This instruction does not round to 24-bits. It is a '2-address'
10670 // instruction in that the result goes back to src2. This eliminates
10671 // a move from the macro; possibly the register allocator will have
10672 // to add it back (and maybe not).
10673 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10674 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10675 match(Set src2 (AddF (MulF src0 src1) src2));
10677 format %{ "FLD $src0 ===MACRO3===\n\t"
10678 "FMUL ST,$src1\n\t"
10679 "FADDP $src2,ST" %}
10680 opcode(0xD9); /* LoadF D9 /0 */
10681 ins_encode( Push_Reg_FPR(src0),
10682 FMul_ST_reg(src1),
10683 FAddP_reg_ST(src2) );
10684 ins_pipe( fpu_reg_reg_reg );
10685 %}
10687 // MACRO4 -- divFPR subFPR
10688 // This instruction does not round to 24-bits
10689 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10690 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10691 match(Set dst (DivF (SubF src2 src1) src3));
10693 format %{ "FLD $src2 ===MACRO4===\n\t"
10694 "FSUB ST,$src1\n\t"
10695 "FDIV ST,$src3\n\t"
10696 "FSTP $dst" %}
10697 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10698 ins_encode( Push_Reg_FPR(src2),
10699 subFPR_divFPR_encode(src1,src3),
10700 Pop_Reg_FPR(dst) );
10701 ins_pipe( fpu_reg_reg_reg_reg );
10702 %}
10704 // Spill to obtain 24-bit precision
10705 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10706 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10707 match(Set dst (DivF src1 src2));
10709 format %{ "FDIV $dst,$src1,$src2" %}
10710 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10711 ins_encode( Push_Reg_FPR(src1),
10712 OpcReg_FPR(src2),
10713 Pop_Mem_FPR(dst) );
10714 ins_pipe( fpu_mem_reg_reg );
10715 %}
10716 //
10717 // This instruction does not round to 24-bits
10718 instruct divFPR_reg(regFPR dst, regFPR src) %{
10719 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10720 match(Set dst (DivF dst src));
10722 format %{ "FDIV $dst,$src" %}
10723 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10724 ins_encode( Push_Reg_FPR(src),
10725 OpcP, RegOpc(dst) );
10726 ins_pipe( fpu_reg_reg );
10727 %}
10730 // Spill to obtain 24-bit precision
10731 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10732 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10733 match(Set dst (ModF src1 src2));
10734 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10736 format %{ "FMOD $dst,$src1,$src2" %}
10737 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10738 emitModDPR(),
10739 Push_Result_Mod_DPR(src2),
10740 Pop_Mem_FPR(dst));
10741 ins_pipe( pipe_slow );
10742 %}
10743 //
10744 // This instruction does not round to 24-bits
10745 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10746 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10747 match(Set dst (ModF dst src));
10748 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10750 format %{ "FMOD $dst,$src" %}
10751 ins_encode(Push_Reg_Mod_DPR(dst, src),
10752 emitModDPR(),
10753 Push_Result_Mod_DPR(src),
10754 Pop_Reg_FPR(dst));
10755 ins_pipe( pipe_slow );
10756 %}
10758 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10759 predicate(UseSSE>=1);
10760 match(Set dst (ModF src0 src1));
10761 effect(KILL rax, KILL cr);
10762 format %{ "SUB ESP,4\t # FMOD\n"
10763 "\tMOVSS [ESP+0],$src1\n"
10764 "\tFLD_S [ESP+0]\n"
10765 "\tMOVSS [ESP+0],$src0\n"
10766 "\tFLD_S [ESP+0]\n"
10767 "loop:\tFPREM\n"
10768 "\tFWAIT\n"
10769 "\tFNSTSW AX\n"
10770 "\tSAHF\n"
10771 "\tJP loop\n"
10772 "\tFSTP_S [ESP+0]\n"
10773 "\tMOVSS $dst,[ESP+0]\n"
10774 "\tADD ESP,4\n"
10775 "\tFSTP ST0\t # Restore FPU Stack"
10776 %}
10777 ins_cost(250);
10778 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10779 ins_pipe( pipe_slow );
10780 %}
10783 //----------Arithmetic Conversion Instructions---------------------------------
10784 // The conversions operations are all Alpha sorted. Please keep it that way!
10786 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10787 predicate(UseSSE==0);
10788 match(Set dst (RoundFloat src));
10789 ins_cost(125);
10790 format %{ "FST_S $dst,$src\t# F-round" %}
10791 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10792 ins_pipe( fpu_mem_reg );
10793 %}
10795 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10796 predicate(UseSSE<=1);
10797 match(Set dst (RoundDouble src));
10798 ins_cost(125);
10799 format %{ "FST_D $dst,$src\t# D-round" %}
10800 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10801 ins_pipe( fpu_mem_reg );
10802 %}
10804 // Force rounding to 24-bit precision and 6-bit exponent
10805 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10806 predicate(UseSSE==0);
10807 match(Set dst (ConvD2F src));
10808 format %{ "FST_S $dst,$src\t# F-round" %}
10809 expand %{
10810 roundFloat_mem_reg(dst,src);
10811 %}
10812 %}
10814 // Force rounding to 24-bit precision and 6-bit exponent
10815 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10816 predicate(UseSSE==1);
10817 match(Set dst (ConvD2F src));
10818 effect( KILL cr );
10819 format %{ "SUB ESP,4\n\t"
10820 "FST_S [ESP],$src\t# F-round\n\t"
10821 "MOVSS $dst,[ESP]\n\t"
10822 "ADD ESP,4" %}
10823 ins_encode %{
10824 __ subptr(rsp, 4);
10825 if ($src$$reg != FPR1L_enc) {
10826 __ fld_s($src$$reg-1);
10827 __ fstp_s(Address(rsp, 0));
10828 } else {
10829 __ fst_s(Address(rsp, 0));
10830 }
10831 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10832 __ addptr(rsp, 4);
10833 %}
10834 ins_pipe( pipe_slow );
10835 %}
10837 // Force rounding double precision to single precision
10838 instruct convD2F_reg(regF dst, regD src) %{
10839 predicate(UseSSE>=2);
10840 match(Set dst (ConvD2F src));
10841 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10842 ins_encode %{
10843 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10844 %}
10845 ins_pipe( pipe_slow );
10846 %}
10848 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10849 predicate(UseSSE==0);
10850 match(Set dst (ConvF2D src));
10851 format %{ "FST_S $dst,$src\t# D-round" %}
10852 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10853 ins_pipe( fpu_reg_reg );
10854 %}
10856 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10857 predicate(UseSSE==1);
10858 match(Set dst (ConvF2D src));
10859 format %{ "FST_D $dst,$src\t# D-round" %}
10860 expand %{
10861 roundDouble_mem_reg(dst,src);
10862 %}
10863 %}
10865 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10866 predicate(UseSSE==1);
10867 match(Set dst (ConvF2D src));
10868 effect( KILL cr );
10869 format %{ "SUB ESP,4\n\t"
10870 "MOVSS [ESP] $src\n\t"
10871 "FLD_S [ESP]\n\t"
10872 "ADD ESP,4\n\t"
10873 "FSTP $dst\t# D-round" %}
10874 ins_encode %{
10875 __ subptr(rsp, 4);
10876 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10877 __ fld_s(Address(rsp, 0));
10878 __ addptr(rsp, 4);
10879 __ fstp_d($dst$$reg);
10880 %}
10881 ins_pipe( pipe_slow );
10882 %}
10884 instruct convF2D_reg(regD dst, regF src) %{
10885 predicate(UseSSE>=2);
10886 match(Set dst (ConvF2D src));
10887 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10888 ins_encode %{
10889 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10890 %}
10891 ins_pipe( pipe_slow );
10892 %}
10894 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10895 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10896 predicate(UseSSE<=1);
10897 match(Set dst (ConvD2I src));
10898 effect( KILL tmp, KILL cr );
10899 format %{ "FLD $src\t# Convert double to int \n\t"
10900 "FLDCW trunc mode\n\t"
10901 "SUB ESP,4\n\t"
10902 "FISTp [ESP + #0]\n\t"
10903 "FLDCW std/24-bit mode\n\t"
10904 "POP EAX\n\t"
10905 "CMP EAX,0x80000000\n\t"
10906 "JNE,s fast\n\t"
10907 "FLD_D $src\n\t"
10908 "CALL d2i_wrapper\n"
10909 "fast:" %}
10910 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10911 ins_pipe( pipe_slow );
10912 %}
10914 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10915 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10916 predicate(UseSSE>=2);
10917 match(Set dst (ConvD2I src));
10918 effect( KILL tmp, KILL cr );
10919 format %{ "CVTTSD2SI $dst, $src\n\t"
10920 "CMP $dst,0x80000000\n\t"
10921 "JNE,s fast\n\t"
10922 "SUB ESP, 8\n\t"
10923 "MOVSD [ESP], $src\n\t"
10924 "FLD_D [ESP]\n\t"
10925 "ADD ESP, 8\n\t"
10926 "CALL d2i_wrapper\n"
10927 "fast:" %}
10928 ins_encode %{
10929 Label fast;
10930 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10931 __ cmpl($dst$$Register, 0x80000000);
10932 __ jccb(Assembler::notEqual, fast);
10933 __ subptr(rsp, 8);
10934 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10935 __ fld_d(Address(rsp, 0));
10936 __ addptr(rsp, 8);
10937 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10938 __ bind(fast);
10939 %}
10940 ins_pipe( pipe_slow );
10941 %}
10943 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10944 predicate(UseSSE<=1);
10945 match(Set dst (ConvD2L src));
10946 effect( KILL cr );
10947 format %{ "FLD $src\t# Convert double to long\n\t"
10948 "FLDCW trunc mode\n\t"
10949 "SUB ESP,8\n\t"
10950 "FISTp [ESP + #0]\n\t"
10951 "FLDCW std/24-bit mode\n\t"
10952 "POP EAX\n\t"
10953 "POP EDX\n\t"
10954 "CMP EDX,0x80000000\n\t"
10955 "JNE,s fast\n\t"
10956 "TEST EAX,EAX\n\t"
10957 "JNE,s fast\n\t"
10958 "FLD $src\n\t"
10959 "CALL d2l_wrapper\n"
10960 "fast:" %}
10961 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
10962 ins_pipe( pipe_slow );
10963 %}
10965 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10966 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10967 predicate (UseSSE>=2);
10968 match(Set dst (ConvD2L src));
10969 effect( KILL cr );
10970 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10971 "MOVSD [ESP],$src\n\t"
10972 "FLD_D [ESP]\n\t"
10973 "FLDCW trunc mode\n\t"
10974 "FISTp [ESP + #0]\n\t"
10975 "FLDCW std/24-bit mode\n\t"
10976 "POP EAX\n\t"
10977 "POP EDX\n\t"
10978 "CMP EDX,0x80000000\n\t"
10979 "JNE,s fast\n\t"
10980 "TEST EAX,EAX\n\t"
10981 "JNE,s fast\n\t"
10982 "SUB ESP,8\n\t"
10983 "MOVSD [ESP],$src\n\t"
10984 "FLD_D [ESP]\n\t"
10985 "ADD ESP,8\n\t"
10986 "CALL d2l_wrapper\n"
10987 "fast:" %}
10988 ins_encode %{
10989 Label fast;
10990 __ subptr(rsp, 8);
10991 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10992 __ fld_d(Address(rsp, 0));
10993 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10994 __ fistp_d(Address(rsp, 0));
10995 // Restore the rounding mode, mask the exception
10996 if (Compile::current()->in_24_bit_fp_mode()) {
10997 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10998 } else {
10999 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11000 }
11001 // Load the converted long, adjust CPU stack
11002 __ pop(rax);
11003 __ pop(rdx);
11004 __ cmpl(rdx, 0x80000000);
11005 __ jccb(Assembler::notEqual, fast);
11006 __ testl(rax, rax);
11007 __ jccb(Assembler::notEqual, fast);
11008 __ subptr(rsp, 8);
11009 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11010 __ fld_d(Address(rsp, 0));
11011 __ addptr(rsp, 8);
11012 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11013 __ bind(fast);
11014 %}
11015 ins_pipe( pipe_slow );
11016 %}
11018 // Convert a double to an int. Java semantics require we do complex
11019 // manglations in the corner cases. So we set the rounding mode to
11020 // 'zero', store the darned double down as an int, and reset the
11021 // rounding mode to 'nearest'. The hardware stores a flag value down
11022 // if we would overflow or converted a NAN; we check for this and
11023 // and go the slow path if needed.
11024 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
11025 predicate(UseSSE==0);
11026 match(Set dst (ConvF2I src));
11027 effect( KILL tmp, KILL cr );
11028 format %{ "FLD $src\t# Convert float to int \n\t"
11029 "FLDCW trunc mode\n\t"
11030 "SUB ESP,4\n\t"
11031 "FISTp [ESP + #0]\n\t"
11032 "FLDCW std/24-bit mode\n\t"
11033 "POP EAX\n\t"
11034 "CMP EAX,0x80000000\n\t"
11035 "JNE,s fast\n\t"
11036 "FLD $src\n\t"
11037 "CALL d2i_wrapper\n"
11038 "fast:" %}
11039 // DPR2I_encoding works for FPR2I
11040 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
11041 ins_pipe( pipe_slow );
11042 %}
11044 // Convert a float in xmm to an int reg.
11045 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11046 predicate(UseSSE>=1);
11047 match(Set dst (ConvF2I src));
11048 effect( KILL tmp, KILL cr );
11049 format %{ "CVTTSS2SI $dst, $src\n\t"
11050 "CMP $dst,0x80000000\n\t"
11051 "JNE,s fast\n\t"
11052 "SUB ESP, 4\n\t"
11053 "MOVSS [ESP], $src\n\t"
11054 "FLD [ESP]\n\t"
11055 "ADD ESP, 4\n\t"
11056 "CALL d2i_wrapper\n"
11057 "fast:" %}
11058 ins_encode %{
11059 Label fast;
11060 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11061 __ cmpl($dst$$Register, 0x80000000);
11062 __ jccb(Assembler::notEqual, fast);
11063 __ subptr(rsp, 4);
11064 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11065 __ fld_s(Address(rsp, 0));
11066 __ addptr(rsp, 4);
11067 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11068 __ bind(fast);
11069 %}
11070 ins_pipe( pipe_slow );
11071 %}
11073 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11074 predicate(UseSSE==0);
11075 match(Set dst (ConvF2L src));
11076 effect( KILL cr );
11077 format %{ "FLD $src\t# Convert float to long\n\t"
11078 "FLDCW trunc mode\n\t"
11079 "SUB ESP,8\n\t"
11080 "FISTp [ESP + #0]\n\t"
11081 "FLDCW std/24-bit mode\n\t"
11082 "POP EAX\n\t"
11083 "POP EDX\n\t"
11084 "CMP EDX,0x80000000\n\t"
11085 "JNE,s fast\n\t"
11086 "TEST EAX,EAX\n\t"
11087 "JNE,s fast\n\t"
11088 "FLD $src\n\t"
11089 "CALL d2l_wrapper\n"
11090 "fast:" %}
11091 // DPR2L_encoding works for FPR2L
11092 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11093 ins_pipe( pipe_slow );
11094 %}
11096 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11097 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11098 predicate (UseSSE>=1);
11099 match(Set dst (ConvF2L src));
11100 effect( KILL cr );
11101 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11102 "MOVSS [ESP],$src\n\t"
11103 "FLD_S [ESP]\n\t"
11104 "FLDCW trunc mode\n\t"
11105 "FISTp [ESP + #0]\n\t"
11106 "FLDCW std/24-bit mode\n\t"
11107 "POP EAX\n\t"
11108 "POP EDX\n\t"
11109 "CMP EDX,0x80000000\n\t"
11110 "JNE,s fast\n\t"
11111 "TEST EAX,EAX\n\t"
11112 "JNE,s fast\n\t"
11113 "SUB ESP,4\t# Convert float to long\n\t"
11114 "MOVSS [ESP],$src\n\t"
11115 "FLD_S [ESP]\n\t"
11116 "ADD ESP,4\n\t"
11117 "CALL d2l_wrapper\n"
11118 "fast:" %}
11119 ins_encode %{
11120 Label fast;
11121 __ subptr(rsp, 8);
11122 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11123 __ fld_s(Address(rsp, 0));
11124 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11125 __ fistp_d(Address(rsp, 0));
11126 // Restore the rounding mode, mask the exception
11127 if (Compile::current()->in_24_bit_fp_mode()) {
11128 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11129 } else {
11130 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11131 }
11132 // Load the converted long, adjust CPU stack
11133 __ pop(rax);
11134 __ pop(rdx);
11135 __ cmpl(rdx, 0x80000000);
11136 __ jccb(Assembler::notEqual, fast);
11137 __ testl(rax, rax);
11138 __ jccb(Assembler::notEqual, fast);
11139 __ subptr(rsp, 4);
11140 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11141 __ fld_s(Address(rsp, 0));
11142 __ addptr(rsp, 4);
11143 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11144 __ bind(fast);
11145 %}
11146 ins_pipe( pipe_slow );
11147 %}
11149 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11150 predicate( UseSSE<=1 );
11151 match(Set dst (ConvI2D src));
11152 format %{ "FILD $src\n\t"
11153 "FSTP $dst" %}
11154 opcode(0xDB, 0x0); /* DB /0 */
11155 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11156 ins_pipe( fpu_reg_mem );
11157 %}
11159 instruct convI2D_reg(regD dst, eRegI src) %{
11160 predicate( UseSSE>=2 && !UseXmmI2D );
11161 match(Set dst (ConvI2D src));
11162 format %{ "CVTSI2SD $dst,$src" %}
11163 ins_encode %{
11164 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11165 %}
11166 ins_pipe( pipe_slow );
11167 %}
11169 instruct convI2D_mem(regD dst, memory mem) %{
11170 predicate( UseSSE>=2 );
11171 match(Set dst (ConvI2D (LoadI mem)));
11172 format %{ "CVTSI2SD $dst,$mem" %}
11173 ins_encode %{
11174 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11175 %}
11176 ins_pipe( pipe_slow );
11177 %}
11179 instruct convXI2D_reg(regD dst, eRegI src)
11180 %{
11181 predicate( UseSSE>=2 && UseXmmI2D );
11182 match(Set dst (ConvI2D src));
11184 format %{ "MOVD $dst,$src\n\t"
11185 "CVTDQ2PD $dst,$dst\t# i2d" %}
11186 ins_encode %{
11187 __ movdl($dst$$XMMRegister, $src$$Register);
11188 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11189 %}
11190 ins_pipe(pipe_slow); // XXX
11191 %}
11193 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11194 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11195 match(Set dst (ConvI2D (LoadI mem)));
11196 format %{ "FILD $mem\n\t"
11197 "FSTP $dst" %}
11198 opcode(0xDB); /* DB /0 */
11199 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11200 Pop_Reg_DPR(dst));
11201 ins_pipe( fpu_reg_mem );
11202 %}
11204 // Convert a byte to a float; no rounding step needed.
11205 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11206 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11207 match(Set dst (ConvI2F src));
11208 format %{ "FILD $src\n\t"
11209 "FSTP $dst" %}
11211 opcode(0xDB, 0x0); /* DB /0 */
11212 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11213 ins_pipe( fpu_reg_mem );
11214 %}
11216 // In 24-bit mode, force exponent rounding by storing back out
11217 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11218 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11219 match(Set dst (ConvI2F src));
11220 ins_cost(200);
11221 format %{ "FILD $src\n\t"
11222 "FSTP_S $dst" %}
11223 opcode(0xDB, 0x0); /* DB /0 */
11224 ins_encode( Push_Mem_I(src),
11225 Pop_Mem_FPR(dst));
11226 ins_pipe( fpu_mem_mem );
11227 %}
11229 // In 24-bit mode, force exponent rounding by storing back out
11230 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11231 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11232 match(Set dst (ConvI2F (LoadI mem)));
11233 ins_cost(200);
11234 format %{ "FILD $mem\n\t"
11235 "FSTP_S $dst" %}
11236 opcode(0xDB); /* DB /0 */
11237 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11238 Pop_Mem_FPR(dst));
11239 ins_pipe( fpu_mem_mem );
11240 %}
11242 // This instruction does not round to 24-bits
11243 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11244 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11245 match(Set dst (ConvI2F src));
11246 format %{ "FILD $src\n\t"
11247 "FSTP $dst" %}
11248 opcode(0xDB, 0x0); /* DB /0 */
11249 ins_encode( Push_Mem_I(src),
11250 Pop_Reg_FPR(dst));
11251 ins_pipe( fpu_reg_mem );
11252 %}
11254 // This instruction does not round to 24-bits
11255 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11256 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11257 match(Set dst (ConvI2F (LoadI mem)));
11258 format %{ "FILD $mem\n\t"
11259 "FSTP $dst" %}
11260 opcode(0xDB); /* DB /0 */
11261 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11262 Pop_Reg_FPR(dst));
11263 ins_pipe( fpu_reg_mem );
11264 %}
11266 // Convert an int to a float in xmm; no rounding step needed.
11267 instruct convI2F_reg(regF dst, eRegI src) %{
11268 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11269 match(Set dst (ConvI2F src));
11270 format %{ "CVTSI2SS $dst, $src" %}
11271 ins_encode %{
11272 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11273 %}
11274 ins_pipe( pipe_slow );
11275 %}
11277 instruct convXI2F_reg(regF dst, eRegI src)
11278 %{
11279 predicate( UseSSE>=2 && UseXmmI2F );
11280 match(Set dst (ConvI2F src));
11282 format %{ "MOVD $dst,$src\n\t"
11283 "CVTDQ2PS $dst,$dst\t# i2f" %}
11284 ins_encode %{
11285 __ movdl($dst$$XMMRegister, $src$$Register);
11286 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11287 %}
11288 ins_pipe(pipe_slow); // XXX
11289 %}
11291 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
11292 match(Set dst (ConvI2L src));
11293 effect(KILL cr);
11294 ins_cost(375);
11295 format %{ "MOV $dst.lo,$src\n\t"
11296 "MOV $dst.hi,$src\n\t"
11297 "SAR $dst.hi,31" %}
11298 ins_encode(convert_int_long(dst,src));
11299 ins_pipe( ialu_reg_reg_long );
11300 %}
11302 // Zero-extend convert int to long
11303 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
11304 match(Set dst (AndL (ConvI2L src) mask) );
11305 effect( KILL flags );
11306 ins_cost(250);
11307 format %{ "MOV $dst.lo,$src\n\t"
11308 "XOR $dst.hi,$dst.hi" %}
11309 opcode(0x33); // XOR
11310 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11311 ins_pipe( ialu_reg_reg_long );
11312 %}
11314 // Zero-extend long
11315 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11316 match(Set dst (AndL src mask) );
11317 effect( KILL flags );
11318 ins_cost(250);
11319 format %{ "MOV $dst.lo,$src.lo\n\t"
11320 "XOR $dst.hi,$dst.hi\n\t" %}
11321 opcode(0x33); // XOR
11322 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11323 ins_pipe( ialu_reg_reg_long );
11324 %}
11326 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11327 predicate (UseSSE<=1);
11328 match(Set dst (ConvL2D src));
11329 effect( KILL cr );
11330 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11331 "PUSH $src.lo\n\t"
11332 "FILD ST,[ESP + #0]\n\t"
11333 "ADD ESP,8\n\t"
11334 "FSTP_D $dst\t# D-round" %}
11335 opcode(0xDF, 0x5); /* DF /5 */
11336 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11337 ins_pipe( pipe_slow );
11338 %}
11340 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11341 predicate (UseSSE>=2);
11342 match(Set dst (ConvL2D src));
11343 effect( KILL cr );
11344 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11345 "PUSH $src.lo\n\t"
11346 "FILD_D [ESP]\n\t"
11347 "FSTP_D [ESP]\n\t"
11348 "MOVSD $dst,[ESP]\n\t"
11349 "ADD ESP,8" %}
11350 opcode(0xDF, 0x5); /* DF /5 */
11351 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11352 ins_pipe( pipe_slow );
11353 %}
11355 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11356 predicate (UseSSE>=1);
11357 match(Set dst (ConvL2F src));
11358 effect( KILL cr );
11359 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11360 "PUSH $src.lo\n\t"
11361 "FILD_D [ESP]\n\t"
11362 "FSTP_S [ESP]\n\t"
11363 "MOVSS $dst,[ESP]\n\t"
11364 "ADD ESP,8" %}
11365 opcode(0xDF, 0x5); /* DF /5 */
11366 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11367 ins_pipe( pipe_slow );
11368 %}
11370 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11371 match(Set dst (ConvL2F src));
11372 effect( KILL cr );
11373 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11374 "PUSH $src.lo\n\t"
11375 "FILD ST,[ESP + #0]\n\t"
11376 "ADD ESP,8\n\t"
11377 "FSTP_S $dst\t# F-round" %}
11378 opcode(0xDF, 0x5); /* DF /5 */
11379 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11380 ins_pipe( pipe_slow );
11381 %}
11383 instruct convL2I_reg( eRegI dst, eRegL src ) %{
11384 match(Set dst (ConvL2I src));
11385 effect( DEF dst, USE src );
11386 format %{ "MOV $dst,$src.lo" %}
11387 ins_encode(enc_CopyL_Lo(dst,src));
11388 ins_pipe( ialu_reg_reg );
11389 %}
11392 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
11393 match(Set dst (MoveF2I src));
11394 effect( DEF dst, USE src );
11395 ins_cost(100);
11396 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11397 ins_encode %{
11398 __ movl($dst$$Register, Address(rsp, $src$$disp));
11399 %}
11400 ins_pipe( ialu_reg_mem );
11401 %}
11403 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11404 predicate(UseSSE==0);
11405 match(Set dst (MoveF2I src));
11406 effect( DEF dst, USE src );
11408 ins_cost(125);
11409 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11410 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11411 ins_pipe( fpu_mem_reg );
11412 %}
11414 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11415 predicate(UseSSE>=1);
11416 match(Set dst (MoveF2I src));
11417 effect( DEF dst, USE src );
11419 ins_cost(95);
11420 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11421 ins_encode %{
11422 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11423 %}
11424 ins_pipe( pipe_slow );
11425 %}
11427 instruct MoveF2I_reg_reg_sse(eRegI dst, regF src) %{
11428 predicate(UseSSE>=2);
11429 match(Set dst (MoveF2I src));
11430 effect( DEF dst, USE src );
11431 ins_cost(85);
11432 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11433 ins_encode %{
11434 __ movdl($dst$$Register, $src$$XMMRegister);
11435 %}
11436 ins_pipe( pipe_slow );
11437 %}
11439 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
11440 match(Set dst (MoveI2F src));
11441 effect( DEF dst, USE src );
11443 ins_cost(100);
11444 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11445 ins_encode %{
11446 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11447 %}
11448 ins_pipe( ialu_mem_reg );
11449 %}
11452 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11453 predicate(UseSSE==0);
11454 match(Set dst (MoveI2F src));
11455 effect(DEF dst, USE src);
11457 ins_cost(125);
11458 format %{ "FLD_S $src\n\t"
11459 "FSTP $dst\t# MoveI2F_stack_reg" %}
11460 opcode(0xD9); /* D9 /0, FLD m32real */
11461 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11462 Pop_Reg_FPR(dst) );
11463 ins_pipe( fpu_reg_mem );
11464 %}
11466 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11467 predicate(UseSSE>=1);
11468 match(Set dst (MoveI2F src));
11469 effect( DEF dst, USE src );
11471 ins_cost(95);
11472 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11473 ins_encode %{
11474 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11475 %}
11476 ins_pipe( pipe_slow );
11477 %}
11479 instruct MoveI2F_reg_reg_sse(regF dst, eRegI src) %{
11480 predicate(UseSSE>=2);
11481 match(Set dst (MoveI2F src));
11482 effect( DEF dst, USE src );
11484 ins_cost(85);
11485 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11486 ins_encode %{
11487 __ movdl($dst$$XMMRegister, $src$$Register);
11488 %}
11489 ins_pipe( pipe_slow );
11490 %}
11492 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11493 match(Set dst (MoveD2L src));
11494 effect(DEF dst, USE src);
11496 ins_cost(250);
11497 format %{ "MOV $dst.lo,$src\n\t"
11498 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11499 opcode(0x8B, 0x8B);
11500 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11501 ins_pipe( ialu_mem_long_reg );
11502 %}
11504 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11505 predicate(UseSSE<=1);
11506 match(Set dst (MoveD2L src));
11507 effect(DEF dst, USE src);
11509 ins_cost(125);
11510 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11511 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11512 ins_pipe( fpu_mem_reg );
11513 %}
11515 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11516 predicate(UseSSE>=2);
11517 match(Set dst (MoveD2L src));
11518 effect(DEF dst, USE src);
11519 ins_cost(95);
11520 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11521 ins_encode %{
11522 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11523 %}
11524 ins_pipe( pipe_slow );
11525 %}
11527 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11528 predicate(UseSSE>=2);
11529 match(Set dst (MoveD2L src));
11530 effect(DEF dst, USE src, TEMP tmp);
11531 ins_cost(85);
11532 format %{ "MOVD $dst.lo,$src\n\t"
11533 "PSHUFLW $tmp,$src,0x4E\n\t"
11534 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11535 ins_encode %{
11536 __ movdl($dst$$Register, $src$$XMMRegister);
11537 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11538 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11539 %}
11540 ins_pipe( pipe_slow );
11541 %}
11543 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11544 match(Set dst (MoveL2D src));
11545 effect(DEF dst, USE src);
11547 ins_cost(200);
11548 format %{ "MOV $dst,$src.lo\n\t"
11549 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11550 opcode(0x89, 0x89);
11551 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11552 ins_pipe( ialu_mem_long_reg );
11553 %}
11556 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11557 predicate(UseSSE<=1);
11558 match(Set dst (MoveL2D src));
11559 effect(DEF dst, USE src);
11560 ins_cost(125);
11562 format %{ "FLD_D $src\n\t"
11563 "FSTP $dst\t# MoveL2D_stack_reg" %}
11564 opcode(0xDD); /* DD /0, FLD m64real */
11565 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11566 Pop_Reg_DPR(dst) );
11567 ins_pipe( fpu_reg_mem );
11568 %}
11571 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11572 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11573 match(Set dst (MoveL2D src));
11574 effect(DEF dst, USE src);
11576 ins_cost(95);
11577 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11578 ins_encode %{
11579 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11580 %}
11581 ins_pipe( pipe_slow );
11582 %}
11584 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11585 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11586 match(Set dst (MoveL2D src));
11587 effect(DEF dst, USE src);
11589 ins_cost(95);
11590 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11591 ins_encode %{
11592 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11593 %}
11594 ins_pipe( pipe_slow );
11595 %}
11597 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11598 predicate(UseSSE>=2);
11599 match(Set dst (MoveL2D src));
11600 effect(TEMP dst, USE src, TEMP tmp);
11601 ins_cost(85);
11602 format %{ "MOVD $dst,$src.lo\n\t"
11603 "MOVD $tmp,$src.hi\n\t"
11604 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11605 ins_encode %{
11606 __ movdl($dst$$XMMRegister, $src$$Register);
11607 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11608 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11609 %}
11610 ins_pipe( pipe_slow );
11611 %}
11613 // Replicate scalar to packed byte (1 byte) values in xmm
11614 instruct Repl8B_reg(regD dst, regD src) %{
11615 predicate(UseSSE>=2);
11616 match(Set dst (Replicate8B src));
11617 format %{ "MOVDQA $dst,$src\n\t"
11618 "PUNPCKLBW $dst,$dst\n\t"
11619 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11620 ins_encode %{
11621 if ($dst$$reg != $src$$reg) {
11622 __ movdqa($dst$$XMMRegister, $src$$XMMRegister);
11623 }
11624 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
11625 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11626 %}
11627 ins_pipe( pipe_slow );
11628 %}
11630 // Replicate scalar to packed byte (1 byte) values in xmm
11631 instruct Repl8B_eRegI(regD dst, eRegI src) %{
11632 predicate(UseSSE>=2);
11633 match(Set dst (Replicate8B src));
11634 format %{ "MOVD $dst,$src\n\t"
11635 "PUNPCKLBW $dst,$dst\n\t"
11636 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11637 ins_encode %{
11638 __ movdl($dst$$XMMRegister, $src$$Register);
11639 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
11640 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11641 %}
11642 ins_pipe( pipe_slow );
11643 %}
11645 // Replicate scalar zero to packed byte (1 byte) values in xmm
11646 instruct Repl8B_immI0(regD dst, immI0 zero) %{
11647 predicate(UseSSE>=2);
11648 match(Set dst (Replicate8B zero));
11649 format %{ "PXOR $dst,$dst\t! replicate8B" %}
11650 ins_encode %{
11651 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11652 %}
11653 ins_pipe( fpu_reg_reg );
11654 %}
11656 // Replicate scalar to packed shore (2 byte) values in xmm
11657 instruct Repl4S_reg(regD dst, regD src) %{
11658 predicate(UseSSE>=2);
11659 match(Set dst (Replicate4S src));
11660 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
11661 ins_encode %{
11662 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
11663 %}
11664 ins_pipe( fpu_reg_reg );
11665 %}
11667 // Replicate scalar to packed shore (2 byte) values in xmm
11668 instruct Repl4S_eRegI(regD dst, eRegI src) %{
11669 predicate(UseSSE>=2);
11670 match(Set dst (Replicate4S src));
11671 format %{ "MOVD $dst,$src\n\t"
11672 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
11673 ins_encode %{
11674 __ movdl($dst$$XMMRegister, $src$$Register);
11675 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11676 %}
11677 ins_pipe( fpu_reg_reg );
11678 %}
11680 // Replicate scalar zero to packed short (2 byte) values in xmm
11681 instruct Repl4S_immI0(regD dst, immI0 zero) %{
11682 predicate(UseSSE>=2);
11683 match(Set dst (Replicate4S zero));
11684 format %{ "PXOR $dst,$dst\t! replicate4S" %}
11685 ins_encode %{
11686 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11687 %}
11688 ins_pipe( fpu_reg_reg );
11689 %}
11691 // Replicate scalar to packed char (2 byte) values in xmm
11692 instruct Repl4C_reg(regD dst, regD src) %{
11693 predicate(UseSSE>=2);
11694 match(Set dst (Replicate4C src));
11695 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
11696 ins_encode %{
11697 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
11698 %}
11699 ins_pipe( fpu_reg_reg );
11700 %}
11702 // Replicate scalar to packed char (2 byte) values in xmm
11703 instruct Repl4C_eRegI(regD dst, eRegI src) %{
11704 predicate(UseSSE>=2);
11705 match(Set dst (Replicate4C src));
11706 format %{ "MOVD $dst,$src\n\t"
11707 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
11708 ins_encode %{
11709 __ movdl($dst$$XMMRegister, $src$$Register);
11710 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11711 %}
11712 ins_pipe( fpu_reg_reg );
11713 %}
11715 // Replicate scalar zero to packed char (2 byte) values in xmm
11716 instruct Repl4C_immI0(regD dst, immI0 zero) %{
11717 predicate(UseSSE>=2);
11718 match(Set dst (Replicate4C zero));
11719 format %{ "PXOR $dst,$dst\t! replicate4C" %}
11720 ins_encode %{
11721 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11722 %}
11723 ins_pipe( fpu_reg_reg );
11724 %}
11726 // Replicate scalar to packed integer (4 byte) values in xmm
11727 instruct Repl2I_reg(regD dst, regD src) %{
11728 predicate(UseSSE>=2);
11729 match(Set dst (Replicate2I src));
11730 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
11731 ins_encode %{
11732 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00);
11733 %}
11734 ins_pipe( fpu_reg_reg );
11735 %}
11737 // Replicate scalar to packed integer (4 byte) values in xmm
11738 instruct Repl2I_eRegI(regD dst, eRegI src) %{
11739 predicate(UseSSE>=2);
11740 match(Set dst (Replicate2I src));
11741 format %{ "MOVD $dst,$src\n\t"
11742 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
11743 ins_encode %{
11744 __ movdl($dst$$XMMRegister, $src$$Register);
11745 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11746 %}
11747 ins_pipe( fpu_reg_reg );
11748 %}
11750 // Replicate scalar zero to packed integer (2 byte) values in xmm
11751 instruct Repl2I_immI0(regD dst, immI0 zero) %{
11752 predicate(UseSSE>=2);
11753 match(Set dst (Replicate2I zero));
11754 format %{ "PXOR $dst,$dst\t! replicate2I" %}
11755 ins_encode %{
11756 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11757 %}
11758 ins_pipe( fpu_reg_reg );
11759 %}
11761 // Replicate scalar to packed single precision floating point values in xmm
11762 instruct Repl2F_reg(regD dst, regD src) %{
11763 predicate(UseSSE>=2);
11764 match(Set dst (Replicate2F src));
11765 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11766 ins_encode %{
11767 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
11768 %}
11769 ins_pipe( fpu_reg_reg );
11770 %}
11772 // Replicate scalar to packed single precision floating point values in xmm
11773 instruct Repl2F_regF(regD dst, regF src) %{
11774 predicate(UseSSE>=2);
11775 match(Set dst (Replicate2F src));
11776 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11777 ins_encode %{
11778 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
11779 %}
11780 ins_pipe( fpu_reg_reg );
11781 %}
11783 // Replicate scalar to packed single precision floating point values in xmm
11784 instruct Repl2F_immF0(regD dst, immF0 zero) %{
11785 predicate(UseSSE>=2);
11786 match(Set dst (Replicate2F zero));
11787 format %{ "PXOR $dst,$dst\t! replicate2F" %}
11788 ins_encode %{
11789 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11790 %}
11791 ins_pipe( fpu_reg_reg );
11792 %}
11794 // =======================================================================
11795 // fast clearing of an array
11796 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11797 match(Set dummy (ClearArray cnt base));
11798 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11799 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
11800 "XOR EAX,EAX\n\t"
11801 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11802 opcode(0,0x4);
11803 ins_encode( Opcode(0xD1), RegOpc(ECX),
11804 OpcRegReg(0x33,EAX,EAX),
11805 Opcode(0xF3), Opcode(0xAB) );
11806 ins_pipe( pipe_slow );
11807 %}
11809 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11810 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11811 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11812 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11814 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11815 ins_encode %{
11816 __ string_compare($str1$$Register, $str2$$Register,
11817 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11818 $tmp1$$XMMRegister);
11819 %}
11820 ins_pipe( pipe_slow );
11821 %}
11823 // fast string equals
11824 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11825 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11826 match(Set result (StrEquals (Binary str1 str2) cnt));
11827 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11829 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11830 ins_encode %{
11831 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11832 $cnt$$Register, $result$$Register, $tmp3$$Register,
11833 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11834 %}
11835 ins_pipe( pipe_slow );
11836 %}
11838 // fast search of substring with known size.
11839 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11840 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11841 predicate(UseSSE42Intrinsics);
11842 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11843 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11845 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11846 ins_encode %{
11847 int icnt2 = (int)$int_cnt2$$constant;
11848 if (icnt2 >= 8) {
11849 // IndexOf for constant substrings with size >= 8 elements
11850 // which don't need to be loaded through stack.
11851 __ string_indexofC8($str1$$Register, $str2$$Register,
11852 $cnt1$$Register, $cnt2$$Register,
11853 icnt2, $result$$Register,
11854 $vec$$XMMRegister, $tmp$$Register);
11855 } else {
11856 // Small strings are loaded through stack if they cross page boundary.
11857 __ string_indexof($str1$$Register, $str2$$Register,
11858 $cnt1$$Register, $cnt2$$Register,
11859 icnt2, $result$$Register,
11860 $vec$$XMMRegister, $tmp$$Register);
11861 }
11862 %}
11863 ins_pipe( pipe_slow );
11864 %}
11866 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11867 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11868 predicate(UseSSE42Intrinsics);
11869 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11870 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11872 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11873 ins_encode %{
11874 __ string_indexof($str1$$Register, $str2$$Register,
11875 $cnt1$$Register, $cnt2$$Register,
11876 (-1), $result$$Register,
11877 $vec$$XMMRegister, $tmp$$Register);
11878 %}
11879 ins_pipe( pipe_slow );
11880 %}
11882 // fast array equals
11883 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11884 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11885 %{
11886 match(Set result (AryEq ary1 ary2));
11887 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11888 //ins_cost(300);
11890 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11891 ins_encode %{
11892 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11893 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11894 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11895 %}
11896 ins_pipe( pipe_slow );
11897 %}
11899 //----------Control Flow Instructions------------------------------------------
11900 // Signed compare Instructions
11901 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
11902 match(Set cr (CmpI op1 op2));
11903 effect( DEF cr, USE op1, USE op2 );
11904 format %{ "CMP $op1,$op2" %}
11905 opcode(0x3B); /* Opcode 3B /r */
11906 ins_encode( OpcP, RegReg( op1, op2) );
11907 ins_pipe( ialu_cr_reg_reg );
11908 %}
11910 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
11911 match(Set cr (CmpI op1 op2));
11912 effect( DEF cr, USE op1 );
11913 format %{ "CMP $op1,$op2" %}
11914 opcode(0x81,0x07); /* Opcode 81 /7 */
11915 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11916 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11917 ins_pipe( ialu_cr_reg_imm );
11918 %}
11920 // Cisc-spilled version of cmpI_eReg
11921 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
11922 match(Set cr (CmpI op1 (LoadI op2)));
11924 format %{ "CMP $op1,$op2" %}
11925 ins_cost(500);
11926 opcode(0x3B); /* Opcode 3B /r */
11927 ins_encode( OpcP, RegMem( op1, op2) );
11928 ins_pipe( ialu_cr_reg_mem );
11929 %}
11931 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
11932 match(Set cr (CmpI src zero));
11933 effect( DEF cr, USE src );
11935 format %{ "TEST $src,$src" %}
11936 opcode(0x85);
11937 ins_encode( OpcP, RegReg( src, src ) );
11938 ins_pipe( ialu_cr_reg_imm );
11939 %}
11941 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
11942 match(Set cr (CmpI (AndI src con) zero));
11944 format %{ "TEST $src,$con" %}
11945 opcode(0xF7,0x00);
11946 ins_encode( OpcP, RegOpc(src), Con32(con) );
11947 ins_pipe( ialu_cr_reg_imm );
11948 %}
11950 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
11951 match(Set cr (CmpI (AndI src mem) zero));
11953 format %{ "TEST $src,$mem" %}
11954 opcode(0x85);
11955 ins_encode( OpcP, RegMem( src, mem ) );
11956 ins_pipe( ialu_cr_reg_mem );
11957 %}
11959 // Unsigned compare Instructions; really, same as signed except they
11960 // produce an eFlagsRegU instead of eFlagsReg.
11961 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
11962 match(Set cr (CmpU op1 op2));
11964 format %{ "CMPu $op1,$op2" %}
11965 opcode(0x3B); /* Opcode 3B /r */
11966 ins_encode( OpcP, RegReg( op1, op2) );
11967 ins_pipe( ialu_cr_reg_reg );
11968 %}
11970 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
11971 match(Set cr (CmpU op1 op2));
11973 format %{ "CMPu $op1,$op2" %}
11974 opcode(0x81,0x07); /* Opcode 81 /7 */
11975 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11976 ins_pipe( ialu_cr_reg_imm );
11977 %}
11979 // // Cisc-spilled version of cmpU_eReg
11980 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
11981 match(Set cr (CmpU op1 (LoadI op2)));
11983 format %{ "CMPu $op1,$op2" %}
11984 ins_cost(500);
11985 opcode(0x3B); /* Opcode 3B /r */
11986 ins_encode( OpcP, RegMem( op1, op2) );
11987 ins_pipe( ialu_cr_reg_mem );
11988 %}
11990 // // Cisc-spilled version of cmpU_eReg
11991 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
11992 // match(Set cr (CmpU (LoadI op1) op2));
11993 //
11994 // format %{ "CMPu $op1,$op2" %}
11995 // ins_cost(500);
11996 // opcode(0x39); /* Opcode 39 /r */
11997 // ins_encode( OpcP, RegMem( op1, op2) );
11998 //%}
12000 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12001 match(Set cr (CmpU src zero));
12003 format %{ "TESTu $src,$src" %}
12004 opcode(0x85);
12005 ins_encode( OpcP, RegReg( src, src ) );
12006 ins_pipe( ialu_cr_reg_imm );
12007 %}
12009 // Unsigned pointer compare Instructions
12010 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12011 match(Set cr (CmpP op1 op2));
12013 format %{ "CMPu $op1,$op2" %}
12014 opcode(0x3B); /* Opcode 3B /r */
12015 ins_encode( OpcP, RegReg( op1, op2) );
12016 ins_pipe( ialu_cr_reg_reg );
12017 %}
12019 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12020 match(Set cr (CmpP op1 op2));
12022 format %{ "CMPu $op1,$op2" %}
12023 opcode(0x81,0x07); /* Opcode 81 /7 */
12024 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12025 ins_pipe( ialu_cr_reg_imm );
12026 %}
12028 // // Cisc-spilled version of cmpP_eReg
12029 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12030 match(Set cr (CmpP op1 (LoadP op2)));
12032 format %{ "CMPu $op1,$op2" %}
12033 ins_cost(500);
12034 opcode(0x3B); /* Opcode 3B /r */
12035 ins_encode( OpcP, RegMem( op1, op2) );
12036 ins_pipe( ialu_cr_reg_mem );
12037 %}
12039 // // Cisc-spilled version of cmpP_eReg
12040 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12041 // match(Set cr (CmpP (LoadP op1) op2));
12042 //
12043 // format %{ "CMPu $op1,$op2" %}
12044 // ins_cost(500);
12045 // opcode(0x39); /* Opcode 39 /r */
12046 // ins_encode( OpcP, RegMem( op1, op2) );
12047 //%}
12049 // Compare raw pointer (used in out-of-heap check).
12050 // Only works because non-oop pointers must be raw pointers
12051 // and raw pointers have no anti-dependencies.
12052 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12053 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12054 match(Set cr (CmpP op1 (LoadP op2)));
12056 format %{ "CMPu $op1,$op2" %}
12057 opcode(0x3B); /* Opcode 3B /r */
12058 ins_encode( OpcP, RegMem( op1, op2) );
12059 ins_pipe( ialu_cr_reg_mem );
12060 %}
12062 //
12063 // This will generate a signed flags result. This should be ok
12064 // since any compare to a zero should be eq/neq.
12065 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12066 match(Set cr (CmpP src zero));
12068 format %{ "TEST $src,$src" %}
12069 opcode(0x85);
12070 ins_encode( OpcP, RegReg( src, src ) );
12071 ins_pipe( ialu_cr_reg_imm );
12072 %}
12074 // Cisc-spilled version of testP_reg
12075 // This will generate a signed flags result. This should be ok
12076 // since any compare to a zero should be eq/neq.
12077 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12078 match(Set cr (CmpP (LoadP op) zero));
12080 format %{ "TEST $op,0xFFFFFFFF" %}
12081 ins_cost(500);
12082 opcode(0xF7); /* Opcode F7 /0 */
12083 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12084 ins_pipe( ialu_cr_reg_imm );
12085 %}
12087 // Yanked all unsigned pointer compare operations.
12088 // Pointer compares are done with CmpP which is already unsigned.
12090 //----------Max and Min--------------------------------------------------------
12091 // Min Instructions
12092 ////
12093 // *** Min and Max using the conditional move are slower than the
12094 // *** branch version on a Pentium III.
12095 // // Conditional move for min
12096 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12097 // effect( USE_DEF op2, USE op1, USE cr );
12098 // format %{ "CMOVlt $op2,$op1\t! min" %}
12099 // opcode(0x4C,0x0F);
12100 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12101 // ins_pipe( pipe_cmov_reg );
12102 //%}
12103 //
12104 //// Min Register with Register (P6 version)
12105 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12106 // predicate(VM_Version::supports_cmov() );
12107 // match(Set op2 (MinI op1 op2));
12108 // ins_cost(200);
12109 // expand %{
12110 // eFlagsReg cr;
12111 // compI_eReg(cr,op1,op2);
12112 // cmovI_reg_lt(op2,op1,cr);
12113 // %}
12114 //%}
12116 // Min Register with Register (generic version)
12117 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12118 match(Set dst (MinI dst src));
12119 effect(KILL flags);
12120 ins_cost(300);
12122 format %{ "MIN $dst,$src" %}
12123 opcode(0xCC);
12124 ins_encode( min_enc(dst,src) );
12125 ins_pipe( pipe_slow );
12126 %}
12128 // Max Register with Register
12129 // *** Min and Max using the conditional move are slower than the
12130 // *** branch version on a Pentium III.
12131 // // Conditional move for max
12132 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12133 // effect( USE_DEF op2, USE op1, USE cr );
12134 // format %{ "CMOVgt $op2,$op1\t! max" %}
12135 // opcode(0x4F,0x0F);
12136 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12137 // ins_pipe( pipe_cmov_reg );
12138 //%}
12139 //
12140 // // Max Register with Register (P6 version)
12141 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12142 // predicate(VM_Version::supports_cmov() );
12143 // match(Set op2 (MaxI op1 op2));
12144 // ins_cost(200);
12145 // expand %{
12146 // eFlagsReg cr;
12147 // compI_eReg(cr,op1,op2);
12148 // cmovI_reg_gt(op2,op1,cr);
12149 // %}
12150 //%}
12152 // Max Register with Register (generic version)
12153 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12154 match(Set dst (MaxI dst src));
12155 effect(KILL flags);
12156 ins_cost(300);
12158 format %{ "MAX $dst,$src" %}
12159 opcode(0xCC);
12160 ins_encode( max_enc(dst,src) );
12161 ins_pipe( pipe_slow );
12162 %}
12164 // ============================================================================
12165 // Counted Loop limit node which represents exact final iterator value.
12166 // Note: the resulting value should fit into integer range since
12167 // counted loops have limit check on overflow.
12168 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
12169 match(Set limit (LoopLimit (Binary init limit) stride));
12170 effect(TEMP limit_hi, TEMP tmp, KILL flags);
12171 ins_cost(300);
12173 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
12174 ins_encode %{
12175 int strd = (int)$stride$$constant;
12176 assert(strd != 1 && strd != -1, "sanity");
12177 int m1 = (strd > 0) ? 1 : -1;
12178 // Convert limit to long (EAX:EDX)
12179 __ cdql();
12180 // Convert init to long (init:tmp)
12181 __ movl($tmp$$Register, $init$$Register);
12182 __ sarl($tmp$$Register, 31);
12183 // $limit - $init
12184 __ subl($limit$$Register, $init$$Register);
12185 __ sbbl($limit_hi$$Register, $tmp$$Register);
12186 // + ($stride - 1)
12187 if (strd > 0) {
12188 __ addl($limit$$Register, (strd - 1));
12189 __ adcl($limit_hi$$Register, 0);
12190 __ movl($tmp$$Register, strd);
12191 } else {
12192 __ addl($limit$$Register, (strd + 1));
12193 __ adcl($limit_hi$$Register, -1);
12194 __ lneg($limit_hi$$Register, $limit$$Register);
12195 __ movl($tmp$$Register, -strd);
12196 }
12197 // signed devision: (EAX:EDX) / pos_stride
12198 __ idivl($tmp$$Register);
12199 if (strd < 0) {
12200 // restore sign
12201 __ negl($tmp$$Register);
12202 }
12203 // (EAX) * stride
12204 __ mull($tmp$$Register);
12205 // + init (ignore upper bits)
12206 __ addl($limit$$Register, $init$$Register);
12207 %}
12208 ins_pipe( pipe_slow );
12209 %}
12211 // ============================================================================
12212 // Branch Instructions
12213 // Jump Table
12214 instruct jumpXtnd(eRegI switch_val) %{
12215 match(Jump switch_val);
12216 ins_cost(350);
12217 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12218 ins_encode %{
12219 // Jump to Address(table_base + switch_reg)
12220 Address index(noreg, $switch_val$$Register, Address::times_1);
12221 __ jump(ArrayAddress($constantaddress, index));
12222 %}
12223 ins_pipe(pipe_jmp);
12224 %}
12226 // Jump Direct - Label defines a relative address from JMP+1
12227 instruct jmpDir(label labl) %{
12228 match(Goto);
12229 effect(USE labl);
12231 ins_cost(300);
12232 format %{ "JMP $labl" %}
12233 size(5);
12234 ins_encode %{
12235 Label* L = $labl$$label;
12236 __ jmp(*L, false); // Always long jump
12237 %}
12238 ins_pipe( pipe_jmp );
12239 %}
12241 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12242 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12243 match(If cop cr);
12244 effect(USE labl);
12246 ins_cost(300);
12247 format %{ "J$cop $labl" %}
12248 size(6);
12249 ins_encode %{
12250 Label* L = $labl$$label;
12251 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12252 %}
12253 ins_pipe( pipe_jcc );
12254 %}
12256 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12257 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12258 match(CountedLoopEnd cop cr);
12259 effect(USE labl);
12261 ins_cost(300);
12262 format %{ "J$cop $labl\t# Loop end" %}
12263 size(6);
12264 ins_encode %{
12265 Label* L = $labl$$label;
12266 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12267 %}
12268 ins_pipe( pipe_jcc );
12269 %}
12271 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12272 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12273 match(CountedLoopEnd cop cmp);
12274 effect(USE labl);
12276 ins_cost(300);
12277 format %{ "J$cop,u $labl\t# Loop end" %}
12278 size(6);
12279 ins_encode %{
12280 Label* L = $labl$$label;
12281 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12282 %}
12283 ins_pipe( pipe_jcc );
12284 %}
12286 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12287 match(CountedLoopEnd cop cmp);
12288 effect(USE labl);
12290 ins_cost(200);
12291 format %{ "J$cop,u $labl\t# Loop end" %}
12292 size(6);
12293 ins_encode %{
12294 Label* L = $labl$$label;
12295 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12296 %}
12297 ins_pipe( pipe_jcc );
12298 %}
12300 // Jump Direct Conditional - using unsigned comparison
12301 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12302 match(If cop cmp);
12303 effect(USE labl);
12305 ins_cost(300);
12306 format %{ "J$cop,u $labl" %}
12307 size(6);
12308 ins_encode %{
12309 Label* L = $labl$$label;
12310 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12311 %}
12312 ins_pipe(pipe_jcc);
12313 %}
12315 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12316 match(If cop cmp);
12317 effect(USE labl);
12319 ins_cost(200);
12320 format %{ "J$cop,u $labl" %}
12321 size(6);
12322 ins_encode %{
12323 Label* L = $labl$$label;
12324 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12325 %}
12326 ins_pipe(pipe_jcc);
12327 %}
12329 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12330 match(If cop cmp);
12331 effect(USE labl);
12333 ins_cost(200);
12334 format %{ $$template
12335 if ($cop$$cmpcode == Assembler::notEqual) {
12336 $$emit$$"JP,u $labl\n\t"
12337 $$emit$$"J$cop,u $labl"
12338 } else {
12339 $$emit$$"JP,u done\n\t"
12340 $$emit$$"J$cop,u $labl\n\t"
12341 $$emit$$"done:"
12342 }
12343 %}
12344 ins_encode %{
12345 Label* l = $labl$$label;
12346 if ($cop$$cmpcode == Assembler::notEqual) {
12347 __ jcc(Assembler::parity, *l, false);
12348 __ jcc(Assembler::notEqual, *l, false);
12349 } else if ($cop$$cmpcode == Assembler::equal) {
12350 Label done;
12351 __ jccb(Assembler::parity, done);
12352 __ jcc(Assembler::equal, *l, false);
12353 __ bind(done);
12354 } else {
12355 ShouldNotReachHere();
12356 }
12357 %}
12358 ins_pipe(pipe_jcc);
12359 %}
12361 // ============================================================================
12362 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12363 // array for an instance of the superklass. Set a hidden internal cache on a
12364 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12365 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12366 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12367 match(Set result (PartialSubtypeCheck sub super));
12368 effect( KILL rcx, KILL cr );
12370 ins_cost(1100); // slightly larger than the next version
12371 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12372 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12373 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12374 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12375 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12376 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12377 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12378 "miss:\t" %}
12380 opcode(0x1); // Force a XOR of EDI
12381 ins_encode( enc_PartialSubtypeCheck() );
12382 ins_pipe( pipe_slow );
12383 %}
12385 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12386 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12387 effect( KILL rcx, KILL result );
12389 ins_cost(1000);
12390 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12391 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12392 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12393 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12394 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12395 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12396 "miss:\t" %}
12398 opcode(0x0); // No need to XOR EDI
12399 ins_encode( enc_PartialSubtypeCheck() );
12400 ins_pipe( pipe_slow );
12401 %}
12403 // ============================================================================
12404 // Branch Instructions -- short offset versions
12405 //
12406 // These instructions are used to replace jumps of a long offset (the default
12407 // match) with jumps of a shorter offset. These instructions are all tagged
12408 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12409 // match rules in general matching. Instead, the ADLC generates a conversion
12410 // method in the MachNode which can be used to do in-place replacement of the
12411 // long variant with the shorter variant. The compiler will determine if a
12412 // branch can be taken by the is_short_branch_offset() predicate in the machine
12413 // specific code section of the file.
12415 // Jump Direct - Label defines a relative address from JMP+1
12416 instruct jmpDir_short(label labl) %{
12417 match(Goto);
12418 effect(USE labl);
12420 ins_cost(300);
12421 format %{ "JMP,s $labl" %}
12422 size(2);
12423 ins_encode %{
12424 Label* L = $labl$$label;
12425 __ jmpb(*L);
12426 %}
12427 ins_pipe( pipe_jmp );
12428 ins_short_branch(1);
12429 %}
12431 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12432 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12433 match(If cop cr);
12434 effect(USE labl);
12436 ins_cost(300);
12437 format %{ "J$cop,s $labl" %}
12438 size(2);
12439 ins_encode %{
12440 Label* L = $labl$$label;
12441 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12442 %}
12443 ins_pipe( pipe_jcc );
12444 ins_short_branch(1);
12445 %}
12447 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12448 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12449 match(CountedLoopEnd cop cr);
12450 effect(USE labl);
12452 ins_cost(300);
12453 format %{ "J$cop,s $labl\t# Loop end" %}
12454 size(2);
12455 ins_encode %{
12456 Label* L = $labl$$label;
12457 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12458 %}
12459 ins_pipe( pipe_jcc );
12460 ins_short_branch(1);
12461 %}
12463 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12464 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12465 match(CountedLoopEnd cop cmp);
12466 effect(USE labl);
12468 ins_cost(300);
12469 format %{ "J$cop,us $labl\t# Loop end" %}
12470 size(2);
12471 ins_encode %{
12472 Label* L = $labl$$label;
12473 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12474 %}
12475 ins_pipe( pipe_jcc );
12476 ins_short_branch(1);
12477 %}
12479 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12480 match(CountedLoopEnd cop cmp);
12481 effect(USE labl);
12483 ins_cost(300);
12484 format %{ "J$cop,us $labl\t# Loop end" %}
12485 size(2);
12486 ins_encode %{
12487 Label* L = $labl$$label;
12488 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12489 %}
12490 ins_pipe( pipe_jcc );
12491 ins_short_branch(1);
12492 %}
12494 // Jump Direct Conditional - using unsigned comparison
12495 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12496 match(If cop cmp);
12497 effect(USE labl);
12499 ins_cost(300);
12500 format %{ "J$cop,us $labl" %}
12501 size(2);
12502 ins_encode %{
12503 Label* L = $labl$$label;
12504 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12505 %}
12506 ins_pipe( pipe_jcc );
12507 ins_short_branch(1);
12508 %}
12510 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12511 match(If cop cmp);
12512 effect(USE labl);
12514 ins_cost(300);
12515 format %{ "J$cop,us $labl" %}
12516 size(2);
12517 ins_encode %{
12518 Label* L = $labl$$label;
12519 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12520 %}
12521 ins_pipe( pipe_jcc );
12522 ins_short_branch(1);
12523 %}
12525 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12526 match(If cop cmp);
12527 effect(USE labl);
12529 ins_cost(300);
12530 format %{ $$template
12531 if ($cop$$cmpcode == Assembler::notEqual) {
12532 $$emit$$"JP,u,s $labl\n\t"
12533 $$emit$$"J$cop,u,s $labl"
12534 } else {
12535 $$emit$$"JP,u,s done\n\t"
12536 $$emit$$"J$cop,u,s $labl\n\t"
12537 $$emit$$"done:"
12538 }
12539 %}
12540 size(4);
12541 ins_encode %{
12542 Label* l = $labl$$label;
12543 if ($cop$$cmpcode == Assembler::notEqual) {
12544 __ jccb(Assembler::parity, *l);
12545 __ jccb(Assembler::notEqual, *l);
12546 } else if ($cop$$cmpcode == Assembler::equal) {
12547 Label done;
12548 __ jccb(Assembler::parity, done);
12549 __ jccb(Assembler::equal, *l);
12550 __ bind(done);
12551 } else {
12552 ShouldNotReachHere();
12553 }
12554 %}
12555 ins_pipe(pipe_jcc);
12556 ins_short_branch(1);
12557 %}
12559 // ============================================================================
12560 // Long Compare
12561 //
12562 // Currently we hold longs in 2 registers. Comparing such values efficiently
12563 // is tricky. The flavor of compare used depends on whether we are testing
12564 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12565 // The GE test is the negated LT test. The LE test can be had by commuting
12566 // the operands (yielding a GE test) and then negating; negate again for the
12567 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12568 // NE test is negated from that.
12570 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12571 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12572 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12573 // are collapsed internally in the ADLC's dfa-gen code. The match for
12574 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12575 // foo match ends up with the wrong leaf. One fix is to not match both
12576 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12577 // both forms beat the trinary form of long-compare and both are very useful
12578 // on Intel which has so few registers.
12580 // Manifest a CmpL result in an integer register. Very painful.
12581 // This is the test to avoid.
12582 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12583 match(Set dst (CmpL3 src1 src2));
12584 effect( KILL flags );
12585 ins_cost(1000);
12586 format %{ "XOR $dst,$dst\n\t"
12587 "CMP $src1.hi,$src2.hi\n\t"
12588 "JLT,s m_one\n\t"
12589 "JGT,s p_one\n\t"
12590 "CMP $src1.lo,$src2.lo\n\t"
12591 "JB,s m_one\n\t"
12592 "JEQ,s done\n"
12593 "p_one:\tINC $dst\n\t"
12594 "JMP,s done\n"
12595 "m_one:\tDEC $dst\n"
12596 "done:" %}
12597 ins_encode %{
12598 Label p_one, m_one, done;
12599 __ xorptr($dst$$Register, $dst$$Register);
12600 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12601 __ jccb(Assembler::less, m_one);
12602 __ jccb(Assembler::greater, p_one);
12603 __ cmpl($src1$$Register, $src2$$Register);
12604 __ jccb(Assembler::below, m_one);
12605 __ jccb(Assembler::equal, done);
12606 __ bind(p_one);
12607 __ incrementl($dst$$Register);
12608 __ jmpb(done);
12609 __ bind(m_one);
12610 __ decrementl($dst$$Register);
12611 __ bind(done);
12612 %}
12613 ins_pipe( pipe_slow );
12614 %}
12616 //======
12617 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12618 // compares. Can be used for LE or GT compares by reversing arguments.
12619 // NOT GOOD FOR EQ/NE tests.
12620 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12621 match( Set flags (CmpL src zero ));
12622 ins_cost(100);
12623 format %{ "TEST $src.hi,$src.hi" %}
12624 opcode(0x85);
12625 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12626 ins_pipe( ialu_cr_reg_reg );
12627 %}
12629 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12630 // compares. Can be used for LE or GT compares by reversing arguments.
12631 // NOT GOOD FOR EQ/NE tests.
12632 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
12633 match( Set flags (CmpL src1 src2 ));
12634 effect( TEMP tmp );
12635 ins_cost(300);
12636 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12637 "MOV $tmp,$src1.hi\n\t"
12638 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12639 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12640 ins_pipe( ialu_cr_reg_reg );
12641 %}
12643 // Long compares reg < zero/req OR reg >= zero/req.
12644 // Just a wrapper for a normal branch, plus the predicate test.
12645 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12646 match(If cmp flags);
12647 effect(USE labl);
12648 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12649 expand %{
12650 jmpCon(cmp,flags,labl); // JLT or JGE...
12651 %}
12652 %}
12654 // Compare 2 longs and CMOVE longs.
12655 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12656 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12657 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12658 ins_cost(400);
12659 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12660 "CMOV$cmp $dst.hi,$src.hi" %}
12661 opcode(0x0F,0x40);
12662 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12663 ins_pipe( pipe_cmov_reg_long );
12664 %}
12666 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12667 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12668 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12669 ins_cost(500);
12670 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12671 "CMOV$cmp $dst.hi,$src.hi" %}
12672 opcode(0x0F,0x40);
12673 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12674 ins_pipe( pipe_cmov_reg_long );
12675 %}
12677 // Compare 2 longs and CMOVE ints.
12678 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
12679 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12680 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12681 ins_cost(200);
12682 format %{ "CMOV$cmp $dst,$src" %}
12683 opcode(0x0F,0x40);
12684 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12685 ins_pipe( pipe_cmov_reg );
12686 %}
12688 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
12689 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12690 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12691 ins_cost(250);
12692 format %{ "CMOV$cmp $dst,$src" %}
12693 opcode(0x0F,0x40);
12694 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12695 ins_pipe( pipe_cmov_mem );
12696 %}
12698 // Compare 2 longs and CMOVE ints.
12699 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12700 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12701 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12702 ins_cost(200);
12703 format %{ "CMOV$cmp $dst,$src" %}
12704 opcode(0x0F,0x40);
12705 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12706 ins_pipe( pipe_cmov_reg );
12707 %}
12709 // Compare 2 longs and CMOVE doubles
12710 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12711 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12712 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12713 ins_cost(200);
12714 expand %{
12715 fcmovDPR_regS(cmp,flags,dst,src);
12716 %}
12717 %}
12719 // Compare 2 longs and CMOVE doubles
12720 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12721 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12722 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12723 ins_cost(200);
12724 expand %{
12725 fcmovD_regS(cmp,flags,dst,src);
12726 %}
12727 %}
12729 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12730 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12731 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12732 ins_cost(200);
12733 expand %{
12734 fcmovFPR_regS(cmp,flags,dst,src);
12735 %}
12736 %}
12738 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12739 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12740 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12741 ins_cost(200);
12742 expand %{
12743 fcmovF_regS(cmp,flags,dst,src);
12744 %}
12745 %}
12747 //======
12748 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12749 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
12750 match( Set flags (CmpL src zero ));
12751 effect(TEMP tmp);
12752 ins_cost(200);
12753 format %{ "MOV $tmp,$src.lo\n\t"
12754 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12755 ins_encode( long_cmp_flags0( src, tmp ) );
12756 ins_pipe( ialu_reg_reg_long );
12757 %}
12759 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12760 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12761 match( Set flags (CmpL src1 src2 ));
12762 ins_cost(200+300);
12763 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12764 "JNE,s skip\n\t"
12765 "CMP $src1.hi,$src2.hi\n\t"
12766 "skip:\t" %}
12767 ins_encode( long_cmp_flags1( src1, src2 ) );
12768 ins_pipe( ialu_cr_reg_reg );
12769 %}
12771 // Long compare reg == zero/reg OR reg != zero/reg
12772 // Just a wrapper for a normal branch, plus the predicate test.
12773 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12774 match(If cmp flags);
12775 effect(USE labl);
12776 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12777 expand %{
12778 jmpCon(cmp,flags,labl); // JEQ or JNE...
12779 %}
12780 %}
12782 // Compare 2 longs and CMOVE longs.
12783 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12784 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12785 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12786 ins_cost(400);
12787 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12788 "CMOV$cmp $dst.hi,$src.hi" %}
12789 opcode(0x0F,0x40);
12790 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12791 ins_pipe( pipe_cmov_reg_long );
12792 %}
12794 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12795 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12796 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12797 ins_cost(500);
12798 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12799 "CMOV$cmp $dst.hi,$src.hi" %}
12800 opcode(0x0F,0x40);
12801 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12802 ins_pipe( pipe_cmov_reg_long );
12803 %}
12805 // Compare 2 longs and CMOVE ints.
12806 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
12807 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12808 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12809 ins_cost(200);
12810 format %{ "CMOV$cmp $dst,$src" %}
12811 opcode(0x0F,0x40);
12812 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12813 ins_pipe( pipe_cmov_reg );
12814 %}
12816 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
12817 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12818 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12819 ins_cost(250);
12820 format %{ "CMOV$cmp $dst,$src" %}
12821 opcode(0x0F,0x40);
12822 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12823 ins_pipe( pipe_cmov_mem );
12824 %}
12826 // Compare 2 longs and CMOVE ints.
12827 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12828 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12829 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12830 ins_cost(200);
12831 format %{ "CMOV$cmp $dst,$src" %}
12832 opcode(0x0F,0x40);
12833 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12834 ins_pipe( pipe_cmov_reg );
12835 %}
12837 // Compare 2 longs and CMOVE doubles
12838 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12839 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12840 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12841 ins_cost(200);
12842 expand %{
12843 fcmovDPR_regS(cmp,flags,dst,src);
12844 %}
12845 %}
12847 // Compare 2 longs and CMOVE doubles
12848 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12849 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12850 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12851 ins_cost(200);
12852 expand %{
12853 fcmovD_regS(cmp,flags,dst,src);
12854 %}
12855 %}
12857 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12858 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12859 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12860 ins_cost(200);
12861 expand %{
12862 fcmovFPR_regS(cmp,flags,dst,src);
12863 %}
12864 %}
12866 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12867 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12868 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12869 ins_cost(200);
12870 expand %{
12871 fcmovF_regS(cmp,flags,dst,src);
12872 %}
12873 %}
12875 //======
12876 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12877 // Same as cmpL_reg_flags_LEGT except must negate src
12878 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
12879 match( Set flags (CmpL src zero ));
12880 effect( TEMP tmp );
12881 ins_cost(300);
12882 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12883 "CMP $tmp,$src.lo\n\t"
12884 "SBB $tmp,$src.hi\n\t" %}
12885 ins_encode( long_cmp_flags3(src, tmp) );
12886 ins_pipe( ialu_reg_reg_long );
12887 %}
12889 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12890 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12891 // requires a commuted test to get the same result.
12892 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
12893 match( Set flags (CmpL src1 src2 ));
12894 effect( TEMP tmp );
12895 ins_cost(300);
12896 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12897 "MOV $tmp,$src2.hi\n\t"
12898 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12899 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12900 ins_pipe( ialu_cr_reg_reg );
12901 %}
12903 // Long compares reg < zero/req OR reg >= zero/req.
12904 // Just a wrapper for a normal branch, plus the predicate test
12905 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12906 match(If cmp flags);
12907 effect(USE labl);
12908 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12909 ins_cost(300);
12910 expand %{
12911 jmpCon(cmp,flags,labl); // JGT or JLE...
12912 %}
12913 %}
12915 // Compare 2 longs and CMOVE longs.
12916 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12917 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12918 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12919 ins_cost(400);
12920 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12921 "CMOV$cmp $dst.hi,$src.hi" %}
12922 opcode(0x0F,0x40);
12923 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12924 ins_pipe( pipe_cmov_reg_long );
12925 %}
12927 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12928 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12929 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12930 ins_cost(500);
12931 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12932 "CMOV$cmp $dst.hi,$src.hi+4" %}
12933 opcode(0x0F,0x40);
12934 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12935 ins_pipe( pipe_cmov_reg_long );
12936 %}
12938 // Compare 2 longs and CMOVE ints.
12939 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
12940 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12941 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12942 ins_cost(200);
12943 format %{ "CMOV$cmp $dst,$src" %}
12944 opcode(0x0F,0x40);
12945 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12946 ins_pipe( pipe_cmov_reg );
12947 %}
12949 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
12950 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12951 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12952 ins_cost(250);
12953 format %{ "CMOV$cmp $dst,$src" %}
12954 opcode(0x0F,0x40);
12955 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12956 ins_pipe( pipe_cmov_mem );
12957 %}
12959 // Compare 2 longs and CMOVE ptrs.
12960 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12961 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12962 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12963 ins_cost(200);
12964 format %{ "CMOV$cmp $dst,$src" %}
12965 opcode(0x0F,0x40);
12966 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12967 ins_pipe( pipe_cmov_reg );
12968 %}
12970 // Compare 2 longs and CMOVE doubles
12971 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12972 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12973 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12974 ins_cost(200);
12975 expand %{
12976 fcmovDPR_regS(cmp,flags,dst,src);
12977 %}
12978 %}
12980 // Compare 2 longs and CMOVE doubles
12981 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12982 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12983 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12984 ins_cost(200);
12985 expand %{
12986 fcmovD_regS(cmp,flags,dst,src);
12987 %}
12988 %}
12990 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12991 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12992 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12993 ins_cost(200);
12994 expand %{
12995 fcmovFPR_regS(cmp,flags,dst,src);
12996 %}
12997 %}
13000 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13001 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13002 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13003 ins_cost(200);
13004 expand %{
13005 fcmovF_regS(cmp,flags,dst,src);
13006 %}
13007 %}
13010 // ============================================================================
13011 // Procedure Call/Return Instructions
13012 // Call Java Static Instruction
13013 // Note: If this code changes, the corresponding ret_addr_offset() and
13014 // compute_padding() functions will have to be adjusted.
13015 instruct CallStaticJavaDirect(method meth) %{
13016 match(CallStaticJava);
13017 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
13018 effect(USE meth);
13020 ins_cost(300);
13021 format %{ "CALL,static " %}
13022 opcode(0xE8); /* E8 cd */
13023 ins_encode( pre_call_FPU,
13024 Java_Static_Call( meth ),
13025 call_epilog,
13026 post_call_FPU );
13027 ins_pipe( pipe_slow );
13028 ins_alignment(4);
13029 %}
13031 // Call Java Static Instruction (method handle version)
13032 // Note: If this code changes, the corresponding ret_addr_offset() and
13033 // compute_padding() functions will have to be adjusted.
13034 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
13035 match(CallStaticJava);
13036 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
13037 effect(USE meth);
13038 // EBP is saved by all callees (for interpreter stack correction).
13039 // We use it here for a similar purpose, in {preserve,restore}_SP.
13041 ins_cost(300);
13042 format %{ "CALL,static/MethodHandle " %}
13043 opcode(0xE8); /* E8 cd */
13044 ins_encode( pre_call_FPU,
13045 preserve_SP,
13046 Java_Static_Call( meth ),
13047 restore_SP,
13048 call_epilog,
13049 post_call_FPU );
13050 ins_pipe( pipe_slow );
13051 ins_alignment(4);
13052 %}
13054 // Call Java Dynamic Instruction
13055 // Note: If this code changes, the corresponding ret_addr_offset() and
13056 // compute_padding() functions will have to be adjusted.
13057 instruct CallDynamicJavaDirect(method meth) %{
13058 match(CallDynamicJava);
13059 effect(USE meth);
13061 ins_cost(300);
13062 format %{ "MOV EAX,(oop)-1\n\t"
13063 "CALL,dynamic" %}
13064 opcode(0xE8); /* E8 cd */
13065 ins_encode( pre_call_FPU,
13066 Java_Dynamic_Call( meth ),
13067 call_epilog,
13068 post_call_FPU );
13069 ins_pipe( pipe_slow );
13070 ins_alignment(4);
13071 %}
13073 // Call Runtime Instruction
13074 instruct CallRuntimeDirect(method meth) %{
13075 match(CallRuntime );
13076 effect(USE meth);
13078 ins_cost(300);
13079 format %{ "CALL,runtime " %}
13080 opcode(0xE8); /* E8 cd */
13081 // Use FFREEs to clear entries in float stack
13082 ins_encode( pre_call_FPU,
13083 FFree_Float_Stack_All,
13084 Java_To_Runtime( meth ),
13085 post_call_FPU );
13086 ins_pipe( pipe_slow );
13087 %}
13089 // Call runtime without safepoint
13090 instruct CallLeafDirect(method meth) %{
13091 match(CallLeaf);
13092 effect(USE meth);
13094 ins_cost(300);
13095 format %{ "CALL_LEAF,runtime " %}
13096 opcode(0xE8); /* E8 cd */
13097 ins_encode( pre_call_FPU,
13098 FFree_Float_Stack_All,
13099 Java_To_Runtime( meth ),
13100 Verify_FPU_For_Leaf, post_call_FPU );
13101 ins_pipe( pipe_slow );
13102 %}
13104 instruct CallLeafNoFPDirect(method meth) %{
13105 match(CallLeafNoFP);
13106 effect(USE meth);
13108 ins_cost(300);
13109 format %{ "CALL_LEAF_NOFP,runtime " %}
13110 opcode(0xE8); /* E8 cd */
13111 ins_encode(Java_To_Runtime(meth));
13112 ins_pipe( pipe_slow );
13113 %}
13116 // Return Instruction
13117 // Remove the return address & jump to it.
13118 instruct Ret() %{
13119 match(Return);
13120 format %{ "RET" %}
13121 opcode(0xC3);
13122 ins_encode(OpcP);
13123 ins_pipe( pipe_jmp );
13124 %}
13126 // Tail Call; Jump from runtime stub to Java code.
13127 // Also known as an 'interprocedural jump'.
13128 // Target of jump will eventually return to caller.
13129 // TailJump below removes the return address.
13130 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13131 match(TailCall jump_target method_oop );
13132 ins_cost(300);
13133 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13134 opcode(0xFF, 0x4); /* Opcode FF /4 */
13135 ins_encode( OpcP, RegOpc(jump_target) );
13136 ins_pipe( pipe_jmp );
13137 %}
13140 // Tail Jump; remove the return address; jump to target.
13141 // TailCall above leaves the return address around.
13142 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13143 match( TailJump jump_target ex_oop );
13144 ins_cost(300);
13145 format %{ "POP EDX\t# pop return address into dummy\n\t"
13146 "JMP $jump_target " %}
13147 opcode(0xFF, 0x4); /* Opcode FF /4 */
13148 ins_encode( enc_pop_rdx,
13149 OpcP, RegOpc(jump_target) );
13150 ins_pipe( pipe_jmp );
13151 %}
13153 // Create exception oop: created by stack-crawling runtime code.
13154 // Created exception is now available to this handler, and is setup
13155 // just prior to jumping to this handler. No code emitted.
13156 instruct CreateException( eAXRegP ex_oop )
13157 %{
13158 match(Set ex_oop (CreateEx));
13160 size(0);
13161 // use the following format syntax
13162 format %{ "# exception oop is in EAX; no code emitted" %}
13163 ins_encode();
13164 ins_pipe( empty );
13165 %}
13168 // Rethrow exception:
13169 // The exception oop will come in the first argument position.
13170 // Then JUMP (not call) to the rethrow stub code.
13171 instruct RethrowException()
13172 %{
13173 match(Rethrow);
13175 // use the following format syntax
13176 format %{ "JMP rethrow_stub" %}
13177 ins_encode(enc_rethrow);
13178 ins_pipe( pipe_jmp );
13179 %}
13181 // inlined locking and unlocking
13184 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
13185 match( Set cr (FastLock object box) );
13186 effect( TEMP tmp, TEMP scr, USE_KILL box );
13187 ins_cost(300);
13188 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
13189 ins_encode( Fast_Lock(object,box,tmp,scr) );
13190 ins_pipe( pipe_slow );
13191 %}
13193 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13194 match( Set cr (FastUnlock object box) );
13195 effect( TEMP tmp, USE_KILL box );
13196 ins_cost(300);
13197 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
13198 ins_encode( Fast_Unlock(object,box,tmp) );
13199 ins_pipe( pipe_slow );
13200 %}
13204 // ============================================================================
13205 // Safepoint Instruction
13206 instruct safePoint_poll(eFlagsReg cr) %{
13207 match(SafePoint);
13208 effect(KILL cr);
13210 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13211 // On SPARC that might be acceptable as we can generate the address with
13212 // just a sethi, saving an or. By polling at offset 0 we can end up
13213 // putting additional pressure on the index-0 in the D$. Because of
13214 // alignment (just like the situation at hand) the lower indices tend
13215 // to see more traffic. It'd be better to change the polling address
13216 // to offset 0 of the last $line in the polling page.
13218 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13219 ins_cost(125);
13220 size(6) ;
13221 ins_encode( Safepoint_Poll() );
13222 ins_pipe( ialu_reg_mem );
13223 %}
13226 // ============================================================================
13227 // This name is KNOWN by the ADLC and cannot be changed.
13228 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13229 // for this guy.
13230 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13231 match(Set dst (ThreadLocal));
13232 effect(DEF dst, KILL cr);
13234 format %{ "MOV $dst, Thread::current()" %}
13235 ins_encode %{
13236 Register dstReg = as_Register($dst$$reg);
13237 __ get_thread(dstReg);
13238 %}
13239 ins_pipe( ialu_reg_fat );
13240 %}
13244 //----------PEEPHOLE RULES-----------------------------------------------------
13245 // These must follow all instruction definitions as they use the names
13246 // defined in the instructions definitions.
13247 //
13248 // peepmatch ( root_instr_name [preceding_instruction]* );
13249 //
13250 // peepconstraint %{
13251 // (instruction_number.operand_name relational_op instruction_number.operand_name
13252 // [, ...] );
13253 // // instruction numbers are zero-based using left to right order in peepmatch
13254 //
13255 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13256 // // provide an instruction_number.operand_name for each operand that appears
13257 // // in the replacement instruction's match rule
13258 //
13259 // ---------VM FLAGS---------------------------------------------------------
13260 //
13261 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13262 //
13263 // Each peephole rule is given an identifying number starting with zero and
13264 // increasing by one in the order seen by the parser. An individual peephole
13265 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13266 // on the command-line.
13267 //
13268 // ---------CURRENT LIMITATIONS----------------------------------------------
13269 //
13270 // Only match adjacent instructions in same basic block
13271 // Only equality constraints
13272 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13273 // Only one replacement instruction
13274 //
13275 // ---------EXAMPLE----------------------------------------------------------
13276 //
13277 // // pertinent parts of existing instructions in architecture description
13278 // instruct movI(eRegI dst, eRegI src) %{
13279 // match(Set dst (CopyI src));
13280 // %}
13281 //
13282 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13283 // match(Set dst (AddI dst src));
13284 // effect(KILL cr);
13285 // %}
13286 //
13287 // // Change (inc mov) to lea
13288 // peephole %{
13289 // // increment preceeded by register-register move
13290 // peepmatch ( incI_eReg movI );
13291 // // require that the destination register of the increment
13292 // // match the destination register of the move
13293 // peepconstraint ( 0.dst == 1.dst );
13294 // // construct a replacement instruction that sets
13295 // // the destination to ( move's source register + one )
13296 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13297 // %}
13298 //
13299 // Implementation no longer uses movX instructions since
13300 // machine-independent system no longer uses CopyX nodes.
13301 //
13302 // peephole %{
13303 // peepmatch ( incI_eReg movI );
13304 // peepconstraint ( 0.dst == 1.dst );
13305 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13306 // %}
13307 //
13308 // peephole %{
13309 // peepmatch ( decI_eReg movI );
13310 // peepconstraint ( 0.dst == 1.dst );
13311 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13312 // %}
13313 //
13314 // peephole %{
13315 // peepmatch ( addI_eReg_imm movI );
13316 // peepconstraint ( 0.dst == 1.dst );
13317 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13318 // %}
13319 //
13320 // peephole %{
13321 // peepmatch ( addP_eReg_imm movP );
13322 // peepconstraint ( 0.dst == 1.dst );
13323 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13324 // %}
13326 // // Change load of spilled value to only a spill
13327 // instruct storeI(memory mem, eRegI src) %{
13328 // match(Set mem (StoreI mem src));
13329 // %}
13330 //
13331 // instruct loadI(eRegI dst, memory mem) %{
13332 // match(Set dst (LoadI mem));
13333 // %}
13334 //
13335 peephole %{
13336 peepmatch ( loadI storeI );
13337 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13338 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13339 %}
13341 //----------SMARTSPILL RULES---------------------------------------------------
13342 // These must follow all instruction definitions as they use the names
13343 // defined in the instructions definitions.