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src/share/vm/c1/c1_LIR.cpp@8843990f569c
src/share/vm/c1/c1_LIR.cpp
Thu, 16 Aug 2018 15:34:19 +0800
- author
- fujie
- date
- Thu, 16 Aug 2018 15:34:19 +0800
- changeset 9215
- 8843990f569c
- parent 9214
- 950e185f5ded
- child 9249
- 8401c6dc109a
- permissions
- -rw-r--r--
#7407 [C1] enable adjusted EdgeMoveOptimizer::optimize for mips
Summary:bool LIR_OprDesc::has_common_register(LIR_Opr opr) should return true for [t1t1|J] and [t1|I].
1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 /*
26 * This file has been modified by Loongson Technology in 2015, 2018. These
27 * modifications are Copyright (c) 2015, 2018 Loongson Technology, and are made
28 * available on the same license terms set forth above.
29 */
31 #include "precompiled.hpp"
32 #include "c1/c1_InstructionPrinter.hpp"
33 #include "c1/c1_LIR.hpp"
34 #include "c1/c1_LIRAssembler.hpp"
35 #include "c1/c1_ValueStack.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "runtime/sharedRuntime.hpp"
39 Register LIR_OprDesc::as_register() const {
40 return FrameMap::cpu_rnr2reg(cpu_regnr());
41 }
43 Register LIR_OprDesc::as_register_lo() const {
44 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
45 }
47 Register LIR_OprDesc::as_register_hi() const {
48 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
49 }
51 #if defined(X86)
53 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
54 return FrameMap::nr2xmmreg(xmm_regnr());
55 }
57 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
58 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
59 return FrameMap::nr2xmmreg(xmm_regnrLo());
60 }
62 #endif // X86
64 #if defined(SPARC) || defined(PPC) || defined(MIPS)
66 FloatRegister LIR_OprDesc::as_float_reg() const {
67 return FrameMap::nr2floatreg(fpu_regnr());
68 }
70 FloatRegister LIR_OprDesc::as_double_reg() const {
71 return FrameMap::nr2floatreg(fpu_regnrHi());
72 }
74 #endif
76 #ifdef ARM
78 FloatRegister LIR_OprDesc::as_float_reg() const {
79 return as_FloatRegister(fpu_regnr());
80 }
82 FloatRegister LIR_OprDesc::as_double_reg() const {
83 return as_FloatRegister(fpu_regnrLo());
84 }
86 #endif
89 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
91 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
92 ValueTag tag = type->tag();
93 switch (tag) {
94 case metaDataTag : {
95 ClassConstant* c = type->as_ClassConstant();
96 if (c != NULL && !c->value()->is_loaded()) {
97 return LIR_OprFact::metadataConst(NULL);
98 } else if (c != NULL) {
99 return LIR_OprFact::metadataConst(c->value()->constant_encoding());
100 } else {
101 MethodConstant* m = type->as_MethodConstant();
102 assert (m != NULL, "not a class or a method?");
103 return LIR_OprFact::metadataConst(m->value()->constant_encoding());
104 }
105 }
106 case objectTag : {
107 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
108 }
109 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
110 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
111 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
112 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
113 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
114 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
115 }
116 }
119 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
120 switch (type->tag()) {
121 case objectTag: return LIR_OprFact::oopConst(NULL);
122 case addressTag:return LIR_OprFact::addressConst(0);
123 case intTag: return LIR_OprFact::intConst(0);
124 case floatTag: return LIR_OprFact::floatConst(0.0);
125 case longTag: return LIR_OprFact::longConst(0);
126 case doubleTag: return LIR_OprFact::doubleConst(0.0);
127 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
128 }
129 return illegalOpr;
130 }
134 //---------------------------------------------------
137 LIR_Address::Scale LIR_Address::scale(BasicType type) {
138 int elem_size = type2aelembytes(type);
139 switch (elem_size) {
140 case 1: return LIR_Address::times_1;
141 case 2: return LIR_Address::times_2;
142 case 4: return LIR_Address::times_4;
143 case 8: return LIR_Address::times_8;
144 }
145 ShouldNotReachHere();
146 return LIR_Address::times_1;
147 }
150 #ifndef PRODUCT
151 void LIR_Address::verify0() const {
152 #if defined(SPARC) || defined(PPC) || defined(MIPS)
153 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
154 assert(disp() == 0 || index()->is_illegal(), "can't have both");
155 #endif
156 #ifdef _LP64
157 assert(base()->is_cpu_register(), "wrong base operand");
158 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
159 #ifndef MIPS
160 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
161 "wrong type for addresses");
162 #endif
163 #else
164 assert(base()->is_single_cpu(), "wrong base operand");
165 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
166 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
167 "wrong type for addresses");
168 #endif
169 }
170 #endif
173 //---------------------------------------------------
175 char LIR_OprDesc::type_char(BasicType t) {
176 switch (t) {
177 case T_ARRAY:
178 t = T_OBJECT;
179 case T_BOOLEAN:
180 case T_CHAR:
181 case T_FLOAT:
182 case T_DOUBLE:
183 case T_BYTE:
184 case T_SHORT:
185 case T_INT:
186 case T_LONG:
187 case T_OBJECT:
188 case T_ADDRESS:
189 case T_VOID:
190 return ::type2char(t);
191 case T_METADATA:
192 return 'M';
193 case T_ILLEGAL:
194 return '?';
196 default:
197 ShouldNotReachHere();
198 return '?';
199 }
200 }
202 #ifndef PRODUCT
203 void LIR_OprDesc::validate_type() const {
205 #ifdef ASSERT
206 if (!is_pointer() && !is_illegal()) {
207 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
208 switch (as_BasicType(type_field())) {
209 case T_LONG:
210 assert((kindfield == cpu_register || kindfield == stack_value) &&
211 size_field() == double_size, "must match");
212 break;
213 case T_FLOAT:
214 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
215 assert((kindfield == fpu_register || kindfield == stack_value
216 ARM_ONLY(|| kindfield == cpu_register)
217 PPC_ONLY(|| kindfield == cpu_register) ) &&
218 size_field() == single_size, "must match");
219 break;
220 case T_DOUBLE:
221 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
222 assert((kindfield == fpu_register || kindfield == stack_value
223 ARM_ONLY(|| kindfield == cpu_register)
224 PPC_ONLY(|| kindfield == cpu_register) ) &&
225 size_field() == double_size, "must match");
226 break;
227 case T_BOOLEAN:
228 case T_CHAR:
229 case T_BYTE:
230 case T_SHORT:
231 case T_INT:
232 case T_ADDRESS:
233 case T_OBJECT:
234 case T_METADATA:
235 case T_ARRAY:
236 assert((kindfield == cpu_register || kindfield == stack_value) &&
237 size_field() == single_size, "must match");
238 break;
240 case T_ILLEGAL:
241 // XXX TKR also means unknown right now
242 // assert(is_illegal(), "must match");
243 break;
245 default:
246 ShouldNotReachHere();
247 }
248 }
249 #endif
251 }
252 #endif // PRODUCT
255 bool LIR_OprDesc::is_oop() const {
256 if (is_pointer()) {
257 return pointer()->is_oop_pointer();
258 } else {
259 OprType t= type_field();
260 assert(t != unknown_type, "not set");
261 return t == object_type;
262 }
263 }
265 #ifdef MIPS
266 bool LIR_OprDesc::has_common_register(LIR_Opr opr) const {
267 if (!(is_register() && opr->is_register())) return false;
269 if (is_single_cpu()) {
270 if (opr->is_single_cpu()) {
271 return as_register() == opr->as_register();
272 } else if (opr->is_double_cpu()) {
273 Register dst = as_register();
274 Register lo = opr->as_register_lo();
275 #ifdef _LP64
276 if (dst == lo) return true;
277 #else
278 Register hi = opr->as_register_hi();
279 if (dst == lo || dst == hi) return true;
280 #endif
281 }
283 } else if (is_double_cpu()) {
284 Register dst_lo = as_register_lo();
285 #ifndef _LP64
286 Register dst_hi = as_register_hi();
287 #endif
289 if (opr->is_single_cpu()) {
290 Register src = opr->as_register();
291 #ifndef _LP64
292 if (dst_lo == src || dst_hi == src) return true;
293 #else
294 if (dst_lo == src) return true;
295 #endif
296 } else if (opr->is_double_cpu()) {
297 Register src_lo = opr->as_register_lo();
298 #ifndef _LP64
299 Register src_hi = opr->as_register_hi();
300 if (dst_lo == src_lo ||
301 dst_lo == src_hi ||
302 dst_hi == src_lo ||
303 dst_hi == src_hi) return true;
304 #else
305 if (dst_lo == src_lo) return true;
306 #endif
307 }
308 }
309 return false;
310 }
311 #endif
313 void LIR_Op2::verify() const {
314 #ifdef ASSERT
315 switch (code()) {
316 case lir_cmove:
317 case lir_xchg:
318 break;
320 default:
321 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
322 "can't produce oops from arith");
323 }
325 if (TwoOperandLIRForm) {
326 switch (code()) {
327 case lir_add:
328 case lir_sub:
329 case lir_mul:
330 case lir_mul_strictfp:
331 case lir_div:
332 case lir_div_strictfp:
333 case lir_rem:
334 case lir_logic_and:
335 case lir_logic_or:
336 case lir_logic_xor:
337 case lir_shl:
338 case lir_shr:
339 assert(in_opr1() == result_opr(), "opr1 and result must match");
340 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
341 break;
343 // special handling for lir_ushr because of write barriers
344 case lir_ushr:
345 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
346 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
347 break;
349 }
350 }
351 #endif
352 }
355 #ifndef MIPS
356 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
357 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
358 , _cond(cond)
359 , _type(type)
360 , _label(block->label())
361 , _block(block)
362 , _ublock(NULL)
363 , _stub(NULL) {
364 }
366 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
367 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
368 , _cond(cond)
369 , _type(type)
370 , _label(stub->entry())
371 , _block(NULL)
372 , _ublock(NULL)
373 , _stub(stub) {
374 }
376 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
377 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
378 , _cond(cond)
379 , _type(type)
380 , _label(block->label())
381 , _block(block)
382 , _ublock(ublock)
383 , _stub(NULL)
384 {
385 }
387 #else
388 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
389 BlockBegin* block):
390 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
391 _cond(cond),
392 _type(type),
393 _label(block->label()),
394 _block(block),
395 _ublock(NULL),
396 _stub(NULL) {
397 }
399 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
400 CodeStub* stub):
401 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
402 _cond(cond),
403 _type(type),
404 _label(stub->entry()),
405 _block(NULL),
406 _ublock(NULL),
407 _stub(stub) {
408 }
411 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
412 BlockBegin *block, BlockBegin *ublock):
413 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
414 _cond(cond),
415 _type(type),
416 _label(block->label()),
417 _block(block),
418 _ublock(ublock),
419 _stub(NULL) {
420 }
422 #endif
423 void LIR_OpBranch::change_block(BlockBegin* b) {
424 assert(_block != NULL, "must have old block");
425 assert(_block->label() == label(), "must be equal");
427 _block = b;
428 _label = b->label();
429 }
431 void LIR_OpBranch::change_ublock(BlockBegin* b) {
432 assert(_ublock != NULL, "must have old block");
433 _ublock = b;
434 }
436 void LIR_OpBranch::negate_cond() {
437 switch (_cond) {
438 case lir_cond_equal: _cond = lir_cond_notEqual; break;
439 case lir_cond_notEqual: _cond = lir_cond_equal; break;
440 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
441 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
442 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
443 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
444 default: ShouldNotReachHere();
445 }
446 }
449 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
450 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
451 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
452 CodeStub* stub)
454 : LIR_Op(code, result, NULL)
455 , _object(object)
456 , _array(LIR_OprFact::illegalOpr)
457 , _klass(klass)
458 , _tmp1(tmp1)
459 , _tmp2(tmp2)
460 , _tmp3(tmp3)
461 , _fast_check(fast_check)
462 , _stub(stub)
463 , _info_for_patch(info_for_patch)
464 , _info_for_exception(info_for_exception)
465 , _profiled_method(NULL)
466 , _profiled_bci(-1)
467 , _should_profile(false)
468 {
469 if (code == lir_checkcast) {
470 assert(info_for_exception != NULL, "checkcast throws exceptions");
471 } else if (code == lir_instanceof) {
472 assert(info_for_exception == NULL, "instanceof throws no exceptions");
473 } else {
474 ShouldNotReachHere();
475 }
476 }
480 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
481 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
482 , _object(object)
483 , _array(array)
484 , _klass(NULL)
485 , _tmp1(tmp1)
486 , _tmp2(tmp2)
487 , _tmp3(tmp3)
488 , _fast_check(false)
489 , _stub(NULL)
490 , _info_for_patch(NULL)
491 , _info_for_exception(info_for_exception)
492 , _profiled_method(NULL)
493 , _profiled_bci(-1)
494 , _should_profile(false)
495 {
496 if (code == lir_store_check) {
497 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
498 assert(info_for_exception != NULL, "store_check throws exceptions");
499 } else {
500 ShouldNotReachHere();
501 }
502 }
505 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
506 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
507 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
508 , _tmp(tmp)
509 , _src(src)
510 , _src_pos(src_pos)
511 , _dst(dst)
512 , _dst_pos(dst_pos)
513 , _flags(flags)
514 , _expected_type(expected_type)
515 , _length(length) {
516 _stub = new ArrayCopyStub(this);
517 }
519 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res)
520 : LIR_Op(lir_updatecrc32, res, NULL)
521 , _crc(crc)
522 , _val(val) {
523 }
525 //-------------------verify--------------------------
527 void LIR_Op1::verify() const {
528 switch(code()) {
529 case lir_move:
530 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
531 break;
532 case lir_null_check:
533 assert(in_opr()->is_register(), "must be");
534 break;
535 case lir_return:
536 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
537 break;
538 }
539 }
541 void LIR_OpRTCall::verify() const {
542 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
543 }
545 //-------------------visits--------------------------
547 // complete rework of LIR instruction visitor.
548 // The virtual call for each instruction type is replaced by a big
549 // switch that adds the operands for each instruction
551 void LIR_OpVisitState::visit(LIR_Op* op) {
552 // copy information from the LIR_Op
553 reset();
554 set_op(op);
556 switch (op->code()) {
558 // LIR_Op0
559 case lir_word_align: // result and info always invalid
560 case lir_backwardbranch_target: // result and info always invalid
561 case lir_build_frame: // result and info always invalid
562 case lir_fpop_raw: // result and info always invalid
563 case lir_24bit_FPU: // result and info always invalid
564 case lir_reset_FPU: // result and info always invalid
565 case lir_breakpoint: // result and info always invalid
566 case lir_membar: // result and info always invalid
567 case lir_membar_acquire: // result and info always invalid
568 case lir_membar_release: // result and info always invalid
569 case lir_membar_loadload: // result and info always invalid
570 case lir_membar_storestore: // result and info always invalid
571 case lir_membar_loadstore: // result and info always invalid
572 case lir_membar_storeload: // result and info always invalid
573 {
574 assert(op->as_Op0() != NULL, "must be");
575 assert(op->_info == NULL, "info not used by this instruction");
576 assert(op->_result->is_illegal(), "not used");
577 break;
578 }
580 case lir_nop: // may have info, result always invalid
581 case lir_std_entry: // may have result, info always invalid
582 case lir_osr_entry: // may have result, info always invalid
583 case lir_get_thread: // may have result, info always invalid
584 {
585 assert(op->as_Op0() != NULL, "must be");
586 if (op->_info != NULL) do_info(op->_info);
587 if (op->_result->is_valid()) do_output(op->_result);
588 break;
589 }
592 // LIR_OpLabel
593 case lir_label: // result and info always invalid
594 {
595 assert(op->as_OpLabel() != NULL, "must be");
596 assert(op->_info == NULL, "info not used by this instruction");
597 assert(op->_result->is_illegal(), "not used");
598 break;
599 }
602 // LIR_Op1
603 case lir_fxch: // input always valid, result and info always invalid
604 case lir_fld: // input always valid, result and info always invalid
605 case lir_ffree: // input always valid, result and info always invalid
606 case lir_push: // input always valid, result and info always invalid
607 case lir_pop: // input always valid, result and info always invalid
608 case lir_return: // input always valid, result and info always invalid
609 case lir_leal: // input and result always valid, info always invalid
610 case lir_neg: // input and result always valid, info always invalid
611 case lir_monaddr: // input and result always valid, info always invalid
612 case lir_null_check: // input and info always valid, result always invalid
613 case lir_move: // input and result always valid, may have info
614 case lir_pack64: // input and result always valid
615 case lir_unpack64: // input and result always valid
616 case lir_prefetchr: // input always valid, result and info always invalid
617 case lir_prefetchw: // input always valid, result and info always invalid
618 {
619 assert(op->as_Op1() != NULL, "must be");
620 LIR_Op1* op1 = (LIR_Op1*)op;
622 if (op1->_info) do_info(op1->_info);
623 if (op1->_opr->is_valid()) do_input(op1->_opr);
624 if (op1->_result->is_valid()) do_output(op1->_result);
626 break;
627 }
629 case lir_safepoint:
630 {
631 assert(op->as_Op1() != NULL, "must be");
632 LIR_Op1* op1 = (LIR_Op1*)op;
634 assert(op1->_info != NULL, ""); do_info(op1->_info);
635 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
636 assert(op1->_result->is_illegal(), "safepoint does not produce value");
638 break;
639 }
641 // LIR_OpConvert;
642 case lir_convert: // input and result always valid, info always invalid
643 {
644 assert(op->as_OpConvert() != NULL, "must be");
645 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
647 assert(opConvert->_info == NULL, "must be");
648 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
649 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
650 #ifdef PPC
651 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
652 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
653 #endif
654 do_stub(opConvert->_stub);
656 break;
657 }
659 // LIR_OpBranch;
660 case lir_branch: // may have info, input and result register always invalid
661 case lir_cond_float_branch: // may have info, input and result register always invalid
662 {
663 assert(op->as_OpBranch() != NULL, "must be");
664 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
666 #ifdef MIPS
667 if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
668 if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
669 if (opBranch->_tmp1->is_valid()) do_temp(opBranch->_tmp1);
670 if (opBranch->_tmp2->is_valid()) do_temp(opBranch->_tmp2);
671 if (opBranch->_tmp3->is_valid()) do_temp(opBranch->_tmp3);
672 if (opBranch->_tmp4->is_valid()) do_temp(opBranch->_tmp4);
673 if (opBranch->_tmp5->is_valid()) do_temp(opBranch->_tmp5);
674 #endif
675 if (opBranch->_info != NULL) do_info(opBranch->_info);
676 assert(opBranch->_result->is_illegal(), "not used");
677 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
679 break;
680 }
682 #ifdef MIPS
683 case lir_cmove_mips:
684 {
685 assert(op->as_Op4() != NULL, "must be");
686 LIR_Op4* op4 = (LIR_Op4*)op;
688 assert(op4->_info == NULL, "must be");
689 assert(op4->_opr1->is_valid() && op4->_opr2->is_valid() && op4->_opr3->is_valid() && op4->_opr4->is_valid() && op4->_result->is_valid(), "used");
691 do_input(op4->_opr1);
692 do_input(op4->_opr2);
693 do_input(op4->_opr3);
694 do_input(op4->_opr4);
695 if (op4->_tmp1->is_valid()) do_temp(op4->_tmp1);
696 if (op4->_tmp2->is_valid()) do_temp(op4->_tmp2);
697 if (op4->_tmp3->is_valid()) do_temp(op4->_tmp3);
698 if (op4->_tmp4->is_valid()) do_temp(op4->_tmp4);
699 if (op4->_tmp5->is_valid()) do_temp(op4->_tmp5);
700 do_output(op4->_result);
702 break;
703 }
704 #endif
706 // LIR_OpAllocObj
707 case lir_alloc_object:
708 {
709 assert(op->as_OpAllocObj() != NULL, "must be");
710 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
712 if (opAllocObj->_info) do_info(opAllocObj->_info);
713 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
714 do_temp(opAllocObj->_opr);
715 }
716 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
717 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
718 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
719 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
720 #ifdef MIPS
721 if (opAllocObj->_tmp5->is_valid()) do_temp(opAllocObj->_tmp5);
722 if (opAllocObj->_tmp6->is_valid()) do_temp(opAllocObj->_tmp6);
723 #endif
724 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
725 do_stub(opAllocObj->_stub);
726 break;
727 }
730 // LIR_OpRoundFP;
731 case lir_roundfp: {
732 assert(op->as_OpRoundFP() != NULL, "must be");
733 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
735 assert(op->_info == NULL, "info not used by this instruction");
736 assert(opRoundFP->_tmp->is_illegal(), "not used");
737 do_input(opRoundFP->_opr);
738 do_output(opRoundFP->_result);
740 break;
741 }
744 // LIR_Op2
745 #ifdef MIPS
746 case lir_null_check_for_branch:
747 #else
748 case lir_cmp:
749 #endif
750 case lir_cmp_l2i:
751 case lir_ucmp_fd2i:
752 case lir_cmp_fd2i:
753 case lir_add:
754 case lir_sub:
755 case lir_mul:
756 case lir_div:
757 case lir_rem:
758 case lir_sqrt:
759 case lir_abs:
760 case lir_logic_and:
761 case lir_logic_or:
762 case lir_logic_xor:
763 case lir_shl:
764 case lir_shr:
765 case lir_ushr:
766 case lir_xadd:
767 case lir_xchg:
768 case lir_assert:
769 {
770 assert(op->as_Op2() != NULL, "must be");
771 LIR_Op2* op2 = (LIR_Op2*)op;
772 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
773 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
775 if (op2->_info) do_info(op2->_info);
776 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
777 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
778 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
779 if (op2->_result->is_valid()) do_output(op2->_result);
780 if (op->code() == lir_xchg || op->code() == lir_xadd) {
781 // on ARM and PPC, return value is loaded first so could
782 // destroy inputs. On other platforms that implement those
783 // (x86, sparc), the extra constrainsts are harmless.
784 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
785 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
786 }
788 break;
789 }
791 // special handling for cmove: right input operand must not be equal
792 // to the result operand, otherwise the backend fails
793 case lir_cmove:
794 {
795 assert(op->as_Op2() != NULL, "must be");
796 LIR_Op2* op2 = (LIR_Op2*)op;
798 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
799 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
800 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
802 do_input(op2->_opr1);
803 do_input(op2->_opr2);
804 do_temp(op2->_opr2);
805 do_output(op2->_result);
807 break;
808 }
810 // vspecial handling for strict operations: register input operands
811 // as temp to guarantee that they do not overlap with other
812 // registers
813 case lir_mul_strictfp:
814 case lir_div_strictfp:
815 {
816 assert(op->as_Op2() != NULL, "must be");
817 LIR_Op2* op2 = (LIR_Op2*)op;
819 assert(op2->_info == NULL, "not used");
820 assert(op2->_opr1->is_valid(), "used");
821 assert(op2->_opr2->is_valid(), "used");
822 assert(op2->_result->is_valid(), "used");
823 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
824 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
826 do_input(op2->_opr1); do_temp(op2->_opr1);
827 do_input(op2->_opr2); do_temp(op2->_opr2);
828 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
829 do_output(op2->_result);
831 break;
832 }
834 case lir_throw: {
835 assert(op->as_Op2() != NULL, "must be");
836 LIR_Op2* op2 = (LIR_Op2*)op;
838 if (op2->_info) do_info(op2->_info);
839 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
840 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
841 assert(op2->_result->is_illegal(), "no result");
842 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
843 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
845 break;
846 }
848 case lir_unwind: {
849 assert(op->as_Op1() != NULL, "must be");
850 LIR_Op1* op1 = (LIR_Op1*)op;
852 assert(op1->_info == NULL, "no info");
853 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
854 assert(op1->_result->is_illegal(), "no result");
856 break;
857 }
860 case lir_tan:
861 case lir_sin:
862 case lir_cos:
863 case lir_log:
864 case lir_log10:
865 case lir_exp: {
866 assert(op->as_Op2() != NULL, "must be");
867 LIR_Op2* op2 = (LIR_Op2*)op;
869 // On x86 tan/sin/cos need two temporary fpu stack slots and
870 // log/log10 need one so handle opr2 and tmp as temp inputs.
871 // Register input operand as temp to guarantee that it doesn't
872 // overlap with the input.
873 assert(op2->_info == NULL, "not used");
874 assert(op2->_tmp5->is_illegal(), "not used");
875 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used");
876 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used");
877 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used");
878 assert(op2->_opr1->is_valid(), "used");
879 do_input(op2->_opr1); do_temp(op2->_opr1);
881 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
882 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
883 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2);
884 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3);
885 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4);
886 if (op2->_result->is_valid()) do_output(op2->_result);
888 break;
889 }
891 case lir_pow: {
892 assert(op->as_Op2() != NULL, "must be");
893 LIR_Op2* op2 = (LIR_Op2*)op;
895 // On x86 pow needs two temporary fpu stack slots: tmp1 and
896 // tmp2. Register input operands as temps to guarantee that it
897 // doesn't overlap with the temporary slots.
898 assert(op2->_info == NULL, "not used");
899 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used");
900 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid()
901 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used");
902 assert(op2->_result->is_valid(), "used");
904 do_input(op2->_opr1); do_temp(op2->_opr1);
905 do_input(op2->_opr2); do_temp(op2->_opr2);
906 do_temp(op2->_tmp1);
907 do_temp(op2->_tmp2);
908 do_temp(op2->_tmp3);
909 do_temp(op2->_tmp4);
910 do_temp(op2->_tmp5);
911 do_output(op2->_result);
913 break;
914 }
916 // LIR_Op3
917 #ifdef MIPS
918 case lir_frem:
919 #endif
920 case lir_idiv:
921 case lir_irem: {
922 assert(op->as_Op3() != NULL, "must be");
923 LIR_Op3* op3= (LIR_Op3*)op;
925 if (op3->_info) do_info(op3->_info);
926 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
928 // second operand is input and temp, so ensure that second operand
929 // and third operand get not the same register
930 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
931 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
932 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
934 if (op3->_result->is_valid()) do_output(op3->_result);
936 break;
937 }
940 // LIR_OpJavaCall
941 case lir_static_call:
942 case lir_optvirtual_call:
943 case lir_icvirtual_call:
944 case lir_virtual_call:
945 case lir_dynamic_call: {
946 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
947 assert(opJavaCall != NULL, "must be");
949 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
951 // only visit register parameters
952 int n = opJavaCall->_arguments->length();
953 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
954 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
955 do_input(*opJavaCall->_arguments->adr_at(i));
956 }
957 }
959 if (opJavaCall->_info) do_info(opJavaCall->_info);
960 if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr &&
961 opJavaCall->is_method_handle_invoke()) {
962 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
963 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
964 }
965 do_call();
966 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
968 break;
969 }
972 // LIR_OpRTCall
973 case lir_rtcall: {
974 assert(op->as_OpRTCall() != NULL, "must be");
975 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
977 // only visit register parameters
978 int n = opRTCall->_arguments->length();
979 for (int i = 0; i < n; i++) {
980 if (!opRTCall->_arguments->at(i)->is_pointer()) {
981 do_input(*opRTCall->_arguments->adr_at(i));
982 }
983 }
984 if (opRTCall->_info) do_info(opRTCall->_info);
985 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
986 do_call();
987 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
989 break;
990 }
993 // LIR_OpArrayCopy
994 case lir_arraycopy: {
995 assert(op->as_OpArrayCopy() != NULL, "must be");
996 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
998 assert(opArrayCopy->_result->is_illegal(), "unused");
999 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
1000 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
1001 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
1002 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
1003 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
1004 #ifndef MIPS
1005 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
1006 #endif
1007 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
1009 // the implementation of arraycopy always has a call into the runtime
1010 do_call();
1012 break;
1013 }
1016 // LIR_OpUpdateCRC32
1017 case lir_updatecrc32: {
1018 assert(op->as_OpUpdateCRC32() != NULL, "must be");
1019 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op;
1021 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc);
1022 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val);
1023 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result);
1024 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
1026 break;
1027 }
1030 // LIR_OpLock
1031 case lir_lock:
1032 case lir_unlock: {
1033 assert(op->as_OpLock() != NULL, "must be");
1034 LIR_OpLock* opLock = (LIR_OpLock*)op;
1036 if (opLock->_info) do_info(opLock->_info);
1038 // TODO: check if these operands really have to be temp
1039 // (or if input is sufficient). This may have influence on the oop map!
1040 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
1041 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
1042 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
1044 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
1045 assert(opLock->_result->is_illegal(), "unused");
1047 do_stub(opLock->_stub);
1049 break;
1050 }
1053 // LIR_OpDelay
1054 case lir_delay_slot: {
1055 assert(op->as_OpDelay() != NULL, "must be");
1056 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
1058 visit(opDelay->delay_op());
1059 break;
1060 }
1062 // LIR_OpTypeCheck
1063 case lir_instanceof:
1064 case lir_checkcast:
1065 case lir_store_check: {
1066 assert(op->as_OpTypeCheck() != NULL, "must be");
1067 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
1069 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
1070 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
1071 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
1072 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
1073 do_temp(opTypeCheck->_object);
1074 }
1075 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
1076 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
1077 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
1078 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
1079 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
1080 do_stub(opTypeCheck->_stub);
1081 break;
1082 }
1084 // LIR_OpCompareAndSwap
1085 case lir_cas_long:
1086 case lir_cas_obj:
1087 case lir_cas_int: {
1088 assert(op->as_OpCompareAndSwap() != NULL, "must be");
1089 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
1091 assert(opCompareAndSwap->_addr->is_valid(), "used");
1092 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
1093 assert(opCompareAndSwap->_new_value->is_valid(), "used");
1094 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
1095 do_input(opCompareAndSwap->_addr);
1096 do_temp(opCompareAndSwap->_addr);
1097 do_input(opCompareAndSwap->_cmp_value);
1098 do_temp(opCompareAndSwap->_cmp_value);
1099 do_input(opCompareAndSwap->_new_value);
1100 do_temp(opCompareAndSwap->_new_value);
1101 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
1102 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
1103 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
1105 break;
1106 }
1109 // LIR_OpAllocArray;
1110 case lir_alloc_array: {
1111 assert(op->as_OpAllocArray() != NULL, "must be");
1112 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
1114 if (opAllocArray->_info) do_info(opAllocArray->_info);
1115 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
1116 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
1117 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
1118 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
1119 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
1120 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
1121 #ifdef MIPS
1122 if (opAllocArray->_tmp5->is_valid()) do_temp(opAllocArray->_tmp5);
1123 #endif
1124 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
1125 do_stub(opAllocArray->_stub);
1126 break;
1127 }
1129 // LIR_OpProfileCall:
1130 case lir_profile_call: {
1131 assert(op->as_OpProfileCall() != NULL, "must be");
1132 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
1134 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
1135 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
1136 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
1137 break;
1138 }
1140 // LIR_OpProfileType:
1141 case lir_profile_type: {
1142 assert(op->as_OpProfileType() != NULL, "must be");
1143 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op;
1145 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp);
1146 do_input(opProfileType->_obj);
1147 do_temp(opProfileType->_tmp);
1148 break;
1149 }
1150 default:
1151 ShouldNotReachHere();
1152 }
1153 }
1156 void LIR_OpVisitState::do_stub(CodeStub* stub) {
1157 if (stub != NULL) {
1158 stub->visit(this);
1159 }
1160 }
1162 XHandlers* LIR_OpVisitState::all_xhandler() {
1163 XHandlers* result = NULL;
1165 int i;
1166 for (i = 0; i < info_count(); i++) {
1167 if (info_at(i)->exception_handlers() != NULL) {
1168 result = info_at(i)->exception_handlers();
1169 break;
1170 }
1171 }
1173 #ifdef ASSERT
1174 for (i = 0; i < info_count(); i++) {
1175 assert(info_at(i)->exception_handlers() == NULL ||
1176 info_at(i)->exception_handlers() == result,
1177 "only one xhandler list allowed per LIR-operation");
1178 }
1179 #endif
1181 if (result != NULL) {
1182 return result;
1183 } else {
1184 return new XHandlers();
1185 }
1187 return result;
1188 }
1191 #ifdef ASSERT
1192 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1193 visit(op);
1195 return opr_count(inputMode) == 0 &&
1196 opr_count(outputMode) == 0 &&
1197 opr_count(tempMode) == 0 &&
1198 info_count() == 0 &&
1199 !has_call() &&
1200 !has_slow_case();
1201 }
1202 #endif
1204 //---------------------------------------------------
1207 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1208 masm->emit_call(this);
1209 }
1211 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1212 masm->emit_rtcall(this);
1213 }
1215 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1216 masm->emit_opLabel(this);
1217 }
1219 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1220 masm->emit_arraycopy(this);
1221 masm->append_code_stub(stub());
1222 }
1224 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) {
1225 masm->emit_updatecrc32(this);
1226 }
1228 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1229 masm->emit_op0(this);
1230 }
1232 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1233 masm->emit_op1(this);
1234 }
1236 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1237 masm->emit_alloc_obj(this);
1238 masm->append_code_stub(stub());
1239 }
1241 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1242 masm->emit_opBranch(this);
1243 if (stub()) {
1244 masm->append_code_stub(stub());
1245 }
1246 }
1248 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1249 masm->emit_opConvert(this);
1250 if (stub() != NULL) {
1251 masm->append_code_stub(stub());
1252 }
1253 }
1255 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1256 masm->emit_op2(this);
1257 }
1259 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1260 masm->emit_alloc_array(this);
1261 masm->append_code_stub(stub());
1262 }
1264 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1265 masm->emit_opTypeCheck(this);
1266 if (stub()) {
1267 masm->append_code_stub(stub());
1268 }
1269 }
1271 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1272 masm->emit_compare_and_swap(this);
1273 }
1275 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1276 masm->emit_op3(this);
1277 }
1279 #ifdef MIPS
1280 void LIR_Op4::emit_code(LIR_Assembler* masm) {
1281 masm->emit_op4(this);
1282 }
1283 #endif
1285 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1286 masm->emit_lock(this);
1287 if (stub()) {
1288 masm->append_code_stub(stub());
1289 }
1290 }
1292 #ifdef ASSERT
1293 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1294 masm->emit_assert(this);
1295 }
1296 #endif
1298 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1299 masm->emit_delay(this);
1300 }
1302 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1303 masm->emit_profile_call(this);
1304 }
1306 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1307 masm->emit_profile_type(this);
1308 }
1310 // LIR_List
1311 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1312 : _operations(8)
1313 , _compilation(compilation)
1314 #ifndef PRODUCT
1315 , _block(block)
1316 #endif
1317 #ifdef ASSERT
1318 , _file(NULL)
1319 , _line(0)
1320 #endif
1321 { }
1324 #ifdef ASSERT
1325 void LIR_List::set_file_and_line(const char * file, int line) {
1326 const char * f = strrchr(file, '/');
1327 if (f == NULL) f = strrchr(file, '\\');
1328 if (f == NULL) {
1329 f = file;
1330 } else {
1331 f++;
1332 }
1333 _file = f;
1334 _line = line;
1335 }
1336 #endif
1339 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1340 assert(this == buffer->lir_list(), "wrong lir list");
1341 const int n = _operations.length();
1343 if (buffer->number_of_ops() > 0) {
1344 // increase size of instructions list
1345 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1346 // insert ops from buffer into instructions list
1347 int op_index = buffer->number_of_ops() - 1;
1348 int ip_index = buffer->number_of_insertion_points() - 1;
1349 int from_index = n - 1;
1350 int to_index = _operations.length() - 1;
1351 for (; ip_index >= 0; ip_index --) {
1352 int index = buffer->index_at(ip_index);
1353 // make room after insertion point
1354 while (index < from_index) {
1355 _operations.at_put(to_index --, _operations.at(from_index --));
1356 }
1357 // insert ops from buffer
1358 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1359 _operations.at_put(to_index --, buffer->op_at(op_index --));
1360 }
1361 }
1362 }
1364 buffer->finish();
1365 }
1368 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1369 assert(reg->type() == T_OBJECT, "bad reg");
1370 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1371 }
1373 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1374 assert(reg->type() == T_METADATA, "bad reg");
1375 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1376 }
1378 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1379 append(new LIR_Op1(
1380 lir_move,
1381 LIR_OprFact::address(addr),
1382 src,
1383 addr->type(),
1384 patch_code,
1385 info));
1386 }
1389 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1390 append(new LIR_Op1(
1391 lir_move,
1392 LIR_OprFact::address(address),
1393 dst,
1394 address->type(),
1395 patch_code,
1396 info, lir_move_volatile));
1397 }
1399 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1400 #ifdef MIPS
1401 add(base, offset, base);
1402 offset = 0;
1403 #endif
1404 append(new LIR_Op1(
1405 lir_move,
1406 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1407 dst,
1408 type,
1409 patch_code,
1410 info, lir_move_volatile));
1411 }
1414 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1415 append(new LIR_Op1(
1416 is_store ? lir_prefetchw : lir_prefetchr,
1417 LIR_OprFact::address(addr)));
1418 }
1421 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1422 append(new LIR_Op1(
1423 lir_move,
1424 LIR_OprFact::intConst(v),
1425 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1426 type,
1427 patch_code,
1428 info));
1429 }
1432 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1433 append(new LIR_Op1(
1434 lir_move,
1435 LIR_OprFact::oopConst(o),
1436 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1437 type,
1438 patch_code,
1439 info));
1440 }
1443 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1444 append(new LIR_Op1(
1445 lir_move,
1446 src,
1447 LIR_OprFact::address(addr),
1448 addr->type(),
1449 patch_code,
1450 info));
1451 }
1454 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1455 append(new LIR_Op1(
1456 lir_move,
1457 src,
1458 LIR_OprFact::address(addr),
1459 addr->type(),
1460 patch_code,
1461 info,
1462 lir_move_volatile));
1463 }
1465 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1466 #ifdef MIPS
1467 add(base, offset, base);
1468 offset = 0;
1469 #endif
1470 append(new LIR_Op1(
1471 lir_move,
1472 src,
1473 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1474 type,
1475 patch_code,
1476 info, lir_move_volatile));
1477 }
1479 #ifdef MIPS
1480 void LIR_List::frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1481 append(new LIR_Op3(
1482 lir_frem,
1483 left,
1484 right,
1485 tmp,
1486 res,
1487 info));
1488 }
1489 #endif
1491 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1492 append(new LIR_Op3(
1493 lir_idiv,
1494 left,
1495 right,
1496 tmp,
1497 res,
1498 info));
1499 }
1502 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1503 append(new LIR_Op3(
1504 lir_idiv,
1505 left,
1506 LIR_OprFact::intConst(right),
1507 tmp,
1508 res,
1509 info));
1510 }
1513 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1514 append(new LIR_Op3(
1515 lir_irem,
1516 left,
1517 right,
1518 tmp,
1519 res,
1520 info));
1521 }
1524 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1525 append(new LIR_Op3(
1526 lir_irem,
1527 left,
1528 LIR_OprFact::intConst(right),
1529 tmp,
1530 res,
1531 info));
1532 }
1535 #ifndef MIPS
1536 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1537 append(new LIR_Op2(
1538 lir_cmp,
1539 condition,
1540 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1541 LIR_OprFact::intConst(c),
1542 info));
1543 }
1545 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1546 append(new LIR_Op2(
1547 lir_cmp,
1548 condition,
1549 reg,
1550 LIR_OprFact::address(addr),
1551 info));
1552 }
1553 #endif
1555 void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) {
1556 if (deoptimize_on_null) {
1557 // Emit an explicit null check and deoptimize if opr is null
1558 CodeStub* deopt = new DeoptimizeStub(info);
1559 #ifndef MIPS
1560 cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1561 branch(lir_cond_equal, T_OBJECT, deopt);
1562 #else
1563 null_check_for_branch(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1564 branch(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL), T_OBJECT, deopt);
1565 #endif
1566 } else {
1567 // Emit an implicit null check
1568 append(new LIR_Op1(lir_null_check, opr, info));
1569 }
1570 }
1572 #ifndef MIPS
1573 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1574 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1575 append(new LIR_OpAllocObj(
1576 klass,
1577 dst,
1578 t1,
1579 t2,
1580 t3,
1581 t4,
1582 header_size,
1583 object_size,
1584 init_check,
1585 stub));
1586 }
1588 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1589 append(new LIR_OpAllocArray(
1590 klass,
1591 len,
1592 dst,
1593 t1,
1594 t2,
1595 t3,
1596 t4,
1597 type,
1598 stub));
1599 }
1600 #else
1601 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, LIR_Opr t5, LIR_Opr t6,
1602 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1603 append(new LIR_OpAllocObj(
1604 klass,
1605 dst,
1606 t1,
1607 t2,
1608 t3,
1609 t4,
1610 t5,
1611 t6,
1612 header_size,
1613 object_size,
1614 init_check,
1615 stub));
1616 }
1617 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, LIR_Opr t5,
1618 BasicType type, LIR_Opr klass, CodeStub* stub) {
1619 append(new LIR_OpAllocArray(
1620 klass,
1621 len,
1622 dst,
1623 t1,
1624 t2,
1625 t3,
1626 t4,
1627 t5,
1628 type,
1629 stub));
1630 }
1632 #endif
1634 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1635 append(new LIR_Op2(
1636 lir_shl,
1637 value,
1638 count,
1639 dst,
1640 tmp));
1641 }
1643 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1644 append(new LIR_Op2(
1645 lir_shr,
1646 value,
1647 count,
1648 dst,
1649 tmp));
1650 }
1653 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1654 append(new LIR_Op2(
1655 lir_ushr,
1656 value,
1657 count,
1658 dst,
1659 tmp));
1660 }
1662 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1663 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1664 left,
1665 right,
1666 dst));
1667 }
1669 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1670 append(new LIR_OpLock(
1671 lir_lock,
1672 hdr,
1673 obj,
1674 lock,
1675 scratch,
1676 stub,
1677 info));
1678 }
1680 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1681 append(new LIR_OpLock(
1682 lir_unlock,
1683 hdr,
1684 obj,
1685 lock,
1686 scratch,
1687 stub,
1688 NULL));
1689 }
1692 void check_LIR() {
1693 // cannot do the proper checking as PRODUCT and other modes return different results
1694 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1695 }
1699 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1700 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1701 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1702 ciMethod* profiled_method, int profiled_bci) {
1703 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1704 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1705 if (profiled_method != NULL) {
1706 c->set_profiled_method(profiled_method);
1707 c->set_profiled_bci(profiled_bci);
1708 c->set_should_profile(true);
1709 }
1710 append(c);
1711 }
1713 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1714 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1715 if (profiled_method != NULL) {
1716 c->set_profiled_method(profiled_method);
1717 c->set_profiled_bci(profiled_bci);
1718 c->set_should_profile(true);
1719 }
1720 append(c);
1721 }
1724 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1725 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1726 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1727 if (profiled_method != NULL) {
1728 c->set_profiled_method(profiled_method);
1729 c->set_profiled_bci(profiled_bci);
1730 c->set_should_profile(true);
1731 }
1732 append(c);
1733 }
1735 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1736 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1737 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1738 }
1740 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1741 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1742 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1743 }
1745 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1746 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1747 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1748 }
1751 #ifdef PRODUCT
1753 void print_LIR(BlockList* blocks) {
1754 }
1756 #else
1757 // LIR_OprDesc
1758 void LIR_OprDesc::print() const {
1759 print(tty);
1760 }
1762 void LIR_OprDesc::print(outputStream* out) const {
1763 if (is_illegal()) {
1764 return;
1765 }
1767 out->print("[");
1768 if (is_pointer()) {
1769 pointer()->print_value_on(out);
1770 } else if (is_single_stack()) {
1771 out->print("stack:%d", single_stack_ix());
1772 } else if (is_double_stack()) {
1773 out->print("dbl_stack:%d",double_stack_ix());
1774 } else if (is_virtual()) {
1775 out->print("R%d", vreg_number());
1776 } else if (is_single_cpu()) {
1777 out->print("%s", as_register()->name());
1778 } else if (is_double_cpu()) {
1779 out->print("%s", as_register_hi()->name());
1780 out->print("%s", as_register_lo()->name());
1781 #if defined(X86)
1782 } else if (is_single_xmm()) {
1783 out->print("%s", as_xmm_float_reg()->name());
1784 } else if (is_double_xmm()) {
1785 out->print("%s", as_xmm_double_reg()->name());
1786 } else if (is_single_fpu()) {
1787 out->print("fpu%d", fpu_regnr());
1788 } else if (is_double_fpu()) {
1789 out->print("fpu%d", fpu_regnrLo());
1790 #elif defined(ARM)
1791 } else if (is_single_fpu()) {
1792 out->print("s%d", fpu_regnr());
1793 } else if (is_double_fpu()) {
1794 out->print("d%d", fpu_regnrLo() >> 1);
1795 #else
1796 } else if (is_single_fpu()) {
1797 out->print("%s", as_float_reg()->name());
1798 } else if (is_double_fpu()) {
1799 out->print("%s", as_double_reg()->name());
1800 #endif
1802 } else if (is_illegal()) {
1803 out->print("-");
1804 } else {
1805 out->print("Unknown Operand");
1806 }
1807 if (!is_illegal()) {
1808 out->print("|%c", type_char());
1809 }
1810 if (is_register() && is_last_use()) {
1811 out->print("(last_use)");
1812 }
1813 out->print("]");
1814 }
1817 // LIR_Address
1818 void LIR_Const::print_value_on(outputStream* out) const {
1819 switch (type()) {
1820 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1821 case T_INT: out->print("int:%d", as_jint()); break;
1822 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1823 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1824 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1825 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break;
1826 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break;
1827 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break;
1828 }
1829 }
1831 // LIR_Address
1832 void LIR_Address::print_value_on(outputStream* out) const {
1833 out->print("Base:"); _base->print(out);
1834 #ifndef MIPS
1835 if (!_index->is_illegal()) {
1836 out->print(" Index:"); _index->print(out);
1837 switch (scale()) {
1838 case times_1: break;
1839 case times_2: out->print(" * 2"); break;
1840 case times_4: out->print(" * 4"); break;
1841 case times_8: out->print(" * 8"); break;
1842 }
1843 }
1844 #endif
1845 out->print(" Disp: " INTX_FORMAT, _disp);
1846 }
1848 // debug output of block header without InstructionPrinter
1849 // (because phi functions are not necessary for LIR)
1850 static void print_block(BlockBegin* x) {
1851 // print block id
1852 BlockEnd* end = x->end();
1853 tty->print("B%d ", x->block_id());
1855 // print flags
1856 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1857 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1858 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1859 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1860 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1861 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1862 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1864 // print block bci range
1865 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1867 // print predecessors and successors
1868 if (x->number_of_preds() > 0) {
1869 tty->print("preds: ");
1870 for (int i = 0; i < x->number_of_preds(); i ++) {
1871 tty->print("B%d ", x->pred_at(i)->block_id());
1872 }
1873 }
1875 if (x->number_of_sux() > 0) {
1876 tty->print("sux: ");
1877 for (int i = 0; i < x->number_of_sux(); i ++) {
1878 tty->print("B%d ", x->sux_at(i)->block_id());
1879 }
1880 }
1882 // print exception handlers
1883 if (x->number_of_exception_handlers() > 0) {
1884 tty->print("xhandler: ");
1885 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1886 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1887 }
1888 }
1890 tty->cr();
1891 }
1893 void print_LIR(BlockList* blocks) {
1894 tty->print_cr("LIR:");
1895 int i;
1896 for (i = 0; i < blocks->length(); i++) {
1897 BlockBegin* bb = blocks->at(i);
1898 print_block(bb);
1899 tty->print("__id_Instruction___________________________________________"); tty->cr();
1900 bb->lir()->print_instructions();
1901 }
1902 }
1904 void LIR_List::print_instructions() {
1905 for (int i = 0; i < _operations.length(); i++) {
1906 _operations.at(i)->print(); tty->cr();
1907 }
1908 tty->cr();
1909 }
1911 // LIR_Ops printing routines
1912 // LIR_Op
1913 void LIR_Op::print_on(outputStream* out) const {
1914 if (id() != -1 || PrintCFGToFile) {
1915 out->print("%4d ", id());
1916 } else {
1917 out->print(" ");
1918 }
1919 out->print("%s ", name());
1920 print_instr(out);
1921 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1922 #ifdef ASSERT
1923 if (Verbose && _file != NULL) {
1924 out->print(" (%s:%d)", _file, _line);
1925 }
1926 #endif
1927 }
1929 const char * LIR_Op::name() const {
1930 const char* s = NULL;
1931 switch(code()) {
1932 // LIR_Op0
1933 case lir_membar: s = "membar"; break;
1934 case lir_membar_acquire: s = "membar_acquire"; break;
1935 case lir_membar_release: s = "membar_release"; break;
1936 case lir_membar_loadload: s = "membar_loadload"; break;
1937 case lir_membar_storestore: s = "membar_storestore"; break;
1938 case lir_membar_loadstore: s = "membar_loadstore"; break;
1939 case lir_membar_storeload: s = "membar_storeload"; break;
1940 case lir_word_align: s = "word_align"; break;
1941 case lir_label: s = "label"; break;
1942 case lir_nop: s = "nop"; break;
1943 case lir_backwardbranch_target: s = "backbranch"; break;
1944 case lir_std_entry: s = "std_entry"; break;
1945 case lir_osr_entry: s = "osr_entry"; break;
1946 case lir_build_frame: s = "build_frm"; break;
1947 case lir_fpop_raw: s = "fpop_raw"; break;
1948 case lir_24bit_FPU: s = "24bit_FPU"; break;
1949 case lir_reset_FPU: s = "reset_FPU"; break;
1950 case lir_breakpoint: s = "breakpoint"; break;
1951 case lir_get_thread: s = "get_thread"; break;
1952 // LIR_Op1
1953 case lir_fxch: s = "fxch"; break;
1954 case lir_fld: s = "fld"; break;
1955 case lir_ffree: s = "ffree"; break;
1956 case lir_push: s = "push"; break;
1957 case lir_pop: s = "pop"; break;
1958 case lir_null_check: s = "null_check"; break;
1959 case lir_return: s = "return"; break;
1960 case lir_safepoint: s = "safepoint"; break;
1961 case lir_neg: s = "neg"; break;
1962 case lir_leal: s = "leal"; break;
1963 case lir_branch: s = "branch"; break;
1964 case lir_cond_float_branch: s = "flt_cond_br"; break;
1965 case lir_move: s = "move"; break;
1966 case lir_roundfp: s = "roundfp"; break;
1967 case lir_rtcall: s = "rtcall"; break;
1968 case lir_throw: s = "throw"; break;
1969 case lir_unwind: s = "unwind"; break;
1970 case lir_convert: s = "convert"; break;
1971 case lir_alloc_object: s = "alloc_obj"; break;
1972 case lir_monaddr: s = "mon_addr"; break;
1973 case lir_pack64: s = "pack64"; break;
1974 case lir_unpack64: s = "unpack64"; break;
1975 // LIR_Op2
1976 #ifdef MIPS
1977 case lir_null_check_for_branch: s = "null_check_for_branch"; break;
1978 #else
1979 case lir_cmp: s = "cmp"; break;
1980 #endif
1981 case lir_cmp_l2i: s = "cmp_l2i"; break;
1982 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1983 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1984 case lir_cmove: s = "cmove"; break;
1985 case lir_add: s = "add"; break;
1986 case lir_sub: s = "sub"; break;
1987 case lir_mul: s = "mul"; break;
1988 case lir_mul_strictfp: s = "mul_strictfp"; break;
1989 case lir_div: s = "div"; break;
1990 case lir_div_strictfp: s = "div_strictfp"; break;
1991 case lir_rem: s = "rem"; break;
1992 case lir_abs: s = "abs"; break;
1993 case lir_sqrt: s = "sqrt"; break;
1994 case lir_sin: s = "sin"; break;
1995 case lir_cos: s = "cos"; break;
1996 case lir_tan: s = "tan"; break;
1997 case lir_log: s = "log"; break;
1998 case lir_log10: s = "log10"; break;
1999 case lir_exp: s = "exp"; break;
2000 case lir_pow: s = "pow"; break;
2001 case lir_logic_and: s = "logic_and"; break;
2002 case lir_logic_or: s = "logic_or"; break;
2003 case lir_logic_xor: s = "logic_xor"; break;
2004 case lir_shl: s = "shift_left"; break;
2005 case lir_shr: s = "shift_right"; break;
2006 case lir_ushr: s = "ushift_right"; break;
2007 case lir_alloc_array: s = "alloc_array"; break;
2008 case lir_xadd: s = "xadd"; break;
2009 case lir_xchg: s = "xchg"; break;
2010 // LIR_Op3
2011 #ifdef MIPS
2012 case lir_frem: s = "frem"; break;
2013 #endif
2014 case lir_idiv: s = "idiv"; break;
2015 case lir_irem: s = "irem"; break;
2016 #ifdef MIPS
2017 // LIR_Op4
2018 case lir_cmove_mips: s = "cmove_mips"; break;
2019 #endif
2020 // LIR_OpJavaCall
2021 case lir_static_call: s = "static"; break;
2022 case lir_optvirtual_call: s = "optvirtual"; break;
2023 case lir_icvirtual_call: s = "icvirtual"; break;
2024 case lir_virtual_call: s = "virtual"; break;
2025 case lir_dynamic_call: s = "dynamic"; break;
2026 // LIR_OpArrayCopy
2027 case lir_arraycopy: s = "arraycopy"; break;
2028 // LIR_OpUpdateCRC32
2029 case lir_updatecrc32: s = "updatecrc32"; break;
2030 // LIR_OpLock
2031 case lir_lock: s = "lock"; break;
2032 case lir_unlock: s = "unlock"; break;
2033 // LIR_OpDelay
2034 case lir_delay_slot: s = "delay"; break;
2035 // LIR_OpTypeCheck
2036 case lir_instanceof: s = "instanceof"; break;
2037 case lir_checkcast: s = "checkcast"; break;
2038 case lir_store_check: s = "store_check"; break;
2039 // LIR_OpCompareAndSwap
2040 case lir_cas_long: s = "cas_long"; break;
2041 case lir_cas_obj: s = "cas_obj"; break;
2042 case lir_cas_int: s = "cas_int"; break;
2043 // LIR_OpProfileCall
2044 case lir_profile_call: s = "profile_call"; break;
2045 // LIR_OpProfileType
2046 case lir_profile_type: s = "profile_type"; break;
2047 // LIR_OpAssert
2048 #ifdef ASSERT
2049 case lir_assert: s = "assert"; break;
2050 #endif
2051 case lir_none: ShouldNotReachHere();break;
2052 default: s = "illegal_op"; break;
2053 }
2054 return s;
2055 }
2057 // LIR_OpJavaCall
2058 void LIR_OpJavaCall::print_instr(outputStream* out) const {
2059 out->print("call: ");
2060 out->print("[addr: " INTPTR_FORMAT "]", p2i(address()));
2061 if (receiver()->is_valid()) {
2062 out->print(" [recv: "); receiver()->print(out); out->print("]");
2063 }
2064 if (result_opr()->is_valid()) {
2065 out->print(" [result: "); result_opr()->print(out); out->print("]");
2066 }
2067 }
2069 // LIR_OpLabel
2070 void LIR_OpLabel::print_instr(outputStream* out) const {
2071 out->print("[label:" INTPTR_FORMAT "]", p2i(_label));
2072 }
2074 // LIR_OpArrayCopy
2075 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
2076 src()->print(out); out->print(" ");
2077 src_pos()->print(out); out->print(" ");
2078 dst()->print(out); out->print(" ");
2079 dst_pos()->print(out); out->print(" ");
2080 length()->print(out); out->print(" ");
2081 tmp()->print(out); out->print(" ");
2082 }
2084 // LIR_OpUpdateCRC32
2085 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const {
2086 crc()->print(out); out->print(" ");
2087 val()->print(out); out->print(" ");
2088 result_opr()->print(out); out->print(" ");
2089 }
2091 // LIR_OpCompareAndSwap
2092 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
2093 addr()->print(out); out->print(" ");
2094 cmp_value()->print(out); out->print(" ");
2095 new_value()->print(out); out->print(" ");
2096 tmp1()->print(out); out->print(" ");
2097 tmp2()->print(out); out->print(" ");
2099 }
2101 // LIR_Op0
2102 void LIR_Op0::print_instr(outputStream* out) const {
2103 result_opr()->print(out);
2104 }
2106 // LIR_Op1
2107 const char * LIR_Op1::name() const {
2108 if (code() == lir_move) {
2109 switch (move_kind()) {
2110 case lir_move_normal:
2111 return "move";
2112 case lir_move_unaligned:
2113 return "unaligned move";
2114 case lir_move_volatile:
2115 return "volatile_move";
2116 case lir_move_wide:
2117 return "wide_move";
2118 default:
2119 ShouldNotReachHere();
2120 return "illegal_op";
2121 }
2122 } else {
2123 return LIR_Op::name();
2124 }
2125 }
2128 void LIR_Op1::print_instr(outputStream* out) const {
2129 _opr->print(out); out->print(" ");
2130 result_opr()->print(out); out->print(" ");
2131 print_patch_code(out, patch_code());
2132 }
2135 // LIR_Op1
2136 void LIR_OpRTCall::print_instr(outputStream* out) const {
2137 intx a = (intx)addr();
2138 out->print("%s", Runtime1::name_for_address(addr()));
2139 out->print(" ");
2140 tmp()->print(out);
2141 }
2143 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
2144 switch(code) {
2145 case lir_patch_none: break;
2146 case lir_patch_low: out->print("[patch_low]"); break;
2147 case lir_patch_high: out->print("[patch_high]"); break;
2148 case lir_patch_normal: out->print("[patch_normal]"); break;
2149 default: ShouldNotReachHere();
2150 }
2151 }
2153 // LIR_OpBranch
2154 void LIR_OpBranch::print_instr(outputStream* out) const {
2155 print_condition(out, cond()); out->print(" ");
2156 #ifdef MIPS
2157 in_opr1()->print(out); out->print(" ");
2158 in_opr2()->print(out); out->print(" ");
2159 #endif
2160 if (block() != NULL) {
2161 out->print("[B%d] ", block()->block_id());
2162 } else if (stub() != NULL) {
2163 out->print("[");
2164 stub()->print_name(out);
2165 out->print(": " INTPTR_FORMAT "]", p2i(stub()));
2166 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
2167 } else {
2168 out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
2169 }
2170 if (ublock() != NULL) {
2171 out->print("unordered: [B%d] ", ublock()->block_id());
2172 }
2173 }
2175 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
2176 switch(cond) {
2177 case lir_cond_equal: out->print("[EQ]"); break;
2178 case lir_cond_notEqual: out->print("[NE]"); break;
2179 case lir_cond_less: out->print("[LT]"); break;
2180 case lir_cond_lessEqual: out->print("[LE]"); break;
2181 case lir_cond_greaterEqual: out->print("[GE]"); break;
2182 case lir_cond_greater: out->print("[GT]"); break;
2183 case lir_cond_belowEqual: out->print("[BE]"); break;
2184 case lir_cond_aboveEqual: out->print("[AE]"); break;
2185 case lir_cond_always: out->print("[AL]"); break;
2186 default: out->print("[%d]",cond); break;
2187 }
2188 }
2190 // LIR_OpConvert
2191 void LIR_OpConvert::print_instr(outputStream* out) const {
2192 print_bytecode(out, bytecode());
2193 in_opr()->print(out); out->print(" ");
2194 result_opr()->print(out); out->print(" ");
2195 #ifdef PPC
2196 if(tmp1()->is_valid()) {
2197 tmp1()->print(out); out->print(" ");
2198 tmp2()->print(out); out->print(" ");
2199 }
2200 #endif
2201 }
2203 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
2204 switch(code) {
2205 case Bytecodes::_d2f: out->print("[d2f] "); break;
2206 case Bytecodes::_d2i: out->print("[d2i] "); break;
2207 case Bytecodes::_d2l: out->print("[d2l] "); break;
2208 case Bytecodes::_f2d: out->print("[f2d] "); break;
2209 case Bytecodes::_f2i: out->print("[f2i] "); break;
2210 case Bytecodes::_f2l: out->print("[f2l] "); break;
2211 case Bytecodes::_i2b: out->print("[i2b] "); break;
2212 case Bytecodes::_i2c: out->print("[i2c] "); break;
2213 case Bytecodes::_i2d: out->print("[i2d] "); break;
2214 case Bytecodes::_i2f: out->print("[i2f] "); break;
2215 case Bytecodes::_i2l: out->print("[i2l] "); break;
2216 case Bytecodes::_i2s: out->print("[i2s] "); break;
2217 case Bytecodes::_l2i: out->print("[l2i] "); break;
2218 case Bytecodes::_l2f: out->print("[l2f] "); break;
2219 case Bytecodes::_l2d: out->print("[l2d] "); break;
2220 default:
2221 out->print("[?%d]",code);
2222 break;
2223 }
2224 }
2226 void LIR_OpAllocObj::print_instr(outputStream* out) const {
2227 klass()->print(out); out->print(" ");
2228 obj()->print(out); out->print(" ");
2229 tmp1()->print(out); out->print(" ");
2230 tmp2()->print(out); out->print(" ");
2231 tmp3()->print(out); out->print(" ");
2232 tmp4()->print(out); out->print(" ");
2233 #ifdef MIPS
2234 tmp5()->print(out); out->print(" ");
2235 tmp6()->print(out); out->print(" ");
2236 #endif
2237 out->print("[hdr:%d]", header_size()); out->print(" ");
2238 out->print("[obj:%d]", object_size()); out->print(" ");
2239 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2240 }
2242 void LIR_OpRoundFP::print_instr(outputStream* out) const {
2243 _opr->print(out); out->print(" ");
2244 tmp()->print(out); out->print(" ");
2245 result_opr()->print(out); out->print(" ");
2246 }
2248 // LIR_Op2
2249 void LIR_Op2::print_instr(outputStream* out) const {
2250 #ifndef MIPS
2251 if (code() == lir_cmove) {
2252 print_condition(out, condition()); out->print(" ");
2253 }
2254 #endif
2255 in_opr1()->print(out); out->print(" ");
2256 in_opr2()->print(out); out->print(" ");
2257 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
2258 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
2259 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
2260 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
2261 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
2262 result_opr()->print(out);
2263 }
2265 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2266 klass()->print(out); out->print(" ");
2267 len()->print(out); out->print(" ");
2268 obj()->print(out); out->print(" ");
2269 tmp1()->print(out); out->print(" ");
2270 tmp2()->print(out); out->print(" ");
2271 tmp3()->print(out); out->print(" ");
2272 tmp4()->print(out); out->print(" ");
2273 #ifdef MIPS
2274 tmp5()->print(out); out->print(" ");
2275 #endif
2276 out->print("[type:0x%x]", type()); out->print(" ");
2277 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2278 }
2281 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
2282 object()->print(out); out->print(" ");
2283 if (code() == lir_store_check) {
2284 array()->print(out); out->print(" ");
2285 }
2286 if (code() != lir_store_check) {
2287 klass()->print_name_on(out); out->print(" ");
2288 if (fast_check()) out->print("fast_check ");
2289 }
2290 tmp1()->print(out); out->print(" ");
2291 tmp2()->print(out); out->print(" ");
2292 tmp3()->print(out); out->print(" ");
2293 result_opr()->print(out); out->print(" ");
2294 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2295 }
2298 // LIR_Op3
2299 void LIR_Op3::print_instr(outputStream* out) const {
2300 in_opr1()->print(out); out->print(" ");
2301 in_opr2()->print(out); out->print(" ");
2302 in_opr3()->print(out); out->print(" ");
2303 result_opr()->print(out);
2304 }
2306 #ifdef MIPS
2307 // LIR_Op4
2308 void LIR_Op4::print_instr(outputStream* out) const {
2309 print_condition(out, cond()); out->print(" ");
2310 in_opr1()->print(out); out->print(" ");
2311 in_opr2()->print(out); out->print(" ");
2312 in_opr3()->print(out); out->print(" ");
2313 in_opr4()->print(out); out->print(" ");
2314 result_opr()->print(out);
2315 }
2316 #endif
2318 void LIR_OpLock::print_instr(outputStream* out) const {
2319 hdr_opr()->print(out); out->print(" ");
2320 obj_opr()->print(out); out->print(" ");
2321 lock_opr()->print(out); out->print(" ");
2322 if (_scratch->is_valid()) {
2323 _scratch->print(out); out->print(" ");
2324 }
2325 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2326 }
2328 #ifdef ASSERT
2329 void LIR_OpAssert::print_instr(outputStream* out) const {
2330 tty->print_cr("function LIR_OpAssert::print_instr unimplemented yet! ");
2331 Unimplemented();
2332 /*
2333 print_condition(out, condition()); out->print(" ");
2334 in_opr1()->print(out); out->print(" ");
2335 in_opr2()->print(out); out->print(", \"");
2336 out->print("%s", msg()); out->print("\"");
2337 */
2338 }
2339 #endif
2342 void LIR_OpDelay::print_instr(outputStream* out) const {
2343 _op->print_on(out);
2344 }
2347 // LIR_OpProfileCall
2348 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2349 profiled_method()->name()->print_symbol_on(out);
2350 out->print(".");
2351 profiled_method()->holder()->name()->print_symbol_on(out);
2352 out->print(" @ %d ", profiled_bci());
2353 mdo()->print(out); out->print(" ");
2354 recv()->print(out); out->print(" ");
2355 tmp1()->print(out); out->print(" ");
2356 }
2358 // LIR_OpProfileType
2359 void LIR_OpProfileType::print_instr(outputStream* out) const {
2360 out->print("exact = ");
2361 if (exact_klass() == NULL) {
2362 out->print("unknown");
2363 } else {
2364 exact_klass()->print_name_on(out);
2365 }
2366 out->print(" current = "); ciTypeEntries::print_ciklass(out, current_klass());
2367 out->print(" ");
2368 mdp()->print(out); out->print(" ");
2369 obj()->print(out); out->print(" ");
2370 tmp()->print(out); out->print(" ");
2371 }
2373 #endif // PRODUCT
2375 // Implementation of LIR_InsertionBuffer
2377 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2378 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2380 int i = number_of_insertion_points() - 1;
2381 if (i < 0 || index_at(i) < index) {
2382 append_new(index, 1);
2383 } else {
2384 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2385 assert(count_at(i) > 0, "check");
2386 set_count_at(i, count_at(i) + 1);
2387 }
2388 _ops.push(op);
2390 DEBUG_ONLY(verify());
2391 }
2393 #ifdef ASSERT
2394 void LIR_InsertionBuffer::verify() {
2395 int sum = 0;
2396 int prev_idx = -1;
2398 for (int i = 0; i < number_of_insertion_points(); i++) {
2399 assert(prev_idx < index_at(i), "index must be ordered ascending");
2400 sum += count_at(i);
2401 }
2402 assert(sum == number_of_ops(), "wrong total sum");
2403 }
2404 #endif
