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src/share/vm/c1/c1_LIR.cpp@950e185f5ded
src/share/vm/c1/c1_LIR.cpp
Wed, 15 Aug 2018 11:00:24 +0800
- author
- wangxue
- date
- Wed, 15 Aug 2018 11:00:24 +0800
- changeset 9214
- 950e185f5ded
- parent 9167
- 1336d592e5b8
- child 9215
- 8843990f569c
- permissions
- -rw-r--r--
#7323 [C1] Used a wrong register in LIR_Assembler::emit_profile_type().
Reviewed-by: aoqi
1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 /*
26 * This file has been modified by Loongson Technology in 2015, 2018. These
27 * modifications are Copyright (c) 2015, 2018 Loongson Technology, and are made
28 * available on the same license terms set forth above.
29 */
31 #include "precompiled.hpp"
32 #include "c1/c1_InstructionPrinter.hpp"
33 #include "c1/c1_LIR.hpp"
34 #include "c1/c1_LIRAssembler.hpp"
35 #include "c1/c1_ValueStack.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "runtime/sharedRuntime.hpp"
39 Register LIR_OprDesc::as_register() const {
40 return FrameMap::cpu_rnr2reg(cpu_regnr());
41 }
43 Register LIR_OprDesc::as_register_lo() const {
44 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
45 }
47 Register LIR_OprDesc::as_register_hi() const {
48 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
49 }
51 #if defined(X86)
53 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
54 return FrameMap::nr2xmmreg(xmm_regnr());
55 }
57 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
58 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
59 return FrameMap::nr2xmmreg(xmm_regnrLo());
60 }
62 #endif // X86
64 #if defined(SPARC) || defined(PPC) || defined(MIPS)
66 FloatRegister LIR_OprDesc::as_float_reg() const {
67 return FrameMap::nr2floatreg(fpu_regnr());
68 }
70 FloatRegister LIR_OprDesc::as_double_reg() const {
71 return FrameMap::nr2floatreg(fpu_regnrHi());
72 }
74 #endif
76 #ifdef ARM
78 FloatRegister LIR_OprDesc::as_float_reg() const {
79 return as_FloatRegister(fpu_regnr());
80 }
82 FloatRegister LIR_OprDesc::as_double_reg() const {
83 return as_FloatRegister(fpu_regnrLo());
84 }
86 #endif
89 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
91 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
92 ValueTag tag = type->tag();
93 switch (tag) {
94 case metaDataTag : {
95 ClassConstant* c = type->as_ClassConstant();
96 if (c != NULL && !c->value()->is_loaded()) {
97 return LIR_OprFact::metadataConst(NULL);
98 } else if (c != NULL) {
99 return LIR_OprFact::metadataConst(c->value()->constant_encoding());
100 } else {
101 MethodConstant* m = type->as_MethodConstant();
102 assert (m != NULL, "not a class or a method?");
103 return LIR_OprFact::metadataConst(m->value()->constant_encoding());
104 }
105 }
106 case objectTag : {
107 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
108 }
109 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
110 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
111 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
112 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
113 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
114 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
115 }
116 }
119 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
120 switch (type->tag()) {
121 case objectTag: return LIR_OprFact::oopConst(NULL);
122 case addressTag:return LIR_OprFact::addressConst(0);
123 case intTag: return LIR_OprFact::intConst(0);
124 case floatTag: return LIR_OprFact::floatConst(0.0);
125 case longTag: return LIR_OprFact::longConst(0);
126 case doubleTag: return LIR_OprFact::doubleConst(0.0);
127 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
128 }
129 return illegalOpr;
130 }
134 //---------------------------------------------------
137 LIR_Address::Scale LIR_Address::scale(BasicType type) {
138 int elem_size = type2aelembytes(type);
139 switch (elem_size) {
140 case 1: return LIR_Address::times_1;
141 case 2: return LIR_Address::times_2;
142 case 4: return LIR_Address::times_4;
143 case 8: return LIR_Address::times_8;
144 }
145 ShouldNotReachHere();
146 return LIR_Address::times_1;
147 }
150 #ifndef PRODUCT
151 void LIR_Address::verify0() const {
152 #if defined(SPARC) || defined(PPC) || defined(MIPS)
153 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
154 assert(disp() == 0 || index()->is_illegal(), "can't have both");
155 #endif
156 #ifdef _LP64
157 assert(base()->is_cpu_register(), "wrong base operand");
158 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
159 #ifndef MIPS
160 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
161 "wrong type for addresses");
162 #endif
163 #else
164 assert(base()->is_single_cpu(), "wrong base operand");
165 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
166 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
167 "wrong type for addresses");
168 #endif
169 }
170 #endif
173 //---------------------------------------------------
175 char LIR_OprDesc::type_char(BasicType t) {
176 switch (t) {
177 case T_ARRAY:
178 t = T_OBJECT;
179 case T_BOOLEAN:
180 case T_CHAR:
181 case T_FLOAT:
182 case T_DOUBLE:
183 case T_BYTE:
184 case T_SHORT:
185 case T_INT:
186 case T_LONG:
187 case T_OBJECT:
188 case T_ADDRESS:
189 case T_VOID:
190 return ::type2char(t);
191 case T_METADATA:
192 return 'M';
193 case T_ILLEGAL:
194 return '?';
196 default:
197 ShouldNotReachHere();
198 return '?';
199 }
200 }
202 #ifndef PRODUCT
203 void LIR_OprDesc::validate_type() const {
205 #ifdef ASSERT
206 if (!is_pointer() && !is_illegal()) {
207 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
208 switch (as_BasicType(type_field())) {
209 case T_LONG:
210 assert((kindfield == cpu_register || kindfield == stack_value) &&
211 size_field() == double_size, "must match");
212 break;
213 case T_FLOAT:
214 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
215 assert((kindfield == fpu_register || kindfield == stack_value
216 ARM_ONLY(|| kindfield == cpu_register)
217 PPC_ONLY(|| kindfield == cpu_register) ) &&
218 size_field() == single_size, "must match");
219 break;
220 case T_DOUBLE:
221 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
222 assert((kindfield == fpu_register || kindfield == stack_value
223 ARM_ONLY(|| kindfield == cpu_register)
224 PPC_ONLY(|| kindfield == cpu_register) ) &&
225 size_field() == double_size, "must match");
226 break;
227 case T_BOOLEAN:
228 case T_CHAR:
229 case T_BYTE:
230 case T_SHORT:
231 case T_INT:
232 case T_ADDRESS:
233 case T_OBJECT:
234 case T_METADATA:
235 case T_ARRAY:
236 assert((kindfield == cpu_register || kindfield == stack_value) &&
237 size_field() == single_size, "must match");
238 break;
240 case T_ILLEGAL:
241 // XXX TKR also means unknown right now
242 // assert(is_illegal(), "must match");
243 break;
245 default:
246 ShouldNotReachHere();
247 }
248 }
249 #endif
251 }
252 #endif // PRODUCT
255 bool LIR_OprDesc::is_oop() const {
256 if (is_pointer()) {
257 return pointer()->is_oop_pointer();
258 } else {
259 OprType t= type_field();
260 assert(t != unknown_type, "not set");
261 return t == object_type;
262 }
263 }
265 #ifdef MIPS
266 bool LIR_OprDesc::has_common_register(LIR_Opr opr) const {
267 #ifdef _LP64
268 return is_same_register(opr);
269 #else
270 if (!(is_register() && opr->is_register())) return false;
271 if (!(kind_field() == opr->kind_field())) return false;
273 if (is_single_cpu()) {
274 if (opr->is_single_cpu()) {
275 return as_register() == opr->as_register();
276 } else {
277 Register dst = as_register();
278 Register lo = opr->as_register_lo();
279 Register hi = opr->as_register_hi();
280 if (dst == lo || dst == hi) return true;
281 }
283 } else {
284 Register dst_lo = as_register_lo();
285 Register dst_hi = as_register_hi();
287 if (opr->is_single_cpu()) {
288 Register src = opr->as_register();
289 if (dst_lo == src || dst_hi == src) return true;
290 } else {
291 Register src_lo = opr->as_register_lo();
292 Register src_hi = opr->as_register_hi();
293 if (dst_lo == src_lo ||
294 dst_lo == src_hi ||
295 dst_hi == src_lo ||
296 dst_hi == src_hi) return true;
297 }
298 }
299 return false;
300 #endif
301 }
302 #endif
304 void LIR_Op2::verify() const {
305 #ifdef ASSERT
306 switch (code()) {
307 case lir_cmove:
308 case lir_xchg:
309 break;
311 default:
312 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
313 "can't produce oops from arith");
314 }
316 if (TwoOperandLIRForm) {
317 switch (code()) {
318 case lir_add:
319 case lir_sub:
320 case lir_mul:
321 case lir_mul_strictfp:
322 case lir_div:
323 case lir_div_strictfp:
324 case lir_rem:
325 case lir_logic_and:
326 case lir_logic_or:
327 case lir_logic_xor:
328 case lir_shl:
329 case lir_shr:
330 assert(in_opr1() == result_opr(), "opr1 and result must match");
331 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
332 break;
334 // special handling for lir_ushr because of write barriers
335 case lir_ushr:
336 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
337 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
338 break;
340 }
341 }
342 #endif
343 }
346 #ifndef MIPS
347 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
348 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
349 , _cond(cond)
350 , _type(type)
351 , _label(block->label())
352 , _block(block)
353 , _ublock(NULL)
354 , _stub(NULL) {
355 }
357 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
358 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
359 , _cond(cond)
360 , _type(type)
361 , _label(stub->entry())
362 , _block(NULL)
363 , _ublock(NULL)
364 , _stub(stub) {
365 }
367 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
368 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
369 , _cond(cond)
370 , _type(type)
371 , _label(block->label())
372 , _block(block)
373 , _ublock(ublock)
374 , _stub(NULL)
375 {
376 }
378 #else
379 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
380 BlockBegin* block):
381 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
382 _cond(cond),
383 _type(type),
384 _label(block->label()),
385 _block(block),
386 _ublock(NULL),
387 _stub(NULL) {
388 }
390 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
391 CodeStub* stub):
392 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
393 _cond(cond),
394 _type(type),
395 _label(stub->entry()),
396 _block(NULL),
397 _ublock(NULL),
398 _stub(stub) {
399 }
402 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
403 BlockBegin *block, BlockBegin *ublock):
404 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
405 _cond(cond),
406 _type(type),
407 _label(block->label()),
408 _block(block),
409 _ublock(ublock),
410 _stub(NULL) {
411 }
413 #endif
414 void LIR_OpBranch::change_block(BlockBegin* b) {
415 assert(_block != NULL, "must have old block");
416 assert(_block->label() == label(), "must be equal");
418 _block = b;
419 _label = b->label();
420 }
422 void LIR_OpBranch::change_ublock(BlockBegin* b) {
423 assert(_ublock != NULL, "must have old block");
424 _ublock = b;
425 }
427 void LIR_OpBranch::negate_cond() {
428 switch (_cond) {
429 case lir_cond_equal: _cond = lir_cond_notEqual; break;
430 case lir_cond_notEqual: _cond = lir_cond_equal; break;
431 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
432 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
433 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
434 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
435 default: ShouldNotReachHere();
436 }
437 }
440 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
441 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
442 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
443 CodeStub* stub)
445 : LIR_Op(code, result, NULL)
446 , _object(object)
447 , _array(LIR_OprFact::illegalOpr)
448 , _klass(klass)
449 , _tmp1(tmp1)
450 , _tmp2(tmp2)
451 , _tmp3(tmp3)
452 , _fast_check(fast_check)
453 , _stub(stub)
454 , _info_for_patch(info_for_patch)
455 , _info_for_exception(info_for_exception)
456 , _profiled_method(NULL)
457 , _profiled_bci(-1)
458 , _should_profile(false)
459 {
460 if (code == lir_checkcast) {
461 assert(info_for_exception != NULL, "checkcast throws exceptions");
462 } else if (code == lir_instanceof) {
463 assert(info_for_exception == NULL, "instanceof throws no exceptions");
464 } else {
465 ShouldNotReachHere();
466 }
467 }
471 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
472 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
473 , _object(object)
474 , _array(array)
475 , _klass(NULL)
476 , _tmp1(tmp1)
477 , _tmp2(tmp2)
478 , _tmp3(tmp3)
479 , _fast_check(false)
480 , _stub(NULL)
481 , _info_for_patch(NULL)
482 , _info_for_exception(info_for_exception)
483 , _profiled_method(NULL)
484 , _profiled_bci(-1)
485 , _should_profile(false)
486 {
487 if (code == lir_store_check) {
488 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
489 assert(info_for_exception != NULL, "store_check throws exceptions");
490 } else {
491 ShouldNotReachHere();
492 }
493 }
496 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
497 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
498 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
499 , _tmp(tmp)
500 , _src(src)
501 , _src_pos(src_pos)
502 , _dst(dst)
503 , _dst_pos(dst_pos)
504 , _flags(flags)
505 , _expected_type(expected_type)
506 , _length(length) {
507 _stub = new ArrayCopyStub(this);
508 }
510 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res)
511 : LIR_Op(lir_updatecrc32, res, NULL)
512 , _crc(crc)
513 , _val(val) {
514 }
516 //-------------------verify--------------------------
518 void LIR_Op1::verify() const {
519 switch(code()) {
520 case lir_move:
521 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
522 break;
523 case lir_null_check:
524 assert(in_opr()->is_register(), "must be");
525 break;
526 case lir_return:
527 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
528 break;
529 }
530 }
532 void LIR_OpRTCall::verify() const {
533 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
534 }
536 //-------------------visits--------------------------
538 // complete rework of LIR instruction visitor.
539 // The virtual call for each instruction type is replaced by a big
540 // switch that adds the operands for each instruction
542 void LIR_OpVisitState::visit(LIR_Op* op) {
543 // copy information from the LIR_Op
544 reset();
545 set_op(op);
547 switch (op->code()) {
549 // LIR_Op0
550 case lir_word_align: // result and info always invalid
551 case lir_backwardbranch_target: // result and info always invalid
552 case lir_build_frame: // result and info always invalid
553 case lir_fpop_raw: // result and info always invalid
554 case lir_24bit_FPU: // result and info always invalid
555 case lir_reset_FPU: // result and info always invalid
556 case lir_breakpoint: // result and info always invalid
557 case lir_membar: // result and info always invalid
558 case lir_membar_acquire: // result and info always invalid
559 case lir_membar_release: // result and info always invalid
560 case lir_membar_loadload: // result and info always invalid
561 case lir_membar_storestore: // result and info always invalid
562 case lir_membar_loadstore: // result and info always invalid
563 case lir_membar_storeload: // result and info always invalid
564 {
565 assert(op->as_Op0() != NULL, "must be");
566 assert(op->_info == NULL, "info not used by this instruction");
567 assert(op->_result->is_illegal(), "not used");
568 break;
569 }
571 case lir_nop: // may have info, result always invalid
572 case lir_std_entry: // may have result, info always invalid
573 case lir_osr_entry: // may have result, info always invalid
574 case lir_get_thread: // may have result, info always invalid
575 {
576 assert(op->as_Op0() != NULL, "must be");
577 if (op->_info != NULL) do_info(op->_info);
578 if (op->_result->is_valid()) do_output(op->_result);
579 break;
580 }
583 // LIR_OpLabel
584 case lir_label: // result and info always invalid
585 {
586 assert(op->as_OpLabel() != NULL, "must be");
587 assert(op->_info == NULL, "info not used by this instruction");
588 assert(op->_result->is_illegal(), "not used");
589 break;
590 }
593 // LIR_Op1
594 case lir_fxch: // input always valid, result and info always invalid
595 case lir_fld: // input always valid, result and info always invalid
596 case lir_ffree: // input always valid, result and info always invalid
597 case lir_push: // input always valid, result and info always invalid
598 case lir_pop: // input always valid, result and info always invalid
599 case lir_return: // input always valid, result and info always invalid
600 case lir_leal: // input and result always valid, info always invalid
601 case lir_neg: // input and result always valid, info always invalid
602 case lir_monaddr: // input and result always valid, info always invalid
603 case lir_null_check: // input and info always valid, result always invalid
604 case lir_move: // input and result always valid, may have info
605 case lir_pack64: // input and result always valid
606 case lir_unpack64: // input and result always valid
607 case lir_prefetchr: // input always valid, result and info always invalid
608 case lir_prefetchw: // input always valid, result and info always invalid
609 {
610 assert(op->as_Op1() != NULL, "must be");
611 LIR_Op1* op1 = (LIR_Op1*)op;
613 if (op1->_info) do_info(op1->_info);
614 if (op1->_opr->is_valid()) do_input(op1->_opr);
615 if (op1->_result->is_valid()) do_output(op1->_result);
617 break;
618 }
620 case lir_safepoint:
621 {
622 assert(op->as_Op1() != NULL, "must be");
623 LIR_Op1* op1 = (LIR_Op1*)op;
625 assert(op1->_info != NULL, ""); do_info(op1->_info);
626 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
627 assert(op1->_result->is_illegal(), "safepoint does not produce value");
629 break;
630 }
632 // LIR_OpConvert;
633 case lir_convert: // input and result always valid, info always invalid
634 {
635 assert(op->as_OpConvert() != NULL, "must be");
636 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
638 assert(opConvert->_info == NULL, "must be");
639 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
640 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
641 #ifdef PPC
642 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
643 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
644 #endif
645 do_stub(opConvert->_stub);
647 break;
648 }
650 // LIR_OpBranch;
651 case lir_branch: // may have info, input and result register always invalid
652 case lir_cond_float_branch: // may have info, input and result register always invalid
653 {
654 assert(op->as_OpBranch() != NULL, "must be");
655 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
657 #ifdef MIPS
658 if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
659 if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
660 if (opBranch->_tmp1->is_valid()) do_temp(opBranch->_tmp1);
661 if (opBranch->_tmp2->is_valid()) do_temp(opBranch->_tmp2);
662 if (opBranch->_tmp3->is_valid()) do_temp(opBranch->_tmp3);
663 if (opBranch->_tmp4->is_valid()) do_temp(opBranch->_tmp4);
664 if (opBranch->_tmp5->is_valid()) do_temp(opBranch->_tmp5);
665 #endif
666 if (opBranch->_info != NULL) do_info(opBranch->_info);
667 assert(opBranch->_result->is_illegal(), "not used");
668 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
670 break;
671 }
673 #ifdef MIPS
674 case lir_cmove_mips:
675 {
676 assert(op->as_Op4() != NULL, "must be");
677 LIR_Op4* op4 = (LIR_Op4*)op;
679 assert(op4->_info == NULL, "must be");
680 assert(op4->_opr1->is_valid() && op4->_opr2->is_valid() && op4->_opr3->is_valid() && op4->_opr4->is_valid() && op4->_result->is_valid(), "used");
682 do_input(op4->_opr1);
683 do_input(op4->_opr2);
684 do_input(op4->_opr3);
685 do_input(op4->_opr4);
686 if (op4->_tmp1->is_valid()) do_temp(op4->_tmp1);
687 if (op4->_tmp2->is_valid()) do_temp(op4->_tmp2);
688 if (op4->_tmp3->is_valid()) do_temp(op4->_tmp3);
689 if (op4->_tmp4->is_valid()) do_temp(op4->_tmp4);
690 if (op4->_tmp5->is_valid()) do_temp(op4->_tmp5);
691 do_output(op4->_result);
693 break;
694 }
695 #endif
697 // LIR_OpAllocObj
698 case lir_alloc_object:
699 {
700 assert(op->as_OpAllocObj() != NULL, "must be");
701 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
703 if (opAllocObj->_info) do_info(opAllocObj->_info);
704 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
705 do_temp(opAllocObj->_opr);
706 }
707 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
708 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
709 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
710 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
711 #ifdef MIPS
712 if (opAllocObj->_tmp5->is_valid()) do_temp(opAllocObj->_tmp5);
713 if (opAllocObj->_tmp6->is_valid()) do_temp(opAllocObj->_tmp6);
714 #endif
715 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
716 do_stub(opAllocObj->_stub);
717 break;
718 }
721 // LIR_OpRoundFP;
722 case lir_roundfp: {
723 assert(op->as_OpRoundFP() != NULL, "must be");
724 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
726 assert(op->_info == NULL, "info not used by this instruction");
727 assert(opRoundFP->_tmp->is_illegal(), "not used");
728 do_input(opRoundFP->_opr);
729 do_output(opRoundFP->_result);
731 break;
732 }
735 // LIR_Op2
736 #ifdef MIPS
737 case lir_null_check_for_branch:
738 #else
739 case lir_cmp:
740 #endif
741 case lir_cmp_l2i:
742 case lir_ucmp_fd2i:
743 case lir_cmp_fd2i:
744 case lir_add:
745 case lir_sub:
746 case lir_mul:
747 case lir_div:
748 case lir_rem:
749 case lir_sqrt:
750 case lir_abs:
751 case lir_logic_and:
752 case lir_logic_or:
753 case lir_logic_xor:
754 case lir_shl:
755 case lir_shr:
756 case lir_ushr:
757 case lir_xadd:
758 case lir_xchg:
759 case lir_assert:
760 {
761 assert(op->as_Op2() != NULL, "must be");
762 LIR_Op2* op2 = (LIR_Op2*)op;
763 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
764 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
766 if (op2->_info) do_info(op2->_info);
767 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
768 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
769 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
770 if (op2->_result->is_valid()) do_output(op2->_result);
771 if (op->code() == lir_xchg || op->code() == lir_xadd) {
772 // on ARM and PPC, return value is loaded first so could
773 // destroy inputs. On other platforms that implement those
774 // (x86, sparc), the extra constrainsts are harmless.
775 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
776 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
777 }
779 break;
780 }
782 // special handling for cmove: right input operand must not be equal
783 // to the result operand, otherwise the backend fails
784 case lir_cmove:
785 {
786 assert(op->as_Op2() != NULL, "must be");
787 LIR_Op2* op2 = (LIR_Op2*)op;
789 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
790 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
791 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
793 do_input(op2->_opr1);
794 do_input(op2->_opr2);
795 do_temp(op2->_opr2);
796 do_output(op2->_result);
798 break;
799 }
801 // vspecial handling for strict operations: register input operands
802 // as temp to guarantee that they do not overlap with other
803 // registers
804 case lir_mul_strictfp:
805 case lir_div_strictfp:
806 {
807 assert(op->as_Op2() != NULL, "must be");
808 LIR_Op2* op2 = (LIR_Op2*)op;
810 assert(op2->_info == NULL, "not used");
811 assert(op2->_opr1->is_valid(), "used");
812 assert(op2->_opr2->is_valid(), "used");
813 assert(op2->_result->is_valid(), "used");
814 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
815 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
817 do_input(op2->_opr1); do_temp(op2->_opr1);
818 do_input(op2->_opr2); do_temp(op2->_opr2);
819 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
820 do_output(op2->_result);
822 break;
823 }
825 case lir_throw: {
826 assert(op->as_Op2() != NULL, "must be");
827 LIR_Op2* op2 = (LIR_Op2*)op;
829 if (op2->_info) do_info(op2->_info);
830 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
831 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
832 assert(op2->_result->is_illegal(), "no result");
833 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
834 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
836 break;
837 }
839 case lir_unwind: {
840 assert(op->as_Op1() != NULL, "must be");
841 LIR_Op1* op1 = (LIR_Op1*)op;
843 assert(op1->_info == NULL, "no info");
844 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
845 assert(op1->_result->is_illegal(), "no result");
847 break;
848 }
851 case lir_tan:
852 case lir_sin:
853 case lir_cos:
854 case lir_log:
855 case lir_log10:
856 case lir_exp: {
857 assert(op->as_Op2() != NULL, "must be");
858 LIR_Op2* op2 = (LIR_Op2*)op;
860 // On x86 tan/sin/cos need two temporary fpu stack slots and
861 // log/log10 need one so handle opr2 and tmp as temp inputs.
862 // Register input operand as temp to guarantee that it doesn't
863 // overlap with the input.
864 assert(op2->_info == NULL, "not used");
865 assert(op2->_tmp5->is_illegal(), "not used");
866 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used");
867 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used");
868 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used");
869 assert(op2->_opr1->is_valid(), "used");
870 do_input(op2->_opr1); do_temp(op2->_opr1);
872 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
873 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
874 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2);
875 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3);
876 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4);
877 if (op2->_result->is_valid()) do_output(op2->_result);
879 break;
880 }
882 case lir_pow: {
883 assert(op->as_Op2() != NULL, "must be");
884 LIR_Op2* op2 = (LIR_Op2*)op;
886 // On x86 pow needs two temporary fpu stack slots: tmp1 and
887 // tmp2. Register input operands as temps to guarantee that it
888 // doesn't overlap with the temporary slots.
889 assert(op2->_info == NULL, "not used");
890 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used");
891 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid()
892 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used");
893 assert(op2->_result->is_valid(), "used");
895 do_input(op2->_opr1); do_temp(op2->_opr1);
896 do_input(op2->_opr2); do_temp(op2->_opr2);
897 do_temp(op2->_tmp1);
898 do_temp(op2->_tmp2);
899 do_temp(op2->_tmp3);
900 do_temp(op2->_tmp4);
901 do_temp(op2->_tmp5);
902 do_output(op2->_result);
904 break;
905 }
907 // LIR_Op3
908 #ifdef MIPS
909 case lir_frem:
910 #endif
911 case lir_idiv:
912 case lir_irem: {
913 assert(op->as_Op3() != NULL, "must be");
914 LIR_Op3* op3= (LIR_Op3*)op;
916 if (op3->_info) do_info(op3->_info);
917 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
919 // second operand is input and temp, so ensure that second operand
920 // and third operand get not the same register
921 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
922 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
923 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
925 if (op3->_result->is_valid()) do_output(op3->_result);
927 break;
928 }
931 // LIR_OpJavaCall
932 case lir_static_call:
933 case lir_optvirtual_call:
934 case lir_icvirtual_call:
935 case lir_virtual_call:
936 case lir_dynamic_call: {
937 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
938 assert(opJavaCall != NULL, "must be");
940 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
942 // only visit register parameters
943 int n = opJavaCall->_arguments->length();
944 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
945 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
946 do_input(*opJavaCall->_arguments->adr_at(i));
947 }
948 }
950 if (opJavaCall->_info) do_info(opJavaCall->_info);
951 if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr &&
952 opJavaCall->is_method_handle_invoke()) {
953 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
954 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
955 }
956 do_call();
957 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
959 break;
960 }
963 // LIR_OpRTCall
964 case lir_rtcall: {
965 assert(op->as_OpRTCall() != NULL, "must be");
966 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
968 // only visit register parameters
969 int n = opRTCall->_arguments->length();
970 for (int i = 0; i < n; i++) {
971 if (!opRTCall->_arguments->at(i)->is_pointer()) {
972 do_input(*opRTCall->_arguments->adr_at(i));
973 }
974 }
975 if (opRTCall->_info) do_info(opRTCall->_info);
976 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
977 do_call();
978 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
980 break;
981 }
984 // LIR_OpArrayCopy
985 case lir_arraycopy: {
986 assert(op->as_OpArrayCopy() != NULL, "must be");
987 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
989 assert(opArrayCopy->_result->is_illegal(), "unused");
990 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
991 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
992 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
993 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
994 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
995 #ifndef MIPS
996 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
997 #endif
998 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
1000 // the implementation of arraycopy always has a call into the runtime
1001 do_call();
1003 break;
1004 }
1007 // LIR_OpUpdateCRC32
1008 case lir_updatecrc32: {
1009 assert(op->as_OpUpdateCRC32() != NULL, "must be");
1010 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op;
1012 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc);
1013 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val);
1014 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result);
1015 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
1017 break;
1018 }
1021 // LIR_OpLock
1022 case lir_lock:
1023 case lir_unlock: {
1024 assert(op->as_OpLock() != NULL, "must be");
1025 LIR_OpLock* opLock = (LIR_OpLock*)op;
1027 if (opLock->_info) do_info(opLock->_info);
1029 // TODO: check if these operands really have to be temp
1030 // (or if input is sufficient). This may have influence on the oop map!
1031 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
1032 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
1033 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
1035 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
1036 assert(opLock->_result->is_illegal(), "unused");
1038 do_stub(opLock->_stub);
1040 break;
1041 }
1044 // LIR_OpDelay
1045 case lir_delay_slot: {
1046 assert(op->as_OpDelay() != NULL, "must be");
1047 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
1049 visit(opDelay->delay_op());
1050 break;
1051 }
1053 // LIR_OpTypeCheck
1054 case lir_instanceof:
1055 case lir_checkcast:
1056 case lir_store_check: {
1057 assert(op->as_OpTypeCheck() != NULL, "must be");
1058 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
1060 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
1061 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
1062 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
1063 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
1064 do_temp(opTypeCheck->_object);
1065 }
1066 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
1067 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
1068 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
1069 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
1070 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
1071 do_stub(opTypeCheck->_stub);
1072 break;
1073 }
1075 // LIR_OpCompareAndSwap
1076 case lir_cas_long:
1077 case lir_cas_obj:
1078 case lir_cas_int: {
1079 assert(op->as_OpCompareAndSwap() != NULL, "must be");
1080 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
1082 assert(opCompareAndSwap->_addr->is_valid(), "used");
1083 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
1084 assert(opCompareAndSwap->_new_value->is_valid(), "used");
1085 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
1086 do_input(opCompareAndSwap->_addr);
1087 do_temp(opCompareAndSwap->_addr);
1088 do_input(opCompareAndSwap->_cmp_value);
1089 do_temp(opCompareAndSwap->_cmp_value);
1090 do_input(opCompareAndSwap->_new_value);
1091 do_temp(opCompareAndSwap->_new_value);
1092 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
1093 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
1094 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
1096 break;
1097 }
1100 // LIR_OpAllocArray;
1101 case lir_alloc_array: {
1102 assert(op->as_OpAllocArray() != NULL, "must be");
1103 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
1105 if (opAllocArray->_info) do_info(opAllocArray->_info);
1106 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
1107 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
1108 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
1109 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
1110 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
1111 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
1112 #ifdef MIPS
1113 if (opAllocArray->_tmp5->is_valid()) do_temp(opAllocArray->_tmp5);
1114 #endif
1115 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
1116 do_stub(opAllocArray->_stub);
1117 break;
1118 }
1120 // LIR_OpProfileCall:
1121 case lir_profile_call: {
1122 assert(op->as_OpProfileCall() != NULL, "must be");
1123 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
1125 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
1126 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
1127 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
1128 break;
1129 }
1131 // LIR_OpProfileType:
1132 case lir_profile_type: {
1133 assert(op->as_OpProfileType() != NULL, "must be");
1134 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op;
1136 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp);
1137 do_input(opProfileType->_obj);
1138 do_temp(opProfileType->_tmp);
1139 break;
1140 }
1141 default:
1142 ShouldNotReachHere();
1143 }
1144 }
1147 void LIR_OpVisitState::do_stub(CodeStub* stub) {
1148 if (stub != NULL) {
1149 stub->visit(this);
1150 }
1151 }
1153 XHandlers* LIR_OpVisitState::all_xhandler() {
1154 XHandlers* result = NULL;
1156 int i;
1157 for (i = 0; i < info_count(); i++) {
1158 if (info_at(i)->exception_handlers() != NULL) {
1159 result = info_at(i)->exception_handlers();
1160 break;
1161 }
1162 }
1164 #ifdef ASSERT
1165 for (i = 0; i < info_count(); i++) {
1166 assert(info_at(i)->exception_handlers() == NULL ||
1167 info_at(i)->exception_handlers() == result,
1168 "only one xhandler list allowed per LIR-operation");
1169 }
1170 #endif
1172 if (result != NULL) {
1173 return result;
1174 } else {
1175 return new XHandlers();
1176 }
1178 return result;
1179 }
1182 #ifdef ASSERT
1183 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1184 visit(op);
1186 return opr_count(inputMode) == 0 &&
1187 opr_count(outputMode) == 0 &&
1188 opr_count(tempMode) == 0 &&
1189 info_count() == 0 &&
1190 !has_call() &&
1191 !has_slow_case();
1192 }
1193 #endif
1195 //---------------------------------------------------
1198 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1199 masm->emit_call(this);
1200 }
1202 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1203 masm->emit_rtcall(this);
1204 }
1206 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1207 masm->emit_opLabel(this);
1208 }
1210 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1211 masm->emit_arraycopy(this);
1212 masm->append_code_stub(stub());
1213 }
1215 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) {
1216 masm->emit_updatecrc32(this);
1217 }
1219 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1220 masm->emit_op0(this);
1221 }
1223 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1224 masm->emit_op1(this);
1225 }
1227 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1228 masm->emit_alloc_obj(this);
1229 masm->append_code_stub(stub());
1230 }
1232 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1233 masm->emit_opBranch(this);
1234 if (stub()) {
1235 masm->append_code_stub(stub());
1236 }
1237 }
1239 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1240 masm->emit_opConvert(this);
1241 if (stub() != NULL) {
1242 masm->append_code_stub(stub());
1243 }
1244 }
1246 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1247 masm->emit_op2(this);
1248 }
1250 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1251 masm->emit_alloc_array(this);
1252 masm->append_code_stub(stub());
1253 }
1255 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1256 masm->emit_opTypeCheck(this);
1257 if (stub()) {
1258 masm->append_code_stub(stub());
1259 }
1260 }
1262 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1263 masm->emit_compare_and_swap(this);
1264 }
1266 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1267 masm->emit_op3(this);
1268 }
1270 #ifdef MIPS
1271 void LIR_Op4::emit_code(LIR_Assembler* masm) {
1272 masm->emit_op4(this);
1273 }
1274 #endif
1276 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1277 masm->emit_lock(this);
1278 if (stub()) {
1279 masm->append_code_stub(stub());
1280 }
1281 }
1283 #ifdef ASSERT
1284 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1285 masm->emit_assert(this);
1286 }
1287 #endif
1289 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1290 masm->emit_delay(this);
1291 }
1293 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1294 masm->emit_profile_call(this);
1295 }
1297 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1298 masm->emit_profile_type(this);
1299 }
1301 // LIR_List
1302 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1303 : _operations(8)
1304 , _compilation(compilation)
1305 #ifndef PRODUCT
1306 , _block(block)
1307 #endif
1308 #ifdef ASSERT
1309 , _file(NULL)
1310 , _line(0)
1311 #endif
1312 { }
1315 #ifdef ASSERT
1316 void LIR_List::set_file_and_line(const char * file, int line) {
1317 const char * f = strrchr(file, '/');
1318 if (f == NULL) f = strrchr(file, '\\');
1319 if (f == NULL) {
1320 f = file;
1321 } else {
1322 f++;
1323 }
1324 _file = f;
1325 _line = line;
1326 }
1327 #endif
1330 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1331 assert(this == buffer->lir_list(), "wrong lir list");
1332 const int n = _operations.length();
1334 if (buffer->number_of_ops() > 0) {
1335 // increase size of instructions list
1336 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1337 // insert ops from buffer into instructions list
1338 int op_index = buffer->number_of_ops() - 1;
1339 int ip_index = buffer->number_of_insertion_points() - 1;
1340 int from_index = n - 1;
1341 int to_index = _operations.length() - 1;
1342 for (; ip_index >= 0; ip_index --) {
1343 int index = buffer->index_at(ip_index);
1344 // make room after insertion point
1345 while (index < from_index) {
1346 _operations.at_put(to_index --, _operations.at(from_index --));
1347 }
1348 // insert ops from buffer
1349 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1350 _operations.at_put(to_index --, buffer->op_at(op_index --));
1351 }
1352 }
1353 }
1355 buffer->finish();
1356 }
1359 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1360 assert(reg->type() == T_OBJECT, "bad reg");
1361 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1362 }
1364 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1365 assert(reg->type() == T_METADATA, "bad reg");
1366 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1367 }
1369 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1370 append(new LIR_Op1(
1371 lir_move,
1372 LIR_OprFact::address(addr),
1373 src,
1374 addr->type(),
1375 patch_code,
1376 info));
1377 }
1380 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1381 append(new LIR_Op1(
1382 lir_move,
1383 LIR_OprFact::address(address),
1384 dst,
1385 address->type(),
1386 patch_code,
1387 info, lir_move_volatile));
1388 }
1390 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1391 #ifdef MIPS
1392 add(base, offset, base);
1393 offset = 0;
1394 #endif
1395 append(new LIR_Op1(
1396 lir_move,
1397 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1398 dst,
1399 type,
1400 patch_code,
1401 info, lir_move_volatile));
1402 }
1405 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1406 append(new LIR_Op1(
1407 is_store ? lir_prefetchw : lir_prefetchr,
1408 LIR_OprFact::address(addr)));
1409 }
1412 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1413 append(new LIR_Op1(
1414 lir_move,
1415 LIR_OprFact::intConst(v),
1416 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1417 type,
1418 patch_code,
1419 info));
1420 }
1423 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1424 append(new LIR_Op1(
1425 lir_move,
1426 LIR_OprFact::oopConst(o),
1427 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1428 type,
1429 patch_code,
1430 info));
1431 }
1434 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1435 append(new LIR_Op1(
1436 lir_move,
1437 src,
1438 LIR_OprFact::address(addr),
1439 addr->type(),
1440 patch_code,
1441 info));
1442 }
1445 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1446 append(new LIR_Op1(
1447 lir_move,
1448 src,
1449 LIR_OprFact::address(addr),
1450 addr->type(),
1451 patch_code,
1452 info,
1453 lir_move_volatile));
1454 }
1456 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1457 #ifdef MIPS
1458 add(base, offset, base);
1459 offset = 0;
1460 #endif
1461 append(new LIR_Op1(
1462 lir_move,
1463 src,
1464 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1465 type,
1466 patch_code,
1467 info, lir_move_volatile));
1468 }
1470 #ifdef MIPS
1471 void LIR_List::frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1472 append(new LIR_Op3(
1473 lir_frem,
1474 left,
1475 right,
1476 tmp,
1477 res,
1478 info));
1479 }
1480 #endif
1482 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1483 append(new LIR_Op3(
1484 lir_idiv,
1485 left,
1486 right,
1487 tmp,
1488 res,
1489 info));
1490 }
1493 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1494 append(new LIR_Op3(
1495 lir_idiv,
1496 left,
1497 LIR_OprFact::intConst(right),
1498 tmp,
1499 res,
1500 info));
1501 }
1504 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1505 append(new LIR_Op3(
1506 lir_irem,
1507 left,
1508 right,
1509 tmp,
1510 res,
1511 info));
1512 }
1515 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1516 append(new LIR_Op3(
1517 lir_irem,
1518 left,
1519 LIR_OprFact::intConst(right),
1520 tmp,
1521 res,
1522 info));
1523 }
1526 #ifndef MIPS
1527 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1528 append(new LIR_Op2(
1529 lir_cmp,
1530 condition,
1531 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1532 LIR_OprFact::intConst(c),
1533 info));
1534 }
1536 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1537 append(new LIR_Op2(
1538 lir_cmp,
1539 condition,
1540 reg,
1541 LIR_OprFact::address(addr),
1542 info));
1543 }
1544 #endif
1546 void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) {
1547 if (deoptimize_on_null) {
1548 // Emit an explicit null check and deoptimize if opr is null
1549 CodeStub* deopt = new DeoptimizeStub(info);
1550 #ifndef MIPS
1551 cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1552 branch(lir_cond_equal, T_OBJECT, deopt);
1553 #else
1554 null_check_for_branch(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1555 branch(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL), T_OBJECT, deopt);
1556 #endif
1557 } else {
1558 // Emit an implicit null check
1559 append(new LIR_Op1(lir_null_check, opr, info));
1560 }
1561 }
1563 #ifndef MIPS
1564 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1565 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1566 append(new LIR_OpAllocObj(
1567 klass,
1568 dst,
1569 t1,
1570 t2,
1571 t3,
1572 t4,
1573 header_size,
1574 object_size,
1575 init_check,
1576 stub));
1577 }
1579 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1580 append(new LIR_OpAllocArray(
1581 klass,
1582 len,
1583 dst,
1584 t1,
1585 t2,
1586 t3,
1587 t4,
1588 type,
1589 stub));
1590 }
1591 #else
1592 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, LIR_Opr t5, LIR_Opr t6,
1593 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1594 append(new LIR_OpAllocObj(
1595 klass,
1596 dst,
1597 t1,
1598 t2,
1599 t3,
1600 t4,
1601 t5,
1602 t6,
1603 header_size,
1604 object_size,
1605 init_check,
1606 stub));
1607 }
1608 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, LIR_Opr t5,
1609 BasicType type, LIR_Opr klass, CodeStub* stub) {
1610 append(new LIR_OpAllocArray(
1611 klass,
1612 len,
1613 dst,
1614 t1,
1615 t2,
1616 t3,
1617 t4,
1618 t5,
1619 type,
1620 stub));
1621 }
1623 #endif
1625 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1626 append(new LIR_Op2(
1627 lir_shl,
1628 value,
1629 count,
1630 dst,
1631 tmp));
1632 }
1634 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1635 append(new LIR_Op2(
1636 lir_shr,
1637 value,
1638 count,
1639 dst,
1640 tmp));
1641 }
1644 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1645 append(new LIR_Op2(
1646 lir_ushr,
1647 value,
1648 count,
1649 dst,
1650 tmp));
1651 }
1653 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1654 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1655 left,
1656 right,
1657 dst));
1658 }
1660 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1661 append(new LIR_OpLock(
1662 lir_lock,
1663 hdr,
1664 obj,
1665 lock,
1666 scratch,
1667 stub,
1668 info));
1669 }
1671 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1672 append(new LIR_OpLock(
1673 lir_unlock,
1674 hdr,
1675 obj,
1676 lock,
1677 scratch,
1678 stub,
1679 NULL));
1680 }
1683 void check_LIR() {
1684 // cannot do the proper checking as PRODUCT and other modes return different results
1685 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1686 }
1690 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1691 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1692 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1693 ciMethod* profiled_method, int profiled_bci) {
1694 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1695 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1696 if (profiled_method != NULL) {
1697 c->set_profiled_method(profiled_method);
1698 c->set_profiled_bci(profiled_bci);
1699 c->set_should_profile(true);
1700 }
1701 append(c);
1702 }
1704 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1705 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1706 if (profiled_method != NULL) {
1707 c->set_profiled_method(profiled_method);
1708 c->set_profiled_bci(profiled_bci);
1709 c->set_should_profile(true);
1710 }
1711 append(c);
1712 }
1715 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1716 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1717 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1718 if (profiled_method != NULL) {
1719 c->set_profiled_method(profiled_method);
1720 c->set_profiled_bci(profiled_bci);
1721 c->set_should_profile(true);
1722 }
1723 append(c);
1724 }
1726 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1727 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1728 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1729 }
1731 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1732 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1733 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1734 }
1736 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1737 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1738 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1739 }
1742 #ifdef PRODUCT
1744 void print_LIR(BlockList* blocks) {
1745 }
1747 #else
1748 // LIR_OprDesc
1749 void LIR_OprDesc::print() const {
1750 print(tty);
1751 }
1753 void LIR_OprDesc::print(outputStream* out) const {
1754 if (is_illegal()) {
1755 return;
1756 }
1758 out->print("[");
1759 if (is_pointer()) {
1760 pointer()->print_value_on(out);
1761 } else if (is_single_stack()) {
1762 out->print("stack:%d", single_stack_ix());
1763 } else if (is_double_stack()) {
1764 out->print("dbl_stack:%d",double_stack_ix());
1765 } else if (is_virtual()) {
1766 out->print("R%d", vreg_number());
1767 } else if (is_single_cpu()) {
1768 out->print("%s", as_register()->name());
1769 } else if (is_double_cpu()) {
1770 out->print("%s", as_register_hi()->name());
1771 out->print("%s", as_register_lo()->name());
1772 #if defined(X86)
1773 } else if (is_single_xmm()) {
1774 out->print("%s", as_xmm_float_reg()->name());
1775 } else if (is_double_xmm()) {
1776 out->print("%s", as_xmm_double_reg()->name());
1777 } else if (is_single_fpu()) {
1778 out->print("fpu%d", fpu_regnr());
1779 } else if (is_double_fpu()) {
1780 out->print("fpu%d", fpu_regnrLo());
1781 #elif defined(ARM)
1782 } else if (is_single_fpu()) {
1783 out->print("s%d", fpu_regnr());
1784 } else if (is_double_fpu()) {
1785 out->print("d%d", fpu_regnrLo() >> 1);
1786 #else
1787 } else if (is_single_fpu()) {
1788 out->print("%s", as_float_reg()->name());
1789 } else if (is_double_fpu()) {
1790 out->print("%s", as_double_reg()->name());
1791 #endif
1793 } else if (is_illegal()) {
1794 out->print("-");
1795 } else {
1796 out->print("Unknown Operand");
1797 }
1798 if (!is_illegal()) {
1799 out->print("|%c", type_char());
1800 }
1801 if (is_register() && is_last_use()) {
1802 out->print("(last_use)");
1803 }
1804 out->print("]");
1805 }
1808 // LIR_Address
1809 void LIR_Const::print_value_on(outputStream* out) const {
1810 switch (type()) {
1811 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1812 case T_INT: out->print("int:%d", as_jint()); break;
1813 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1814 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1815 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1816 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break;
1817 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break;
1818 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break;
1819 }
1820 }
1822 // LIR_Address
1823 void LIR_Address::print_value_on(outputStream* out) const {
1824 out->print("Base:"); _base->print(out);
1825 #ifndef MIPS
1826 if (!_index->is_illegal()) {
1827 out->print(" Index:"); _index->print(out);
1828 switch (scale()) {
1829 case times_1: break;
1830 case times_2: out->print(" * 2"); break;
1831 case times_4: out->print(" * 4"); break;
1832 case times_8: out->print(" * 8"); break;
1833 }
1834 }
1835 #endif
1836 out->print(" Disp: " INTX_FORMAT, _disp);
1837 }
1839 // debug output of block header without InstructionPrinter
1840 // (because phi functions are not necessary for LIR)
1841 static void print_block(BlockBegin* x) {
1842 // print block id
1843 BlockEnd* end = x->end();
1844 tty->print("B%d ", x->block_id());
1846 // print flags
1847 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1848 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1849 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1850 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1851 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1852 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1853 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1855 // print block bci range
1856 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1858 // print predecessors and successors
1859 if (x->number_of_preds() > 0) {
1860 tty->print("preds: ");
1861 for (int i = 0; i < x->number_of_preds(); i ++) {
1862 tty->print("B%d ", x->pred_at(i)->block_id());
1863 }
1864 }
1866 if (x->number_of_sux() > 0) {
1867 tty->print("sux: ");
1868 for (int i = 0; i < x->number_of_sux(); i ++) {
1869 tty->print("B%d ", x->sux_at(i)->block_id());
1870 }
1871 }
1873 // print exception handlers
1874 if (x->number_of_exception_handlers() > 0) {
1875 tty->print("xhandler: ");
1876 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1877 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1878 }
1879 }
1881 tty->cr();
1882 }
1884 void print_LIR(BlockList* blocks) {
1885 tty->print_cr("LIR:");
1886 int i;
1887 for (i = 0; i < blocks->length(); i++) {
1888 BlockBegin* bb = blocks->at(i);
1889 print_block(bb);
1890 tty->print("__id_Instruction___________________________________________"); tty->cr();
1891 bb->lir()->print_instructions();
1892 }
1893 }
1895 void LIR_List::print_instructions() {
1896 for (int i = 0; i < _operations.length(); i++) {
1897 _operations.at(i)->print(); tty->cr();
1898 }
1899 tty->cr();
1900 }
1902 // LIR_Ops printing routines
1903 // LIR_Op
1904 void LIR_Op::print_on(outputStream* out) const {
1905 if (id() != -1 || PrintCFGToFile) {
1906 out->print("%4d ", id());
1907 } else {
1908 out->print(" ");
1909 }
1910 out->print("%s ", name());
1911 print_instr(out);
1912 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1913 #ifdef ASSERT
1914 if (Verbose && _file != NULL) {
1915 out->print(" (%s:%d)", _file, _line);
1916 }
1917 #endif
1918 }
1920 const char * LIR_Op::name() const {
1921 const char* s = NULL;
1922 switch(code()) {
1923 // LIR_Op0
1924 case lir_membar: s = "membar"; break;
1925 case lir_membar_acquire: s = "membar_acquire"; break;
1926 case lir_membar_release: s = "membar_release"; break;
1927 case lir_membar_loadload: s = "membar_loadload"; break;
1928 case lir_membar_storestore: s = "membar_storestore"; break;
1929 case lir_membar_loadstore: s = "membar_loadstore"; break;
1930 case lir_membar_storeload: s = "membar_storeload"; break;
1931 case lir_word_align: s = "word_align"; break;
1932 case lir_label: s = "label"; break;
1933 case lir_nop: s = "nop"; break;
1934 case lir_backwardbranch_target: s = "backbranch"; break;
1935 case lir_std_entry: s = "std_entry"; break;
1936 case lir_osr_entry: s = "osr_entry"; break;
1937 case lir_build_frame: s = "build_frm"; break;
1938 case lir_fpop_raw: s = "fpop_raw"; break;
1939 case lir_24bit_FPU: s = "24bit_FPU"; break;
1940 case lir_reset_FPU: s = "reset_FPU"; break;
1941 case lir_breakpoint: s = "breakpoint"; break;
1942 case lir_get_thread: s = "get_thread"; break;
1943 // LIR_Op1
1944 case lir_fxch: s = "fxch"; break;
1945 case lir_fld: s = "fld"; break;
1946 case lir_ffree: s = "ffree"; break;
1947 case lir_push: s = "push"; break;
1948 case lir_pop: s = "pop"; break;
1949 case lir_null_check: s = "null_check"; break;
1950 case lir_return: s = "return"; break;
1951 case lir_safepoint: s = "safepoint"; break;
1952 case lir_neg: s = "neg"; break;
1953 case lir_leal: s = "leal"; break;
1954 case lir_branch: s = "branch"; break;
1955 case lir_cond_float_branch: s = "flt_cond_br"; break;
1956 case lir_move: s = "move"; break;
1957 case lir_roundfp: s = "roundfp"; break;
1958 case lir_rtcall: s = "rtcall"; break;
1959 case lir_throw: s = "throw"; break;
1960 case lir_unwind: s = "unwind"; break;
1961 case lir_convert: s = "convert"; break;
1962 case lir_alloc_object: s = "alloc_obj"; break;
1963 case lir_monaddr: s = "mon_addr"; break;
1964 case lir_pack64: s = "pack64"; break;
1965 case lir_unpack64: s = "unpack64"; break;
1966 // LIR_Op2
1967 #ifdef MIPS
1968 case lir_null_check_for_branch: s = "null_check_for_branch"; break;
1969 #else
1970 case lir_cmp: s = "cmp"; break;
1971 #endif
1972 case lir_cmp_l2i: s = "cmp_l2i"; break;
1973 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1974 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1975 case lir_cmove: s = "cmove"; break;
1976 case lir_add: s = "add"; break;
1977 case lir_sub: s = "sub"; break;
1978 case lir_mul: s = "mul"; break;
1979 case lir_mul_strictfp: s = "mul_strictfp"; break;
1980 case lir_div: s = "div"; break;
1981 case lir_div_strictfp: s = "div_strictfp"; break;
1982 case lir_rem: s = "rem"; break;
1983 case lir_abs: s = "abs"; break;
1984 case lir_sqrt: s = "sqrt"; break;
1985 case lir_sin: s = "sin"; break;
1986 case lir_cos: s = "cos"; break;
1987 case lir_tan: s = "tan"; break;
1988 case lir_log: s = "log"; break;
1989 case lir_log10: s = "log10"; break;
1990 case lir_exp: s = "exp"; break;
1991 case lir_pow: s = "pow"; break;
1992 case lir_logic_and: s = "logic_and"; break;
1993 case lir_logic_or: s = "logic_or"; break;
1994 case lir_logic_xor: s = "logic_xor"; break;
1995 case lir_shl: s = "shift_left"; break;
1996 case lir_shr: s = "shift_right"; break;
1997 case lir_ushr: s = "ushift_right"; break;
1998 case lir_alloc_array: s = "alloc_array"; break;
1999 case lir_xadd: s = "xadd"; break;
2000 case lir_xchg: s = "xchg"; break;
2001 // LIR_Op3
2002 #ifdef MIPS
2003 case lir_frem: s = "frem"; break;
2004 #endif
2005 case lir_idiv: s = "idiv"; break;
2006 case lir_irem: s = "irem"; break;
2007 #ifdef MIPS
2008 // LIR_Op4
2009 case lir_cmove_mips: s = "cmove_mips"; break;
2010 #endif
2011 // LIR_OpJavaCall
2012 case lir_static_call: s = "static"; break;
2013 case lir_optvirtual_call: s = "optvirtual"; break;
2014 case lir_icvirtual_call: s = "icvirtual"; break;
2015 case lir_virtual_call: s = "virtual"; break;
2016 case lir_dynamic_call: s = "dynamic"; break;
2017 // LIR_OpArrayCopy
2018 case lir_arraycopy: s = "arraycopy"; break;
2019 // LIR_OpUpdateCRC32
2020 case lir_updatecrc32: s = "updatecrc32"; break;
2021 // LIR_OpLock
2022 case lir_lock: s = "lock"; break;
2023 case lir_unlock: s = "unlock"; break;
2024 // LIR_OpDelay
2025 case lir_delay_slot: s = "delay"; break;
2026 // LIR_OpTypeCheck
2027 case lir_instanceof: s = "instanceof"; break;
2028 case lir_checkcast: s = "checkcast"; break;
2029 case lir_store_check: s = "store_check"; break;
2030 // LIR_OpCompareAndSwap
2031 case lir_cas_long: s = "cas_long"; break;
2032 case lir_cas_obj: s = "cas_obj"; break;
2033 case lir_cas_int: s = "cas_int"; break;
2034 // LIR_OpProfileCall
2035 case lir_profile_call: s = "profile_call"; break;
2036 // LIR_OpProfileType
2037 case lir_profile_type: s = "profile_type"; break;
2038 // LIR_OpAssert
2039 #ifdef ASSERT
2040 case lir_assert: s = "assert"; break;
2041 #endif
2042 case lir_none: ShouldNotReachHere();break;
2043 default: s = "illegal_op"; break;
2044 }
2045 return s;
2046 }
2048 // LIR_OpJavaCall
2049 void LIR_OpJavaCall::print_instr(outputStream* out) const {
2050 out->print("call: ");
2051 out->print("[addr: " INTPTR_FORMAT "]", p2i(address()));
2052 if (receiver()->is_valid()) {
2053 out->print(" [recv: "); receiver()->print(out); out->print("]");
2054 }
2055 if (result_opr()->is_valid()) {
2056 out->print(" [result: "); result_opr()->print(out); out->print("]");
2057 }
2058 }
2060 // LIR_OpLabel
2061 void LIR_OpLabel::print_instr(outputStream* out) const {
2062 out->print("[label:" INTPTR_FORMAT "]", p2i(_label));
2063 }
2065 // LIR_OpArrayCopy
2066 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
2067 src()->print(out); out->print(" ");
2068 src_pos()->print(out); out->print(" ");
2069 dst()->print(out); out->print(" ");
2070 dst_pos()->print(out); out->print(" ");
2071 length()->print(out); out->print(" ");
2072 tmp()->print(out); out->print(" ");
2073 }
2075 // LIR_OpUpdateCRC32
2076 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const {
2077 crc()->print(out); out->print(" ");
2078 val()->print(out); out->print(" ");
2079 result_opr()->print(out); out->print(" ");
2080 }
2082 // LIR_OpCompareAndSwap
2083 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
2084 addr()->print(out); out->print(" ");
2085 cmp_value()->print(out); out->print(" ");
2086 new_value()->print(out); out->print(" ");
2087 tmp1()->print(out); out->print(" ");
2088 tmp2()->print(out); out->print(" ");
2090 }
2092 // LIR_Op0
2093 void LIR_Op0::print_instr(outputStream* out) const {
2094 result_opr()->print(out);
2095 }
2097 // LIR_Op1
2098 const char * LIR_Op1::name() const {
2099 if (code() == lir_move) {
2100 switch (move_kind()) {
2101 case lir_move_normal:
2102 return "move";
2103 case lir_move_unaligned:
2104 return "unaligned move";
2105 case lir_move_volatile:
2106 return "volatile_move";
2107 case lir_move_wide:
2108 return "wide_move";
2109 default:
2110 ShouldNotReachHere();
2111 return "illegal_op";
2112 }
2113 } else {
2114 return LIR_Op::name();
2115 }
2116 }
2119 void LIR_Op1::print_instr(outputStream* out) const {
2120 _opr->print(out); out->print(" ");
2121 result_opr()->print(out); out->print(" ");
2122 print_patch_code(out, patch_code());
2123 }
2126 // LIR_Op1
2127 void LIR_OpRTCall::print_instr(outputStream* out) const {
2128 intx a = (intx)addr();
2129 out->print("%s", Runtime1::name_for_address(addr()));
2130 out->print(" ");
2131 tmp()->print(out);
2132 }
2134 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
2135 switch(code) {
2136 case lir_patch_none: break;
2137 case lir_patch_low: out->print("[patch_low]"); break;
2138 case lir_patch_high: out->print("[patch_high]"); break;
2139 case lir_patch_normal: out->print("[patch_normal]"); break;
2140 default: ShouldNotReachHere();
2141 }
2142 }
2144 // LIR_OpBranch
2145 void LIR_OpBranch::print_instr(outputStream* out) const {
2146 print_condition(out, cond()); out->print(" ");
2147 #ifdef MIPS
2148 in_opr1()->print(out); out->print(" ");
2149 in_opr2()->print(out); out->print(" ");
2150 #endif
2151 if (block() != NULL) {
2152 out->print("[B%d] ", block()->block_id());
2153 } else if (stub() != NULL) {
2154 out->print("[");
2155 stub()->print_name(out);
2156 out->print(": " INTPTR_FORMAT "]", p2i(stub()));
2157 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
2158 } else {
2159 out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
2160 }
2161 if (ublock() != NULL) {
2162 out->print("unordered: [B%d] ", ublock()->block_id());
2163 }
2164 }
2166 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
2167 switch(cond) {
2168 case lir_cond_equal: out->print("[EQ]"); break;
2169 case lir_cond_notEqual: out->print("[NE]"); break;
2170 case lir_cond_less: out->print("[LT]"); break;
2171 case lir_cond_lessEqual: out->print("[LE]"); break;
2172 case lir_cond_greaterEqual: out->print("[GE]"); break;
2173 case lir_cond_greater: out->print("[GT]"); break;
2174 case lir_cond_belowEqual: out->print("[BE]"); break;
2175 case lir_cond_aboveEqual: out->print("[AE]"); break;
2176 case lir_cond_always: out->print("[AL]"); break;
2177 default: out->print("[%d]",cond); break;
2178 }
2179 }
2181 // LIR_OpConvert
2182 void LIR_OpConvert::print_instr(outputStream* out) const {
2183 print_bytecode(out, bytecode());
2184 in_opr()->print(out); out->print(" ");
2185 result_opr()->print(out); out->print(" ");
2186 #ifdef PPC
2187 if(tmp1()->is_valid()) {
2188 tmp1()->print(out); out->print(" ");
2189 tmp2()->print(out); out->print(" ");
2190 }
2191 #endif
2192 }
2194 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
2195 switch(code) {
2196 case Bytecodes::_d2f: out->print("[d2f] "); break;
2197 case Bytecodes::_d2i: out->print("[d2i] "); break;
2198 case Bytecodes::_d2l: out->print("[d2l] "); break;
2199 case Bytecodes::_f2d: out->print("[f2d] "); break;
2200 case Bytecodes::_f2i: out->print("[f2i] "); break;
2201 case Bytecodes::_f2l: out->print("[f2l] "); break;
2202 case Bytecodes::_i2b: out->print("[i2b] "); break;
2203 case Bytecodes::_i2c: out->print("[i2c] "); break;
2204 case Bytecodes::_i2d: out->print("[i2d] "); break;
2205 case Bytecodes::_i2f: out->print("[i2f] "); break;
2206 case Bytecodes::_i2l: out->print("[i2l] "); break;
2207 case Bytecodes::_i2s: out->print("[i2s] "); break;
2208 case Bytecodes::_l2i: out->print("[l2i] "); break;
2209 case Bytecodes::_l2f: out->print("[l2f] "); break;
2210 case Bytecodes::_l2d: out->print("[l2d] "); break;
2211 default:
2212 out->print("[?%d]",code);
2213 break;
2214 }
2215 }
2217 void LIR_OpAllocObj::print_instr(outputStream* out) const {
2218 klass()->print(out); out->print(" ");
2219 obj()->print(out); out->print(" ");
2220 tmp1()->print(out); out->print(" ");
2221 tmp2()->print(out); out->print(" ");
2222 tmp3()->print(out); out->print(" ");
2223 tmp4()->print(out); out->print(" ");
2224 #ifdef MIPS
2225 tmp5()->print(out); out->print(" ");
2226 tmp6()->print(out); out->print(" ");
2227 #endif
2228 out->print("[hdr:%d]", header_size()); out->print(" ");
2229 out->print("[obj:%d]", object_size()); out->print(" ");
2230 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2231 }
2233 void LIR_OpRoundFP::print_instr(outputStream* out) const {
2234 _opr->print(out); out->print(" ");
2235 tmp()->print(out); out->print(" ");
2236 result_opr()->print(out); out->print(" ");
2237 }
2239 // LIR_Op2
2240 void LIR_Op2::print_instr(outputStream* out) const {
2241 #ifndef MIPS
2242 if (code() == lir_cmove) {
2243 print_condition(out, condition()); out->print(" ");
2244 }
2245 #endif
2246 in_opr1()->print(out); out->print(" ");
2247 in_opr2()->print(out); out->print(" ");
2248 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
2249 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
2250 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
2251 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
2252 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
2253 result_opr()->print(out);
2254 }
2256 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2257 klass()->print(out); out->print(" ");
2258 len()->print(out); out->print(" ");
2259 obj()->print(out); out->print(" ");
2260 tmp1()->print(out); out->print(" ");
2261 tmp2()->print(out); out->print(" ");
2262 tmp3()->print(out); out->print(" ");
2263 tmp4()->print(out); out->print(" ");
2264 #ifdef MIPS
2265 tmp5()->print(out); out->print(" ");
2266 #endif
2267 out->print("[type:0x%x]", type()); out->print(" ");
2268 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2269 }
2272 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
2273 object()->print(out); out->print(" ");
2274 if (code() == lir_store_check) {
2275 array()->print(out); out->print(" ");
2276 }
2277 if (code() != lir_store_check) {
2278 klass()->print_name_on(out); out->print(" ");
2279 if (fast_check()) out->print("fast_check ");
2280 }
2281 tmp1()->print(out); out->print(" ");
2282 tmp2()->print(out); out->print(" ");
2283 tmp3()->print(out); out->print(" ");
2284 result_opr()->print(out); out->print(" ");
2285 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2286 }
2289 // LIR_Op3
2290 void LIR_Op3::print_instr(outputStream* out) const {
2291 in_opr1()->print(out); out->print(" ");
2292 in_opr2()->print(out); out->print(" ");
2293 in_opr3()->print(out); out->print(" ");
2294 result_opr()->print(out);
2295 }
2297 #ifdef MIPS
2298 // LIR_Op4
2299 void LIR_Op4::print_instr(outputStream* out) const {
2300 print_condition(out, cond()); out->print(" ");
2301 in_opr1()->print(out); out->print(" ");
2302 in_opr2()->print(out); out->print(" ");
2303 in_opr3()->print(out); out->print(" ");
2304 in_opr4()->print(out); out->print(" ");
2305 result_opr()->print(out);
2306 }
2307 #endif
2309 void LIR_OpLock::print_instr(outputStream* out) const {
2310 hdr_opr()->print(out); out->print(" ");
2311 obj_opr()->print(out); out->print(" ");
2312 lock_opr()->print(out); out->print(" ");
2313 if (_scratch->is_valid()) {
2314 _scratch->print(out); out->print(" ");
2315 }
2316 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2317 }
2319 #ifdef ASSERT
2320 void LIR_OpAssert::print_instr(outputStream* out) const {
2321 tty->print_cr("function LIR_OpAssert::print_instr unimplemented yet! ");
2322 Unimplemented();
2323 /*
2324 print_condition(out, condition()); out->print(" ");
2325 in_opr1()->print(out); out->print(" ");
2326 in_opr2()->print(out); out->print(", \"");
2327 out->print("%s", msg()); out->print("\"");
2328 */
2329 }
2330 #endif
2333 void LIR_OpDelay::print_instr(outputStream* out) const {
2334 _op->print_on(out);
2335 }
2338 // LIR_OpProfileCall
2339 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2340 profiled_method()->name()->print_symbol_on(out);
2341 out->print(".");
2342 profiled_method()->holder()->name()->print_symbol_on(out);
2343 out->print(" @ %d ", profiled_bci());
2344 mdo()->print(out); out->print(" ");
2345 recv()->print(out); out->print(" ");
2346 tmp1()->print(out); out->print(" ");
2347 }
2349 // LIR_OpProfileType
2350 void LIR_OpProfileType::print_instr(outputStream* out) const {
2351 out->print("exact = ");
2352 if (exact_klass() == NULL) {
2353 out->print("unknown");
2354 } else {
2355 exact_klass()->print_name_on(out);
2356 }
2357 out->print(" current = "); ciTypeEntries::print_ciklass(out, current_klass());
2358 out->print(" ");
2359 mdp()->print(out); out->print(" ");
2360 obj()->print(out); out->print(" ");
2361 tmp()->print(out); out->print(" ");
2362 }
2364 #endif // PRODUCT
2366 // Implementation of LIR_InsertionBuffer
2368 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2369 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2371 int i = number_of_insertion_points() - 1;
2372 if (i < 0 || index_at(i) < index) {
2373 append_new(index, 1);
2374 } else {
2375 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2376 assert(count_at(i) > 0, "check");
2377 set_count_at(i, count_at(i) + 1);
2378 }
2379 _ops.push(op);
2381 DEBUG_ONLY(verify());
2382 }
2384 #ifdef ASSERT
2385 void LIR_InsertionBuffer::verify() {
2386 int sum = 0;
2387 int prev_idx = -1;
2389 for (int i = 0; i < number_of_insertion_points(); i++) {
2390 assert(prev_idx < index_at(i), "index must be ordered ascending");
2391 sum += count_at(i);
2392 }
2393 assert(sum == number_of_ops(), "wrong total sum");
2394 }
2395 #endif
