Tue, 24 Jul 2012 10:51:00 -0700
7023639: JSR 292 method handle invocation needs a fast path for compiled code
6984705: JSR 292 method handle creation should not go through JNI
Summary: remove assembly code for JDK 7 chained method handles
Reviewed-by: jrose, twisti, kvn, mhaupt
Contributed-by: John Rose <john.r.rose@oracle.com>, Christian Thalinger <christian.thalinger@oracle.com>, Michael Haupt <michael.haupt@oracle.com>
1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "assembler_x86.inline.hpp"
27 #include "gc_interface/collectedHeap.inline.hpp"
28 #include "interpreter/interpreter.hpp"
29 #include "memory/cardTableModRefBS.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "prims/methodHandles.hpp"
32 #include "runtime/biasedLocking.hpp"
33 #include "runtime/interfaceSupport.hpp"
34 #include "runtime/objectMonitor.hpp"
35 #include "runtime/os.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #ifndef SERIALGC
39 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
40 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
41 #include "gc_implementation/g1/heapRegion.hpp"
42 #endif
44 #ifdef PRODUCT
45 #define BLOCK_COMMENT(str) /* nothing */
46 #define STOP(error) stop(error)
47 #else
48 #define BLOCK_COMMENT(str) block_comment(str)
49 #define STOP(error) block_comment(error); stop(error)
50 #endif
52 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
53 // Implementation of AddressLiteral
55 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
56 _is_lval = false;
57 _target = target;
58 switch (rtype) {
59 case relocInfo::oop_type:
60 // Oops are a special case. Normally they would be their own section
61 // but in cases like icBuffer they are literals in the code stream that
62 // we don't have a section for. We use none so that we get a literal address
63 // which is always patchable.
64 break;
65 case relocInfo::external_word_type:
66 _rspec = external_word_Relocation::spec(target);
67 break;
68 case relocInfo::internal_word_type:
69 _rspec = internal_word_Relocation::spec(target);
70 break;
71 case relocInfo::opt_virtual_call_type:
72 _rspec = opt_virtual_call_Relocation::spec();
73 break;
74 case relocInfo::static_call_type:
75 _rspec = static_call_Relocation::spec();
76 break;
77 case relocInfo::runtime_call_type:
78 _rspec = runtime_call_Relocation::spec();
79 break;
80 case relocInfo::poll_type:
81 case relocInfo::poll_return_type:
82 _rspec = Relocation::spec_simple(rtype);
83 break;
84 case relocInfo::none:
85 break;
86 default:
87 ShouldNotReachHere();
88 break;
89 }
90 }
92 // Implementation of Address
94 #ifdef _LP64
96 Address Address::make_array(ArrayAddress adr) {
97 // Not implementable on 64bit machines
98 // Should have been handled higher up the call chain.
99 ShouldNotReachHere();
100 return Address();
101 }
103 // exceedingly dangerous constructor
104 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
105 _base = noreg;
106 _index = noreg;
107 _scale = no_scale;
108 _disp = disp;
109 switch (rtype) {
110 case relocInfo::external_word_type:
111 _rspec = external_word_Relocation::spec(loc);
112 break;
113 case relocInfo::internal_word_type:
114 _rspec = internal_word_Relocation::spec(loc);
115 break;
116 case relocInfo::runtime_call_type:
117 // HMM
118 _rspec = runtime_call_Relocation::spec();
119 break;
120 case relocInfo::poll_type:
121 case relocInfo::poll_return_type:
122 _rspec = Relocation::spec_simple(rtype);
123 break;
124 case relocInfo::none:
125 break;
126 default:
127 ShouldNotReachHere();
128 }
129 }
130 #else // LP64
132 Address Address::make_array(ArrayAddress adr) {
133 AddressLiteral base = adr.base();
134 Address index = adr.index();
135 assert(index._disp == 0, "must not have disp"); // maybe it can?
136 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
137 array._rspec = base._rspec;
138 return array;
139 }
141 // exceedingly dangerous constructor
142 Address::Address(address loc, RelocationHolder spec) {
143 _base = noreg;
144 _index = noreg;
145 _scale = no_scale;
146 _disp = (intptr_t) loc;
147 _rspec = spec;
148 }
150 #endif // _LP64
154 // Convert the raw encoding form into the form expected by the constructor for
155 // Address. An index of 4 (rsp) corresponds to having no index, so convert
156 // that to noreg for the Address constructor.
157 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) {
158 RelocationHolder rspec;
159 if (disp_is_oop) {
160 rspec = Relocation::spec_simple(relocInfo::oop_type);
161 }
162 bool valid_index = index != rsp->encoding();
163 if (valid_index) {
164 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
165 madr._rspec = rspec;
166 return madr;
167 } else {
168 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
169 madr._rspec = rspec;
170 return madr;
171 }
172 }
174 // Implementation of Assembler
176 int AbstractAssembler::code_fill_byte() {
177 return (u_char)'\xF4'; // hlt
178 }
180 // make this go away someday
181 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
182 if (rtype == relocInfo::none)
183 emit_long(data);
184 else emit_data(data, Relocation::spec_simple(rtype), format);
185 }
187 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
188 assert(imm_operand == 0, "default format must be immediate in this file");
189 assert(inst_mark() != NULL, "must be inside InstructionMark");
190 if (rspec.type() != relocInfo::none) {
191 #ifdef ASSERT
192 check_relocation(rspec, format);
193 #endif
194 // Do not use AbstractAssembler::relocate, which is not intended for
195 // embedded words. Instead, relocate to the enclosing instruction.
197 // hack. call32 is too wide for mask so use disp32
198 if (format == call32_operand)
199 code_section()->relocate(inst_mark(), rspec, disp32_operand);
200 else
201 code_section()->relocate(inst_mark(), rspec, format);
202 }
203 emit_long(data);
204 }
206 static int encode(Register r) {
207 int enc = r->encoding();
208 if (enc >= 8) {
209 enc -= 8;
210 }
211 return enc;
212 }
214 static int encode(XMMRegister r) {
215 int enc = r->encoding();
216 if (enc >= 8) {
217 enc -= 8;
218 }
219 return enc;
220 }
222 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
223 assert(dst->has_byte_register(), "must have byte register");
224 assert(isByte(op1) && isByte(op2), "wrong opcode");
225 assert(isByte(imm8), "not a byte");
226 assert((op1 & 0x01) == 0, "should be 8bit operation");
227 emit_byte(op1);
228 emit_byte(op2 | encode(dst));
229 emit_byte(imm8);
230 }
233 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
234 assert(isByte(op1) && isByte(op2), "wrong opcode");
235 assert((op1 & 0x01) == 1, "should be 32bit operation");
236 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
237 if (is8bit(imm32)) {
238 emit_byte(op1 | 0x02); // set sign bit
239 emit_byte(op2 | encode(dst));
240 emit_byte(imm32 & 0xFF);
241 } else {
242 emit_byte(op1);
243 emit_byte(op2 | encode(dst));
244 emit_long(imm32);
245 }
246 }
248 // Force generation of a 4 byte immediate value even if it fits into 8bit
249 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert((op1 & 0x01) == 1, "should be 32bit operation");
252 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
253 emit_byte(op1);
254 emit_byte(op2 | encode(dst));
255 emit_long(imm32);
256 }
258 // immediate-to-memory forms
259 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
260 assert((op1 & 0x01) == 1, "should be 32bit operation");
261 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
262 if (is8bit(imm32)) {
263 emit_byte(op1 | 0x02); // set sign bit
264 emit_operand(rm, adr, 1);
265 emit_byte(imm32 & 0xFF);
266 } else {
267 emit_byte(op1);
268 emit_operand(rm, adr, 4);
269 emit_long(imm32);
270 }
271 }
273 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) {
274 LP64_ONLY(ShouldNotReachHere());
275 assert(isByte(op1) && isByte(op2), "wrong opcode");
276 assert((op1 & 0x01) == 1, "should be 32bit operation");
277 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
278 InstructionMark im(this);
279 emit_byte(op1);
280 emit_byte(op2 | encode(dst));
281 emit_data((intptr_t)obj, relocInfo::oop_type, 0);
282 }
285 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
286 assert(isByte(op1) && isByte(op2), "wrong opcode");
287 emit_byte(op1);
288 emit_byte(op2 | encode(dst) << 3 | encode(src));
289 }
292 void Assembler::emit_operand(Register reg, Register base, Register index,
293 Address::ScaleFactor scale, int disp,
294 RelocationHolder const& rspec,
295 int rip_relative_correction) {
296 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
298 // Encode the registers as needed in the fields they are used in
300 int regenc = encode(reg) << 3;
301 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
302 int baseenc = base->is_valid() ? encode(base) : 0;
304 if (base->is_valid()) {
305 if (index->is_valid()) {
306 assert(scale != Address::no_scale, "inconsistent address");
307 // [base + index*scale + disp]
308 if (disp == 0 && rtype == relocInfo::none &&
309 base != rbp LP64_ONLY(&& base != r13)) {
310 // [base + index*scale]
311 // [00 reg 100][ss index base]
312 assert(index != rsp, "illegal addressing mode");
313 emit_byte(0x04 | regenc);
314 emit_byte(scale << 6 | indexenc | baseenc);
315 } else if (is8bit(disp) && rtype == relocInfo::none) {
316 // [base + index*scale + imm8]
317 // [01 reg 100][ss index base] imm8
318 assert(index != rsp, "illegal addressing mode");
319 emit_byte(0x44 | regenc);
320 emit_byte(scale << 6 | indexenc | baseenc);
321 emit_byte(disp & 0xFF);
322 } else {
323 // [base + index*scale + disp32]
324 // [10 reg 100][ss index base] disp32
325 assert(index != rsp, "illegal addressing mode");
326 emit_byte(0x84 | regenc);
327 emit_byte(scale << 6 | indexenc | baseenc);
328 emit_data(disp, rspec, disp32_operand);
329 }
330 } else if (base == rsp LP64_ONLY(|| base == r12)) {
331 // [rsp + disp]
332 if (disp == 0 && rtype == relocInfo::none) {
333 // [rsp]
334 // [00 reg 100][00 100 100]
335 emit_byte(0x04 | regenc);
336 emit_byte(0x24);
337 } else if (is8bit(disp) && rtype == relocInfo::none) {
338 // [rsp + imm8]
339 // [01 reg 100][00 100 100] disp8
340 emit_byte(0x44 | regenc);
341 emit_byte(0x24);
342 emit_byte(disp & 0xFF);
343 } else {
344 // [rsp + imm32]
345 // [10 reg 100][00 100 100] disp32
346 emit_byte(0x84 | regenc);
347 emit_byte(0x24);
348 emit_data(disp, rspec, disp32_operand);
349 }
350 } else {
351 // [base + disp]
352 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
353 if (disp == 0 && rtype == relocInfo::none &&
354 base != rbp LP64_ONLY(&& base != r13)) {
355 // [base]
356 // [00 reg base]
357 emit_byte(0x00 | regenc | baseenc);
358 } else if (is8bit(disp) && rtype == relocInfo::none) {
359 // [base + disp8]
360 // [01 reg base] disp8
361 emit_byte(0x40 | regenc | baseenc);
362 emit_byte(disp & 0xFF);
363 } else {
364 // [base + disp32]
365 // [10 reg base] disp32
366 emit_byte(0x80 | regenc | baseenc);
367 emit_data(disp, rspec, disp32_operand);
368 }
369 }
370 } else {
371 if (index->is_valid()) {
372 assert(scale != Address::no_scale, "inconsistent address");
373 // [index*scale + disp]
374 // [00 reg 100][ss index 101] disp32
375 assert(index != rsp, "illegal addressing mode");
376 emit_byte(0x04 | regenc);
377 emit_byte(scale << 6 | indexenc | 0x05);
378 emit_data(disp, rspec, disp32_operand);
379 } else if (rtype != relocInfo::none ) {
380 // [disp] (64bit) RIP-RELATIVE (32bit) abs
381 // [00 000 101] disp32
383 emit_byte(0x05 | regenc);
384 // Note that the RIP-rel. correction applies to the generated
385 // disp field, but _not_ to the target address in the rspec.
387 // disp was created by converting the target address minus the pc
388 // at the start of the instruction. That needs more correction here.
389 // intptr_t disp = target - next_ip;
390 assert(inst_mark() != NULL, "must be inside InstructionMark");
391 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
392 int64_t adjusted = disp;
393 // Do rip-rel adjustment for 64bit
394 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
395 assert(is_simm32(adjusted),
396 "must be 32bit offset (RIP relative address)");
397 emit_data((int32_t) adjusted, rspec, disp32_operand);
399 } else {
400 // 32bit never did this, did everything as the rip-rel/disp code above
401 // [disp] ABSOLUTE
402 // [00 reg 100][00 100 101] disp32
403 emit_byte(0x04 | regenc);
404 emit_byte(0x25);
405 emit_data(disp, rspec, disp32_operand);
406 }
407 }
408 }
410 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
411 Address::ScaleFactor scale, int disp,
412 RelocationHolder const& rspec) {
413 emit_operand((Register)reg, base, index, scale, disp, rspec);
414 }
416 // Secret local extension to Assembler::WhichOperand:
417 #define end_pc_operand (_WhichOperand_limit)
419 address Assembler::locate_operand(address inst, WhichOperand which) {
420 // Decode the given instruction, and return the address of
421 // an embedded 32-bit operand word.
423 // If "which" is disp32_operand, selects the displacement portion
424 // of an effective address specifier.
425 // If "which" is imm64_operand, selects the trailing immediate constant.
426 // If "which" is call32_operand, selects the displacement of a call or jump.
427 // Caller is responsible for ensuring that there is such an operand,
428 // and that it is 32/64 bits wide.
430 // If "which" is end_pc_operand, find the end of the instruction.
432 address ip = inst;
433 bool is_64bit = false;
435 debug_only(bool has_disp32 = false);
436 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
438 again_after_prefix:
439 switch (0xFF & *ip++) {
441 // These convenience macros generate groups of "case" labels for the switch.
442 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
443 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
444 case (x)+4: case (x)+5: case (x)+6: case (x)+7
445 #define REP16(x) REP8((x)+0): \
446 case REP8((x)+8)
448 case CS_segment:
449 case SS_segment:
450 case DS_segment:
451 case ES_segment:
452 case FS_segment:
453 case GS_segment:
454 // Seems dubious
455 LP64_ONLY(assert(false, "shouldn't have that prefix"));
456 assert(ip == inst+1, "only one prefix allowed");
457 goto again_after_prefix;
459 case 0x67:
460 case REX:
461 case REX_B:
462 case REX_X:
463 case REX_XB:
464 case REX_R:
465 case REX_RB:
466 case REX_RX:
467 case REX_RXB:
468 NOT_LP64(assert(false, "64bit prefixes"));
469 goto again_after_prefix;
471 case REX_W:
472 case REX_WB:
473 case REX_WX:
474 case REX_WXB:
475 case REX_WR:
476 case REX_WRB:
477 case REX_WRX:
478 case REX_WRXB:
479 NOT_LP64(assert(false, "64bit prefixes"));
480 is_64bit = true;
481 goto again_after_prefix;
483 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
484 case 0x88: // movb a, r
485 case 0x89: // movl a, r
486 case 0x8A: // movb r, a
487 case 0x8B: // movl r, a
488 case 0x8F: // popl a
489 debug_only(has_disp32 = true);
490 break;
492 case 0x68: // pushq #32
493 if (which == end_pc_operand) {
494 return ip + 4;
495 }
496 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
497 return ip; // not produced by emit_operand
499 case 0x66: // movw ... (size prefix)
500 again_after_size_prefix2:
501 switch (0xFF & *ip++) {
502 case REX:
503 case REX_B:
504 case REX_X:
505 case REX_XB:
506 case REX_R:
507 case REX_RB:
508 case REX_RX:
509 case REX_RXB:
510 case REX_W:
511 case REX_WB:
512 case REX_WX:
513 case REX_WXB:
514 case REX_WR:
515 case REX_WRB:
516 case REX_WRX:
517 case REX_WRXB:
518 NOT_LP64(assert(false, "64bit prefix found"));
519 goto again_after_size_prefix2;
520 case 0x8B: // movw r, a
521 case 0x89: // movw a, r
522 debug_only(has_disp32 = true);
523 break;
524 case 0xC7: // movw a, #16
525 debug_only(has_disp32 = true);
526 tail_size = 2; // the imm16
527 break;
528 case 0x0F: // several SSE/SSE2 variants
529 ip--; // reparse the 0x0F
530 goto again_after_prefix;
531 default:
532 ShouldNotReachHere();
533 }
534 break;
536 case REP8(0xB8): // movl/q r, #32/#64(oop?)
537 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
538 // these asserts are somewhat nonsensical
539 #ifndef _LP64
540 assert(which == imm_operand || which == disp32_operand,
541 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip));
542 #else
543 assert((which == call32_operand || which == imm_operand) && is_64bit ||
544 which == narrow_oop_operand && !is_64bit,
545 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip));
546 #endif // _LP64
547 return ip;
549 case 0x69: // imul r, a, #32
550 case 0xC7: // movl a, #32(oop?)
551 tail_size = 4;
552 debug_only(has_disp32 = true); // has both kinds of operands!
553 break;
555 case 0x0F: // movx..., etc.
556 switch (0xFF & *ip++) {
557 case 0x3A: // pcmpestri
558 tail_size = 1;
559 case 0x38: // ptest, pmovzxbw
560 ip++; // skip opcode
561 debug_only(has_disp32 = true); // has both kinds of operands!
562 break;
564 case 0x70: // pshufd r, r/a, #8
565 debug_only(has_disp32 = true); // has both kinds of operands!
566 case 0x73: // psrldq r, #8
567 tail_size = 1;
568 break;
570 case 0x12: // movlps
571 case 0x28: // movaps
572 case 0x2E: // ucomiss
573 case 0x2F: // comiss
574 case 0x54: // andps
575 case 0x55: // andnps
576 case 0x56: // orps
577 case 0x57: // xorps
578 case 0x6E: // movd
579 case 0x7E: // movd
580 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
581 debug_only(has_disp32 = true);
582 break;
584 case 0xAD: // shrd r, a, %cl
585 case 0xAF: // imul r, a
586 case 0xBE: // movsbl r, a (movsxb)
587 case 0xBF: // movswl r, a (movsxw)
588 case 0xB6: // movzbl r, a (movzxb)
589 case 0xB7: // movzwl r, a (movzxw)
590 case REP16(0x40): // cmovl cc, r, a
591 case 0xB0: // cmpxchgb
592 case 0xB1: // cmpxchg
593 case 0xC1: // xaddl
594 case 0xC7: // cmpxchg8
595 case REP16(0x90): // setcc a
596 debug_only(has_disp32 = true);
597 // fall out of the switch to decode the address
598 break;
600 case 0xC4: // pinsrw r, a, #8
601 debug_only(has_disp32 = true);
602 case 0xC5: // pextrw r, r, #8
603 tail_size = 1; // the imm8
604 break;
606 case 0xAC: // shrd r, a, #8
607 debug_only(has_disp32 = true);
608 tail_size = 1; // the imm8
609 break;
611 case REP16(0x80): // jcc rdisp32
612 if (which == end_pc_operand) return ip + 4;
613 assert(which == call32_operand, "jcc has no disp32 or imm");
614 return ip;
615 default:
616 ShouldNotReachHere();
617 }
618 break;
620 case 0x81: // addl a, #32; addl r, #32
621 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
622 // on 32bit in the case of cmpl, the imm might be an oop
623 tail_size = 4;
624 debug_only(has_disp32 = true); // has both kinds of operands!
625 break;
627 case 0x83: // addl a, #8; addl r, #8
628 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
629 debug_only(has_disp32 = true); // has both kinds of operands!
630 tail_size = 1;
631 break;
633 case 0x9B:
634 switch (0xFF & *ip++) {
635 case 0xD9: // fnstcw a
636 debug_only(has_disp32 = true);
637 break;
638 default:
639 ShouldNotReachHere();
640 }
641 break;
643 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
644 case REP4(0x10): // adc...
645 case REP4(0x20): // and...
646 case REP4(0x30): // xor...
647 case REP4(0x08): // or...
648 case REP4(0x18): // sbb...
649 case REP4(0x28): // sub...
650 case 0xF7: // mull a
651 case 0x8D: // lea r, a
652 case 0x87: // xchg r, a
653 case REP4(0x38): // cmp...
654 case 0x85: // test r, a
655 debug_only(has_disp32 = true); // has both kinds of operands!
656 break;
658 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
659 case 0xC6: // movb a, #8
660 case 0x80: // cmpb a, #8
661 case 0x6B: // imul r, a, #8
662 debug_only(has_disp32 = true); // has both kinds of operands!
663 tail_size = 1; // the imm8
664 break;
666 case 0xC4: // VEX_3bytes
667 case 0xC5: // VEX_2bytes
668 assert((UseAVX > 0), "shouldn't have VEX prefix");
669 assert(ip == inst+1, "no prefixes allowed");
670 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
671 // but they have prefix 0x0F and processed when 0x0F processed above.
672 //
673 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
674 // instructions (these instructions are not supported in 64-bit mode).
675 // To distinguish them bits [7:6] are set in the VEX second byte since
676 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
677 // those VEX bits REX and vvvv bits are inverted.
678 //
679 // Fortunately C2 doesn't generate these instructions so we don't need
680 // to check for them in product version.
682 // Check second byte
683 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
685 // First byte
686 if ((0xFF & *inst) == VEX_3bytes) {
687 ip++; // third byte
688 is_64bit = ((VEX_W & *ip) == VEX_W);
689 }
690 ip++; // opcode
691 // To find the end of instruction (which == end_pc_operand).
692 switch (0xFF & *ip) {
693 case 0x61: // pcmpestri r, r/a, #8
694 case 0x70: // pshufd r, r/a, #8
695 case 0x73: // psrldq r, #8
696 tail_size = 1; // the imm8
697 break;
698 default:
699 break;
700 }
701 ip++; // skip opcode
702 debug_only(has_disp32 = true); // has both kinds of operands!
703 break;
705 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
706 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
707 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
708 case 0xDD: // fld_d a; fst_d a; fstp_d a
709 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
710 case 0xDF: // fild_d a; fistp_d a
711 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
712 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
713 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
714 debug_only(has_disp32 = true);
715 break;
717 case 0xE8: // call rdisp32
718 case 0xE9: // jmp rdisp32
719 if (which == end_pc_operand) return ip + 4;
720 assert(which == call32_operand, "call has no disp32 or imm");
721 return ip;
723 case 0xF0: // Lock
724 assert(os::is_MP(), "only on MP");
725 goto again_after_prefix;
727 case 0xF3: // For SSE
728 case 0xF2: // For SSE2
729 switch (0xFF & *ip++) {
730 case REX:
731 case REX_B:
732 case REX_X:
733 case REX_XB:
734 case REX_R:
735 case REX_RB:
736 case REX_RX:
737 case REX_RXB:
738 case REX_W:
739 case REX_WB:
740 case REX_WX:
741 case REX_WXB:
742 case REX_WR:
743 case REX_WRB:
744 case REX_WRX:
745 case REX_WRXB:
746 NOT_LP64(assert(false, "found 64bit prefix"));
747 ip++;
748 default:
749 ip++;
750 }
751 debug_only(has_disp32 = true); // has both kinds of operands!
752 break;
754 default:
755 ShouldNotReachHere();
757 #undef REP8
758 #undef REP16
759 }
761 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
762 #ifdef _LP64
763 assert(which != imm_operand, "instruction is not a movq reg, imm64");
764 #else
765 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
766 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
767 #endif // LP64
768 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
770 // parse the output of emit_operand
771 int op2 = 0xFF & *ip++;
772 int base = op2 & 0x07;
773 int op3 = -1;
774 const int b100 = 4;
775 const int b101 = 5;
776 if (base == b100 && (op2 >> 6) != 3) {
777 op3 = 0xFF & *ip++;
778 base = op3 & 0x07; // refetch the base
779 }
780 // now ip points at the disp (if any)
782 switch (op2 >> 6) {
783 case 0:
784 // [00 reg 100][ss index base]
785 // [00 reg 100][00 100 esp]
786 // [00 reg base]
787 // [00 reg 100][ss index 101][disp32]
788 // [00 reg 101] [disp32]
790 if (base == b101) {
791 if (which == disp32_operand)
792 return ip; // caller wants the disp32
793 ip += 4; // skip the disp32
794 }
795 break;
797 case 1:
798 // [01 reg 100][ss index base][disp8]
799 // [01 reg 100][00 100 esp][disp8]
800 // [01 reg base] [disp8]
801 ip += 1; // skip the disp8
802 break;
804 case 2:
805 // [10 reg 100][ss index base][disp32]
806 // [10 reg 100][00 100 esp][disp32]
807 // [10 reg base] [disp32]
808 if (which == disp32_operand)
809 return ip; // caller wants the disp32
810 ip += 4; // skip the disp32
811 break;
813 case 3:
814 // [11 reg base] (not a memory addressing mode)
815 break;
816 }
818 if (which == end_pc_operand) {
819 return ip + tail_size;
820 }
822 #ifdef _LP64
823 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
824 #else
825 assert(which == imm_operand, "instruction has only an imm field");
826 #endif // LP64
827 return ip;
828 }
830 address Assembler::locate_next_instruction(address inst) {
831 // Secretly share code with locate_operand:
832 return locate_operand(inst, end_pc_operand);
833 }
836 #ifdef ASSERT
837 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
838 address inst = inst_mark();
839 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
840 address opnd;
842 Relocation* r = rspec.reloc();
843 if (r->type() == relocInfo::none) {
844 return;
845 } else if (r->is_call() || format == call32_operand) {
846 // assert(format == imm32_operand, "cannot specify a nonzero format");
847 opnd = locate_operand(inst, call32_operand);
848 } else if (r->is_data()) {
849 assert(format == imm_operand || format == disp32_operand
850 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
851 opnd = locate_operand(inst, (WhichOperand)format);
852 } else {
853 assert(format == imm_operand, "cannot specify a format");
854 return;
855 }
856 assert(opnd == pc(), "must put operand where relocs can find it");
857 }
858 #endif // ASSERT
860 void Assembler::emit_operand32(Register reg, Address adr) {
861 assert(reg->encoding() < 8, "no extended registers");
862 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
863 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
864 adr._rspec);
865 }
867 void Assembler::emit_operand(Register reg, Address adr,
868 int rip_relative_correction) {
869 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
870 adr._rspec,
871 rip_relative_correction);
872 }
874 void Assembler::emit_operand(XMMRegister reg, Address adr) {
875 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
876 adr._rspec);
877 }
879 // MMX operations
880 void Assembler::emit_operand(MMXRegister reg, Address adr) {
881 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
882 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
883 }
885 // work around gcc (3.2.1-7a) bug
886 void Assembler::emit_operand(Address adr, MMXRegister reg) {
887 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
888 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
889 }
892 void Assembler::emit_farith(int b1, int b2, int i) {
893 assert(isByte(b1) && isByte(b2), "wrong opcode");
894 assert(0 <= i && i < 8, "illegal stack offset");
895 emit_byte(b1);
896 emit_byte(b2 + i);
897 }
900 // Now the Assembler instructions (identical for 32/64 bits)
902 void Assembler::adcl(Address dst, int32_t imm32) {
903 InstructionMark im(this);
904 prefix(dst);
905 emit_arith_operand(0x81, rdx, dst, imm32);
906 }
908 void Assembler::adcl(Address dst, Register src) {
909 InstructionMark im(this);
910 prefix(dst, src);
911 emit_byte(0x11);
912 emit_operand(src, dst);
913 }
915 void Assembler::adcl(Register dst, int32_t imm32) {
916 prefix(dst);
917 emit_arith(0x81, 0xD0, dst, imm32);
918 }
920 void Assembler::adcl(Register dst, Address src) {
921 InstructionMark im(this);
922 prefix(src, dst);
923 emit_byte(0x13);
924 emit_operand(dst, src);
925 }
927 void Assembler::adcl(Register dst, Register src) {
928 (void) prefix_and_encode(dst->encoding(), src->encoding());
929 emit_arith(0x13, 0xC0, dst, src);
930 }
932 void Assembler::addl(Address dst, int32_t imm32) {
933 InstructionMark im(this);
934 prefix(dst);
935 emit_arith_operand(0x81, rax, dst, imm32);
936 }
938 void Assembler::addl(Address dst, Register src) {
939 InstructionMark im(this);
940 prefix(dst, src);
941 emit_byte(0x01);
942 emit_operand(src, dst);
943 }
945 void Assembler::addl(Register dst, int32_t imm32) {
946 prefix(dst);
947 emit_arith(0x81, 0xC0, dst, imm32);
948 }
950 void Assembler::addl(Register dst, Address src) {
951 InstructionMark im(this);
952 prefix(src, dst);
953 emit_byte(0x03);
954 emit_operand(dst, src);
955 }
957 void Assembler::addl(Register dst, Register src) {
958 (void) prefix_and_encode(dst->encoding(), src->encoding());
959 emit_arith(0x03, 0xC0, dst, src);
960 }
962 void Assembler::addr_nop_4() {
963 assert(UseAddressNop, "no CPU support");
964 // 4 bytes: NOP DWORD PTR [EAX+0]
965 emit_byte(0x0F);
966 emit_byte(0x1F);
967 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
968 emit_byte(0); // 8-bits offset (1 byte)
969 }
971 void Assembler::addr_nop_5() {
972 assert(UseAddressNop, "no CPU support");
973 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
974 emit_byte(0x0F);
975 emit_byte(0x1F);
976 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
977 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
978 emit_byte(0); // 8-bits offset (1 byte)
979 }
981 void Assembler::addr_nop_7() {
982 assert(UseAddressNop, "no CPU support");
983 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
984 emit_byte(0x0F);
985 emit_byte(0x1F);
986 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
987 emit_long(0); // 32-bits offset (4 bytes)
988 }
990 void Assembler::addr_nop_8() {
991 assert(UseAddressNop, "no CPU support");
992 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
993 emit_byte(0x0F);
994 emit_byte(0x1F);
995 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
996 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
997 emit_long(0); // 32-bits offset (4 bytes)
998 }
1000 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1001 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1002 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1003 emit_byte(0x58);
1004 emit_byte(0xC0 | encode);
1005 }
1007 void Assembler::addsd(XMMRegister dst, Address src) {
1008 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1009 InstructionMark im(this);
1010 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1011 emit_byte(0x58);
1012 emit_operand(dst, src);
1013 }
1015 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1016 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1017 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1018 emit_byte(0x58);
1019 emit_byte(0xC0 | encode);
1020 }
1022 void Assembler::addss(XMMRegister dst, Address src) {
1023 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1024 InstructionMark im(this);
1025 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1026 emit_byte(0x58);
1027 emit_operand(dst, src);
1028 }
1030 void Assembler::andl(Address dst, int32_t imm32) {
1031 InstructionMark im(this);
1032 prefix(dst);
1033 emit_byte(0x81);
1034 emit_operand(rsp, dst, 4);
1035 emit_long(imm32);
1036 }
1038 void Assembler::andl(Register dst, int32_t imm32) {
1039 prefix(dst);
1040 emit_arith(0x81, 0xE0, dst, imm32);
1041 }
1043 void Assembler::andl(Register dst, Address src) {
1044 InstructionMark im(this);
1045 prefix(src, dst);
1046 emit_byte(0x23);
1047 emit_operand(dst, src);
1048 }
1050 void Assembler::andl(Register dst, Register src) {
1051 (void) prefix_and_encode(dst->encoding(), src->encoding());
1052 emit_arith(0x23, 0xC0, dst, src);
1053 }
1055 void Assembler::andpd(XMMRegister dst, Address src) {
1056 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1057 InstructionMark im(this);
1058 simd_prefix(dst, dst, src, VEX_SIMD_66);
1059 emit_byte(0x54);
1060 emit_operand(dst, src);
1061 }
1063 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
1064 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1065 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
1066 emit_byte(0x54);
1067 emit_byte(0xC0 | encode);
1068 }
1070 void Assembler::andps(XMMRegister dst, Address src) {
1071 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1072 InstructionMark im(this);
1073 simd_prefix(dst, dst, src, VEX_SIMD_NONE);
1074 emit_byte(0x54);
1075 emit_operand(dst, src);
1076 }
1078 void Assembler::andps(XMMRegister dst, XMMRegister src) {
1079 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1080 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE);
1081 emit_byte(0x54);
1082 emit_byte(0xC0 | encode);
1083 }
1085 void Assembler::bsfl(Register dst, Register src) {
1086 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1087 emit_byte(0x0F);
1088 emit_byte(0xBC);
1089 emit_byte(0xC0 | encode);
1090 }
1092 void Assembler::bsrl(Register dst, Register src) {
1093 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
1094 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1095 emit_byte(0x0F);
1096 emit_byte(0xBD);
1097 emit_byte(0xC0 | encode);
1098 }
1100 void Assembler::bswapl(Register reg) { // bswap
1101 int encode = prefix_and_encode(reg->encoding());
1102 emit_byte(0x0F);
1103 emit_byte(0xC8 | encode);
1104 }
1106 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1107 // suspect disp32 is always good
1108 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1110 if (L.is_bound()) {
1111 const int long_size = 5;
1112 int offs = (int)( target(L) - pc() );
1113 assert(offs <= 0, "assembler error");
1114 InstructionMark im(this);
1115 // 1110 1000 #32-bit disp
1116 emit_byte(0xE8);
1117 emit_data(offs - long_size, rtype, operand);
1118 } else {
1119 InstructionMark im(this);
1120 // 1110 1000 #32-bit disp
1121 L.add_patch_at(code(), locator());
1123 emit_byte(0xE8);
1124 emit_data(int(0), rtype, operand);
1125 }
1126 }
1128 void Assembler::call(Register dst) {
1129 int encode = prefix_and_encode(dst->encoding());
1130 emit_byte(0xFF);
1131 emit_byte(0xD0 | encode);
1132 }
1135 void Assembler::call(Address adr) {
1136 InstructionMark im(this);
1137 prefix(adr);
1138 emit_byte(0xFF);
1139 emit_operand(rdx, adr);
1140 }
1142 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1143 assert(entry != NULL, "call most probably wrong");
1144 InstructionMark im(this);
1145 emit_byte(0xE8);
1146 intptr_t disp = entry - (_code_pos + sizeof(int32_t));
1147 assert(is_simm32(disp), "must be 32bit offset (call2)");
1148 // Technically, should use call32_operand, but this format is
1149 // implied by the fact that we're emitting a call instruction.
1151 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1152 emit_data((int) disp, rspec, operand);
1153 }
1155 void Assembler::cdql() {
1156 emit_byte(0x99);
1157 }
1159 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1160 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1161 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1162 emit_byte(0x0F);
1163 emit_byte(0x40 | cc);
1164 emit_byte(0xC0 | encode);
1165 }
1168 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1169 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1170 prefix(src, dst);
1171 emit_byte(0x0F);
1172 emit_byte(0x40 | cc);
1173 emit_operand(dst, src);
1174 }
1176 void Assembler::cmpb(Address dst, int imm8) {
1177 InstructionMark im(this);
1178 prefix(dst);
1179 emit_byte(0x80);
1180 emit_operand(rdi, dst, 1);
1181 emit_byte(imm8);
1182 }
1184 void Assembler::cmpl(Address dst, int32_t imm32) {
1185 InstructionMark im(this);
1186 prefix(dst);
1187 emit_byte(0x81);
1188 emit_operand(rdi, dst, 4);
1189 emit_long(imm32);
1190 }
1192 void Assembler::cmpl(Register dst, int32_t imm32) {
1193 prefix(dst);
1194 emit_arith(0x81, 0xF8, dst, imm32);
1195 }
1197 void Assembler::cmpl(Register dst, Register src) {
1198 (void) prefix_and_encode(dst->encoding(), src->encoding());
1199 emit_arith(0x3B, 0xC0, dst, src);
1200 }
1203 void Assembler::cmpl(Register dst, Address src) {
1204 InstructionMark im(this);
1205 prefix(src, dst);
1206 emit_byte(0x3B);
1207 emit_operand(dst, src);
1208 }
1210 void Assembler::cmpw(Address dst, int imm16) {
1211 InstructionMark im(this);
1212 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1213 emit_byte(0x66);
1214 emit_byte(0x81);
1215 emit_operand(rdi, dst, 2);
1216 emit_word(imm16);
1217 }
1219 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1220 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1221 // The ZF is set if the compared values were equal, and cleared otherwise.
1222 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1223 if (Atomics & 2) {
1224 // caveat: no instructionmark, so this isn't relocatable.
1225 // Emit a synthetic, non-atomic, CAS equivalent.
1226 // Beware. The synthetic form sets all ICCs, not just ZF.
1227 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r)
1228 cmpl(rax, adr);
1229 movl(rax, adr);
1230 if (reg != rax) {
1231 Label L ;
1232 jcc(Assembler::notEqual, L);
1233 movl(adr, reg);
1234 bind(L);
1235 }
1236 } else {
1237 InstructionMark im(this);
1238 prefix(adr, reg);
1239 emit_byte(0x0F);
1240 emit_byte(0xB1);
1241 emit_operand(reg, adr);
1242 }
1243 }
1245 void Assembler::comisd(XMMRegister dst, Address src) {
1246 // NOTE: dbx seems to decode this as comiss even though the
1247 // 0x66 is there. Strangly ucomisd comes out correct
1248 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1249 InstructionMark im(this);
1250 simd_prefix(dst, src, VEX_SIMD_66);
1251 emit_byte(0x2F);
1252 emit_operand(dst, src);
1253 }
1255 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1256 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1257 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1258 emit_byte(0x2F);
1259 emit_byte(0xC0 | encode);
1260 }
1262 void Assembler::comiss(XMMRegister dst, Address src) {
1263 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1264 InstructionMark im(this);
1265 simd_prefix(dst, src, VEX_SIMD_NONE);
1266 emit_byte(0x2F);
1267 emit_operand(dst, src);
1268 }
1270 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1271 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1272 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
1273 emit_byte(0x2F);
1274 emit_byte(0xC0 | encode);
1275 }
1277 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1278 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1279 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1280 emit_byte(0xE6);
1281 emit_byte(0xC0 | encode);
1282 }
1284 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1285 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1286 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
1287 emit_byte(0x5B);
1288 emit_byte(0xC0 | encode);
1289 }
1291 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1292 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1293 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1294 emit_byte(0x5A);
1295 emit_byte(0xC0 | encode);
1296 }
1298 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1299 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1300 InstructionMark im(this);
1301 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1302 emit_byte(0x5A);
1303 emit_operand(dst, src);
1304 }
1306 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1307 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1308 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1309 emit_byte(0x2A);
1310 emit_byte(0xC0 | encode);
1311 }
1313 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1314 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1315 InstructionMark im(this);
1316 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1317 emit_byte(0x2A);
1318 emit_operand(dst, src);
1319 }
1321 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1322 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1323 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1324 emit_byte(0x2A);
1325 emit_byte(0xC0 | encode);
1326 }
1328 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1329 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1330 InstructionMark im(this);
1331 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1332 emit_byte(0x2A);
1333 emit_operand(dst, src);
1334 }
1336 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1337 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1338 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1339 emit_byte(0x5A);
1340 emit_byte(0xC0 | encode);
1341 }
1343 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1344 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1345 InstructionMark im(this);
1346 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1347 emit_byte(0x5A);
1348 emit_operand(dst, src);
1349 }
1352 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1353 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1354 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
1355 emit_byte(0x2C);
1356 emit_byte(0xC0 | encode);
1357 }
1359 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1360 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1361 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1362 emit_byte(0x2C);
1363 emit_byte(0xC0 | encode);
1364 }
1366 void Assembler::decl(Address dst) {
1367 // Don't use it directly. Use MacroAssembler::decrement() instead.
1368 InstructionMark im(this);
1369 prefix(dst);
1370 emit_byte(0xFF);
1371 emit_operand(rcx, dst);
1372 }
1374 void Assembler::divsd(XMMRegister dst, Address src) {
1375 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1376 InstructionMark im(this);
1377 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1378 emit_byte(0x5E);
1379 emit_operand(dst, src);
1380 }
1382 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1383 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1384 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1385 emit_byte(0x5E);
1386 emit_byte(0xC0 | encode);
1387 }
1389 void Assembler::divss(XMMRegister dst, Address src) {
1390 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1391 InstructionMark im(this);
1392 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1393 emit_byte(0x5E);
1394 emit_operand(dst, src);
1395 }
1397 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1398 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1399 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1400 emit_byte(0x5E);
1401 emit_byte(0xC0 | encode);
1402 }
1404 void Assembler::emms() {
1405 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1406 emit_byte(0x0F);
1407 emit_byte(0x77);
1408 }
1410 void Assembler::hlt() {
1411 emit_byte(0xF4);
1412 }
1414 void Assembler::idivl(Register src) {
1415 int encode = prefix_and_encode(src->encoding());
1416 emit_byte(0xF7);
1417 emit_byte(0xF8 | encode);
1418 }
1420 void Assembler::divl(Register src) { // Unsigned
1421 int encode = prefix_and_encode(src->encoding());
1422 emit_byte(0xF7);
1423 emit_byte(0xF0 | encode);
1424 }
1426 void Assembler::imull(Register dst, Register src) {
1427 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1428 emit_byte(0x0F);
1429 emit_byte(0xAF);
1430 emit_byte(0xC0 | encode);
1431 }
1434 void Assembler::imull(Register dst, Register src, int value) {
1435 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1436 if (is8bit(value)) {
1437 emit_byte(0x6B);
1438 emit_byte(0xC0 | encode);
1439 emit_byte(value & 0xFF);
1440 } else {
1441 emit_byte(0x69);
1442 emit_byte(0xC0 | encode);
1443 emit_long(value);
1444 }
1445 }
1447 void Assembler::incl(Address dst) {
1448 // Don't use it directly. Use MacroAssembler::increment() instead.
1449 InstructionMark im(this);
1450 prefix(dst);
1451 emit_byte(0xFF);
1452 emit_operand(rax, dst);
1453 }
1455 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1456 InstructionMark im(this);
1457 assert((0 <= cc) && (cc < 16), "illegal cc");
1458 if (L.is_bound()) {
1459 address dst = target(L);
1460 assert(dst != NULL, "jcc most probably wrong");
1462 const int short_size = 2;
1463 const int long_size = 6;
1464 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos;
1465 if (maybe_short && is8bit(offs - short_size)) {
1466 // 0111 tttn #8-bit disp
1467 emit_byte(0x70 | cc);
1468 emit_byte((offs - short_size) & 0xFF);
1469 } else {
1470 // 0000 1111 1000 tttn #32-bit disp
1471 assert(is_simm32(offs - long_size),
1472 "must be 32bit offset (call4)");
1473 emit_byte(0x0F);
1474 emit_byte(0x80 | cc);
1475 emit_long(offs - long_size);
1476 }
1477 } else {
1478 // Note: could eliminate cond. jumps to this jump if condition
1479 // is the same however, seems to be rather unlikely case.
1480 // Note: use jccb() if label to be bound is very close to get
1481 // an 8-bit displacement
1482 L.add_patch_at(code(), locator());
1483 emit_byte(0x0F);
1484 emit_byte(0x80 | cc);
1485 emit_long(0);
1486 }
1487 }
1489 void Assembler::jccb(Condition cc, Label& L) {
1490 if (L.is_bound()) {
1491 const int short_size = 2;
1492 address entry = target(L);
1493 #ifdef ASSERT
1494 intptr_t dist = (intptr_t)entry - ((intptr_t)_code_pos + short_size);
1495 intptr_t delta = short_branch_delta();
1496 if (delta != 0) {
1497 dist += (dist < 0 ? (-delta) :delta);
1498 }
1499 assert(is8bit(dist), "Dispacement too large for a short jmp");
1500 #endif
1501 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos;
1502 // 0111 tttn #8-bit disp
1503 emit_byte(0x70 | cc);
1504 emit_byte((offs - short_size) & 0xFF);
1505 } else {
1506 InstructionMark im(this);
1507 L.add_patch_at(code(), locator());
1508 emit_byte(0x70 | cc);
1509 emit_byte(0);
1510 }
1511 }
1513 void Assembler::jmp(Address adr) {
1514 InstructionMark im(this);
1515 prefix(adr);
1516 emit_byte(0xFF);
1517 emit_operand(rsp, adr);
1518 }
1520 void Assembler::jmp(Label& L, bool maybe_short) {
1521 if (L.is_bound()) {
1522 address entry = target(L);
1523 assert(entry != NULL, "jmp most probably wrong");
1524 InstructionMark im(this);
1525 const int short_size = 2;
1526 const int long_size = 5;
1527 intptr_t offs = entry - _code_pos;
1528 if (maybe_short && is8bit(offs - short_size)) {
1529 emit_byte(0xEB);
1530 emit_byte((offs - short_size) & 0xFF);
1531 } else {
1532 emit_byte(0xE9);
1533 emit_long(offs - long_size);
1534 }
1535 } else {
1536 // By default, forward jumps are always 32-bit displacements, since
1537 // we can't yet know where the label will be bound. If you're sure that
1538 // the forward jump will not run beyond 256 bytes, use jmpb to
1539 // force an 8-bit displacement.
1540 InstructionMark im(this);
1541 L.add_patch_at(code(), locator());
1542 emit_byte(0xE9);
1543 emit_long(0);
1544 }
1545 }
1547 void Assembler::jmp(Register entry) {
1548 int encode = prefix_and_encode(entry->encoding());
1549 emit_byte(0xFF);
1550 emit_byte(0xE0 | encode);
1551 }
1553 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1554 InstructionMark im(this);
1555 emit_byte(0xE9);
1556 assert(dest != NULL, "must have a target");
1557 intptr_t disp = dest - (_code_pos + sizeof(int32_t));
1558 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1559 emit_data(disp, rspec.reloc(), call32_operand);
1560 }
1562 void Assembler::jmpb(Label& L) {
1563 if (L.is_bound()) {
1564 const int short_size = 2;
1565 address entry = target(L);
1566 assert(entry != NULL, "jmp most probably wrong");
1567 #ifdef ASSERT
1568 intptr_t dist = (intptr_t)entry - ((intptr_t)_code_pos + short_size);
1569 intptr_t delta = short_branch_delta();
1570 if (delta != 0) {
1571 dist += (dist < 0 ? (-delta) :delta);
1572 }
1573 assert(is8bit(dist), "Dispacement too large for a short jmp");
1574 #endif
1575 intptr_t offs = entry - _code_pos;
1576 emit_byte(0xEB);
1577 emit_byte((offs - short_size) & 0xFF);
1578 } else {
1579 InstructionMark im(this);
1580 L.add_patch_at(code(), locator());
1581 emit_byte(0xEB);
1582 emit_byte(0);
1583 }
1584 }
1586 void Assembler::ldmxcsr( Address src) {
1587 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1588 InstructionMark im(this);
1589 prefix(src);
1590 emit_byte(0x0F);
1591 emit_byte(0xAE);
1592 emit_operand(as_Register(2), src);
1593 }
1595 void Assembler::leal(Register dst, Address src) {
1596 InstructionMark im(this);
1597 #ifdef _LP64
1598 emit_byte(0x67); // addr32
1599 prefix(src, dst);
1600 #endif // LP64
1601 emit_byte(0x8D);
1602 emit_operand(dst, src);
1603 }
1605 void Assembler::lock() {
1606 if (Atomics & 1) {
1607 // Emit either nothing, a NOP, or a NOP: prefix
1608 emit_byte(0x90) ;
1609 } else {
1610 emit_byte(0xF0);
1611 }
1612 }
1614 void Assembler::lzcntl(Register dst, Register src) {
1615 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1616 emit_byte(0xF3);
1617 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1618 emit_byte(0x0F);
1619 emit_byte(0xBD);
1620 emit_byte(0xC0 | encode);
1621 }
1623 // Emit mfence instruction
1624 void Assembler::mfence() {
1625 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1626 emit_byte( 0x0F );
1627 emit_byte( 0xAE );
1628 emit_byte( 0xF0 );
1629 }
1631 void Assembler::mov(Register dst, Register src) {
1632 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1633 }
1635 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1636 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1637 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1638 emit_byte(0x28);
1639 emit_byte(0xC0 | encode);
1640 }
1642 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1643 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1644 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
1645 emit_byte(0x28);
1646 emit_byte(0xC0 | encode);
1647 }
1649 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
1650 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1651 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE);
1652 emit_byte(0x16);
1653 emit_byte(0xC0 | encode);
1654 }
1656 void Assembler::movb(Register dst, Address src) {
1657 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1658 InstructionMark im(this);
1659 prefix(src, dst, true);
1660 emit_byte(0x8A);
1661 emit_operand(dst, src);
1662 }
1665 void Assembler::movb(Address dst, int imm8) {
1666 InstructionMark im(this);
1667 prefix(dst);
1668 emit_byte(0xC6);
1669 emit_operand(rax, dst, 1);
1670 emit_byte(imm8);
1671 }
1674 void Assembler::movb(Address dst, Register src) {
1675 assert(src->has_byte_register(), "must have byte register");
1676 InstructionMark im(this);
1677 prefix(dst, src, true);
1678 emit_byte(0x88);
1679 emit_operand(src, dst);
1680 }
1682 void Assembler::movdl(XMMRegister dst, Register src) {
1683 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1684 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1685 emit_byte(0x6E);
1686 emit_byte(0xC0 | encode);
1687 }
1689 void Assembler::movdl(Register dst, XMMRegister src) {
1690 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1691 // swap src/dst to get correct prefix
1692 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66);
1693 emit_byte(0x7E);
1694 emit_byte(0xC0 | encode);
1695 }
1697 void Assembler::movdl(XMMRegister dst, Address src) {
1698 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1699 InstructionMark im(this);
1700 simd_prefix(dst, src, VEX_SIMD_66);
1701 emit_byte(0x6E);
1702 emit_operand(dst, src);
1703 }
1705 void Assembler::movdl(Address dst, XMMRegister src) {
1706 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1707 InstructionMark im(this);
1708 simd_prefix(dst, src, VEX_SIMD_66);
1709 emit_byte(0x7E);
1710 emit_operand(src, dst);
1711 }
1713 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1714 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1715 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1716 emit_byte(0x6F);
1717 emit_byte(0xC0 | encode);
1718 }
1720 void Assembler::movdqu(XMMRegister dst, Address src) {
1721 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1722 InstructionMark im(this);
1723 simd_prefix(dst, src, VEX_SIMD_F3);
1724 emit_byte(0x6F);
1725 emit_operand(dst, src);
1726 }
1728 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1729 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1730 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1731 emit_byte(0x6F);
1732 emit_byte(0xC0 | encode);
1733 }
1735 void Assembler::movdqu(Address dst, XMMRegister src) {
1736 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1737 InstructionMark im(this);
1738 simd_prefix(dst, src, VEX_SIMD_F3);
1739 emit_byte(0x7F);
1740 emit_operand(src, dst);
1741 }
1743 // Move Unaligned 256bit Vector
1744 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
1745 assert(UseAVX, "");
1746 bool vector256 = true;
1747 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1748 emit_byte(0x6F);
1749 emit_byte(0xC0 | encode);
1750 }
1752 void Assembler::vmovdqu(XMMRegister dst, Address src) {
1753 assert(UseAVX, "");
1754 InstructionMark im(this);
1755 bool vector256 = true;
1756 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1757 emit_byte(0x6F);
1758 emit_operand(dst, src);
1759 }
1761 void Assembler::vmovdqu(Address dst, XMMRegister src) {
1762 assert(UseAVX, "");
1763 InstructionMark im(this);
1764 bool vector256 = true;
1765 // swap src<->dst for encoding
1766 assert(src != xnoreg, "sanity");
1767 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256);
1768 emit_byte(0x7F);
1769 emit_operand(src, dst);
1770 }
1772 // Uses zero extension on 64bit
1774 void Assembler::movl(Register dst, int32_t imm32) {
1775 int encode = prefix_and_encode(dst->encoding());
1776 emit_byte(0xB8 | encode);
1777 emit_long(imm32);
1778 }
1780 void Assembler::movl(Register dst, Register src) {
1781 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1782 emit_byte(0x8B);
1783 emit_byte(0xC0 | encode);
1784 }
1786 void Assembler::movl(Register dst, Address src) {
1787 InstructionMark im(this);
1788 prefix(src, dst);
1789 emit_byte(0x8B);
1790 emit_operand(dst, src);
1791 }
1793 void Assembler::movl(Address dst, int32_t imm32) {
1794 InstructionMark im(this);
1795 prefix(dst);
1796 emit_byte(0xC7);
1797 emit_operand(rax, dst, 4);
1798 emit_long(imm32);
1799 }
1801 void Assembler::movl(Address dst, Register src) {
1802 InstructionMark im(this);
1803 prefix(dst, src);
1804 emit_byte(0x89);
1805 emit_operand(src, dst);
1806 }
1808 // New cpus require to use movsd and movss to avoid partial register stall
1809 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1810 // The selection is done in MacroAssembler::movdbl() and movflt().
1811 void Assembler::movlpd(XMMRegister dst, Address src) {
1812 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1813 InstructionMark im(this);
1814 simd_prefix(dst, dst, src, VEX_SIMD_66);
1815 emit_byte(0x12);
1816 emit_operand(dst, src);
1817 }
1819 void Assembler::movq( MMXRegister dst, Address src ) {
1820 assert( VM_Version::supports_mmx(), "" );
1821 emit_byte(0x0F);
1822 emit_byte(0x6F);
1823 emit_operand(dst, src);
1824 }
1826 void Assembler::movq( Address dst, MMXRegister src ) {
1827 assert( VM_Version::supports_mmx(), "" );
1828 emit_byte(0x0F);
1829 emit_byte(0x7F);
1830 // workaround gcc (3.2.1-7a) bug
1831 // In that version of gcc with only an emit_operand(MMX, Address)
1832 // gcc will tail jump and try and reverse the parameters completely
1833 // obliterating dst in the process. By having a version available
1834 // that doesn't need to swap the args at the tail jump the bug is
1835 // avoided.
1836 emit_operand(dst, src);
1837 }
1839 void Assembler::movq(XMMRegister dst, Address src) {
1840 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1841 InstructionMark im(this);
1842 simd_prefix(dst, src, VEX_SIMD_F3);
1843 emit_byte(0x7E);
1844 emit_operand(dst, src);
1845 }
1847 void Assembler::movq(Address dst, XMMRegister src) {
1848 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1849 InstructionMark im(this);
1850 simd_prefix(dst, src, VEX_SIMD_66);
1851 emit_byte(0xD6);
1852 emit_operand(src, dst);
1853 }
1855 void Assembler::movsbl(Register dst, Address src) { // movsxb
1856 InstructionMark im(this);
1857 prefix(src, dst);
1858 emit_byte(0x0F);
1859 emit_byte(0xBE);
1860 emit_operand(dst, src);
1861 }
1863 void Assembler::movsbl(Register dst, Register src) { // movsxb
1864 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1865 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1866 emit_byte(0x0F);
1867 emit_byte(0xBE);
1868 emit_byte(0xC0 | encode);
1869 }
1871 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1872 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1873 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1874 emit_byte(0x10);
1875 emit_byte(0xC0 | encode);
1876 }
1878 void Assembler::movsd(XMMRegister dst, Address src) {
1879 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1880 InstructionMark im(this);
1881 simd_prefix(dst, src, VEX_SIMD_F2);
1882 emit_byte(0x10);
1883 emit_operand(dst, src);
1884 }
1886 void Assembler::movsd(Address dst, XMMRegister src) {
1887 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1888 InstructionMark im(this);
1889 simd_prefix(dst, src, VEX_SIMD_F2);
1890 emit_byte(0x11);
1891 emit_operand(src, dst);
1892 }
1894 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1895 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1896 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1897 emit_byte(0x10);
1898 emit_byte(0xC0 | encode);
1899 }
1901 void Assembler::movss(XMMRegister dst, Address src) {
1902 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1903 InstructionMark im(this);
1904 simd_prefix(dst, src, VEX_SIMD_F3);
1905 emit_byte(0x10);
1906 emit_operand(dst, src);
1907 }
1909 void Assembler::movss(Address dst, XMMRegister src) {
1910 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1911 InstructionMark im(this);
1912 simd_prefix(dst, src, VEX_SIMD_F3);
1913 emit_byte(0x11);
1914 emit_operand(src, dst);
1915 }
1917 void Assembler::movswl(Register dst, Address src) { // movsxw
1918 InstructionMark im(this);
1919 prefix(src, dst);
1920 emit_byte(0x0F);
1921 emit_byte(0xBF);
1922 emit_operand(dst, src);
1923 }
1925 void Assembler::movswl(Register dst, Register src) { // movsxw
1926 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1927 emit_byte(0x0F);
1928 emit_byte(0xBF);
1929 emit_byte(0xC0 | encode);
1930 }
1932 void Assembler::movw(Address dst, int imm16) {
1933 InstructionMark im(this);
1935 emit_byte(0x66); // switch to 16-bit mode
1936 prefix(dst);
1937 emit_byte(0xC7);
1938 emit_operand(rax, dst, 2);
1939 emit_word(imm16);
1940 }
1942 void Assembler::movw(Register dst, Address src) {
1943 InstructionMark im(this);
1944 emit_byte(0x66);
1945 prefix(src, dst);
1946 emit_byte(0x8B);
1947 emit_operand(dst, src);
1948 }
1950 void Assembler::movw(Address dst, Register src) {
1951 InstructionMark im(this);
1952 emit_byte(0x66);
1953 prefix(dst, src);
1954 emit_byte(0x89);
1955 emit_operand(src, dst);
1956 }
1958 void Assembler::movzbl(Register dst, Address src) { // movzxb
1959 InstructionMark im(this);
1960 prefix(src, dst);
1961 emit_byte(0x0F);
1962 emit_byte(0xB6);
1963 emit_operand(dst, src);
1964 }
1966 void Assembler::movzbl(Register dst, Register src) { // movzxb
1967 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1968 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1969 emit_byte(0x0F);
1970 emit_byte(0xB6);
1971 emit_byte(0xC0 | encode);
1972 }
1974 void Assembler::movzwl(Register dst, Address src) { // movzxw
1975 InstructionMark im(this);
1976 prefix(src, dst);
1977 emit_byte(0x0F);
1978 emit_byte(0xB7);
1979 emit_operand(dst, src);
1980 }
1982 void Assembler::movzwl(Register dst, Register src) { // movzxw
1983 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1984 emit_byte(0x0F);
1985 emit_byte(0xB7);
1986 emit_byte(0xC0 | encode);
1987 }
1989 void Assembler::mull(Address src) {
1990 InstructionMark im(this);
1991 prefix(src);
1992 emit_byte(0xF7);
1993 emit_operand(rsp, src);
1994 }
1996 void Assembler::mull(Register src) {
1997 int encode = prefix_and_encode(src->encoding());
1998 emit_byte(0xF7);
1999 emit_byte(0xE0 | encode);
2000 }
2002 void Assembler::mulsd(XMMRegister dst, Address src) {
2003 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2004 InstructionMark im(this);
2005 simd_prefix(dst, dst, src, VEX_SIMD_F2);
2006 emit_byte(0x59);
2007 emit_operand(dst, src);
2008 }
2010 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2011 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2012 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
2013 emit_byte(0x59);
2014 emit_byte(0xC0 | encode);
2015 }
2017 void Assembler::mulss(XMMRegister dst, Address src) {
2018 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2019 InstructionMark im(this);
2020 simd_prefix(dst, dst, src, VEX_SIMD_F3);
2021 emit_byte(0x59);
2022 emit_operand(dst, src);
2023 }
2025 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2026 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2027 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
2028 emit_byte(0x59);
2029 emit_byte(0xC0 | encode);
2030 }
2032 void Assembler::negl(Register dst) {
2033 int encode = prefix_and_encode(dst->encoding());
2034 emit_byte(0xF7);
2035 emit_byte(0xD8 | encode);
2036 }
2038 void Assembler::nop(int i) {
2039 #ifdef ASSERT
2040 assert(i > 0, " ");
2041 // The fancy nops aren't currently recognized by debuggers making it a
2042 // pain to disassemble code while debugging. If asserts are on clearly
2043 // speed is not an issue so simply use the single byte traditional nop
2044 // to do alignment.
2046 for (; i > 0 ; i--) emit_byte(0x90);
2047 return;
2049 #endif // ASSERT
2051 if (UseAddressNop && VM_Version::is_intel()) {
2052 //
2053 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2054 // 1: 0x90
2055 // 2: 0x66 0x90
2056 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2057 // 4: 0x0F 0x1F 0x40 0x00
2058 // 5: 0x0F 0x1F 0x44 0x00 0x00
2059 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2060 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2061 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2062 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2063 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2064 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2066 // The rest coding is Intel specific - don't use consecutive address nops
2068 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2069 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2070 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2071 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2073 while(i >= 15) {
2074 // For Intel don't generate consecutive addess nops (mix with regular nops)
2075 i -= 15;
2076 emit_byte(0x66); // size prefix
2077 emit_byte(0x66); // size prefix
2078 emit_byte(0x66); // size prefix
2079 addr_nop_8();
2080 emit_byte(0x66); // size prefix
2081 emit_byte(0x66); // size prefix
2082 emit_byte(0x66); // size prefix
2083 emit_byte(0x90); // nop
2084 }
2085 switch (i) {
2086 case 14:
2087 emit_byte(0x66); // size prefix
2088 case 13:
2089 emit_byte(0x66); // size prefix
2090 case 12:
2091 addr_nop_8();
2092 emit_byte(0x66); // size prefix
2093 emit_byte(0x66); // size prefix
2094 emit_byte(0x66); // size prefix
2095 emit_byte(0x90); // nop
2096 break;
2097 case 11:
2098 emit_byte(0x66); // size prefix
2099 case 10:
2100 emit_byte(0x66); // size prefix
2101 case 9:
2102 emit_byte(0x66); // size prefix
2103 case 8:
2104 addr_nop_8();
2105 break;
2106 case 7:
2107 addr_nop_7();
2108 break;
2109 case 6:
2110 emit_byte(0x66); // size prefix
2111 case 5:
2112 addr_nop_5();
2113 break;
2114 case 4:
2115 addr_nop_4();
2116 break;
2117 case 3:
2118 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2119 emit_byte(0x66); // size prefix
2120 case 2:
2121 emit_byte(0x66); // size prefix
2122 case 1:
2123 emit_byte(0x90); // nop
2124 break;
2125 default:
2126 assert(i == 0, " ");
2127 }
2128 return;
2129 }
2130 if (UseAddressNop && VM_Version::is_amd()) {
2131 //
2132 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2133 // 1: 0x90
2134 // 2: 0x66 0x90
2135 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2136 // 4: 0x0F 0x1F 0x40 0x00
2137 // 5: 0x0F 0x1F 0x44 0x00 0x00
2138 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2139 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2140 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2141 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2142 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2143 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2145 // The rest coding is AMD specific - use consecutive address nops
2147 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2148 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2149 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2150 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2151 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2152 // Size prefixes (0x66) are added for larger sizes
2154 while(i >= 22) {
2155 i -= 11;
2156 emit_byte(0x66); // size prefix
2157 emit_byte(0x66); // size prefix
2158 emit_byte(0x66); // size prefix
2159 addr_nop_8();
2160 }
2161 // Generate first nop for size between 21-12
2162 switch (i) {
2163 case 21:
2164 i -= 1;
2165 emit_byte(0x66); // size prefix
2166 case 20:
2167 case 19:
2168 i -= 1;
2169 emit_byte(0x66); // size prefix
2170 case 18:
2171 case 17:
2172 i -= 1;
2173 emit_byte(0x66); // size prefix
2174 case 16:
2175 case 15:
2176 i -= 8;
2177 addr_nop_8();
2178 break;
2179 case 14:
2180 case 13:
2181 i -= 7;
2182 addr_nop_7();
2183 break;
2184 case 12:
2185 i -= 6;
2186 emit_byte(0x66); // size prefix
2187 addr_nop_5();
2188 break;
2189 default:
2190 assert(i < 12, " ");
2191 }
2193 // Generate second nop for size between 11-1
2194 switch (i) {
2195 case 11:
2196 emit_byte(0x66); // size prefix
2197 case 10:
2198 emit_byte(0x66); // size prefix
2199 case 9:
2200 emit_byte(0x66); // size prefix
2201 case 8:
2202 addr_nop_8();
2203 break;
2204 case 7:
2205 addr_nop_7();
2206 break;
2207 case 6:
2208 emit_byte(0x66); // size prefix
2209 case 5:
2210 addr_nop_5();
2211 break;
2212 case 4:
2213 addr_nop_4();
2214 break;
2215 case 3:
2216 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2217 emit_byte(0x66); // size prefix
2218 case 2:
2219 emit_byte(0x66); // size prefix
2220 case 1:
2221 emit_byte(0x90); // nop
2222 break;
2223 default:
2224 assert(i == 0, " ");
2225 }
2226 return;
2227 }
2229 // Using nops with size prefixes "0x66 0x90".
2230 // From AMD Optimization Guide:
2231 // 1: 0x90
2232 // 2: 0x66 0x90
2233 // 3: 0x66 0x66 0x90
2234 // 4: 0x66 0x66 0x66 0x90
2235 // 5: 0x66 0x66 0x90 0x66 0x90
2236 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2237 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2238 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2239 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2240 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2241 //
2242 while(i > 12) {
2243 i -= 4;
2244 emit_byte(0x66); // size prefix
2245 emit_byte(0x66);
2246 emit_byte(0x66);
2247 emit_byte(0x90); // nop
2248 }
2249 // 1 - 12 nops
2250 if(i > 8) {
2251 if(i > 9) {
2252 i -= 1;
2253 emit_byte(0x66);
2254 }
2255 i -= 3;
2256 emit_byte(0x66);
2257 emit_byte(0x66);
2258 emit_byte(0x90);
2259 }
2260 // 1 - 8 nops
2261 if(i > 4) {
2262 if(i > 6) {
2263 i -= 1;
2264 emit_byte(0x66);
2265 }
2266 i -= 3;
2267 emit_byte(0x66);
2268 emit_byte(0x66);
2269 emit_byte(0x90);
2270 }
2271 switch (i) {
2272 case 4:
2273 emit_byte(0x66);
2274 case 3:
2275 emit_byte(0x66);
2276 case 2:
2277 emit_byte(0x66);
2278 case 1:
2279 emit_byte(0x90);
2280 break;
2281 default:
2282 assert(i == 0, " ");
2283 }
2284 }
2286 void Assembler::notl(Register dst) {
2287 int encode = prefix_and_encode(dst->encoding());
2288 emit_byte(0xF7);
2289 emit_byte(0xD0 | encode );
2290 }
2292 void Assembler::orl(Address dst, int32_t imm32) {
2293 InstructionMark im(this);
2294 prefix(dst);
2295 emit_arith_operand(0x81, rcx, dst, imm32);
2296 }
2298 void Assembler::orl(Register dst, int32_t imm32) {
2299 prefix(dst);
2300 emit_arith(0x81, 0xC8, dst, imm32);
2301 }
2303 void Assembler::orl(Register dst, Address src) {
2304 InstructionMark im(this);
2305 prefix(src, dst);
2306 emit_byte(0x0B);
2307 emit_operand(dst, src);
2308 }
2310 void Assembler::orl(Register dst, Register src) {
2311 (void) prefix_and_encode(dst->encoding(), src->encoding());
2312 emit_arith(0x0B, 0xC0, dst, src);
2313 }
2315 void Assembler::packuswb(XMMRegister dst, Address src) {
2316 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2317 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2318 InstructionMark im(this);
2319 simd_prefix(dst, dst, src, VEX_SIMD_66);
2320 emit_byte(0x67);
2321 emit_operand(dst, src);
2322 }
2324 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2325 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2326 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2327 emit_byte(0x67);
2328 emit_byte(0xC0 | encode);
2329 }
2331 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2332 assert(VM_Version::supports_sse4_2(), "");
2333 InstructionMark im(this);
2334 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2335 emit_byte(0x61);
2336 emit_operand(dst, src);
2337 emit_byte(imm8);
2338 }
2340 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2341 assert(VM_Version::supports_sse4_2(), "");
2342 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2343 emit_byte(0x61);
2344 emit_byte(0xC0 | encode);
2345 emit_byte(imm8);
2346 }
2348 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2349 assert(VM_Version::supports_sse4_1(), "");
2350 InstructionMark im(this);
2351 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2352 emit_byte(0x30);
2353 emit_operand(dst, src);
2354 }
2356 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2357 assert(VM_Version::supports_sse4_1(), "");
2358 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2359 emit_byte(0x30);
2360 emit_byte(0xC0 | encode);
2361 }
2363 // generic
2364 void Assembler::pop(Register dst) {
2365 int encode = prefix_and_encode(dst->encoding());
2366 emit_byte(0x58 | encode);
2367 }
2369 void Assembler::popcntl(Register dst, Address src) {
2370 assert(VM_Version::supports_popcnt(), "must support");
2371 InstructionMark im(this);
2372 emit_byte(0xF3);
2373 prefix(src, dst);
2374 emit_byte(0x0F);
2375 emit_byte(0xB8);
2376 emit_operand(dst, src);
2377 }
2379 void Assembler::popcntl(Register dst, Register src) {
2380 assert(VM_Version::supports_popcnt(), "must support");
2381 emit_byte(0xF3);
2382 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2383 emit_byte(0x0F);
2384 emit_byte(0xB8);
2385 emit_byte(0xC0 | encode);
2386 }
2388 void Assembler::popf() {
2389 emit_byte(0x9D);
2390 }
2392 #ifndef _LP64 // no 32bit push/pop on amd64
2393 void Assembler::popl(Address dst) {
2394 // NOTE: this will adjust stack by 8byte on 64bits
2395 InstructionMark im(this);
2396 prefix(dst);
2397 emit_byte(0x8F);
2398 emit_operand(rax, dst);
2399 }
2400 #endif
2402 void Assembler::prefetch_prefix(Address src) {
2403 prefix(src);
2404 emit_byte(0x0F);
2405 }
2407 void Assembler::prefetchnta(Address src) {
2408 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2409 InstructionMark im(this);
2410 prefetch_prefix(src);
2411 emit_byte(0x18);
2412 emit_operand(rax, src); // 0, src
2413 }
2415 void Assembler::prefetchr(Address src) {
2416 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2417 InstructionMark im(this);
2418 prefetch_prefix(src);
2419 emit_byte(0x0D);
2420 emit_operand(rax, src); // 0, src
2421 }
2423 void Assembler::prefetcht0(Address src) {
2424 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2425 InstructionMark im(this);
2426 prefetch_prefix(src);
2427 emit_byte(0x18);
2428 emit_operand(rcx, src); // 1, src
2429 }
2431 void Assembler::prefetcht1(Address src) {
2432 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2433 InstructionMark im(this);
2434 prefetch_prefix(src);
2435 emit_byte(0x18);
2436 emit_operand(rdx, src); // 2, src
2437 }
2439 void Assembler::prefetcht2(Address src) {
2440 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2441 InstructionMark im(this);
2442 prefetch_prefix(src);
2443 emit_byte(0x18);
2444 emit_operand(rbx, src); // 3, src
2445 }
2447 void Assembler::prefetchw(Address src) {
2448 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2449 InstructionMark im(this);
2450 prefetch_prefix(src);
2451 emit_byte(0x0D);
2452 emit_operand(rcx, src); // 1, src
2453 }
2455 void Assembler::prefix(Prefix p) {
2456 a_byte(p);
2457 }
2459 void Assembler::por(XMMRegister dst, XMMRegister src) {
2460 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2461 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2462 emit_byte(0xEB);
2463 emit_byte(0xC0 | encode);
2464 }
2466 void Assembler::por(XMMRegister dst, Address src) {
2467 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2468 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2469 InstructionMark im(this);
2470 simd_prefix(dst, dst, src, VEX_SIMD_66);
2471 emit_byte(0xEB);
2472 emit_operand(dst, src);
2473 }
2475 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2476 assert(isByte(mode), "invalid value");
2477 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2478 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
2479 emit_byte(0x70);
2480 emit_byte(0xC0 | encode);
2481 emit_byte(mode & 0xFF);
2483 }
2485 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2486 assert(isByte(mode), "invalid value");
2487 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2488 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2489 InstructionMark im(this);
2490 simd_prefix(dst, src, VEX_SIMD_66);
2491 emit_byte(0x70);
2492 emit_operand(dst, src);
2493 emit_byte(mode & 0xFF);
2494 }
2496 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2497 assert(isByte(mode), "invalid value");
2498 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2499 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
2500 emit_byte(0x70);
2501 emit_byte(0xC0 | encode);
2502 emit_byte(mode & 0xFF);
2503 }
2505 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2506 assert(isByte(mode), "invalid value");
2507 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2508 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2509 InstructionMark im(this);
2510 simd_prefix(dst, src, VEX_SIMD_F2);
2511 emit_byte(0x70);
2512 emit_operand(dst, src);
2513 emit_byte(mode & 0xFF);
2514 }
2516 void Assembler::psrlq(XMMRegister dst, int shift) {
2517 // Shift 64 bit value logically right by specified number of bits.
2518 // HMM Table D-1 says sse2 or mmx.
2519 // Do not confuse it with psrldq SSE2 instruction which
2520 // shifts 128 bit value in xmm register by number of bytes.
2521 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2522 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
2523 emit_byte(0x73);
2524 emit_byte(0xC0 | encode);
2525 emit_byte(shift);
2526 }
2528 void Assembler::psrldq(XMMRegister dst, int shift) {
2529 // Shift 128 bit value in xmm register by number of bytes.
2530 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2531 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66);
2532 emit_byte(0x73);
2533 emit_byte(0xC0 | encode);
2534 emit_byte(shift);
2535 }
2537 void Assembler::ptest(XMMRegister dst, Address src) {
2538 assert(VM_Version::supports_sse4_1(), "");
2539 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2540 InstructionMark im(this);
2541 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2542 emit_byte(0x17);
2543 emit_operand(dst, src);
2544 }
2546 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2547 assert(VM_Version::supports_sse4_1(), "");
2548 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2549 emit_byte(0x17);
2550 emit_byte(0xC0 | encode);
2551 }
2553 void Assembler::punpcklbw(XMMRegister dst, Address src) {
2554 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2555 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2556 InstructionMark im(this);
2557 simd_prefix(dst, dst, src, VEX_SIMD_66);
2558 emit_byte(0x60);
2559 emit_operand(dst, src);
2560 }
2562 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2563 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2564 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2565 emit_byte(0x60);
2566 emit_byte(0xC0 | encode);
2567 }
2569 void Assembler::punpckldq(XMMRegister dst, Address src) {
2570 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2571 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2572 InstructionMark im(this);
2573 simd_prefix(dst, dst, src, VEX_SIMD_66);
2574 emit_byte(0x62);
2575 emit_operand(dst, src);
2576 }
2578 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2579 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2580 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2581 emit_byte(0x62);
2582 emit_byte(0xC0 | encode);
2583 }
2585 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
2586 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2587 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2588 emit_byte(0x6C);
2589 emit_byte(0xC0 | encode);
2590 }
2592 void Assembler::push(int32_t imm32) {
2593 // in 64bits we push 64bits onto the stack but only
2594 // take a 32bit immediate
2595 emit_byte(0x68);
2596 emit_long(imm32);
2597 }
2599 void Assembler::push(Register src) {
2600 int encode = prefix_and_encode(src->encoding());
2602 emit_byte(0x50 | encode);
2603 }
2605 void Assembler::pushf() {
2606 emit_byte(0x9C);
2607 }
2609 #ifndef _LP64 // no 32bit push/pop on amd64
2610 void Assembler::pushl(Address src) {
2611 // Note this will push 64bit on 64bit
2612 InstructionMark im(this);
2613 prefix(src);
2614 emit_byte(0xFF);
2615 emit_operand(rsi, src);
2616 }
2617 #endif
2619 void Assembler::pxor(XMMRegister dst, Address src) {
2620 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2621 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2622 InstructionMark im(this);
2623 simd_prefix(dst, dst, src, VEX_SIMD_66);
2624 emit_byte(0xEF);
2625 emit_operand(dst, src);
2626 }
2628 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2629 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2630 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2631 emit_byte(0xEF);
2632 emit_byte(0xC0 | encode);
2633 }
2635 void Assembler::rcll(Register dst, int imm8) {
2636 assert(isShiftCount(imm8), "illegal shift count");
2637 int encode = prefix_and_encode(dst->encoding());
2638 if (imm8 == 1) {
2639 emit_byte(0xD1);
2640 emit_byte(0xD0 | encode);
2641 } else {
2642 emit_byte(0xC1);
2643 emit_byte(0xD0 | encode);
2644 emit_byte(imm8);
2645 }
2646 }
2648 // copies data from [esi] to [edi] using rcx pointer sized words
2649 // generic
2650 void Assembler::rep_mov() {
2651 emit_byte(0xF3);
2652 // MOVSQ
2653 LP64_ONLY(prefix(REX_W));
2654 emit_byte(0xA5);
2655 }
2657 // sets rcx pointer sized words with rax, value at [edi]
2658 // generic
2659 void Assembler::rep_set() { // rep_set
2660 emit_byte(0xF3);
2661 // STOSQ
2662 LP64_ONLY(prefix(REX_W));
2663 emit_byte(0xAB);
2664 }
2666 // scans rcx pointer sized words at [edi] for occurance of rax,
2667 // generic
2668 void Assembler::repne_scan() { // repne_scan
2669 emit_byte(0xF2);
2670 // SCASQ
2671 LP64_ONLY(prefix(REX_W));
2672 emit_byte(0xAF);
2673 }
2675 #ifdef _LP64
2676 // scans rcx 4 byte words at [edi] for occurance of rax,
2677 // generic
2678 void Assembler::repne_scanl() { // repne_scan
2679 emit_byte(0xF2);
2680 // SCASL
2681 emit_byte(0xAF);
2682 }
2683 #endif
2685 void Assembler::ret(int imm16) {
2686 if (imm16 == 0) {
2687 emit_byte(0xC3);
2688 } else {
2689 emit_byte(0xC2);
2690 emit_word(imm16);
2691 }
2692 }
2694 void Assembler::sahf() {
2695 #ifdef _LP64
2696 // Not supported in 64bit mode
2697 ShouldNotReachHere();
2698 #endif
2699 emit_byte(0x9E);
2700 }
2702 void Assembler::sarl(Register dst, int imm8) {
2703 int encode = prefix_and_encode(dst->encoding());
2704 assert(isShiftCount(imm8), "illegal shift count");
2705 if (imm8 == 1) {
2706 emit_byte(0xD1);
2707 emit_byte(0xF8 | encode);
2708 } else {
2709 emit_byte(0xC1);
2710 emit_byte(0xF8 | encode);
2711 emit_byte(imm8);
2712 }
2713 }
2715 void Assembler::sarl(Register dst) {
2716 int encode = prefix_and_encode(dst->encoding());
2717 emit_byte(0xD3);
2718 emit_byte(0xF8 | encode);
2719 }
2721 void Assembler::sbbl(Address dst, int32_t imm32) {
2722 InstructionMark im(this);
2723 prefix(dst);
2724 emit_arith_operand(0x81, rbx, dst, imm32);
2725 }
2727 void Assembler::sbbl(Register dst, int32_t imm32) {
2728 prefix(dst);
2729 emit_arith(0x81, 0xD8, dst, imm32);
2730 }
2733 void Assembler::sbbl(Register dst, Address src) {
2734 InstructionMark im(this);
2735 prefix(src, dst);
2736 emit_byte(0x1B);
2737 emit_operand(dst, src);
2738 }
2740 void Assembler::sbbl(Register dst, Register src) {
2741 (void) prefix_and_encode(dst->encoding(), src->encoding());
2742 emit_arith(0x1B, 0xC0, dst, src);
2743 }
2745 void Assembler::setb(Condition cc, Register dst) {
2746 assert(0 <= cc && cc < 16, "illegal cc");
2747 int encode = prefix_and_encode(dst->encoding(), true);
2748 emit_byte(0x0F);
2749 emit_byte(0x90 | cc);
2750 emit_byte(0xC0 | encode);
2751 }
2753 void Assembler::shll(Register dst, int imm8) {
2754 assert(isShiftCount(imm8), "illegal shift count");
2755 int encode = prefix_and_encode(dst->encoding());
2756 if (imm8 == 1 ) {
2757 emit_byte(0xD1);
2758 emit_byte(0xE0 | encode);
2759 } else {
2760 emit_byte(0xC1);
2761 emit_byte(0xE0 | encode);
2762 emit_byte(imm8);
2763 }
2764 }
2766 void Assembler::shll(Register dst) {
2767 int encode = prefix_and_encode(dst->encoding());
2768 emit_byte(0xD3);
2769 emit_byte(0xE0 | encode);
2770 }
2772 void Assembler::shrl(Register dst, int imm8) {
2773 assert(isShiftCount(imm8), "illegal shift count");
2774 int encode = prefix_and_encode(dst->encoding());
2775 emit_byte(0xC1);
2776 emit_byte(0xE8 | encode);
2777 emit_byte(imm8);
2778 }
2780 void Assembler::shrl(Register dst) {
2781 int encode = prefix_and_encode(dst->encoding());
2782 emit_byte(0xD3);
2783 emit_byte(0xE8 | encode);
2784 }
2786 // copies a single word from [esi] to [edi]
2787 void Assembler::smovl() {
2788 emit_byte(0xA5);
2789 }
2791 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2792 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2793 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
2794 emit_byte(0x51);
2795 emit_byte(0xC0 | encode);
2796 }
2798 void Assembler::sqrtsd(XMMRegister dst, Address src) {
2799 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2800 InstructionMark im(this);
2801 simd_prefix(dst, dst, src, VEX_SIMD_F2);
2802 emit_byte(0x51);
2803 emit_operand(dst, src);
2804 }
2806 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
2807 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2808 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
2809 emit_byte(0x51);
2810 emit_byte(0xC0 | encode);
2811 }
2813 void Assembler::sqrtss(XMMRegister dst, Address src) {
2814 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2815 InstructionMark im(this);
2816 simd_prefix(dst, dst, src, VEX_SIMD_F3);
2817 emit_byte(0x51);
2818 emit_operand(dst, src);
2819 }
2821 void Assembler::stmxcsr( Address dst) {
2822 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2823 InstructionMark im(this);
2824 prefix(dst);
2825 emit_byte(0x0F);
2826 emit_byte(0xAE);
2827 emit_operand(as_Register(3), dst);
2828 }
2830 void Assembler::subl(Address dst, int32_t imm32) {
2831 InstructionMark im(this);
2832 prefix(dst);
2833 emit_arith_operand(0x81, rbp, dst, imm32);
2834 }
2836 void Assembler::subl(Address dst, Register src) {
2837 InstructionMark im(this);
2838 prefix(dst, src);
2839 emit_byte(0x29);
2840 emit_operand(src, dst);
2841 }
2843 void Assembler::subl(Register dst, int32_t imm32) {
2844 prefix(dst);
2845 emit_arith(0x81, 0xE8, dst, imm32);
2846 }
2848 // Force generation of a 4 byte immediate value even if it fits into 8bit
2849 void Assembler::subl_imm32(Register dst, int32_t imm32) {
2850 prefix(dst);
2851 emit_arith_imm32(0x81, 0xE8, dst, imm32);
2852 }
2854 void Assembler::subl(Register dst, Address src) {
2855 InstructionMark im(this);
2856 prefix(src, dst);
2857 emit_byte(0x2B);
2858 emit_operand(dst, src);
2859 }
2861 void Assembler::subl(Register dst, Register src) {
2862 (void) prefix_and_encode(dst->encoding(), src->encoding());
2863 emit_arith(0x2B, 0xC0, dst, src);
2864 }
2866 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2867 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2868 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
2869 emit_byte(0x5C);
2870 emit_byte(0xC0 | encode);
2871 }
2873 void Assembler::subsd(XMMRegister dst, Address src) {
2874 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2875 InstructionMark im(this);
2876 simd_prefix(dst, dst, src, VEX_SIMD_F2);
2877 emit_byte(0x5C);
2878 emit_operand(dst, src);
2879 }
2881 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2882 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2883 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
2884 emit_byte(0x5C);
2885 emit_byte(0xC0 | encode);
2886 }
2888 void Assembler::subss(XMMRegister dst, Address src) {
2889 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2890 InstructionMark im(this);
2891 simd_prefix(dst, dst, src, VEX_SIMD_F3);
2892 emit_byte(0x5C);
2893 emit_operand(dst, src);
2894 }
2896 void Assembler::testb(Register dst, int imm8) {
2897 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2898 (void) prefix_and_encode(dst->encoding(), true);
2899 emit_arith_b(0xF6, 0xC0, dst, imm8);
2900 }
2902 void Assembler::testl(Register dst, int32_t imm32) {
2903 // not using emit_arith because test
2904 // doesn't support sign-extension of
2905 // 8bit operands
2906 int encode = dst->encoding();
2907 if (encode == 0) {
2908 emit_byte(0xA9);
2909 } else {
2910 encode = prefix_and_encode(encode);
2911 emit_byte(0xF7);
2912 emit_byte(0xC0 | encode);
2913 }
2914 emit_long(imm32);
2915 }
2917 void Assembler::testl(Register dst, Register src) {
2918 (void) prefix_and_encode(dst->encoding(), src->encoding());
2919 emit_arith(0x85, 0xC0, dst, src);
2920 }
2922 void Assembler::testl(Register dst, Address src) {
2923 InstructionMark im(this);
2924 prefix(src, dst);
2925 emit_byte(0x85);
2926 emit_operand(dst, src);
2927 }
2929 void Assembler::ucomisd(XMMRegister dst, Address src) {
2930 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2931 InstructionMark im(this);
2932 simd_prefix(dst, src, VEX_SIMD_66);
2933 emit_byte(0x2E);
2934 emit_operand(dst, src);
2935 }
2937 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2938 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2939 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
2940 emit_byte(0x2E);
2941 emit_byte(0xC0 | encode);
2942 }
2944 void Assembler::ucomiss(XMMRegister dst, Address src) {
2945 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2946 InstructionMark im(this);
2947 simd_prefix(dst, src, VEX_SIMD_NONE);
2948 emit_byte(0x2E);
2949 emit_operand(dst, src);
2950 }
2952 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2953 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2954 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
2955 emit_byte(0x2E);
2956 emit_byte(0xC0 | encode);
2957 }
2960 void Assembler::xaddl(Address dst, Register src) {
2961 InstructionMark im(this);
2962 prefix(dst, src);
2963 emit_byte(0x0F);
2964 emit_byte(0xC1);
2965 emit_operand(src, dst);
2966 }
2968 void Assembler::xchgl(Register dst, Address src) { // xchg
2969 InstructionMark im(this);
2970 prefix(src, dst);
2971 emit_byte(0x87);
2972 emit_operand(dst, src);
2973 }
2975 void Assembler::xchgl(Register dst, Register src) {
2976 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2977 emit_byte(0x87);
2978 emit_byte(0xc0 | encode);
2979 }
2981 void Assembler::xorl(Register dst, int32_t imm32) {
2982 prefix(dst);
2983 emit_arith(0x81, 0xF0, dst, imm32);
2984 }
2986 void Assembler::xorl(Register dst, Address src) {
2987 InstructionMark im(this);
2988 prefix(src, dst);
2989 emit_byte(0x33);
2990 emit_operand(dst, src);
2991 }
2993 void Assembler::xorl(Register dst, Register src) {
2994 (void) prefix_and_encode(dst->encoding(), src->encoding());
2995 emit_arith(0x33, 0xC0, dst, src);
2996 }
2998 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2999 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3000 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
3001 emit_byte(0x57);
3002 emit_byte(0xC0 | encode);
3003 }
3005 void Assembler::xorpd(XMMRegister dst, Address src) {
3006 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3007 InstructionMark im(this);
3008 simd_prefix(dst, dst, src, VEX_SIMD_66);
3009 emit_byte(0x57);
3010 emit_operand(dst, src);
3011 }
3014 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
3015 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3016 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE);
3017 emit_byte(0x57);
3018 emit_byte(0xC0 | encode);
3019 }
3021 void Assembler::xorps(XMMRegister dst, Address src) {
3022 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3023 InstructionMark im(this);
3024 simd_prefix(dst, dst, src, VEX_SIMD_NONE);
3025 emit_byte(0x57);
3026 emit_operand(dst, src);
3027 }
3029 // AVX 3-operands non destructive source instructions (encoded with VEX prefix)
3031 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3032 assert(VM_Version::supports_avx(), "");
3033 InstructionMark im(this);
3034 vex_prefix(dst, nds, src, VEX_SIMD_F2);
3035 emit_byte(0x58);
3036 emit_operand(dst, src);
3037 }
3039 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3040 assert(VM_Version::supports_avx(), "");
3041 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
3042 emit_byte(0x58);
3043 emit_byte(0xC0 | encode);
3044 }
3046 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3047 assert(VM_Version::supports_avx(), "");
3048 InstructionMark im(this);
3049 vex_prefix(dst, nds, src, VEX_SIMD_F3);
3050 emit_byte(0x58);
3051 emit_operand(dst, src);
3052 }
3054 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3055 assert(VM_Version::supports_avx(), "");
3056 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
3057 emit_byte(0x58);
3058 emit_byte(0xC0 | encode);
3059 }
3061 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src) {
3062 assert(VM_Version::supports_avx(), "");
3063 InstructionMark im(this);
3064 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector
3065 emit_byte(0x54);
3066 emit_operand(dst, src);
3067 }
3069 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src) {
3070 assert(VM_Version::supports_avx(), "");
3071 InstructionMark im(this);
3072 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector
3073 emit_byte(0x54);
3074 emit_operand(dst, src);
3075 }
3077 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3078 assert(VM_Version::supports_avx(), "");
3079 InstructionMark im(this);
3080 vex_prefix(dst, nds, src, VEX_SIMD_F2);
3081 emit_byte(0x5E);
3082 emit_operand(dst, src);
3083 }
3085 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3086 assert(VM_Version::supports_avx(), "");
3087 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
3088 emit_byte(0x5E);
3089 emit_byte(0xC0 | encode);
3090 }
3092 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3093 assert(VM_Version::supports_avx(), "");
3094 InstructionMark im(this);
3095 vex_prefix(dst, nds, src, VEX_SIMD_F3);
3096 emit_byte(0x5E);
3097 emit_operand(dst, src);
3098 }
3100 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3101 assert(VM_Version::supports_avx(), "");
3102 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
3103 emit_byte(0x5E);
3104 emit_byte(0xC0 | encode);
3105 }
3107 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3108 assert(VM_Version::supports_avx(), "");
3109 InstructionMark im(this);
3110 vex_prefix(dst, nds, src, VEX_SIMD_F2);
3111 emit_byte(0x59);
3112 emit_operand(dst, src);
3113 }
3115 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3116 assert(VM_Version::supports_avx(), "");
3117 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
3118 emit_byte(0x59);
3119 emit_byte(0xC0 | encode);
3120 }
3122 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3123 InstructionMark im(this);
3124 vex_prefix(dst, nds, src, VEX_SIMD_F3);
3125 emit_byte(0x59);
3126 emit_operand(dst, src);
3127 }
3129 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3130 assert(VM_Version::supports_avx(), "");
3131 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
3132 emit_byte(0x59);
3133 emit_byte(0xC0 | encode);
3134 }
3137 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3138 assert(VM_Version::supports_avx(), "");
3139 InstructionMark im(this);
3140 vex_prefix(dst, nds, src, VEX_SIMD_F2);
3141 emit_byte(0x5C);
3142 emit_operand(dst, src);
3143 }
3145 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3146 assert(VM_Version::supports_avx(), "");
3147 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
3148 emit_byte(0x5C);
3149 emit_byte(0xC0 | encode);
3150 }
3152 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3153 assert(VM_Version::supports_avx(), "");
3154 InstructionMark im(this);
3155 vex_prefix(dst, nds, src, VEX_SIMD_F3);
3156 emit_byte(0x5C);
3157 emit_operand(dst, src);
3158 }
3160 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3161 assert(VM_Version::supports_avx(), "");
3162 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
3163 emit_byte(0x5C);
3164 emit_byte(0xC0 | encode);
3165 }
3167 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src) {
3168 assert(VM_Version::supports_avx(), "");
3169 InstructionMark im(this);
3170 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector
3171 emit_byte(0x57);
3172 emit_operand(dst, src);
3173 }
3175 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3176 assert(VM_Version::supports_avx(), "");
3177 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256);
3178 emit_byte(0x57);
3179 emit_byte(0xC0 | encode);
3180 }
3182 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src) {
3183 assert(VM_Version::supports_avx(), "");
3184 InstructionMark im(this);
3185 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector
3186 emit_byte(0x57);
3187 emit_operand(dst, src);
3188 }
3190 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3191 assert(VM_Version::supports_avx(), "");
3192 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, vector256);
3193 emit_byte(0x57);
3194 emit_byte(0xC0 | encode);
3195 }
3197 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3198 assert(VM_Version::supports_avx2() || (!vector256) && VM_Version::supports_avx(), "");
3199 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256);
3200 emit_byte(0xEF);
3201 emit_byte(0xC0 | encode);
3202 }
3204 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3205 assert(VM_Version::supports_avx(), "");
3206 bool vector256 = true;
3207 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3208 emit_byte(0x18);
3209 emit_byte(0xC0 | encode);
3210 // 0x00 - insert into lower 128 bits
3211 // 0x01 - insert into upper 128 bits
3212 emit_byte(0x01);
3213 }
3215 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3216 assert(VM_Version::supports_avx2(), "");
3217 bool vector256 = true;
3218 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3219 emit_byte(0x38);
3220 emit_byte(0xC0 | encode);
3221 // 0x00 - insert into lower 128 bits
3222 // 0x01 - insert into upper 128 bits
3223 emit_byte(0x01);
3224 }
3226 void Assembler::vzeroupper() {
3227 assert(VM_Version::supports_avx(), "");
3228 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
3229 emit_byte(0x77);
3230 }
3233 #ifndef _LP64
3234 // 32bit only pieces of the assembler
3236 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3237 // NO PREFIX AS NEVER 64BIT
3238 InstructionMark im(this);
3239 emit_byte(0x81);
3240 emit_byte(0xF8 | src1->encoding());
3241 emit_data(imm32, rspec, 0);
3242 }
3244 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3245 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
3246 InstructionMark im(this);
3247 emit_byte(0x81);
3248 emit_operand(rdi, src1);
3249 emit_data(imm32, rspec, 0);
3250 }
3252 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
3253 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
3254 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
3255 void Assembler::cmpxchg8(Address adr) {
3256 InstructionMark im(this);
3257 emit_byte(0x0F);
3258 emit_byte(0xc7);
3259 emit_operand(rcx, adr);
3260 }
3262 void Assembler::decl(Register dst) {
3263 // Don't use it directly. Use MacroAssembler::decrementl() instead.
3264 emit_byte(0x48 | dst->encoding());
3265 }
3267 #endif // _LP64
3269 // 64bit typically doesn't use the x87 but needs to for the trig funcs
3271 void Assembler::fabs() {
3272 emit_byte(0xD9);
3273 emit_byte(0xE1);
3274 }
3276 void Assembler::fadd(int i) {
3277 emit_farith(0xD8, 0xC0, i);
3278 }
3280 void Assembler::fadd_d(Address src) {
3281 InstructionMark im(this);
3282 emit_byte(0xDC);
3283 emit_operand32(rax, src);
3284 }
3286 void Assembler::fadd_s(Address src) {
3287 InstructionMark im(this);
3288 emit_byte(0xD8);
3289 emit_operand32(rax, src);
3290 }
3292 void Assembler::fadda(int i) {
3293 emit_farith(0xDC, 0xC0, i);
3294 }
3296 void Assembler::faddp(int i) {
3297 emit_farith(0xDE, 0xC0, i);
3298 }
3300 void Assembler::fchs() {
3301 emit_byte(0xD9);
3302 emit_byte(0xE0);
3303 }
3305 void Assembler::fcom(int i) {
3306 emit_farith(0xD8, 0xD0, i);
3307 }
3309 void Assembler::fcomp(int i) {
3310 emit_farith(0xD8, 0xD8, i);
3311 }
3313 void Assembler::fcomp_d(Address src) {
3314 InstructionMark im(this);
3315 emit_byte(0xDC);
3316 emit_operand32(rbx, src);
3317 }
3319 void Assembler::fcomp_s(Address src) {
3320 InstructionMark im(this);
3321 emit_byte(0xD8);
3322 emit_operand32(rbx, src);
3323 }
3325 void Assembler::fcompp() {
3326 emit_byte(0xDE);
3327 emit_byte(0xD9);
3328 }
3330 void Assembler::fcos() {
3331 emit_byte(0xD9);
3332 emit_byte(0xFF);
3333 }
3335 void Assembler::fdecstp() {
3336 emit_byte(0xD9);
3337 emit_byte(0xF6);
3338 }
3340 void Assembler::fdiv(int i) {
3341 emit_farith(0xD8, 0xF0, i);
3342 }
3344 void Assembler::fdiv_d(Address src) {
3345 InstructionMark im(this);
3346 emit_byte(0xDC);
3347 emit_operand32(rsi, src);
3348 }
3350 void Assembler::fdiv_s(Address src) {
3351 InstructionMark im(this);
3352 emit_byte(0xD8);
3353 emit_operand32(rsi, src);
3354 }
3356 void Assembler::fdiva(int i) {
3357 emit_farith(0xDC, 0xF8, i);
3358 }
3360 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
3361 // is erroneous for some of the floating-point instructions below.
3363 void Assembler::fdivp(int i) {
3364 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
3365 }
3367 void Assembler::fdivr(int i) {
3368 emit_farith(0xD8, 0xF8, i);
3369 }
3371 void Assembler::fdivr_d(Address src) {
3372 InstructionMark im(this);
3373 emit_byte(0xDC);
3374 emit_operand32(rdi, src);
3375 }
3377 void Assembler::fdivr_s(Address src) {
3378 InstructionMark im(this);
3379 emit_byte(0xD8);
3380 emit_operand32(rdi, src);
3381 }
3383 void Assembler::fdivra(int i) {
3384 emit_farith(0xDC, 0xF0, i);
3385 }
3387 void Assembler::fdivrp(int i) {
3388 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
3389 }
3391 void Assembler::ffree(int i) {
3392 emit_farith(0xDD, 0xC0, i);
3393 }
3395 void Assembler::fild_d(Address adr) {
3396 InstructionMark im(this);
3397 emit_byte(0xDF);
3398 emit_operand32(rbp, adr);
3399 }
3401 void Assembler::fild_s(Address adr) {
3402 InstructionMark im(this);
3403 emit_byte(0xDB);
3404 emit_operand32(rax, adr);
3405 }
3407 void Assembler::fincstp() {
3408 emit_byte(0xD9);
3409 emit_byte(0xF7);
3410 }
3412 void Assembler::finit() {
3413 emit_byte(0x9B);
3414 emit_byte(0xDB);
3415 emit_byte(0xE3);
3416 }
3418 void Assembler::fist_s(Address adr) {
3419 InstructionMark im(this);
3420 emit_byte(0xDB);
3421 emit_operand32(rdx, adr);
3422 }
3424 void Assembler::fistp_d(Address adr) {
3425 InstructionMark im(this);
3426 emit_byte(0xDF);
3427 emit_operand32(rdi, adr);
3428 }
3430 void Assembler::fistp_s(Address adr) {
3431 InstructionMark im(this);
3432 emit_byte(0xDB);
3433 emit_operand32(rbx, adr);
3434 }
3436 void Assembler::fld1() {
3437 emit_byte(0xD9);
3438 emit_byte(0xE8);
3439 }
3441 void Assembler::fld_d(Address adr) {
3442 InstructionMark im(this);
3443 emit_byte(0xDD);
3444 emit_operand32(rax, adr);
3445 }
3447 void Assembler::fld_s(Address adr) {
3448 InstructionMark im(this);
3449 emit_byte(0xD9);
3450 emit_operand32(rax, adr);
3451 }
3454 void Assembler::fld_s(int index) {
3455 emit_farith(0xD9, 0xC0, index);
3456 }
3458 void Assembler::fld_x(Address adr) {
3459 InstructionMark im(this);
3460 emit_byte(0xDB);
3461 emit_operand32(rbp, adr);
3462 }
3464 void Assembler::fldcw(Address src) {
3465 InstructionMark im(this);
3466 emit_byte(0xd9);
3467 emit_operand32(rbp, src);
3468 }
3470 void Assembler::fldenv(Address src) {
3471 InstructionMark im(this);
3472 emit_byte(0xD9);
3473 emit_operand32(rsp, src);
3474 }
3476 void Assembler::fldlg2() {
3477 emit_byte(0xD9);
3478 emit_byte(0xEC);
3479 }
3481 void Assembler::fldln2() {
3482 emit_byte(0xD9);
3483 emit_byte(0xED);
3484 }
3486 void Assembler::fldz() {
3487 emit_byte(0xD9);
3488 emit_byte(0xEE);
3489 }
3491 void Assembler::flog() {
3492 fldln2();
3493 fxch();
3494 fyl2x();
3495 }
3497 void Assembler::flog10() {
3498 fldlg2();
3499 fxch();
3500 fyl2x();
3501 }
3503 void Assembler::fmul(int i) {
3504 emit_farith(0xD8, 0xC8, i);
3505 }
3507 void Assembler::fmul_d(Address src) {
3508 InstructionMark im(this);
3509 emit_byte(0xDC);
3510 emit_operand32(rcx, src);
3511 }
3513 void Assembler::fmul_s(Address src) {
3514 InstructionMark im(this);
3515 emit_byte(0xD8);
3516 emit_operand32(rcx, src);
3517 }
3519 void Assembler::fmula(int i) {
3520 emit_farith(0xDC, 0xC8, i);
3521 }
3523 void Assembler::fmulp(int i) {
3524 emit_farith(0xDE, 0xC8, i);
3525 }
3527 void Assembler::fnsave(Address dst) {
3528 InstructionMark im(this);
3529 emit_byte(0xDD);
3530 emit_operand32(rsi, dst);
3531 }
3533 void Assembler::fnstcw(Address src) {
3534 InstructionMark im(this);
3535 emit_byte(0x9B);
3536 emit_byte(0xD9);
3537 emit_operand32(rdi, src);
3538 }
3540 void Assembler::fnstsw_ax() {
3541 emit_byte(0xdF);
3542 emit_byte(0xE0);
3543 }
3545 void Assembler::fprem() {
3546 emit_byte(0xD9);
3547 emit_byte(0xF8);
3548 }
3550 void Assembler::fprem1() {
3551 emit_byte(0xD9);
3552 emit_byte(0xF5);
3553 }
3555 void Assembler::frstor(Address src) {
3556 InstructionMark im(this);
3557 emit_byte(0xDD);
3558 emit_operand32(rsp, src);
3559 }
3561 void Assembler::fsin() {
3562 emit_byte(0xD9);
3563 emit_byte(0xFE);
3564 }
3566 void Assembler::fsqrt() {
3567 emit_byte(0xD9);
3568 emit_byte(0xFA);
3569 }
3571 void Assembler::fst_d(Address adr) {
3572 InstructionMark im(this);
3573 emit_byte(0xDD);
3574 emit_operand32(rdx, adr);
3575 }
3577 void Assembler::fst_s(Address adr) {
3578 InstructionMark im(this);
3579 emit_byte(0xD9);
3580 emit_operand32(rdx, adr);
3581 }
3583 void Assembler::fstp_d(Address adr) {
3584 InstructionMark im(this);
3585 emit_byte(0xDD);
3586 emit_operand32(rbx, adr);
3587 }
3589 void Assembler::fstp_d(int index) {
3590 emit_farith(0xDD, 0xD8, index);
3591 }
3593 void Assembler::fstp_s(Address adr) {
3594 InstructionMark im(this);
3595 emit_byte(0xD9);
3596 emit_operand32(rbx, adr);
3597 }
3599 void Assembler::fstp_x(Address adr) {
3600 InstructionMark im(this);
3601 emit_byte(0xDB);
3602 emit_operand32(rdi, adr);
3603 }
3605 void Assembler::fsub(int i) {
3606 emit_farith(0xD8, 0xE0, i);
3607 }
3609 void Assembler::fsub_d(Address src) {
3610 InstructionMark im(this);
3611 emit_byte(0xDC);
3612 emit_operand32(rsp, src);
3613 }
3615 void Assembler::fsub_s(Address src) {
3616 InstructionMark im(this);
3617 emit_byte(0xD8);
3618 emit_operand32(rsp, src);
3619 }
3621 void Assembler::fsuba(int i) {
3622 emit_farith(0xDC, 0xE8, i);
3623 }
3625 void Assembler::fsubp(int i) {
3626 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
3627 }
3629 void Assembler::fsubr(int i) {
3630 emit_farith(0xD8, 0xE8, i);
3631 }
3633 void Assembler::fsubr_d(Address src) {
3634 InstructionMark im(this);
3635 emit_byte(0xDC);
3636 emit_operand32(rbp, src);
3637 }
3639 void Assembler::fsubr_s(Address src) {
3640 InstructionMark im(this);
3641 emit_byte(0xD8);
3642 emit_operand32(rbp, src);
3643 }
3645 void Assembler::fsubra(int i) {
3646 emit_farith(0xDC, 0xE0, i);
3647 }
3649 void Assembler::fsubrp(int i) {
3650 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
3651 }
3653 void Assembler::ftan() {
3654 emit_byte(0xD9);
3655 emit_byte(0xF2);
3656 emit_byte(0xDD);
3657 emit_byte(0xD8);
3658 }
3660 void Assembler::ftst() {
3661 emit_byte(0xD9);
3662 emit_byte(0xE4);
3663 }
3665 void Assembler::fucomi(int i) {
3666 // make sure the instruction is supported (introduced for P6, together with cmov)
3667 guarantee(VM_Version::supports_cmov(), "illegal instruction");
3668 emit_farith(0xDB, 0xE8, i);
3669 }
3671 void Assembler::fucomip(int i) {
3672 // make sure the instruction is supported (introduced for P6, together with cmov)
3673 guarantee(VM_Version::supports_cmov(), "illegal instruction");
3674 emit_farith(0xDF, 0xE8, i);
3675 }
3677 void Assembler::fwait() {
3678 emit_byte(0x9B);
3679 }
3681 void Assembler::fxch(int i) {
3682 emit_farith(0xD9, 0xC8, i);
3683 }
3685 void Assembler::fyl2x() {
3686 emit_byte(0xD9);
3687 emit_byte(0xF1);
3688 }
3690 void Assembler::frndint() {
3691 emit_byte(0xD9);
3692 emit_byte(0xFC);
3693 }
3695 void Assembler::f2xm1() {
3696 emit_byte(0xD9);
3697 emit_byte(0xF0);
3698 }
3700 void Assembler::fldl2e() {
3701 emit_byte(0xD9);
3702 emit_byte(0xEA);
3703 }
3705 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
3706 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
3707 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
3708 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
3710 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
3711 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
3712 if (pre > 0) {
3713 emit_byte(simd_pre[pre]);
3714 }
3715 if (rex_w) {
3716 prefixq(adr, xreg);
3717 } else {
3718 prefix(adr, xreg);
3719 }
3720 if (opc > 0) {
3721 emit_byte(0x0F);
3722 int opc2 = simd_opc[opc];
3723 if (opc2 > 0) {
3724 emit_byte(opc2);
3725 }
3726 }
3727 }
3729 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
3730 if (pre > 0) {
3731 emit_byte(simd_pre[pre]);
3732 }
3733 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
3734 prefix_and_encode(dst_enc, src_enc);
3735 if (opc > 0) {
3736 emit_byte(0x0F);
3737 int opc2 = simd_opc[opc];
3738 if (opc2 > 0) {
3739 emit_byte(opc2);
3740 }
3741 }
3742 return encode;
3743 }
3746 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) {
3747 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
3748 prefix(VEX_3bytes);
3750 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
3751 byte1 = (~byte1) & 0xE0;
3752 byte1 |= opc;
3753 a_byte(byte1);
3755 int byte2 = ((~nds_enc) & 0xf) << 3;
3756 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre;
3757 emit_byte(byte2);
3758 } else {
3759 prefix(VEX_2bytes);
3761 int byte1 = vex_r ? VEX_R : 0;
3762 byte1 = (~byte1) & 0x80;
3763 byte1 |= ((~nds_enc) & 0xf) << 3;
3764 byte1 |= (vector256 ? 4 : 0) | pre;
3765 emit_byte(byte1);
3766 }
3767 }
3769 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){
3770 bool vex_r = (xreg_enc >= 8);
3771 bool vex_b = adr.base_needs_rex();
3772 bool vex_x = adr.index_needs_rex();
3773 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
3774 }
3776 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) {
3777 bool vex_r = (dst_enc >= 8);
3778 bool vex_b = (src_enc >= 8);
3779 bool vex_x = false;
3780 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
3781 return (((dst_enc & 7) << 3) | (src_enc & 7));
3782 }
3785 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
3786 if (UseAVX > 0) {
3787 int xreg_enc = xreg->encoding();
3788 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3789 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256);
3790 } else {
3791 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
3792 rex_prefix(adr, xreg, pre, opc, rex_w);
3793 }
3794 }
3796 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
3797 int dst_enc = dst->encoding();
3798 int src_enc = src->encoding();
3799 if (UseAVX > 0) {
3800 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3801 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256);
3802 } else {
3803 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
3804 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
3805 }
3806 }
3808 #ifndef _LP64
3810 void Assembler::incl(Register dst) {
3811 // Don't use it directly. Use MacroAssembler::incrementl() instead.
3812 emit_byte(0x40 | dst->encoding());
3813 }
3815 void Assembler::lea(Register dst, Address src) {
3816 leal(dst, src);
3817 }
3819 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
3820 InstructionMark im(this);
3821 emit_byte(0xC7);
3822 emit_operand(rax, dst);
3823 emit_data((int)imm32, rspec, 0);
3824 }
3826 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
3827 InstructionMark im(this);
3828 int encode = prefix_and_encode(dst->encoding());
3829 emit_byte(0xB8 | encode);
3830 emit_data((int)imm32, rspec, 0);
3831 }
3833 void Assembler::popa() { // 32bit
3834 emit_byte(0x61);
3835 }
3837 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
3838 InstructionMark im(this);
3839 emit_byte(0x68);
3840 emit_data(imm32, rspec, 0);
3841 }
3843 void Assembler::pusha() { // 32bit
3844 emit_byte(0x60);
3845 }
3847 void Assembler::set_byte_if_not_zero(Register dst) {
3848 emit_byte(0x0F);
3849 emit_byte(0x95);
3850 emit_byte(0xE0 | dst->encoding());
3851 }
3853 void Assembler::shldl(Register dst, Register src) {
3854 emit_byte(0x0F);
3855 emit_byte(0xA5);
3856 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
3857 }
3859 void Assembler::shrdl(Register dst, Register src) {
3860 emit_byte(0x0F);
3861 emit_byte(0xAD);
3862 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
3863 }
3865 #else // LP64
3867 void Assembler::set_byte_if_not_zero(Register dst) {
3868 int enc = prefix_and_encode(dst->encoding(), true);
3869 emit_byte(0x0F);
3870 emit_byte(0x95);
3871 emit_byte(0xE0 | enc);
3872 }
3874 // 64bit only pieces of the assembler
3875 // This should only be used by 64bit instructions that can use rip-relative
3876 // it cannot be used by instructions that want an immediate value.
3878 bool Assembler::reachable(AddressLiteral adr) {
3879 int64_t disp;
3880 // None will force a 64bit literal to the code stream. Likely a placeholder
3881 // for something that will be patched later and we need to certain it will
3882 // always be reachable.
3883 if (adr.reloc() == relocInfo::none) {
3884 return false;
3885 }
3886 if (adr.reloc() == relocInfo::internal_word_type) {
3887 // This should be rip relative and easily reachable.
3888 return true;
3889 }
3890 if (adr.reloc() == relocInfo::virtual_call_type ||
3891 adr.reloc() == relocInfo::opt_virtual_call_type ||
3892 adr.reloc() == relocInfo::static_call_type ||
3893 adr.reloc() == relocInfo::static_stub_type ) {
3894 // This should be rip relative within the code cache and easily
3895 // reachable until we get huge code caches. (At which point
3896 // ic code is going to have issues).
3897 return true;
3898 }
3899 if (adr.reloc() != relocInfo::external_word_type &&
3900 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
3901 adr.reloc() != relocInfo::poll_type && // relocs to identify them
3902 adr.reloc() != relocInfo::runtime_call_type ) {
3903 return false;
3904 }
3906 // Stress the correction code
3907 if (ForceUnreachable) {
3908 // Must be runtimecall reloc, see if it is in the codecache
3909 // Flipping stuff in the codecache to be unreachable causes issues
3910 // with things like inline caches where the additional instructions
3911 // are not handled.
3912 if (CodeCache::find_blob(adr._target) == NULL) {
3913 return false;
3914 }
3915 }
3916 // For external_word_type/runtime_call_type if it is reachable from where we
3917 // are now (possibly a temp buffer) and where we might end up
3918 // anywhere in the codeCache then we are always reachable.
3919 // This would have to change if we ever save/restore shared code
3920 // to be more pessimistic.
3921 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
3922 if (!is_simm32(disp)) return false;
3923 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
3924 if (!is_simm32(disp)) return false;
3926 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int));
3928 // Because rip relative is a disp + address_of_next_instruction and we
3929 // don't know the value of address_of_next_instruction we apply a fudge factor
3930 // to make sure we will be ok no matter the size of the instruction we get placed into.
3931 // We don't have to fudge the checks above here because they are already worst case.
3933 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
3934 // + 4 because better safe than sorry.
3935 const int fudge = 12 + 4;
3936 if (disp < 0) {
3937 disp -= fudge;
3938 } else {
3939 disp += fudge;
3940 }
3941 return is_simm32(disp);
3942 }
3944 // Check if the polling page is not reachable from the code cache using rip-relative
3945 // addressing.
3946 bool Assembler::is_polling_page_far() {
3947 intptr_t addr = (intptr_t)os::get_polling_page();
3948 return ForceUnreachable ||
3949 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
3950 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
3951 }
3953 void Assembler::emit_data64(jlong data,
3954 relocInfo::relocType rtype,
3955 int format) {
3956 if (rtype == relocInfo::none) {
3957 emit_long64(data);
3958 } else {
3959 emit_data64(data, Relocation::spec_simple(rtype), format);
3960 }
3961 }
3963 void Assembler::emit_data64(jlong data,
3964 RelocationHolder const& rspec,
3965 int format) {
3966 assert(imm_operand == 0, "default format must be immediate in this file");
3967 assert(imm_operand == format, "must be immediate");
3968 assert(inst_mark() != NULL, "must be inside InstructionMark");
3969 // Do not use AbstractAssembler::relocate, which is not intended for
3970 // embedded words. Instead, relocate to the enclosing instruction.
3971 code_section()->relocate(inst_mark(), rspec, format);
3972 #ifdef ASSERT
3973 check_relocation(rspec, format);
3974 #endif
3975 emit_long64(data);
3976 }
3978 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
3979 if (reg_enc >= 8) {
3980 prefix(REX_B);
3981 reg_enc -= 8;
3982 } else if (byteinst && reg_enc >= 4) {
3983 prefix(REX);
3984 }
3985 return reg_enc;
3986 }
3988 int Assembler::prefixq_and_encode(int reg_enc) {
3989 if (reg_enc < 8) {
3990 prefix(REX_W);
3991 } else {
3992 prefix(REX_WB);
3993 reg_enc -= 8;
3994 }
3995 return reg_enc;
3996 }
3998 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
3999 if (dst_enc < 8) {
4000 if (src_enc >= 8) {
4001 prefix(REX_B);
4002 src_enc -= 8;
4003 } else if (byteinst && src_enc >= 4) {
4004 prefix(REX);
4005 }
4006 } else {
4007 if (src_enc < 8) {
4008 prefix(REX_R);
4009 } else {
4010 prefix(REX_RB);
4011 src_enc -= 8;
4012 }
4013 dst_enc -= 8;
4014 }
4015 return dst_enc << 3 | src_enc;
4016 }
4018 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
4019 if (dst_enc < 8) {
4020 if (src_enc < 8) {
4021 prefix(REX_W);
4022 } else {
4023 prefix(REX_WB);
4024 src_enc -= 8;
4025 }
4026 } else {
4027 if (src_enc < 8) {
4028 prefix(REX_WR);
4029 } else {
4030 prefix(REX_WRB);
4031 src_enc -= 8;
4032 }
4033 dst_enc -= 8;
4034 }
4035 return dst_enc << 3 | src_enc;
4036 }
4038 void Assembler::prefix(Register reg) {
4039 if (reg->encoding() >= 8) {
4040 prefix(REX_B);
4041 }
4042 }
4044 void Assembler::prefix(Address adr) {
4045 if (adr.base_needs_rex()) {
4046 if (adr.index_needs_rex()) {
4047 prefix(REX_XB);
4048 } else {
4049 prefix(REX_B);
4050 }
4051 } else {
4052 if (adr.index_needs_rex()) {
4053 prefix(REX_X);
4054 }
4055 }
4056 }
4058 void Assembler::prefixq(Address adr) {
4059 if (adr.base_needs_rex()) {
4060 if (adr.index_needs_rex()) {
4061 prefix(REX_WXB);
4062 } else {
4063 prefix(REX_WB);
4064 }
4065 } else {
4066 if (adr.index_needs_rex()) {
4067 prefix(REX_WX);
4068 } else {
4069 prefix(REX_W);
4070 }
4071 }
4072 }
4075 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
4076 if (reg->encoding() < 8) {
4077 if (adr.base_needs_rex()) {
4078 if (adr.index_needs_rex()) {
4079 prefix(REX_XB);
4080 } else {
4081 prefix(REX_B);
4082 }
4083 } else {
4084 if (adr.index_needs_rex()) {
4085 prefix(REX_X);
4086 } else if (byteinst && reg->encoding() >= 4 ) {
4087 prefix(REX);
4088 }
4089 }
4090 } else {
4091 if (adr.base_needs_rex()) {
4092 if (adr.index_needs_rex()) {
4093 prefix(REX_RXB);
4094 } else {
4095 prefix(REX_RB);
4096 }
4097 } else {
4098 if (adr.index_needs_rex()) {
4099 prefix(REX_RX);
4100 } else {
4101 prefix(REX_R);
4102 }
4103 }
4104 }
4105 }
4107 void Assembler::prefixq(Address adr, Register src) {
4108 if (src->encoding() < 8) {
4109 if (adr.base_needs_rex()) {
4110 if (adr.index_needs_rex()) {
4111 prefix(REX_WXB);
4112 } else {
4113 prefix(REX_WB);
4114 }
4115 } else {
4116 if (adr.index_needs_rex()) {
4117 prefix(REX_WX);
4118 } else {
4119 prefix(REX_W);
4120 }
4121 }
4122 } else {
4123 if (adr.base_needs_rex()) {
4124 if (adr.index_needs_rex()) {
4125 prefix(REX_WRXB);
4126 } else {
4127 prefix(REX_WRB);
4128 }
4129 } else {
4130 if (adr.index_needs_rex()) {
4131 prefix(REX_WRX);
4132 } else {
4133 prefix(REX_WR);
4134 }
4135 }
4136 }
4137 }
4139 void Assembler::prefix(Address adr, XMMRegister reg) {
4140 if (reg->encoding() < 8) {
4141 if (adr.base_needs_rex()) {
4142 if (adr.index_needs_rex()) {
4143 prefix(REX_XB);
4144 } else {
4145 prefix(REX_B);
4146 }
4147 } else {
4148 if (adr.index_needs_rex()) {
4149 prefix(REX_X);
4150 }
4151 }
4152 } else {
4153 if (adr.base_needs_rex()) {
4154 if (adr.index_needs_rex()) {
4155 prefix(REX_RXB);
4156 } else {
4157 prefix(REX_RB);
4158 }
4159 } else {
4160 if (adr.index_needs_rex()) {
4161 prefix(REX_RX);
4162 } else {
4163 prefix(REX_R);
4164 }
4165 }
4166 }
4167 }
4169 void Assembler::prefixq(Address adr, XMMRegister src) {
4170 if (src->encoding() < 8) {
4171 if (adr.base_needs_rex()) {
4172 if (adr.index_needs_rex()) {
4173 prefix(REX_WXB);
4174 } else {
4175 prefix(REX_WB);
4176 }
4177 } else {
4178 if (adr.index_needs_rex()) {
4179 prefix(REX_WX);
4180 } else {
4181 prefix(REX_W);
4182 }
4183 }
4184 } else {
4185 if (adr.base_needs_rex()) {
4186 if (adr.index_needs_rex()) {
4187 prefix(REX_WRXB);
4188 } else {
4189 prefix(REX_WRB);
4190 }
4191 } else {
4192 if (adr.index_needs_rex()) {
4193 prefix(REX_WRX);
4194 } else {
4195 prefix(REX_WR);
4196 }
4197 }
4198 }
4199 }
4201 void Assembler::adcq(Register dst, int32_t imm32) {
4202 (void) prefixq_and_encode(dst->encoding());
4203 emit_arith(0x81, 0xD0, dst, imm32);
4204 }
4206 void Assembler::adcq(Register dst, Address src) {
4207 InstructionMark im(this);
4208 prefixq(src, dst);
4209 emit_byte(0x13);
4210 emit_operand(dst, src);
4211 }
4213 void Assembler::adcq(Register dst, Register src) {
4214 (int) prefixq_and_encode(dst->encoding(), src->encoding());
4215 emit_arith(0x13, 0xC0, dst, src);
4216 }
4218 void Assembler::addq(Address dst, int32_t imm32) {
4219 InstructionMark im(this);
4220 prefixq(dst);
4221 emit_arith_operand(0x81, rax, dst,imm32);
4222 }
4224 void Assembler::addq(Address dst, Register src) {
4225 InstructionMark im(this);
4226 prefixq(dst, src);
4227 emit_byte(0x01);
4228 emit_operand(src, dst);
4229 }
4231 void Assembler::addq(Register dst, int32_t imm32) {
4232 (void) prefixq_and_encode(dst->encoding());
4233 emit_arith(0x81, 0xC0, dst, imm32);
4234 }
4236 void Assembler::addq(Register dst, Address src) {
4237 InstructionMark im(this);
4238 prefixq(src, dst);
4239 emit_byte(0x03);
4240 emit_operand(dst, src);
4241 }
4243 void Assembler::addq(Register dst, Register src) {
4244 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4245 emit_arith(0x03, 0xC0, dst, src);
4246 }
4248 void Assembler::andq(Address dst, int32_t imm32) {
4249 InstructionMark im(this);
4250 prefixq(dst);
4251 emit_byte(0x81);
4252 emit_operand(rsp, dst, 4);
4253 emit_long(imm32);
4254 }
4256 void Assembler::andq(Register dst, int32_t imm32) {
4257 (void) prefixq_and_encode(dst->encoding());
4258 emit_arith(0x81, 0xE0, dst, imm32);
4259 }
4261 void Assembler::andq(Register dst, Address src) {
4262 InstructionMark im(this);
4263 prefixq(src, dst);
4264 emit_byte(0x23);
4265 emit_operand(dst, src);
4266 }
4268 void Assembler::andq(Register dst, Register src) {
4269 (int) prefixq_and_encode(dst->encoding(), src->encoding());
4270 emit_arith(0x23, 0xC0, dst, src);
4271 }
4273 void Assembler::bsfq(Register dst, Register src) {
4274 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4275 emit_byte(0x0F);
4276 emit_byte(0xBC);
4277 emit_byte(0xC0 | encode);
4278 }
4280 void Assembler::bsrq(Register dst, Register src) {
4281 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
4282 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4283 emit_byte(0x0F);
4284 emit_byte(0xBD);
4285 emit_byte(0xC0 | encode);
4286 }
4288 void Assembler::bswapq(Register reg) {
4289 int encode = prefixq_and_encode(reg->encoding());
4290 emit_byte(0x0F);
4291 emit_byte(0xC8 | encode);
4292 }
4294 void Assembler::cdqq() {
4295 prefix(REX_W);
4296 emit_byte(0x99);
4297 }
4299 void Assembler::clflush(Address adr) {
4300 prefix(adr);
4301 emit_byte(0x0F);
4302 emit_byte(0xAE);
4303 emit_operand(rdi, adr);
4304 }
4306 void Assembler::cmovq(Condition cc, Register dst, Register src) {
4307 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4308 emit_byte(0x0F);
4309 emit_byte(0x40 | cc);
4310 emit_byte(0xC0 | encode);
4311 }
4313 void Assembler::cmovq(Condition cc, Register dst, Address src) {
4314 InstructionMark im(this);
4315 prefixq(src, dst);
4316 emit_byte(0x0F);
4317 emit_byte(0x40 | cc);
4318 emit_operand(dst, src);
4319 }
4321 void Assembler::cmpq(Address dst, int32_t imm32) {
4322 InstructionMark im(this);
4323 prefixq(dst);
4324 emit_byte(0x81);
4325 emit_operand(rdi, dst, 4);
4326 emit_long(imm32);
4327 }
4329 void Assembler::cmpq(Register dst, int32_t imm32) {
4330 (void) prefixq_and_encode(dst->encoding());
4331 emit_arith(0x81, 0xF8, dst, imm32);
4332 }
4334 void Assembler::cmpq(Address dst, Register src) {
4335 InstructionMark im(this);
4336 prefixq(dst, src);
4337 emit_byte(0x3B);
4338 emit_operand(src, dst);
4339 }
4341 void Assembler::cmpq(Register dst, Register src) {
4342 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4343 emit_arith(0x3B, 0xC0, dst, src);
4344 }
4346 void Assembler::cmpq(Register dst, Address src) {
4347 InstructionMark im(this);
4348 prefixq(src, dst);
4349 emit_byte(0x3B);
4350 emit_operand(dst, src);
4351 }
4353 void Assembler::cmpxchgq(Register reg, Address adr) {
4354 InstructionMark im(this);
4355 prefixq(adr, reg);
4356 emit_byte(0x0F);
4357 emit_byte(0xB1);
4358 emit_operand(reg, adr);
4359 }
4361 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
4362 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4363 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2);
4364 emit_byte(0x2A);
4365 emit_byte(0xC0 | encode);
4366 }
4368 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
4369 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4370 InstructionMark im(this);
4371 simd_prefix_q(dst, dst, src, VEX_SIMD_F2);
4372 emit_byte(0x2A);
4373 emit_operand(dst, src);
4374 }
4376 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
4377 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4378 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3);
4379 emit_byte(0x2A);
4380 emit_byte(0xC0 | encode);
4381 }
4383 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
4384 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4385 InstructionMark im(this);
4386 simd_prefix_q(dst, dst, src, VEX_SIMD_F3);
4387 emit_byte(0x2A);
4388 emit_operand(dst, src);
4389 }
4391 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
4392 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4393 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2);
4394 emit_byte(0x2C);
4395 emit_byte(0xC0 | encode);
4396 }
4398 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
4399 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4400 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3);
4401 emit_byte(0x2C);
4402 emit_byte(0xC0 | encode);
4403 }
4405 void Assembler::decl(Register dst) {
4406 // Don't use it directly. Use MacroAssembler::decrementl() instead.
4407 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
4408 int encode = prefix_and_encode(dst->encoding());
4409 emit_byte(0xFF);
4410 emit_byte(0xC8 | encode);
4411 }
4413 void Assembler::decq(Register dst) {
4414 // Don't use it directly. Use MacroAssembler::decrementq() instead.
4415 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4416 int encode = prefixq_and_encode(dst->encoding());
4417 emit_byte(0xFF);
4418 emit_byte(0xC8 | encode);
4419 }
4421 void Assembler::decq(Address dst) {
4422 // Don't use it directly. Use MacroAssembler::decrementq() instead.
4423 InstructionMark im(this);
4424 prefixq(dst);
4425 emit_byte(0xFF);
4426 emit_operand(rcx, dst);
4427 }
4429 void Assembler::fxrstor(Address src) {
4430 prefixq(src);
4431 emit_byte(0x0F);
4432 emit_byte(0xAE);
4433 emit_operand(as_Register(1), src);
4434 }
4436 void Assembler::fxsave(Address dst) {
4437 prefixq(dst);
4438 emit_byte(0x0F);
4439 emit_byte(0xAE);
4440 emit_operand(as_Register(0), dst);
4441 }
4443 void Assembler::idivq(Register src) {
4444 int encode = prefixq_and_encode(src->encoding());
4445 emit_byte(0xF7);
4446 emit_byte(0xF8 | encode);
4447 }
4449 void Assembler::imulq(Register dst, Register src) {
4450 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4451 emit_byte(0x0F);
4452 emit_byte(0xAF);
4453 emit_byte(0xC0 | encode);
4454 }
4456 void Assembler::imulq(Register dst, Register src, int value) {
4457 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4458 if (is8bit(value)) {
4459 emit_byte(0x6B);
4460 emit_byte(0xC0 | encode);
4461 emit_byte(value & 0xFF);
4462 } else {
4463 emit_byte(0x69);
4464 emit_byte(0xC0 | encode);
4465 emit_long(value);
4466 }
4467 }
4469 void Assembler::incl(Register dst) {
4470 // Don't use it directly. Use MacroAssembler::incrementl() instead.
4471 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4472 int encode = prefix_and_encode(dst->encoding());
4473 emit_byte(0xFF);
4474 emit_byte(0xC0 | encode);
4475 }
4477 void Assembler::incq(Register dst) {
4478 // Don't use it directly. Use MacroAssembler::incrementq() instead.
4479 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4480 int encode = prefixq_and_encode(dst->encoding());
4481 emit_byte(0xFF);
4482 emit_byte(0xC0 | encode);
4483 }
4485 void Assembler::incq(Address dst) {
4486 // Don't use it directly. Use MacroAssembler::incrementq() instead.
4487 InstructionMark im(this);
4488 prefixq(dst);
4489 emit_byte(0xFF);
4490 emit_operand(rax, dst);
4491 }
4493 void Assembler::lea(Register dst, Address src) {
4494 leaq(dst, src);
4495 }
4497 void Assembler::leaq(Register dst, Address src) {
4498 InstructionMark im(this);
4499 prefixq(src, dst);
4500 emit_byte(0x8D);
4501 emit_operand(dst, src);
4502 }
4504 void Assembler::mov64(Register dst, int64_t imm64) {
4505 InstructionMark im(this);
4506 int encode = prefixq_and_encode(dst->encoding());
4507 emit_byte(0xB8 | encode);
4508 emit_long64(imm64);
4509 }
4511 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
4512 InstructionMark im(this);
4513 int encode = prefixq_and_encode(dst->encoding());
4514 emit_byte(0xB8 | encode);
4515 emit_data64(imm64, rspec);
4516 }
4518 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
4519 InstructionMark im(this);
4520 int encode = prefix_and_encode(dst->encoding());
4521 emit_byte(0xB8 | encode);
4522 emit_data((int)imm32, rspec, narrow_oop_operand);
4523 }
4525 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
4526 InstructionMark im(this);
4527 prefix(dst);
4528 emit_byte(0xC7);
4529 emit_operand(rax, dst, 4);
4530 emit_data((int)imm32, rspec, narrow_oop_operand);
4531 }
4533 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
4534 InstructionMark im(this);
4535 int encode = prefix_and_encode(src1->encoding());
4536 emit_byte(0x81);
4537 emit_byte(0xF8 | encode);
4538 emit_data((int)imm32, rspec, narrow_oop_operand);
4539 }
4541 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
4542 InstructionMark im(this);
4543 prefix(src1);
4544 emit_byte(0x81);
4545 emit_operand(rax, src1, 4);
4546 emit_data((int)imm32, rspec, narrow_oop_operand);
4547 }
4549 void Assembler::lzcntq(Register dst, Register src) {
4550 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
4551 emit_byte(0xF3);
4552 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4553 emit_byte(0x0F);
4554 emit_byte(0xBD);
4555 emit_byte(0xC0 | encode);
4556 }
4558 void Assembler::movdq(XMMRegister dst, Register src) {
4559 // table D-1 says MMX/SSE2
4560 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4561 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66);
4562 emit_byte(0x6E);
4563 emit_byte(0xC0 | encode);
4564 }
4566 void Assembler::movdq(Register dst, XMMRegister src) {
4567 // table D-1 says MMX/SSE2
4568 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4569 // swap src/dst to get correct prefix
4570 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66);
4571 emit_byte(0x7E);
4572 emit_byte(0xC0 | encode);
4573 }
4575 void Assembler::movq(Register dst, Register src) {
4576 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4577 emit_byte(0x8B);
4578 emit_byte(0xC0 | encode);
4579 }
4581 void Assembler::movq(Register dst, Address src) {
4582 InstructionMark im(this);
4583 prefixq(src, dst);
4584 emit_byte(0x8B);
4585 emit_operand(dst, src);
4586 }
4588 void Assembler::movq(Address dst, Register src) {
4589 InstructionMark im(this);
4590 prefixq(dst, src);
4591 emit_byte(0x89);
4592 emit_operand(src, dst);
4593 }
4595 void Assembler::movsbq(Register dst, Address src) {
4596 InstructionMark im(this);
4597 prefixq(src, dst);
4598 emit_byte(0x0F);
4599 emit_byte(0xBE);
4600 emit_operand(dst, src);
4601 }
4603 void Assembler::movsbq(Register dst, Register src) {
4604 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4605 emit_byte(0x0F);
4606 emit_byte(0xBE);
4607 emit_byte(0xC0 | encode);
4608 }
4610 void Assembler::movslq(Register dst, int32_t imm32) {
4611 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
4612 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
4613 // as a result we shouldn't use until tested at runtime...
4614 ShouldNotReachHere();
4615 InstructionMark im(this);
4616 int encode = prefixq_and_encode(dst->encoding());
4617 emit_byte(0xC7 | encode);
4618 emit_long(imm32);
4619 }
4621 void Assembler::movslq(Address dst, int32_t imm32) {
4622 assert(is_simm32(imm32), "lost bits");
4623 InstructionMark im(this);
4624 prefixq(dst);
4625 emit_byte(0xC7);
4626 emit_operand(rax, dst, 4);
4627 emit_long(imm32);
4628 }
4630 void Assembler::movslq(Register dst, Address src) {
4631 InstructionMark im(this);
4632 prefixq(src, dst);
4633 emit_byte(0x63);
4634 emit_operand(dst, src);
4635 }
4637 void Assembler::movslq(Register dst, Register src) {
4638 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4639 emit_byte(0x63);
4640 emit_byte(0xC0 | encode);
4641 }
4643 void Assembler::movswq(Register dst, Address src) {
4644 InstructionMark im(this);
4645 prefixq(src, dst);
4646 emit_byte(0x0F);
4647 emit_byte(0xBF);
4648 emit_operand(dst, src);
4649 }
4651 void Assembler::movswq(Register dst, Register src) {
4652 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4653 emit_byte(0x0F);
4654 emit_byte(0xBF);
4655 emit_byte(0xC0 | encode);
4656 }
4658 void Assembler::movzbq(Register dst, Address src) {
4659 InstructionMark im(this);
4660 prefixq(src, dst);
4661 emit_byte(0x0F);
4662 emit_byte(0xB6);
4663 emit_operand(dst, src);
4664 }
4666 void Assembler::movzbq(Register dst, Register src) {
4667 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4668 emit_byte(0x0F);
4669 emit_byte(0xB6);
4670 emit_byte(0xC0 | encode);
4671 }
4673 void Assembler::movzwq(Register dst, Address src) {
4674 InstructionMark im(this);
4675 prefixq(src, dst);
4676 emit_byte(0x0F);
4677 emit_byte(0xB7);
4678 emit_operand(dst, src);
4679 }
4681 void Assembler::movzwq(Register dst, Register src) {
4682 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4683 emit_byte(0x0F);
4684 emit_byte(0xB7);
4685 emit_byte(0xC0 | encode);
4686 }
4688 void Assembler::negq(Register dst) {
4689 int encode = prefixq_and_encode(dst->encoding());
4690 emit_byte(0xF7);
4691 emit_byte(0xD8 | encode);
4692 }
4694 void Assembler::notq(Register dst) {
4695 int encode = prefixq_and_encode(dst->encoding());
4696 emit_byte(0xF7);
4697 emit_byte(0xD0 | encode);
4698 }
4700 void Assembler::orq(Address dst, int32_t imm32) {
4701 InstructionMark im(this);
4702 prefixq(dst);
4703 emit_byte(0x81);
4704 emit_operand(rcx, dst, 4);
4705 emit_long(imm32);
4706 }
4708 void Assembler::orq(Register dst, int32_t imm32) {
4709 (void) prefixq_and_encode(dst->encoding());
4710 emit_arith(0x81, 0xC8, dst, imm32);
4711 }
4713 void Assembler::orq(Register dst, Address src) {
4714 InstructionMark im(this);
4715 prefixq(src, dst);
4716 emit_byte(0x0B);
4717 emit_operand(dst, src);
4718 }
4720 void Assembler::orq(Register dst, Register src) {
4721 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4722 emit_arith(0x0B, 0xC0, dst, src);
4723 }
4725 void Assembler::popa() { // 64bit
4726 movq(r15, Address(rsp, 0));
4727 movq(r14, Address(rsp, wordSize));
4728 movq(r13, Address(rsp, 2 * wordSize));
4729 movq(r12, Address(rsp, 3 * wordSize));
4730 movq(r11, Address(rsp, 4 * wordSize));
4731 movq(r10, Address(rsp, 5 * wordSize));
4732 movq(r9, Address(rsp, 6 * wordSize));
4733 movq(r8, Address(rsp, 7 * wordSize));
4734 movq(rdi, Address(rsp, 8 * wordSize));
4735 movq(rsi, Address(rsp, 9 * wordSize));
4736 movq(rbp, Address(rsp, 10 * wordSize));
4737 // skip rsp
4738 movq(rbx, Address(rsp, 12 * wordSize));
4739 movq(rdx, Address(rsp, 13 * wordSize));
4740 movq(rcx, Address(rsp, 14 * wordSize));
4741 movq(rax, Address(rsp, 15 * wordSize));
4743 addq(rsp, 16 * wordSize);
4744 }
4746 void Assembler::popcntq(Register dst, Address src) {
4747 assert(VM_Version::supports_popcnt(), "must support");
4748 InstructionMark im(this);
4749 emit_byte(0xF3);
4750 prefixq(src, dst);
4751 emit_byte(0x0F);
4752 emit_byte(0xB8);
4753 emit_operand(dst, src);
4754 }
4756 void Assembler::popcntq(Register dst, Register src) {
4757 assert(VM_Version::supports_popcnt(), "must support");
4758 emit_byte(0xF3);
4759 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4760 emit_byte(0x0F);
4761 emit_byte(0xB8);
4762 emit_byte(0xC0 | encode);
4763 }
4765 void Assembler::popq(Address dst) {
4766 InstructionMark im(this);
4767 prefixq(dst);
4768 emit_byte(0x8F);
4769 emit_operand(rax, dst);
4770 }
4772 void Assembler::pusha() { // 64bit
4773 // we have to store original rsp. ABI says that 128 bytes
4774 // below rsp are local scratch.
4775 movq(Address(rsp, -5 * wordSize), rsp);
4777 subq(rsp, 16 * wordSize);
4779 movq(Address(rsp, 15 * wordSize), rax);
4780 movq(Address(rsp, 14 * wordSize), rcx);
4781 movq(Address(rsp, 13 * wordSize), rdx);
4782 movq(Address(rsp, 12 * wordSize), rbx);
4783 // skip rsp
4784 movq(Address(rsp, 10 * wordSize), rbp);
4785 movq(Address(rsp, 9 * wordSize), rsi);
4786 movq(Address(rsp, 8 * wordSize), rdi);
4787 movq(Address(rsp, 7 * wordSize), r8);
4788 movq(Address(rsp, 6 * wordSize), r9);
4789 movq(Address(rsp, 5 * wordSize), r10);
4790 movq(Address(rsp, 4 * wordSize), r11);
4791 movq(Address(rsp, 3 * wordSize), r12);
4792 movq(Address(rsp, 2 * wordSize), r13);
4793 movq(Address(rsp, wordSize), r14);
4794 movq(Address(rsp, 0), r15);
4795 }
4797 void Assembler::pushq(Address src) {
4798 InstructionMark im(this);
4799 prefixq(src);
4800 emit_byte(0xFF);
4801 emit_operand(rsi, src);
4802 }
4804 void Assembler::rclq(Register dst, int imm8) {
4805 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4806 int encode = prefixq_and_encode(dst->encoding());
4807 if (imm8 == 1) {
4808 emit_byte(0xD1);
4809 emit_byte(0xD0 | encode);
4810 } else {
4811 emit_byte(0xC1);
4812 emit_byte(0xD0 | encode);
4813 emit_byte(imm8);
4814 }
4815 }
4816 void Assembler::sarq(Register dst, int imm8) {
4817 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4818 int encode = prefixq_and_encode(dst->encoding());
4819 if (imm8 == 1) {
4820 emit_byte(0xD1);
4821 emit_byte(0xF8 | encode);
4822 } else {
4823 emit_byte(0xC1);
4824 emit_byte(0xF8 | encode);
4825 emit_byte(imm8);
4826 }
4827 }
4829 void Assembler::sarq(Register dst) {
4830 int encode = prefixq_and_encode(dst->encoding());
4831 emit_byte(0xD3);
4832 emit_byte(0xF8 | encode);
4833 }
4835 void Assembler::sbbq(Address dst, int32_t imm32) {
4836 InstructionMark im(this);
4837 prefixq(dst);
4838 emit_arith_operand(0x81, rbx, dst, imm32);
4839 }
4841 void Assembler::sbbq(Register dst, int32_t imm32) {
4842 (void) prefixq_and_encode(dst->encoding());
4843 emit_arith(0x81, 0xD8, dst, imm32);
4844 }
4846 void Assembler::sbbq(Register dst, Address src) {
4847 InstructionMark im(this);
4848 prefixq(src, dst);
4849 emit_byte(0x1B);
4850 emit_operand(dst, src);
4851 }
4853 void Assembler::sbbq(Register dst, Register src) {
4854 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4855 emit_arith(0x1B, 0xC0, dst, src);
4856 }
4858 void Assembler::shlq(Register dst, int imm8) {
4859 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4860 int encode = prefixq_and_encode(dst->encoding());
4861 if (imm8 == 1) {
4862 emit_byte(0xD1);
4863 emit_byte(0xE0 | encode);
4864 } else {
4865 emit_byte(0xC1);
4866 emit_byte(0xE0 | encode);
4867 emit_byte(imm8);
4868 }
4869 }
4871 void Assembler::shlq(Register dst) {
4872 int encode = prefixq_and_encode(dst->encoding());
4873 emit_byte(0xD3);
4874 emit_byte(0xE0 | encode);
4875 }
4877 void Assembler::shrq(Register dst, int imm8) {
4878 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4879 int encode = prefixq_and_encode(dst->encoding());
4880 emit_byte(0xC1);
4881 emit_byte(0xE8 | encode);
4882 emit_byte(imm8);
4883 }
4885 void Assembler::shrq(Register dst) {
4886 int encode = prefixq_and_encode(dst->encoding());
4887 emit_byte(0xD3);
4888 emit_byte(0xE8 | encode);
4889 }
4891 void Assembler::subq(Address dst, int32_t imm32) {
4892 InstructionMark im(this);
4893 prefixq(dst);
4894 emit_arith_operand(0x81, rbp, dst, imm32);
4895 }
4897 void Assembler::subq(Address dst, Register src) {
4898 InstructionMark im(this);
4899 prefixq(dst, src);
4900 emit_byte(0x29);
4901 emit_operand(src, dst);
4902 }
4904 void Assembler::subq(Register dst, int32_t imm32) {
4905 (void) prefixq_and_encode(dst->encoding());
4906 emit_arith(0x81, 0xE8, dst, imm32);
4907 }
4909 // Force generation of a 4 byte immediate value even if it fits into 8bit
4910 void Assembler::subq_imm32(Register dst, int32_t imm32) {
4911 (void) prefixq_and_encode(dst->encoding());
4912 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4913 }
4915 void Assembler::subq(Register dst, Address src) {
4916 InstructionMark im(this);
4917 prefixq(src, dst);
4918 emit_byte(0x2B);
4919 emit_operand(dst, src);
4920 }
4922 void Assembler::subq(Register dst, Register src) {
4923 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4924 emit_arith(0x2B, 0xC0, dst, src);
4925 }
4927 void Assembler::testq(Register dst, int32_t imm32) {
4928 // not using emit_arith because test
4929 // doesn't support sign-extension of
4930 // 8bit operands
4931 int encode = dst->encoding();
4932 if (encode == 0) {
4933 prefix(REX_W);
4934 emit_byte(0xA9);
4935 } else {
4936 encode = prefixq_and_encode(encode);
4937 emit_byte(0xF7);
4938 emit_byte(0xC0 | encode);
4939 }
4940 emit_long(imm32);
4941 }
4943 void Assembler::testq(Register dst, Register src) {
4944 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4945 emit_arith(0x85, 0xC0, dst, src);
4946 }
4948 void Assembler::xaddq(Address dst, Register src) {
4949 InstructionMark im(this);
4950 prefixq(dst, src);
4951 emit_byte(0x0F);
4952 emit_byte(0xC1);
4953 emit_operand(src, dst);
4954 }
4956 void Assembler::xchgq(Register dst, Address src) {
4957 InstructionMark im(this);
4958 prefixq(src, dst);
4959 emit_byte(0x87);
4960 emit_operand(dst, src);
4961 }
4963 void Assembler::xchgq(Register dst, Register src) {
4964 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4965 emit_byte(0x87);
4966 emit_byte(0xc0 | encode);
4967 }
4969 void Assembler::xorq(Register dst, Register src) {
4970 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4971 emit_arith(0x33, 0xC0, dst, src);
4972 }
4974 void Assembler::xorq(Register dst, Address src) {
4975 InstructionMark im(this);
4976 prefixq(src, dst);
4977 emit_byte(0x33);
4978 emit_operand(dst, src);
4979 }
4981 #endif // !LP64
4983 static Assembler::Condition reverse[] = {
4984 Assembler::noOverflow /* overflow = 0x0 */ ,
4985 Assembler::overflow /* noOverflow = 0x1 */ ,
4986 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
4987 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
4988 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
4989 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
4990 Assembler::above /* belowEqual = 0x6 */ ,
4991 Assembler::belowEqual /* above = 0x7 */ ,
4992 Assembler::positive /* negative = 0x8 */ ,
4993 Assembler::negative /* positive = 0x9 */ ,
4994 Assembler::noParity /* parity = 0xa */ ,
4995 Assembler::parity /* noParity = 0xb */ ,
4996 Assembler::greaterEqual /* less = 0xc */ ,
4997 Assembler::less /* greaterEqual = 0xd */ ,
4998 Assembler::greater /* lessEqual = 0xe */ ,
4999 Assembler::lessEqual /* greater = 0xf, */
5001 };
5004 // Implementation of MacroAssembler
5006 // First all the versions that have distinct versions depending on 32/64 bit
5007 // Unless the difference is trivial (1 line or so).
5009 #ifndef _LP64
5011 // 32bit versions
5013 Address MacroAssembler::as_Address(AddressLiteral adr) {
5014 return Address(adr.target(), adr.rspec());
5015 }
5017 Address MacroAssembler::as_Address(ArrayAddress adr) {
5018 return Address::make_array(adr);
5019 }
5021 int MacroAssembler::biased_locking_enter(Register lock_reg,
5022 Register obj_reg,
5023 Register swap_reg,
5024 Register tmp_reg,
5025 bool swap_reg_contains_mark,
5026 Label& done,
5027 Label* slow_case,
5028 BiasedLockingCounters* counters) {
5029 assert(UseBiasedLocking, "why call this otherwise?");
5030 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg");
5031 assert_different_registers(lock_reg, obj_reg, swap_reg);
5033 if (PrintBiasedLockingStatistics && counters == NULL)
5034 counters = BiasedLocking::counters();
5036 bool need_tmp_reg = false;
5037 if (tmp_reg == noreg) {
5038 need_tmp_reg = true;
5039 tmp_reg = lock_reg;
5040 } else {
5041 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
5042 }
5043 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
5044 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
5045 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
5046 Address saved_mark_addr(lock_reg, 0);
5048 // Biased locking
5049 // See whether the lock is currently biased toward our thread and
5050 // whether the epoch is still valid
5051 // Note that the runtime guarantees sufficient alignment of JavaThread
5052 // pointers to allow age to be placed into low bits
5053 // First check to see whether biasing is even enabled for this object
5054 Label cas_label;
5055 int null_check_offset = -1;
5056 if (!swap_reg_contains_mark) {
5057 null_check_offset = offset();
5058 movl(swap_reg, mark_addr);
5059 }
5060 if (need_tmp_reg) {
5061 push(tmp_reg);
5062 }
5063 movl(tmp_reg, swap_reg);
5064 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place);
5065 cmpl(tmp_reg, markOopDesc::biased_lock_pattern);
5066 if (need_tmp_reg) {
5067 pop(tmp_reg);
5068 }
5069 jcc(Assembler::notEqual, cas_label);
5070 // The bias pattern is present in the object's header. Need to check
5071 // whether the bias owner and the epoch are both still current.
5072 // Note that because there is no current thread register on x86 we
5073 // need to store off the mark word we read out of the object to
5074 // avoid reloading it and needing to recheck invariants below. This
5075 // store is unfortunate but it makes the overall code shorter and
5076 // simpler.
5077 movl(saved_mark_addr, swap_reg);
5078 if (need_tmp_reg) {
5079 push(tmp_reg);
5080 }
5081 get_thread(tmp_reg);
5082 xorl(swap_reg, tmp_reg);
5083 if (swap_reg_contains_mark) {
5084 null_check_offset = offset();
5085 }
5086 movl(tmp_reg, klass_addr);
5087 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset()));
5088 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place));
5089 if (need_tmp_reg) {
5090 pop(tmp_reg);
5091 }
5092 if (counters != NULL) {
5093 cond_inc32(Assembler::zero,
5094 ExternalAddress((address)counters->biased_lock_entry_count_addr()));
5095 }
5096 jcc(Assembler::equal, done);
5098 Label try_revoke_bias;
5099 Label try_rebias;
5101 // At this point we know that the header has the bias pattern and
5102 // that we are not the bias owner in the current epoch. We need to
5103 // figure out more details about the state of the header in order to
5104 // know what operations can be legally performed on the object's
5105 // header.
5107 // If the low three bits in the xor result aren't clear, that means
5108 // the prototype header is no longer biased and we have to revoke
5109 // the bias on this object.
5110 testl(swap_reg, markOopDesc::biased_lock_mask_in_place);
5111 jcc(Assembler::notZero, try_revoke_bias);
5113 // Biasing is still enabled for this data type. See whether the
5114 // epoch of the current bias is still valid, meaning that the epoch
5115 // bits of the mark word are equal to the epoch bits of the
5116 // prototype header. (Note that the prototype header's epoch bits
5117 // only change at a safepoint.) If not, attempt to rebias the object
5118 // toward the current thread. Note that we must be absolutely sure
5119 // that the current epoch is invalid in order to do this because
5120 // otherwise the manipulations it performs on the mark word are
5121 // illegal.
5122 testl(swap_reg, markOopDesc::epoch_mask_in_place);
5123 jcc(Assembler::notZero, try_rebias);
5125 // The epoch of the current bias is still valid but we know nothing
5126 // about the owner; it might be set or it might be clear. Try to
5127 // acquire the bias of the object using an atomic operation. If this
5128 // fails we will go in to the runtime to revoke the object's bias.
5129 // Note that we first construct the presumed unbiased header so we
5130 // don't accidentally blow away another thread's valid bias.
5131 movl(swap_reg, saved_mark_addr);
5132 andl(swap_reg,
5133 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
5134 if (need_tmp_reg) {
5135 push(tmp_reg);
5136 }
5137 get_thread(tmp_reg);
5138 orl(tmp_reg, swap_reg);
5139 if (os::is_MP()) {
5140 lock();
5141 }
5142 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
5143 if (need_tmp_reg) {
5144 pop(tmp_reg);
5145 }
5146 // If the biasing toward our thread failed, this means that
5147 // another thread succeeded in biasing it toward itself and we
5148 // need to revoke that bias. The revocation will occur in the
5149 // interpreter runtime in the slow case.
5150 if (counters != NULL) {
5151 cond_inc32(Assembler::zero,
5152 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr()));
5153 }
5154 if (slow_case != NULL) {
5155 jcc(Assembler::notZero, *slow_case);
5156 }
5157 jmp(done);
5159 bind(try_rebias);
5160 // At this point we know the epoch has expired, meaning that the
5161 // current "bias owner", if any, is actually invalid. Under these
5162 // circumstances _only_, we are allowed to use the current header's
5163 // value as the comparison value when doing the cas to acquire the
5164 // bias in the current epoch. In other words, we allow transfer of
5165 // the bias from one thread to another directly in this situation.
5166 //
5167 // FIXME: due to a lack of registers we currently blow away the age
5168 // bits in this situation. Should attempt to preserve them.
5169 if (need_tmp_reg) {
5170 push(tmp_reg);
5171 }
5172 get_thread(tmp_reg);
5173 movl(swap_reg, klass_addr);
5174 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset()));
5175 movl(swap_reg, saved_mark_addr);
5176 if (os::is_MP()) {
5177 lock();
5178 }
5179 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
5180 if (need_tmp_reg) {
5181 pop(tmp_reg);
5182 }
5183 // If the biasing toward our thread failed, then another thread
5184 // succeeded in biasing it toward itself and we need to revoke that
5185 // bias. The revocation will occur in the runtime in the slow case.
5186 if (counters != NULL) {
5187 cond_inc32(Assembler::zero,
5188 ExternalAddress((address)counters->rebiased_lock_entry_count_addr()));
5189 }
5190 if (slow_case != NULL) {
5191 jcc(Assembler::notZero, *slow_case);
5192 }
5193 jmp(done);
5195 bind(try_revoke_bias);
5196 // The prototype mark in the klass doesn't have the bias bit set any
5197 // more, indicating that objects of this data type are not supposed
5198 // to be biased any more. We are going to try to reset the mark of
5199 // this object to the prototype value and fall through to the
5200 // CAS-based locking scheme. Note that if our CAS fails, it means
5201 // that another thread raced us for the privilege of revoking the
5202 // bias of this particular object, so it's okay to continue in the
5203 // normal locking code.
5204 //
5205 // FIXME: due to a lack of registers we currently blow away the age
5206 // bits in this situation. Should attempt to preserve them.
5207 movl(swap_reg, saved_mark_addr);
5208 if (need_tmp_reg) {
5209 push(tmp_reg);
5210 }
5211 movl(tmp_reg, klass_addr);
5212 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset()));
5213 if (os::is_MP()) {
5214 lock();
5215 }
5216 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
5217 if (need_tmp_reg) {
5218 pop(tmp_reg);
5219 }
5220 // Fall through to the normal CAS-based lock, because no matter what
5221 // the result of the above CAS, some thread must have succeeded in
5222 // removing the bias bit from the object's header.
5223 if (counters != NULL) {
5224 cond_inc32(Assembler::zero,
5225 ExternalAddress((address)counters->revoked_lock_entry_count_addr()));
5226 }
5228 bind(cas_label);
5230 return null_check_offset;
5231 }
5232 void MacroAssembler::call_VM_leaf_base(address entry_point,
5233 int number_of_arguments) {
5234 call(RuntimeAddress(entry_point));
5235 increment(rsp, number_of_arguments * wordSize);
5236 }
5238 void MacroAssembler::cmpoop(Address src1, jobject obj) {
5239 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
5240 }
5242 void MacroAssembler::cmpoop(Register src1, jobject obj) {
5243 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
5244 }
5246 void MacroAssembler::extend_sign(Register hi, Register lo) {
5247 // According to Intel Doc. AP-526, "Integer Divide", p.18.
5248 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
5249 cdql();
5250 } else {
5251 movl(hi, lo);
5252 sarl(hi, 31);
5253 }
5254 }
5256 void MacroAssembler::jC2(Register tmp, Label& L) {
5257 // set parity bit if FPU flag C2 is set (via rax)
5258 save_rax(tmp);
5259 fwait(); fnstsw_ax();
5260 sahf();
5261 restore_rax(tmp);
5262 // branch
5263 jcc(Assembler::parity, L);
5264 }
5266 void MacroAssembler::jnC2(Register tmp, Label& L) {
5267 // set parity bit if FPU flag C2 is set (via rax)
5268 save_rax(tmp);
5269 fwait(); fnstsw_ax();
5270 sahf();
5271 restore_rax(tmp);
5272 // branch
5273 jcc(Assembler::noParity, L);
5274 }
5276 // 32bit can do a case table jump in one instruction but we no longer allow the base
5277 // to be installed in the Address class
5278 void MacroAssembler::jump(ArrayAddress entry) {
5279 jmp(as_Address(entry));
5280 }
5282 // Note: y_lo will be destroyed
5283 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
5284 // Long compare for Java (semantics as described in JVM spec.)
5285 Label high, low, done;
5287 cmpl(x_hi, y_hi);
5288 jcc(Assembler::less, low);
5289 jcc(Assembler::greater, high);
5290 // x_hi is the return register
5291 xorl(x_hi, x_hi);
5292 cmpl(x_lo, y_lo);
5293 jcc(Assembler::below, low);
5294 jcc(Assembler::equal, done);
5296 bind(high);
5297 xorl(x_hi, x_hi);
5298 increment(x_hi);
5299 jmp(done);
5301 bind(low);
5302 xorl(x_hi, x_hi);
5303 decrementl(x_hi);
5305 bind(done);
5306 }
5308 void MacroAssembler::lea(Register dst, AddressLiteral src) {
5309 mov_literal32(dst, (int32_t)src.target(), src.rspec());
5310 }
5312 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
5313 // leal(dst, as_Address(adr));
5314 // see note in movl as to why we must use a move
5315 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
5316 }
5318 void MacroAssembler::leave() {
5319 mov(rsp, rbp);
5320 pop(rbp);
5321 }
5323 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
5324 // Multiplication of two Java long values stored on the stack
5325 // as illustrated below. Result is in rdx:rax.
5326 //
5327 // rsp ---> [ ?? ] \ \
5328 // .... | y_rsp_offset |
5329 // [ y_lo ] / (in bytes) | x_rsp_offset
5330 // [ y_hi ] | (in bytes)
5331 // .... |
5332 // [ x_lo ] /
5333 // [ x_hi ]
5334 // ....
5335 //
5336 // Basic idea: lo(result) = lo(x_lo * y_lo)
5337 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
5338 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
5339 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
5340 Label quick;
5341 // load x_hi, y_hi and check if quick
5342 // multiplication is possible
5343 movl(rbx, x_hi);
5344 movl(rcx, y_hi);
5345 movl(rax, rbx);
5346 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
5347 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
5348 // do full multiplication
5349 // 1st step
5350 mull(y_lo); // x_hi * y_lo
5351 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
5352 // 2nd step
5353 movl(rax, x_lo);
5354 mull(rcx); // x_lo * y_hi
5355 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
5356 // 3rd step
5357 bind(quick); // note: rbx, = 0 if quick multiply!
5358 movl(rax, x_lo);
5359 mull(y_lo); // x_lo * y_lo
5360 addl(rdx, rbx); // correct hi(x_lo * y_lo)
5361 }
5363 void MacroAssembler::lneg(Register hi, Register lo) {
5364 negl(lo);
5365 adcl(hi, 0);
5366 negl(hi);
5367 }
5369 void MacroAssembler::lshl(Register hi, Register lo) {
5370 // Java shift left long support (semantics as described in JVM spec., p.305)
5371 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
5372 // shift value is in rcx !
5373 assert(hi != rcx, "must not use rcx");
5374 assert(lo != rcx, "must not use rcx");
5375 const Register s = rcx; // shift count
5376 const int n = BitsPerWord;
5377 Label L;
5378 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
5379 cmpl(s, n); // if (s < n)
5380 jcc(Assembler::less, L); // else (s >= n)
5381 movl(hi, lo); // x := x << n
5382 xorl(lo, lo);
5383 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
5384 bind(L); // s (mod n) < n
5385 shldl(hi, lo); // x := x << s
5386 shll(lo);
5387 }
5390 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
5391 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
5392 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
5393 assert(hi != rcx, "must not use rcx");
5394 assert(lo != rcx, "must not use rcx");
5395 const Register s = rcx; // shift count
5396 const int n = BitsPerWord;
5397 Label L;
5398 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
5399 cmpl(s, n); // if (s < n)
5400 jcc(Assembler::less, L); // else (s >= n)
5401 movl(lo, hi); // x := x >> n
5402 if (sign_extension) sarl(hi, 31);
5403 else xorl(hi, hi);
5404 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
5405 bind(L); // s (mod n) < n
5406 shrdl(lo, hi); // x := x >> s
5407 if (sign_extension) sarl(hi);
5408 else shrl(hi);
5409 }
5411 void MacroAssembler::movoop(Register dst, jobject obj) {
5412 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
5413 }
5415 void MacroAssembler::movoop(Address dst, jobject obj) {
5416 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
5417 }
5419 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
5420 if (src.is_lval()) {
5421 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
5422 } else {
5423 movl(dst, as_Address(src));
5424 }
5425 }
5427 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
5428 movl(as_Address(dst), src);
5429 }
5431 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
5432 movl(dst, as_Address(src));
5433 }
5435 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
5436 void MacroAssembler::movptr(Address dst, intptr_t src) {
5437 movl(dst, src);
5438 }
5441 void MacroAssembler::pop_callee_saved_registers() {
5442 pop(rcx);
5443 pop(rdx);
5444 pop(rdi);
5445 pop(rsi);
5446 }
5448 void MacroAssembler::pop_fTOS() {
5449 fld_d(Address(rsp, 0));
5450 addl(rsp, 2 * wordSize);
5451 }
5453 void MacroAssembler::push_callee_saved_registers() {
5454 push(rsi);
5455 push(rdi);
5456 push(rdx);
5457 push(rcx);
5458 }
5460 void MacroAssembler::push_fTOS() {
5461 subl(rsp, 2 * wordSize);
5462 fstp_d(Address(rsp, 0));
5463 }
5466 void MacroAssembler::pushoop(jobject obj) {
5467 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
5468 }
5471 void MacroAssembler::pushptr(AddressLiteral src) {
5472 if (src.is_lval()) {
5473 push_literal32((int32_t)src.target(), src.rspec());
5474 } else {
5475 pushl(as_Address(src));
5476 }
5477 }
5479 void MacroAssembler::set_word_if_not_zero(Register dst) {
5480 xorl(dst, dst);
5481 set_byte_if_not_zero(dst);
5482 }
5484 static void pass_arg0(MacroAssembler* masm, Register arg) {
5485 masm->push(arg);
5486 }
5488 static void pass_arg1(MacroAssembler* masm, Register arg) {
5489 masm->push(arg);
5490 }
5492 static void pass_arg2(MacroAssembler* masm, Register arg) {
5493 masm->push(arg);
5494 }
5496 static void pass_arg3(MacroAssembler* masm, Register arg) {
5497 masm->push(arg);
5498 }
5500 #ifndef PRODUCT
5501 extern "C" void findpc(intptr_t x);
5502 #endif
5504 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
5505 // In order to get locks to work, we need to fake a in_VM state
5506 JavaThread* thread = JavaThread::current();
5507 JavaThreadState saved_state = thread->thread_state();
5508 thread->set_thread_state(_thread_in_vm);
5509 if (ShowMessageBoxOnError) {
5510 JavaThread* thread = JavaThread::current();
5511 JavaThreadState saved_state = thread->thread_state();
5512 thread->set_thread_state(_thread_in_vm);
5513 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
5514 ttyLocker ttyl;
5515 BytecodeCounter::print();
5516 }
5517 // To see where a verify_oop failed, get $ebx+40/X for this frame.
5518 // This is the value of eip which points to where verify_oop will return.
5519 if (os::message_box(msg, "Execution stopped, print registers?")) {
5520 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
5521 BREAKPOINT;
5522 assert(false, "start up GDB");
5523 }
5524 } else {
5525 ttyLocker ttyl;
5526 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
5527 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
5528 }
5529 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
5530 }
5532 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
5533 ttyLocker ttyl;
5534 FlagSetting fs(Debugging, true);
5535 tty->print_cr("eip = 0x%08x", eip);
5536 #ifndef PRODUCT
5537 if ((WizardMode || Verbose) && PrintMiscellaneous) {
5538 tty->cr();
5539 findpc(eip);
5540 tty->cr();
5541 }
5542 #endif
5543 #define PRINT_REG(rax) \
5544 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
5545 PRINT_REG(rax);
5546 PRINT_REG(rbx);
5547 PRINT_REG(rcx);
5548 PRINT_REG(rdx);
5549 PRINT_REG(rdi);
5550 PRINT_REG(rsi);
5551 PRINT_REG(rbp);
5552 PRINT_REG(rsp);
5553 #undef PRINT_REG
5554 // Print some words near top of staack.
5555 int* dump_sp = (int*) rsp;
5556 for (int col1 = 0; col1 < 8; col1++) {
5557 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
5558 os::print_location(tty, *dump_sp++);
5559 }
5560 for (int row = 0; row < 16; row++) {
5561 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
5562 for (int col = 0; col < 8; col++) {
5563 tty->print(" 0x%08x", *dump_sp++);
5564 }
5565 tty->cr();
5566 }
5567 // Print some instructions around pc:
5568 Disassembler::decode((address)eip-64, (address)eip);
5569 tty->print_cr("--------");
5570 Disassembler::decode((address)eip, (address)eip+32);
5571 }
5573 void MacroAssembler::stop(const char* msg) {
5574 ExternalAddress message((address)msg);
5575 // push address of message
5576 pushptr(message.addr());
5577 { Label L; call(L, relocInfo::none); bind(L); } // push eip
5578 pusha(); // push registers
5579 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
5580 hlt();
5581 }
5583 void MacroAssembler::warn(const char* msg) {
5584 push_CPU_state();
5586 ExternalAddress message((address) msg);
5587 // push address of message
5588 pushptr(message.addr());
5590 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
5591 addl(rsp, wordSize); // discard argument
5592 pop_CPU_state();
5593 }
5595 void MacroAssembler::print_state() {
5596 { Label L; call(L, relocInfo::none); bind(L); } // push eip
5597 pusha(); // push registers
5599 push_CPU_state();
5600 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
5601 pop_CPU_state();
5603 popa();
5604 addl(rsp, wordSize);
5605 }
5607 #else // _LP64
5609 // 64 bit versions
5611 Address MacroAssembler::as_Address(AddressLiteral adr) {
5612 // amd64 always does this as a pc-rel
5613 // we can be absolute or disp based on the instruction type
5614 // jmp/call are displacements others are absolute
5615 assert(!adr.is_lval(), "must be rval");
5616 assert(reachable(adr), "must be");
5617 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
5619 }
5621 Address MacroAssembler::as_Address(ArrayAddress adr) {
5622 AddressLiteral base = adr.base();
5623 lea(rscratch1, base);
5624 Address index = adr.index();
5625 assert(index._disp == 0, "must not have disp"); // maybe it can?
5626 Address array(rscratch1, index._index, index._scale, index._disp);
5627 return array;
5628 }
5630 int MacroAssembler::biased_locking_enter(Register lock_reg,
5631 Register obj_reg,
5632 Register swap_reg,
5633 Register tmp_reg,
5634 bool swap_reg_contains_mark,
5635 Label& done,
5636 Label* slow_case,
5637 BiasedLockingCounters* counters) {
5638 assert(UseBiasedLocking, "why call this otherwise?");
5639 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
5640 assert(tmp_reg != noreg, "tmp_reg must be supplied");
5641 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
5642 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
5643 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
5644 Address saved_mark_addr(lock_reg, 0);
5646 if (PrintBiasedLockingStatistics && counters == NULL)
5647 counters = BiasedLocking::counters();
5649 // Biased locking
5650 // See whether the lock is currently biased toward our thread and
5651 // whether the epoch is still valid
5652 // Note that the runtime guarantees sufficient alignment of JavaThread
5653 // pointers to allow age to be placed into low bits
5654 // First check to see whether biasing is even enabled for this object
5655 Label cas_label;
5656 int null_check_offset = -1;
5657 if (!swap_reg_contains_mark) {
5658 null_check_offset = offset();
5659 movq(swap_reg, mark_addr);
5660 }
5661 movq(tmp_reg, swap_reg);
5662 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
5663 cmpq(tmp_reg, markOopDesc::biased_lock_pattern);
5664 jcc(Assembler::notEqual, cas_label);
5665 // The bias pattern is present in the object's header. Need to check
5666 // whether the bias owner and the epoch are both still current.
5667 load_prototype_header(tmp_reg, obj_reg);
5668 orq(tmp_reg, r15_thread);
5669 xorq(tmp_reg, swap_reg);
5670 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place));
5671 if (counters != NULL) {
5672 cond_inc32(Assembler::zero,
5673 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
5674 }
5675 jcc(Assembler::equal, done);
5677 Label try_revoke_bias;
5678 Label try_rebias;
5680 // At this point we know that the header has the bias pattern and
5681 // that we are not the bias owner in the current epoch. We need to
5682 // figure out more details about the state of the header in order to
5683 // know what operations can be legally performed on the object's
5684 // header.
5686 // If the low three bits in the xor result aren't clear, that means
5687 // the prototype header is no longer biased and we have to revoke
5688 // the bias on this object.
5689 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
5690 jcc(Assembler::notZero, try_revoke_bias);
5692 // Biasing is still enabled for this data type. See whether the
5693 // epoch of the current bias is still valid, meaning that the epoch
5694 // bits of the mark word are equal to the epoch bits of the
5695 // prototype header. (Note that the prototype header's epoch bits
5696 // only change at a safepoint.) If not, attempt to rebias the object
5697 // toward the current thread. Note that we must be absolutely sure
5698 // that the current epoch is invalid in order to do this because
5699 // otherwise the manipulations it performs on the mark word are
5700 // illegal.
5701 testq(tmp_reg, markOopDesc::epoch_mask_in_place);
5702 jcc(Assembler::notZero, try_rebias);
5704 // The epoch of the current bias is still valid but we know nothing
5705 // about the owner; it might be set or it might be clear. Try to
5706 // acquire the bias of the object using an atomic operation. If this
5707 // fails we will go in to the runtime to revoke the object's bias.
5708 // Note that we first construct the presumed unbiased header so we
5709 // don't accidentally blow away another thread's valid bias.
5710 andq(swap_reg,
5711 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
5712 movq(tmp_reg, swap_reg);
5713 orq(tmp_reg, r15_thread);
5714 if (os::is_MP()) {
5715 lock();
5716 }
5717 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5718 // If the biasing toward our thread failed, this means that
5719 // another thread succeeded in biasing it toward itself and we
5720 // need to revoke that bias. The revocation will occur in the
5721 // interpreter runtime in the slow case.
5722 if (counters != NULL) {
5723 cond_inc32(Assembler::zero,
5724 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
5725 }
5726 if (slow_case != NULL) {
5727 jcc(Assembler::notZero, *slow_case);
5728 }
5729 jmp(done);
5731 bind(try_rebias);
5732 // At this point we know the epoch has expired, meaning that the
5733 // current "bias owner", if any, is actually invalid. Under these
5734 // circumstances _only_, we are allowed to use the current header's
5735 // value as the comparison value when doing the cas to acquire the
5736 // bias in the current epoch. In other words, we allow transfer of
5737 // the bias from one thread to another directly in this situation.
5738 //
5739 // FIXME: due to a lack of registers we currently blow away the age
5740 // bits in this situation. Should attempt to preserve them.
5741 load_prototype_header(tmp_reg, obj_reg);
5742 orq(tmp_reg, r15_thread);
5743 if (os::is_MP()) {
5744 lock();
5745 }
5746 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5747 // If the biasing toward our thread failed, then another thread
5748 // succeeded in biasing it toward itself and we need to revoke that
5749 // bias. The revocation will occur in the runtime in the slow case.
5750 if (counters != NULL) {
5751 cond_inc32(Assembler::zero,
5752 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
5753 }
5754 if (slow_case != NULL) {
5755 jcc(Assembler::notZero, *slow_case);
5756 }
5757 jmp(done);
5759 bind(try_revoke_bias);
5760 // The prototype mark in the klass doesn't have the bias bit set any
5761 // more, indicating that objects of this data type are not supposed
5762 // to be biased any more. We are going to try to reset the mark of
5763 // this object to the prototype value and fall through to the
5764 // CAS-based locking scheme. Note that if our CAS fails, it means
5765 // that another thread raced us for the privilege of revoking the
5766 // bias of this particular object, so it's okay to continue in the
5767 // normal locking code.
5768 //
5769 // FIXME: due to a lack of registers we currently blow away the age
5770 // bits in this situation. Should attempt to preserve them.
5771 load_prototype_header(tmp_reg, obj_reg);
5772 if (os::is_MP()) {
5773 lock();
5774 }
5775 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5776 // Fall through to the normal CAS-based lock, because no matter what
5777 // the result of the above CAS, some thread must have succeeded in
5778 // removing the bias bit from the object's header.
5779 if (counters != NULL) {
5780 cond_inc32(Assembler::zero,
5781 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
5782 }
5784 bind(cas_label);
5786 return null_check_offset;
5787 }
5789 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
5790 Label L, E;
5792 #ifdef _WIN64
5793 // Windows always allocates space for it's register args
5794 assert(num_args <= 4, "only register arguments supported");
5795 subq(rsp, frame::arg_reg_save_area_bytes);
5796 #endif
5798 // Align stack if necessary
5799 testl(rsp, 15);
5800 jcc(Assembler::zero, L);
5802 subq(rsp, 8);
5803 {
5804 call(RuntimeAddress(entry_point));
5805 }
5806 addq(rsp, 8);
5807 jmp(E);
5809 bind(L);
5810 {
5811 call(RuntimeAddress(entry_point));
5812 }
5814 bind(E);
5816 #ifdef _WIN64
5817 // restore stack pointer
5818 addq(rsp, frame::arg_reg_save_area_bytes);
5819 #endif
5821 }
5823 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
5824 assert(!src2.is_lval(), "should use cmpptr");
5826 if (reachable(src2)) {
5827 cmpq(src1, as_Address(src2));
5828 } else {
5829 lea(rscratch1, src2);
5830 Assembler::cmpq(src1, Address(rscratch1, 0));
5831 }
5832 }
5834 int MacroAssembler::corrected_idivq(Register reg) {
5835 // Full implementation of Java ldiv and lrem; checks for special
5836 // case as described in JVM spec., p.243 & p.271. The function
5837 // returns the (pc) offset of the idivl instruction - may be needed
5838 // for implicit exceptions.
5839 //
5840 // normal case special case
5841 //
5842 // input : rax: dividend min_long
5843 // reg: divisor (may not be eax/edx) -1
5844 //
5845 // output: rax: quotient (= rax idiv reg) min_long
5846 // rdx: remainder (= rax irem reg) 0
5847 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
5848 static const int64_t min_long = 0x8000000000000000;
5849 Label normal_case, special_case;
5851 // check for special case
5852 cmp64(rax, ExternalAddress((address) &min_long));
5853 jcc(Assembler::notEqual, normal_case);
5854 xorl(rdx, rdx); // prepare rdx for possible special case (where
5855 // remainder = 0)
5856 cmpq(reg, -1);
5857 jcc(Assembler::equal, special_case);
5859 // handle normal case
5860 bind(normal_case);
5861 cdqq();
5862 int idivq_offset = offset();
5863 idivq(reg);
5865 // normal and special case exit
5866 bind(special_case);
5868 return idivq_offset;
5869 }
5871 void MacroAssembler::decrementq(Register reg, int value) {
5872 if (value == min_jint) { subq(reg, value); return; }
5873 if (value < 0) { incrementq(reg, -value); return; }
5874 if (value == 0) { ; return; }
5875 if (value == 1 && UseIncDec) { decq(reg) ; return; }
5876 /* else */ { subq(reg, value) ; return; }
5877 }
5879 void MacroAssembler::decrementq(Address dst, int value) {
5880 if (value == min_jint) { subq(dst, value); return; }
5881 if (value < 0) { incrementq(dst, -value); return; }
5882 if (value == 0) { ; return; }
5883 if (value == 1 && UseIncDec) { decq(dst) ; return; }
5884 /* else */ { subq(dst, value) ; return; }
5885 }
5887 void MacroAssembler::incrementq(Register reg, int value) {
5888 if (value == min_jint) { addq(reg, value); return; }
5889 if (value < 0) { decrementq(reg, -value); return; }
5890 if (value == 0) { ; return; }
5891 if (value == 1 && UseIncDec) { incq(reg) ; return; }
5892 /* else */ { addq(reg, value) ; return; }
5893 }
5895 void MacroAssembler::incrementq(Address dst, int value) {
5896 if (value == min_jint) { addq(dst, value); return; }
5897 if (value < 0) { decrementq(dst, -value); return; }
5898 if (value == 0) { ; return; }
5899 if (value == 1 && UseIncDec) { incq(dst) ; return; }
5900 /* else */ { addq(dst, value) ; return; }
5901 }
5903 // 32bit can do a case table jump in one instruction but we no longer allow the base
5904 // to be installed in the Address class
5905 void MacroAssembler::jump(ArrayAddress entry) {
5906 lea(rscratch1, entry.base());
5907 Address dispatch = entry.index();
5908 assert(dispatch._base == noreg, "must be");
5909 dispatch._base = rscratch1;
5910 jmp(dispatch);
5911 }
5913 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
5914 ShouldNotReachHere(); // 64bit doesn't use two regs
5915 cmpq(x_lo, y_lo);
5916 }
5918 void MacroAssembler::lea(Register dst, AddressLiteral src) {
5919 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
5920 }
5922 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
5923 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
5924 movptr(dst, rscratch1);
5925 }
5927 void MacroAssembler::leave() {
5928 // %%% is this really better? Why not on 32bit too?
5929 emit_byte(0xC9); // LEAVE
5930 }
5932 void MacroAssembler::lneg(Register hi, Register lo) {
5933 ShouldNotReachHere(); // 64bit doesn't use two regs
5934 negq(lo);
5935 }
5937 void MacroAssembler::movoop(Register dst, jobject obj) {
5938 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
5939 }
5941 void MacroAssembler::movoop(Address dst, jobject obj) {
5942 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
5943 movq(dst, rscratch1);
5944 }
5946 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
5947 if (src.is_lval()) {
5948 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
5949 } else {
5950 if (reachable(src)) {
5951 movq(dst, as_Address(src));
5952 } else {
5953 lea(rscratch1, src);
5954 movq(dst, Address(rscratch1,0));
5955 }
5956 }
5957 }
5959 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
5960 movq(as_Address(dst), src);
5961 }
5963 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
5964 movq(dst, as_Address(src));
5965 }
5967 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
5968 void MacroAssembler::movptr(Address dst, intptr_t src) {
5969 mov64(rscratch1, src);
5970 movq(dst, rscratch1);
5971 }
5973 // These are mostly for initializing NULL
5974 void MacroAssembler::movptr(Address dst, int32_t src) {
5975 movslq(dst, src);
5976 }
5978 void MacroAssembler::movptr(Register dst, int32_t src) {
5979 mov64(dst, (intptr_t)src);
5980 }
5982 void MacroAssembler::pushoop(jobject obj) {
5983 movoop(rscratch1, obj);
5984 push(rscratch1);
5985 }
5987 void MacroAssembler::pushptr(AddressLiteral src) {
5988 lea(rscratch1, src);
5989 if (src.is_lval()) {
5990 push(rscratch1);
5991 } else {
5992 pushq(Address(rscratch1, 0));
5993 }
5994 }
5996 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
5997 bool clear_pc) {
5998 // we must set sp to zero to clear frame
5999 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
6000 // must clear fp, so that compiled frames are not confused; it is
6001 // possible that we need it only for debugging
6002 if (clear_fp) {
6003 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
6004 }
6006 if (clear_pc) {
6007 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
6008 }
6009 }
6011 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
6012 Register last_java_fp,
6013 address last_java_pc) {
6014 // determine last_java_sp register
6015 if (!last_java_sp->is_valid()) {
6016 last_java_sp = rsp;
6017 }
6019 // last_java_fp is optional
6020 if (last_java_fp->is_valid()) {
6021 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
6022 last_java_fp);
6023 }
6025 // last_java_pc is optional
6026 if (last_java_pc != NULL) {
6027 Address java_pc(r15_thread,
6028 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
6029 lea(rscratch1, InternalAddress(last_java_pc));
6030 movptr(java_pc, rscratch1);
6031 }
6033 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
6034 }
6036 static void pass_arg0(MacroAssembler* masm, Register arg) {
6037 if (c_rarg0 != arg ) {
6038 masm->mov(c_rarg0, arg);
6039 }
6040 }
6042 static void pass_arg1(MacroAssembler* masm, Register arg) {
6043 if (c_rarg1 != arg ) {
6044 masm->mov(c_rarg1, arg);
6045 }
6046 }
6048 static void pass_arg2(MacroAssembler* masm, Register arg) {
6049 if (c_rarg2 != arg ) {
6050 masm->mov(c_rarg2, arg);
6051 }
6052 }
6054 static void pass_arg3(MacroAssembler* masm, Register arg) {
6055 if (c_rarg3 != arg ) {
6056 masm->mov(c_rarg3, arg);
6057 }
6058 }
6060 void MacroAssembler::stop(const char* msg) {
6061 address rip = pc();
6062 pusha(); // get regs on stack
6063 lea(c_rarg0, ExternalAddress((address) msg));
6064 lea(c_rarg1, InternalAddress(rip));
6065 movq(c_rarg2, rsp); // pass pointer to regs array
6066 andq(rsp, -16); // align stack as required by ABI
6067 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
6068 hlt();
6069 }
6071 void MacroAssembler::warn(const char* msg) {
6072 push(rbp);
6073 movq(rbp, rsp);
6074 andq(rsp, -16); // align stack as required by push_CPU_state and call
6075 push_CPU_state(); // keeps alignment at 16 bytes
6076 lea(c_rarg0, ExternalAddress((address) msg));
6077 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
6078 pop_CPU_state();
6079 mov(rsp, rbp);
6080 pop(rbp);
6081 }
6083 void MacroAssembler::print_state() {
6084 address rip = pc();
6085 pusha(); // get regs on stack
6086 push(rbp);
6087 movq(rbp, rsp);
6088 andq(rsp, -16); // align stack as required by push_CPU_state and call
6089 push_CPU_state(); // keeps alignment at 16 bytes
6091 lea(c_rarg0, InternalAddress(rip));
6092 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
6093 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
6095 pop_CPU_state();
6096 mov(rsp, rbp);
6097 pop(rbp);
6098 popa();
6099 }
6101 #ifndef PRODUCT
6102 extern "C" void findpc(intptr_t x);
6103 #endif
6105 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
6106 // In order to get locks to work, we need to fake a in_VM state
6107 if (ShowMessageBoxOnError) {
6108 JavaThread* thread = JavaThread::current();
6109 JavaThreadState saved_state = thread->thread_state();
6110 thread->set_thread_state(_thread_in_vm);
6111 #ifndef PRODUCT
6112 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
6113 ttyLocker ttyl;
6114 BytecodeCounter::print();
6115 }
6116 #endif
6117 // To see where a verify_oop failed, get $ebx+40/X for this frame.
6118 // XXX correct this offset for amd64
6119 // This is the value of eip which points to where verify_oop will return.
6120 if (os::message_box(msg, "Execution stopped, print registers?")) {
6121 print_state64(pc, regs);
6122 BREAKPOINT;
6123 assert(false, "start up GDB");
6124 }
6125 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
6126 } else {
6127 ttyLocker ttyl;
6128 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
6129 msg);
6130 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
6131 }
6132 }
6134 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
6135 ttyLocker ttyl;
6136 FlagSetting fs(Debugging, true);
6137 tty->print_cr("rip = 0x%016lx", pc);
6138 #ifndef PRODUCT
6139 tty->cr();
6140 findpc(pc);
6141 tty->cr();
6142 #endif
6143 #define PRINT_REG(rax, value) \
6144 { tty->print("%s = ", #rax); os::print_location(tty, value); }
6145 PRINT_REG(rax, regs[15]);
6146 PRINT_REG(rbx, regs[12]);
6147 PRINT_REG(rcx, regs[14]);
6148 PRINT_REG(rdx, regs[13]);
6149 PRINT_REG(rdi, regs[8]);
6150 PRINT_REG(rsi, regs[9]);
6151 PRINT_REG(rbp, regs[10]);
6152 PRINT_REG(rsp, regs[11]);
6153 PRINT_REG(r8 , regs[7]);
6154 PRINT_REG(r9 , regs[6]);
6155 PRINT_REG(r10, regs[5]);
6156 PRINT_REG(r11, regs[4]);
6157 PRINT_REG(r12, regs[3]);
6158 PRINT_REG(r13, regs[2]);
6159 PRINT_REG(r14, regs[1]);
6160 PRINT_REG(r15, regs[0]);
6161 #undef PRINT_REG
6162 // Print some words near top of staack.
6163 int64_t* rsp = (int64_t*) regs[11];
6164 int64_t* dump_sp = rsp;
6165 for (int col1 = 0; col1 < 8; col1++) {
6166 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
6167 os::print_location(tty, *dump_sp++);
6168 }
6169 for (int row = 0; row < 25; row++) {
6170 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
6171 for (int col = 0; col < 4; col++) {
6172 tty->print(" 0x%016lx", *dump_sp++);
6173 }
6174 tty->cr();
6175 }
6176 // Print some instructions around pc:
6177 Disassembler::decode((address)pc-64, (address)pc);
6178 tty->print_cr("--------");
6179 Disassembler::decode((address)pc, (address)pc+32);
6180 }
6182 #endif // _LP64
6184 // Now versions that are common to 32/64 bit
6186 void MacroAssembler::addptr(Register dst, int32_t imm32) {
6187 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
6188 }
6190 void MacroAssembler::addptr(Register dst, Register src) {
6191 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
6192 }
6194 void MacroAssembler::addptr(Address dst, Register src) {
6195 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
6196 }
6198 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
6199 if (reachable(src)) {
6200 Assembler::addsd(dst, as_Address(src));
6201 } else {
6202 lea(rscratch1, src);
6203 Assembler::addsd(dst, Address(rscratch1, 0));
6204 }
6205 }
6207 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
6208 if (reachable(src)) {
6209 addss(dst, as_Address(src));
6210 } else {
6211 lea(rscratch1, src);
6212 addss(dst, Address(rscratch1, 0));
6213 }
6214 }
6216 void MacroAssembler::align(int modulus) {
6217 if (offset() % modulus != 0) {
6218 nop(modulus - (offset() % modulus));
6219 }
6220 }
6222 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
6223 // Used in sign-masking with aligned address.
6224 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
6225 if (reachable(src)) {
6226 Assembler::andpd(dst, as_Address(src));
6227 } else {
6228 lea(rscratch1, src);
6229 Assembler::andpd(dst, Address(rscratch1, 0));
6230 }
6231 }
6233 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
6234 // Used in sign-masking with aligned address.
6235 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
6236 if (reachable(src)) {
6237 Assembler::andps(dst, as_Address(src));
6238 } else {
6239 lea(rscratch1, src);
6240 Assembler::andps(dst, Address(rscratch1, 0));
6241 }
6242 }
6244 void MacroAssembler::andptr(Register dst, int32_t imm32) {
6245 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
6246 }
6248 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
6249 pushf();
6250 if (os::is_MP())
6251 lock();
6252 incrementl(counter_addr);
6253 popf();
6254 }
6256 // Writes to stack successive pages until offset reached to check for
6257 // stack overflow + shadow pages. This clobbers tmp.
6258 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
6259 movptr(tmp, rsp);
6260 // Bang stack for total size given plus shadow page size.
6261 // Bang one page at a time because large size can bang beyond yellow and
6262 // red zones.
6263 Label loop;
6264 bind(loop);
6265 movl(Address(tmp, (-os::vm_page_size())), size );
6266 subptr(tmp, os::vm_page_size());
6267 subl(size, os::vm_page_size());
6268 jcc(Assembler::greater, loop);
6270 // Bang down shadow pages too.
6271 // The -1 because we already subtracted 1 page.
6272 for (int i = 0; i< StackShadowPages-1; i++) {
6273 // this could be any sized move but this is can be a debugging crumb
6274 // so the bigger the better.
6275 movptr(Address(tmp, (-i*os::vm_page_size())), size );
6276 }
6277 }
6279 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
6280 assert(UseBiasedLocking, "why call this otherwise?");
6282 // Check for biased locking unlock case, which is a no-op
6283 // Note: we do not have to check the thread ID for two reasons.
6284 // First, the interpreter checks for IllegalMonitorStateException at
6285 // a higher level. Second, if the bias was revoked while we held the
6286 // lock, the object could not be rebiased toward another thread, so
6287 // the bias bit would be clear.
6288 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
6289 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
6290 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
6291 jcc(Assembler::equal, done);
6292 }
6294 void MacroAssembler::c2bool(Register x) {
6295 // implements x == 0 ? 0 : 1
6296 // note: must only look at least-significant byte of x
6297 // since C-style booleans are stored in one byte
6298 // only! (was bug)
6299 andl(x, 0xFF);
6300 setb(Assembler::notZero, x);
6301 }
6303 // Wouldn't need if AddressLiteral version had new name
6304 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
6305 Assembler::call(L, rtype);
6306 }
6308 void MacroAssembler::call(Register entry) {
6309 Assembler::call(entry);
6310 }
6312 void MacroAssembler::call(AddressLiteral entry) {
6313 if (reachable(entry)) {
6314 Assembler::call_literal(entry.target(), entry.rspec());
6315 } else {
6316 lea(rscratch1, entry);
6317 Assembler::call(rscratch1);
6318 }
6319 }
6321 // Implementation of call_VM versions
6323 void MacroAssembler::call_VM(Register oop_result,
6324 address entry_point,
6325 bool check_exceptions) {
6326 Label C, E;
6327 call(C, relocInfo::none);
6328 jmp(E);
6330 bind(C);
6331 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
6332 ret(0);
6334 bind(E);
6335 }
6337 void MacroAssembler::call_VM(Register oop_result,
6338 address entry_point,
6339 Register arg_1,
6340 bool check_exceptions) {
6341 Label C, E;
6342 call(C, relocInfo::none);
6343 jmp(E);
6345 bind(C);
6346 pass_arg1(this, arg_1);
6347 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
6348 ret(0);
6350 bind(E);
6351 }
6353 void MacroAssembler::call_VM(Register oop_result,
6354 address entry_point,
6355 Register arg_1,
6356 Register arg_2,
6357 bool check_exceptions) {
6358 Label C, E;
6359 call(C, relocInfo::none);
6360 jmp(E);
6362 bind(C);
6364 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6366 pass_arg2(this, arg_2);
6367 pass_arg1(this, arg_1);
6368 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
6369 ret(0);
6371 bind(E);
6372 }
6374 void MacroAssembler::call_VM(Register oop_result,
6375 address entry_point,
6376 Register arg_1,
6377 Register arg_2,
6378 Register arg_3,
6379 bool check_exceptions) {
6380 Label C, E;
6381 call(C, relocInfo::none);
6382 jmp(E);
6384 bind(C);
6386 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
6387 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
6388 pass_arg3(this, arg_3);
6390 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6391 pass_arg2(this, arg_2);
6393 pass_arg1(this, arg_1);
6394 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
6395 ret(0);
6397 bind(E);
6398 }
6400 void MacroAssembler::call_VM(Register oop_result,
6401 Register last_java_sp,
6402 address entry_point,
6403 int number_of_arguments,
6404 bool check_exceptions) {
6405 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
6406 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
6407 }
6409 void MacroAssembler::call_VM(Register oop_result,
6410 Register last_java_sp,
6411 address entry_point,
6412 Register arg_1,
6413 bool check_exceptions) {
6414 pass_arg1(this, arg_1);
6415 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
6416 }
6418 void MacroAssembler::call_VM(Register oop_result,
6419 Register last_java_sp,
6420 address entry_point,
6421 Register arg_1,
6422 Register arg_2,
6423 bool check_exceptions) {
6425 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6426 pass_arg2(this, arg_2);
6427 pass_arg1(this, arg_1);
6428 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
6429 }
6431 void MacroAssembler::call_VM(Register oop_result,
6432 Register last_java_sp,
6433 address entry_point,
6434 Register arg_1,
6435 Register arg_2,
6436 Register arg_3,
6437 bool check_exceptions) {
6438 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
6439 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
6440 pass_arg3(this, arg_3);
6441 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6442 pass_arg2(this, arg_2);
6443 pass_arg1(this, arg_1);
6444 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
6445 }
6447 void MacroAssembler::super_call_VM(Register oop_result,
6448 Register last_java_sp,
6449 address entry_point,
6450 int number_of_arguments,
6451 bool check_exceptions) {
6452 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
6453 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
6454 }
6456 void MacroAssembler::super_call_VM(Register oop_result,
6457 Register last_java_sp,
6458 address entry_point,
6459 Register arg_1,
6460 bool check_exceptions) {
6461 pass_arg1(this, arg_1);
6462 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
6463 }
6465 void MacroAssembler::super_call_VM(Register oop_result,
6466 Register last_java_sp,
6467 address entry_point,
6468 Register arg_1,
6469 Register arg_2,
6470 bool check_exceptions) {
6472 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6473 pass_arg2(this, arg_2);
6474 pass_arg1(this, arg_1);
6475 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
6476 }
6478 void MacroAssembler::super_call_VM(Register oop_result,
6479 Register last_java_sp,
6480 address entry_point,
6481 Register arg_1,
6482 Register arg_2,
6483 Register arg_3,
6484 bool check_exceptions) {
6485 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
6486 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
6487 pass_arg3(this, arg_3);
6488 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6489 pass_arg2(this, arg_2);
6490 pass_arg1(this, arg_1);
6491 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
6492 }
6494 void MacroAssembler::call_VM_base(Register oop_result,
6495 Register java_thread,
6496 Register last_java_sp,
6497 address entry_point,
6498 int number_of_arguments,
6499 bool check_exceptions) {
6500 // determine java_thread register
6501 if (!java_thread->is_valid()) {
6502 #ifdef _LP64
6503 java_thread = r15_thread;
6504 #else
6505 java_thread = rdi;
6506 get_thread(java_thread);
6507 #endif // LP64
6508 }
6509 // determine last_java_sp register
6510 if (!last_java_sp->is_valid()) {
6511 last_java_sp = rsp;
6512 }
6513 // debugging support
6514 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
6515 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
6516 #ifdef ASSERT
6517 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
6518 // r12 is the heapbase.
6519 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base");)
6520 #endif // ASSERT
6522 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
6523 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
6525 // push java thread (becomes first argument of C function)
6527 NOT_LP64(push(java_thread); number_of_arguments++);
6528 LP64_ONLY(mov(c_rarg0, r15_thread));
6530 // set last Java frame before call
6531 assert(last_java_sp != rbp, "can't use ebp/rbp");
6533 // Only interpreter should have to set fp
6534 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
6536 // do the call, remove parameters
6537 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
6539 // restore the thread (cannot use the pushed argument since arguments
6540 // may be overwritten by C code generated by an optimizing compiler);
6541 // however can use the register value directly if it is callee saved.
6542 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
6543 // rdi & rsi (also r15) are callee saved -> nothing to do
6544 #ifdef ASSERT
6545 guarantee(java_thread != rax, "change this code");
6546 push(rax);
6547 { Label L;
6548 get_thread(rax);
6549 cmpptr(java_thread, rax);
6550 jcc(Assembler::equal, L);
6551 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
6552 bind(L);
6553 }
6554 pop(rax);
6555 #endif
6556 } else {
6557 get_thread(java_thread);
6558 }
6559 // reset last Java frame
6560 // Only interpreter should have to clear fp
6561 reset_last_Java_frame(java_thread, true, false);
6563 #ifndef CC_INTERP
6564 // C++ interp handles this in the interpreter
6565 check_and_handle_popframe(java_thread);
6566 check_and_handle_earlyret(java_thread);
6567 #endif /* CC_INTERP */
6569 if (check_exceptions) {
6570 // check for pending exceptions (java_thread is set upon return)
6571 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
6572 #ifndef _LP64
6573 jump_cc(Assembler::notEqual,
6574 RuntimeAddress(StubRoutines::forward_exception_entry()));
6575 #else
6576 // This used to conditionally jump to forward_exception however it is
6577 // possible if we relocate that the branch will not reach. So we must jump
6578 // around so we can always reach
6580 Label ok;
6581 jcc(Assembler::equal, ok);
6582 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
6583 bind(ok);
6584 #endif // LP64
6585 }
6587 // get oop result if there is one and reset the value in the thread
6588 if (oop_result->is_valid()) {
6589 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
6590 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
6591 verify_oop(oop_result, "broken oop in call_VM_base");
6592 }
6593 }
6595 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
6597 // Calculate the value for last_Java_sp
6598 // somewhat subtle. call_VM does an intermediate call
6599 // which places a return address on the stack just under the
6600 // stack pointer as the user finsihed with it. This allows
6601 // use to retrieve last_Java_pc from last_Java_sp[-1].
6602 // On 32bit we then have to push additional args on the stack to accomplish
6603 // the actual requested call. On 64bit call_VM only can use register args
6604 // so the only extra space is the return address that call_VM created.
6605 // This hopefully explains the calculations here.
6607 #ifdef _LP64
6608 // We've pushed one address, correct last_Java_sp
6609 lea(rax, Address(rsp, wordSize));
6610 #else
6611 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
6612 #endif // LP64
6614 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
6616 }
6618 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
6619 call_VM_leaf_base(entry_point, number_of_arguments);
6620 }
6622 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
6623 pass_arg0(this, arg_0);
6624 call_VM_leaf(entry_point, 1);
6625 }
6627 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
6629 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
6630 pass_arg1(this, arg_1);
6631 pass_arg0(this, arg_0);
6632 call_VM_leaf(entry_point, 2);
6633 }
6635 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
6636 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
6637 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6638 pass_arg2(this, arg_2);
6639 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
6640 pass_arg1(this, arg_1);
6641 pass_arg0(this, arg_0);
6642 call_VM_leaf(entry_point, 3);
6643 }
6645 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
6646 pass_arg0(this, arg_0);
6647 MacroAssembler::call_VM_leaf_base(entry_point, 1);
6648 }
6650 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
6652 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
6653 pass_arg1(this, arg_1);
6654 pass_arg0(this, arg_0);
6655 MacroAssembler::call_VM_leaf_base(entry_point, 2);
6656 }
6658 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
6659 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
6660 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6661 pass_arg2(this, arg_2);
6662 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
6663 pass_arg1(this, arg_1);
6664 pass_arg0(this, arg_0);
6665 MacroAssembler::call_VM_leaf_base(entry_point, 3);
6666 }
6668 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
6669 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
6670 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
6671 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
6672 pass_arg3(this, arg_3);
6673 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
6674 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6675 pass_arg2(this, arg_2);
6676 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
6677 pass_arg1(this, arg_1);
6678 pass_arg0(this, arg_0);
6679 MacroAssembler::call_VM_leaf_base(entry_point, 4);
6680 }
6682 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
6683 }
6685 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
6686 }
6688 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
6689 if (reachable(src1)) {
6690 cmpl(as_Address(src1), imm);
6691 } else {
6692 lea(rscratch1, src1);
6693 cmpl(Address(rscratch1, 0), imm);
6694 }
6695 }
6697 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
6698 assert(!src2.is_lval(), "use cmpptr");
6699 if (reachable(src2)) {
6700 cmpl(src1, as_Address(src2));
6701 } else {
6702 lea(rscratch1, src2);
6703 cmpl(src1, Address(rscratch1, 0));
6704 }
6705 }
6707 void MacroAssembler::cmp32(Register src1, int32_t imm) {
6708 Assembler::cmpl(src1, imm);
6709 }
6711 void MacroAssembler::cmp32(Register src1, Address src2) {
6712 Assembler::cmpl(src1, src2);
6713 }
6715 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
6716 ucomisd(opr1, opr2);
6718 Label L;
6719 if (unordered_is_less) {
6720 movl(dst, -1);
6721 jcc(Assembler::parity, L);
6722 jcc(Assembler::below , L);
6723 movl(dst, 0);
6724 jcc(Assembler::equal , L);
6725 increment(dst);
6726 } else { // unordered is greater
6727 movl(dst, 1);
6728 jcc(Assembler::parity, L);
6729 jcc(Assembler::above , L);
6730 movl(dst, 0);
6731 jcc(Assembler::equal , L);
6732 decrementl(dst);
6733 }
6734 bind(L);
6735 }
6737 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
6738 ucomiss(opr1, opr2);
6740 Label L;
6741 if (unordered_is_less) {
6742 movl(dst, -1);
6743 jcc(Assembler::parity, L);
6744 jcc(Assembler::below , L);
6745 movl(dst, 0);
6746 jcc(Assembler::equal , L);
6747 increment(dst);
6748 } else { // unordered is greater
6749 movl(dst, 1);
6750 jcc(Assembler::parity, L);
6751 jcc(Assembler::above , L);
6752 movl(dst, 0);
6753 jcc(Assembler::equal , L);
6754 decrementl(dst);
6755 }
6756 bind(L);
6757 }
6760 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
6761 if (reachable(src1)) {
6762 cmpb(as_Address(src1), imm);
6763 } else {
6764 lea(rscratch1, src1);
6765 cmpb(Address(rscratch1, 0), imm);
6766 }
6767 }
6769 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
6770 #ifdef _LP64
6771 if (src2.is_lval()) {
6772 movptr(rscratch1, src2);
6773 Assembler::cmpq(src1, rscratch1);
6774 } else if (reachable(src2)) {
6775 cmpq(src1, as_Address(src2));
6776 } else {
6777 lea(rscratch1, src2);
6778 Assembler::cmpq(src1, Address(rscratch1, 0));
6779 }
6780 #else
6781 if (src2.is_lval()) {
6782 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
6783 } else {
6784 cmpl(src1, as_Address(src2));
6785 }
6786 #endif // _LP64
6787 }
6789 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
6790 assert(src2.is_lval(), "not a mem-mem compare");
6791 #ifdef _LP64
6792 // moves src2's literal address
6793 movptr(rscratch1, src2);
6794 Assembler::cmpq(src1, rscratch1);
6795 #else
6796 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
6797 #endif // _LP64
6798 }
6800 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
6801 if (reachable(adr)) {
6802 if (os::is_MP())
6803 lock();
6804 cmpxchgptr(reg, as_Address(adr));
6805 } else {
6806 lea(rscratch1, adr);
6807 if (os::is_MP())
6808 lock();
6809 cmpxchgptr(reg, Address(rscratch1, 0));
6810 }
6811 }
6813 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
6814 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
6815 }
6817 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
6818 if (reachable(src)) {
6819 Assembler::comisd(dst, as_Address(src));
6820 } else {
6821 lea(rscratch1, src);
6822 Assembler::comisd(dst, Address(rscratch1, 0));
6823 }
6824 }
6826 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
6827 if (reachable(src)) {
6828 Assembler::comiss(dst, as_Address(src));
6829 } else {
6830 lea(rscratch1, src);
6831 Assembler::comiss(dst, Address(rscratch1, 0));
6832 }
6833 }
6836 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
6837 Condition negated_cond = negate_condition(cond);
6838 Label L;
6839 jcc(negated_cond, L);
6840 atomic_incl(counter_addr);
6841 bind(L);
6842 }
6844 int MacroAssembler::corrected_idivl(Register reg) {
6845 // Full implementation of Java idiv and irem; checks for
6846 // special case as described in JVM spec., p.243 & p.271.
6847 // The function returns the (pc) offset of the idivl
6848 // instruction - may be needed for implicit exceptions.
6849 //
6850 // normal case special case
6851 //
6852 // input : rax,: dividend min_int
6853 // reg: divisor (may not be rax,/rdx) -1
6854 //
6855 // output: rax,: quotient (= rax, idiv reg) min_int
6856 // rdx: remainder (= rax, irem reg) 0
6857 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
6858 const int min_int = 0x80000000;
6859 Label normal_case, special_case;
6861 // check for special case
6862 cmpl(rax, min_int);
6863 jcc(Assembler::notEqual, normal_case);
6864 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
6865 cmpl(reg, -1);
6866 jcc(Assembler::equal, special_case);
6868 // handle normal case
6869 bind(normal_case);
6870 cdql();
6871 int idivl_offset = offset();
6872 idivl(reg);
6874 // normal and special case exit
6875 bind(special_case);
6877 return idivl_offset;
6878 }
6882 void MacroAssembler::decrementl(Register reg, int value) {
6883 if (value == min_jint) {subl(reg, value) ; return; }
6884 if (value < 0) { incrementl(reg, -value); return; }
6885 if (value == 0) { ; return; }
6886 if (value == 1 && UseIncDec) { decl(reg) ; return; }
6887 /* else */ { subl(reg, value) ; return; }
6888 }
6890 void MacroAssembler::decrementl(Address dst, int value) {
6891 if (value == min_jint) {subl(dst, value) ; return; }
6892 if (value < 0) { incrementl(dst, -value); return; }
6893 if (value == 0) { ; return; }
6894 if (value == 1 && UseIncDec) { decl(dst) ; return; }
6895 /* else */ { subl(dst, value) ; return; }
6896 }
6898 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
6899 assert (shift_value > 0, "illegal shift value");
6900 Label _is_positive;
6901 testl (reg, reg);
6902 jcc (Assembler::positive, _is_positive);
6903 int offset = (1 << shift_value) - 1 ;
6905 if (offset == 1) {
6906 incrementl(reg);
6907 } else {
6908 addl(reg, offset);
6909 }
6911 bind (_is_positive);
6912 sarl(reg, shift_value);
6913 }
6915 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
6916 if (reachable(src)) {
6917 Assembler::divsd(dst, as_Address(src));
6918 } else {
6919 lea(rscratch1, src);
6920 Assembler::divsd(dst, Address(rscratch1, 0));
6921 }
6922 }
6924 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
6925 if (reachable(src)) {
6926 Assembler::divss(dst, as_Address(src));
6927 } else {
6928 lea(rscratch1, src);
6929 Assembler::divss(dst, Address(rscratch1, 0));
6930 }
6931 }
6933 // !defined(COMPILER2) is because of stupid core builds
6934 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
6935 void MacroAssembler::empty_FPU_stack() {
6936 if (VM_Version::supports_mmx()) {
6937 emms();
6938 } else {
6939 for (int i = 8; i-- > 0; ) ffree(i);
6940 }
6941 }
6942 #endif // !LP64 || C1 || !C2
6945 // Defines obj, preserves var_size_in_bytes
6946 void MacroAssembler::eden_allocate(Register obj,
6947 Register var_size_in_bytes,
6948 int con_size_in_bytes,
6949 Register t1,
6950 Label& slow_case) {
6951 assert(obj == rax, "obj must be in rax, for cmpxchg");
6952 assert_different_registers(obj, var_size_in_bytes, t1);
6953 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
6954 jmp(slow_case);
6955 } else {
6956 Register end = t1;
6957 Label retry;
6958 bind(retry);
6959 ExternalAddress heap_top((address) Universe::heap()->top_addr());
6960 movptr(obj, heap_top);
6961 if (var_size_in_bytes == noreg) {
6962 lea(end, Address(obj, con_size_in_bytes));
6963 } else {
6964 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
6965 }
6966 // if end < obj then we wrapped around => object too long => slow case
6967 cmpptr(end, obj);
6968 jcc(Assembler::below, slow_case);
6969 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
6970 jcc(Assembler::above, slow_case);
6971 // Compare obj with the top addr, and if still equal, store the new top addr in
6972 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
6973 // it otherwise. Use lock prefix for atomicity on MPs.
6974 locked_cmpxchgptr(end, heap_top);
6975 jcc(Assembler::notEqual, retry);
6976 }
6977 }
6979 void MacroAssembler::enter() {
6980 push(rbp);
6981 mov(rbp, rsp);
6982 }
6984 // A 5 byte nop that is safe for patching (see patch_verified_entry)
6985 void MacroAssembler::fat_nop() {
6986 if (UseAddressNop) {
6987 addr_nop_5();
6988 } else {
6989 emit_byte(0x26); // es:
6990 emit_byte(0x2e); // cs:
6991 emit_byte(0x64); // fs:
6992 emit_byte(0x65); // gs:
6993 emit_byte(0x90);
6994 }
6995 }
6997 void MacroAssembler::fcmp(Register tmp) {
6998 fcmp(tmp, 1, true, true);
6999 }
7001 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
7002 assert(!pop_right || pop_left, "usage error");
7003 if (VM_Version::supports_cmov()) {
7004 assert(tmp == noreg, "unneeded temp");
7005 if (pop_left) {
7006 fucomip(index);
7007 } else {
7008 fucomi(index);
7009 }
7010 if (pop_right) {
7011 fpop();
7012 }
7013 } else {
7014 assert(tmp != noreg, "need temp");
7015 if (pop_left) {
7016 if (pop_right) {
7017 fcompp();
7018 } else {
7019 fcomp(index);
7020 }
7021 } else {
7022 fcom(index);
7023 }
7024 // convert FPU condition into eflags condition via rax,
7025 save_rax(tmp);
7026 fwait(); fnstsw_ax();
7027 sahf();
7028 restore_rax(tmp);
7029 }
7030 // condition codes set as follows:
7031 //
7032 // CF (corresponds to C0) if x < y
7033 // PF (corresponds to C2) if unordered
7034 // ZF (corresponds to C3) if x = y
7035 }
7037 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
7038 fcmp2int(dst, unordered_is_less, 1, true, true);
7039 }
7041 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
7042 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
7043 Label L;
7044 if (unordered_is_less) {
7045 movl(dst, -1);
7046 jcc(Assembler::parity, L);
7047 jcc(Assembler::below , L);
7048 movl(dst, 0);
7049 jcc(Assembler::equal , L);
7050 increment(dst);
7051 } else { // unordered is greater
7052 movl(dst, 1);
7053 jcc(Assembler::parity, L);
7054 jcc(Assembler::above , L);
7055 movl(dst, 0);
7056 jcc(Assembler::equal , L);
7057 decrementl(dst);
7058 }
7059 bind(L);
7060 }
7062 void MacroAssembler::fld_d(AddressLiteral src) {
7063 fld_d(as_Address(src));
7064 }
7066 void MacroAssembler::fld_s(AddressLiteral src) {
7067 fld_s(as_Address(src));
7068 }
7070 void MacroAssembler::fld_x(AddressLiteral src) {
7071 Assembler::fld_x(as_Address(src));
7072 }
7074 void MacroAssembler::fldcw(AddressLiteral src) {
7075 Assembler::fldcw(as_Address(src));
7076 }
7078 void MacroAssembler::pow_exp_core_encoding() {
7079 // kills rax, rcx, rdx
7080 subptr(rsp,sizeof(jdouble));
7081 // computes 2^X. Stack: X ...
7082 // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and
7083 // keep it on the thread's stack to compute 2^int(X) later
7084 // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1)
7085 // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X))
7086 fld_s(0); // Stack: X X ...
7087 frndint(); // Stack: int(X) X ...
7088 fsuba(1); // Stack: int(X) X-int(X) ...
7089 fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ...
7090 f2xm1(); // Stack: 2^(X-int(X))-1 ...
7091 fld1(); // Stack: 1 2^(X-int(X))-1 ...
7092 faddp(1); // Stack: 2^(X-int(X))
7093 // computes 2^(int(X)): add exponent bias (1023) to int(X), then
7094 // shift int(X)+1023 to exponent position.
7095 // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11
7096 // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent
7097 // values so detect them and set result to NaN.
7098 movl(rax,Address(rsp,0));
7099 movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding
7100 addl(rax, 1023);
7101 movl(rdx,rax);
7102 shll(rax,20);
7103 // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN.
7104 addl(rdx,1);
7105 // Check that 1 < int(X)+1023+1 < 2048
7106 // in 3 steps:
7107 // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048
7108 // 2- (int(X)+1023+1)&-2048 != 0
7109 // 3- (int(X)+1023+1)&-2048 != 1
7110 // Do 2- first because addl just updated the flags.
7111 cmov32(Assembler::equal,rax,rcx);
7112 cmpl(rdx,1);
7113 cmov32(Assembler::equal,rax,rcx);
7114 testl(rdx,rcx);
7115 cmov32(Assembler::notEqual,rax,rcx);
7116 movl(Address(rsp,4),rax);
7117 movl(Address(rsp,0),0);
7118 fmul_d(Address(rsp,0)); // Stack: 2^X ...
7119 addptr(rsp,sizeof(jdouble));
7120 }
7122 void MacroAssembler::increase_precision() {
7123 subptr(rsp, BytesPerWord);
7124 fnstcw(Address(rsp, 0));
7125 movl(rax, Address(rsp, 0));
7126 orl(rax, 0x300);
7127 push(rax);
7128 fldcw(Address(rsp, 0));
7129 pop(rax);
7130 }
7132 void MacroAssembler::restore_precision() {
7133 fldcw(Address(rsp, 0));
7134 addptr(rsp, BytesPerWord);
7135 }
7137 void MacroAssembler::fast_pow() {
7138 // computes X^Y = 2^(Y * log2(X))
7139 // if fast computation is not possible, result is NaN. Requires
7140 // fallback from user of this macro.
7141 // increase precision for intermediate steps of the computation
7142 increase_precision();
7143 fyl2x(); // Stack: (Y*log2(X)) ...
7144 pow_exp_core_encoding(); // Stack: exp(X) ...
7145 restore_precision();
7146 }
7148 void MacroAssembler::fast_exp() {
7149 // computes exp(X) = 2^(X * log2(e))
7150 // if fast computation is not possible, result is NaN. Requires
7151 // fallback from user of this macro.
7152 // increase precision for intermediate steps of the computation
7153 increase_precision();
7154 fldl2e(); // Stack: log2(e) X ...
7155 fmulp(1); // Stack: (X*log2(e)) ...
7156 pow_exp_core_encoding(); // Stack: exp(X) ...
7157 restore_precision();
7158 }
7160 void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) {
7161 // kills rax, rcx, rdx
7162 // pow and exp needs 2 extra registers on the fpu stack.
7163 Label slow_case, done;
7164 Register tmp = noreg;
7165 if (!VM_Version::supports_cmov()) {
7166 // fcmp needs a temporary so preserve rdx,
7167 tmp = rdx;
7168 }
7169 Register tmp2 = rax;
7170 Register tmp3 = rcx;
7172 if (is_exp) {
7173 // Stack: X
7174 fld_s(0); // duplicate argument for runtime call. Stack: X X
7175 fast_exp(); // Stack: exp(X) X
7176 fcmp(tmp, 0, false, false); // Stack: exp(X) X
7177 // exp(X) not equal to itself: exp(X) is NaN go to slow case.
7178 jcc(Assembler::parity, slow_case);
7179 // get rid of duplicate argument. Stack: exp(X)
7180 if (num_fpu_regs_in_use > 0) {
7181 fxch();
7182 fpop();
7183 } else {
7184 ffree(1);
7185 }
7186 jmp(done);
7187 } else {
7188 // Stack: X Y
7189 Label x_negative, y_odd;
7191 fldz(); // Stack: 0 X Y
7192 fcmp(tmp, 1, true, false); // Stack: X Y
7193 jcc(Assembler::above, x_negative);
7195 // X >= 0
7197 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
7198 fld_s(1); // Stack: X Y X Y
7199 fast_pow(); // Stack: X^Y X Y
7200 fcmp(tmp, 0, false, false); // Stack: X^Y X Y
7201 // X^Y not equal to itself: X^Y is NaN go to slow case.
7202 jcc(Assembler::parity, slow_case);
7203 // get rid of duplicate arguments. Stack: X^Y
7204 if (num_fpu_regs_in_use > 0) {
7205 fxch(); fpop();
7206 fxch(); fpop();
7207 } else {
7208 ffree(2);
7209 ffree(1);
7210 }
7211 jmp(done);
7213 // X <= 0
7214 bind(x_negative);
7216 fld_s(1); // Stack: Y X Y
7217 frndint(); // Stack: int(Y) X Y
7218 fcmp(tmp, 2, false, false); // Stack: int(Y) X Y
7219 jcc(Assembler::notEqual, slow_case);
7221 subptr(rsp, 8);
7223 // For X^Y, when X < 0, Y has to be an integer and the final
7224 // result depends on whether it's odd or even. We just checked
7225 // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit
7226 // integer to test its parity. If int(Y) is huge and doesn't fit
7227 // in the 64 bit integer range, the integer indefinite value will
7228 // end up in the gp registers. Huge numbers are all even, the
7229 // integer indefinite number is even so it's fine.
7231 #ifdef ASSERT
7232 // Let's check we don't end up with an integer indefinite number
7233 // when not expected. First test for huge numbers: check whether
7234 // int(Y)+1 == int(Y) which is true for very large numbers and
7235 // those are all even. A 64 bit integer is guaranteed to not
7236 // overflow for numbers where y+1 != y (when precision is set to
7237 // double precision).
7238 Label y_not_huge;
7240 fld1(); // Stack: 1 int(Y) X Y
7241 fadd(1); // Stack: 1+int(Y) int(Y) X Y
7243 #ifdef _LP64
7244 // trip to memory to force the precision down from double extended
7245 // precision
7246 fstp_d(Address(rsp, 0));
7247 fld_d(Address(rsp, 0));
7248 #endif
7250 fcmp(tmp, 1, true, false); // Stack: int(Y) X Y
7251 #endif
7253 // move int(Y) as 64 bit integer to thread's stack
7254 fistp_d(Address(rsp,0)); // Stack: X Y
7256 #ifdef ASSERT
7257 jcc(Assembler::notEqual, y_not_huge);
7259 // Y is huge so we know it's even. It may not fit in a 64 bit
7260 // integer and we don't want the debug code below to see the
7261 // integer indefinite value so overwrite int(Y) on the thread's
7262 // stack with 0.
7263 movl(Address(rsp, 0), 0);
7264 movl(Address(rsp, 4), 0);
7266 bind(y_not_huge);
7267 #endif
7269 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
7270 fld_s(1); // Stack: X Y X Y
7271 fabs(); // Stack: abs(X) Y X Y
7272 fast_pow(); // Stack: abs(X)^Y X Y
7273 fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y
7274 // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case.
7276 pop(tmp2);
7277 NOT_LP64(pop(tmp3));
7278 jcc(Assembler::parity, slow_case);
7280 #ifdef ASSERT
7281 // Check that int(Y) is not integer indefinite value (int
7282 // overflow). Shouldn't happen because for values that would
7283 // overflow, 1+int(Y)==Y which was tested earlier.
7284 #ifndef _LP64
7285 {
7286 Label integer;
7287 testl(tmp2, tmp2);
7288 jcc(Assembler::notZero, integer);
7289 cmpl(tmp3, 0x80000000);
7290 jcc(Assembler::notZero, integer);
7291 STOP("integer indefinite value shouldn't be seen here");
7292 bind(integer);
7293 }
7294 #else
7295 {
7296 Label integer;
7297 mov(tmp3, tmp2); // preserve tmp2 for parity check below
7298 shlq(tmp3, 1);
7299 jcc(Assembler::carryClear, integer);
7300 jcc(Assembler::notZero, integer);
7301 STOP("integer indefinite value shouldn't be seen here");
7302 bind(integer);
7303 }
7304 #endif
7305 #endif
7307 // get rid of duplicate arguments. Stack: X^Y
7308 if (num_fpu_regs_in_use > 0) {
7309 fxch(); fpop();
7310 fxch(); fpop();
7311 } else {
7312 ffree(2);
7313 ffree(1);
7314 }
7316 testl(tmp2, 1);
7317 jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y
7318 // X <= 0, Y even: X^Y = -abs(X)^Y
7320 fchs(); // Stack: -abs(X)^Y Y
7321 jmp(done);
7322 }
7324 // slow case: runtime call
7325 bind(slow_case);
7327 fpop(); // pop incorrect result or int(Y)
7329 fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow),
7330 is_exp ? 1 : 2, num_fpu_regs_in_use);
7332 // Come here with result in F-TOS
7333 bind(done);
7334 }
7336 void MacroAssembler::fpop() {
7337 ffree();
7338 fincstp();
7339 }
7341 void MacroAssembler::fremr(Register tmp) {
7342 save_rax(tmp);
7343 { Label L;
7344 bind(L);
7345 fprem();
7346 fwait(); fnstsw_ax();
7347 #ifdef _LP64
7348 testl(rax, 0x400);
7349 jcc(Assembler::notEqual, L);
7350 #else
7351 sahf();
7352 jcc(Assembler::parity, L);
7353 #endif // _LP64
7354 }
7355 restore_rax(tmp);
7356 // Result is in ST0.
7357 // Note: fxch & fpop to get rid of ST1
7358 // (otherwise FPU stack could overflow eventually)
7359 fxch(1);
7360 fpop();
7361 }
7364 void MacroAssembler::incrementl(AddressLiteral dst) {
7365 if (reachable(dst)) {
7366 incrementl(as_Address(dst));
7367 } else {
7368 lea(rscratch1, dst);
7369 incrementl(Address(rscratch1, 0));
7370 }
7371 }
7373 void MacroAssembler::incrementl(ArrayAddress dst) {
7374 incrementl(as_Address(dst));
7375 }
7377 void MacroAssembler::incrementl(Register reg, int value) {
7378 if (value == min_jint) {addl(reg, value) ; return; }
7379 if (value < 0) { decrementl(reg, -value); return; }
7380 if (value == 0) { ; return; }
7381 if (value == 1 && UseIncDec) { incl(reg) ; return; }
7382 /* else */ { addl(reg, value) ; return; }
7383 }
7385 void MacroAssembler::incrementl(Address dst, int value) {
7386 if (value == min_jint) {addl(dst, value) ; return; }
7387 if (value < 0) { decrementl(dst, -value); return; }
7388 if (value == 0) { ; return; }
7389 if (value == 1 && UseIncDec) { incl(dst) ; return; }
7390 /* else */ { addl(dst, value) ; return; }
7391 }
7393 void MacroAssembler::jump(AddressLiteral dst) {
7394 if (reachable(dst)) {
7395 jmp_literal(dst.target(), dst.rspec());
7396 } else {
7397 lea(rscratch1, dst);
7398 jmp(rscratch1);
7399 }
7400 }
7402 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
7403 if (reachable(dst)) {
7404 InstructionMark im(this);
7405 relocate(dst.reloc());
7406 const int short_size = 2;
7407 const int long_size = 6;
7408 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos);
7409 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
7410 // 0111 tttn #8-bit disp
7411 emit_byte(0x70 | cc);
7412 emit_byte((offs - short_size) & 0xFF);
7413 } else {
7414 // 0000 1111 1000 tttn #32-bit disp
7415 emit_byte(0x0F);
7416 emit_byte(0x80 | cc);
7417 emit_long(offs - long_size);
7418 }
7419 } else {
7420 #ifdef ASSERT
7421 warning("reversing conditional branch");
7422 #endif /* ASSERT */
7423 Label skip;
7424 jccb(reverse[cc], skip);
7425 lea(rscratch1, dst);
7426 Assembler::jmp(rscratch1);
7427 bind(skip);
7428 }
7429 }
7431 void MacroAssembler::ldmxcsr(AddressLiteral src) {
7432 if (reachable(src)) {
7433 Assembler::ldmxcsr(as_Address(src));
7434 } else {
7435 lea(rscratch1, src);
7436 Assembler::ldmxcsr(Address(rscratch1, 0));
7437 }
7438 }
7440 int MacroAssembler::load_signed_byte(Register dst, Address src) {
7441 int off;
7442 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
7443 off = offset();
7444 movsbl(dst, src); // movsxb
7445 } else {
7446 off = load_unsigned_byte(dst, src);
7447 shll(dst, 24);
7448 sarl(dst, 24);
7449 }
7450 return off;
7451 }
7453 // Note: load_signed_short used to be called load_signed_word.
7454 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
7455 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
7456 // The term "word" in HotSpot means a 32- or 64-bit machine word.
7457 int MacroAssembler::load_signed_short(Register dst, Address src) {
7458 int off;
7459 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
7460 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
7461 // version but this is what 64bit has always done. This seems to imply
7462 // that users are only using 32bits worth.
7463 off = offset();
7464 movswl(dst, src); // movsxw
7465 } else {
7466 off = load_unsigned_short(dst, src);
7467 shll(dst, 16);
7468 sarl(dst, 16);
7469 }
7470 return off;
7471 }
7473 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
7474 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
7475 // and "3.9 Partial Register Penalties", p. 22).
7476 int off;
7477 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
7478 off = offset();
7479 movzbl(dst, src); // movzxb
7480 } else {
7481 xorl(dst, dst);
7482 off = offset();
7483 movb(dst, src);
7484 }
7485 return off;
7486 }
7488 // Note: load_unsigned_short used to be called load_unsigned_word.
7489 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
7490 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
7491 // and "3.9 Partial Register Penalties", p. 22).
7492 int off;
7493 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
7494 off = offset();
7495 movzwl(dst, src); // movzxw
7496 } else {
7497 xorl(dst, dst);
7498 off = offset();
7499 movw(dst, src);
7500 }
7501 return off;
7502 }
7504 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
7505 switch (size_in_bytes) {
7506 #ifndef _LP64
7507 case 8:
7508 assert(dst2 != noreg, "second dest register required");
7509 movl(dst, src);
7510 movl(dst2, src.plus_disp(BytesPerInt));
7511 break;
7512 #else
7513 case 8: movq(dst, src); break;
7514 #endif
7515 case 4: movl(dst, src); break;
7516 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
7517 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
7518 default: ShouldNotReachHere();
7519 }
7520 }
7522 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
7523 switch (size_in_bytes) {
7524 #ifndef _LP64
7525 case 8:
7526 assert(src2 != noreg, "second source register required");
7527 movl(dst, src);
7528 movl(dst.plus_disp(BytesPerInt), src2);
7529 break;
7530 #else
7531 case 8: movq(dst, src); break;
7532 #endif
7533 case 4: movl(dst, src); break;
7534 case 2: movw(dst, src); break;
7535 case 1: movb(dst, src); break;
7536 default: ShouldNotReachHere();
7537 }
7538 }
7540 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
7541 if (reachable(dst)) {
7542 movl(as_Address(dst), src);
7543 } else {
7544 lea(rscratch1, dst);
7545 movl(Address(rscratch1, 0), src);
7546 }
7547 }
7549 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
7550 if (reachable(src)) {
7551 movl(dst, as_Address(src));
7552 } else {
7553 lea(rscratch1, src);
7554 movl(dst, Address(rscratch1, 0));
7555 }
7556 }
7558 // C++ bool manipulation
7560 void MacroAssembler::movbool(Register dst, Address src) {
7561 if(sizeof(bool) == 1)
7562 movb(dst, src);
7563 else if(sizeof(bool) == 2)
7564 movw(dst, src);
7565 else if(sizeof(bool) == 4)
7566 movl(dst, src);
7567 else
7568 // unsupported
7569 ShouldNotReachHere();
7570 }
7572 void MacroAssembler::movbool(Address dst, bool boolconst) {
7573 if(sizeof(bool) == 1)
7574 movb(dst, (int) boolconst);
7575 else if(sizeof(bool) == 2)
7576 movw(dst, (int) boolconst);
7577 else if(sizeof(bool) == 4)
7578 movl(dst, (int) boolconst);
7579 else
7580 // unsupported
7581 ShouldNotReachHere();
7582 }
7584 void MacroAssembler::movbool(Address dst, Register src) {
7585 if(sizeof(bool) == 1)
7586 movb(dst, src);
7587 else if(sizeof(bool) == 2)
7588 movw(dst, src);
7589 else if(sizeof(bool) == 4)
7590 movl(dst, src);
7591 else
7592 // unsupported
7593 ShouldNotReachHere();
7594 }
7596 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
7597 movb(as_Address(dst), src);
7598 }
7600 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
7601 if (reachable(src)) {
7602 movdl(dst, as_Address(src));
7603 } else {
7604 lea(rscratch1, src);
7605 movdl(dst, Address(rscratch1, 0));
7606 }
7607 }
7609 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
7610 if (reachable(src)) {
7611 movq(dst, as_Address(src));
7612 } else {
7613 lea(rscratch1, src);
7614 movq(dst, Address(rscratch1, 0));
7615 }
7616 }
7618 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
7619 if (reachable(src)) {
7620 if (UseXmmLoadAndClearUpper) {
7621 movsd (dst, as_Address(src));
7622 } else {
7623 movlpd(dst, as_Address(src));
7624 }
7625 } else {
7626 lea(rscratch1, src);
7627 if (UseXmmLoadAndClearUpper) {
7628 movsd (dst, Address(rscratch1, 0));
7629 } else {
7630 movlpd(dst, Address(rscratch1, 0));
7631 }
7632 }
7633 }
7635 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
7636 if (reachable(src)) {
7637 movss(dst, as_Address(src));
7638 } else {
7639 lea(rscratch1, src);
7640 movss(dst, Address(rscratch1, 0));
7641 }
7642 }
7644 void MacroAssembler::movptr(Register dst, Register src) {
7645 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
7646 }
7648 void MacroAssembler::movptr(Register dst, Address src) {
7649 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
7650 }
7652 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
7653 void MacroAssembler::movptr(Register dst, intptr_t src) {
7654 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
7655 }
7657 void MacroAssembler::movptr(Address dst, Register src) {
7658 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
7659 }
7661 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
7662 if (reachable(src)) {
7663 Assembler::movsd(dst, as_Address(src));
7664 } else {
7665 lea(rscratch1, src);
7666 Assembler::movsd(dst, Address(rscratch1, 0));
7667 }
7668 }
7670 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
7671 if (reachable(src)) {
7672 Assembler::movss(dst, as_Address(src));
7673 } else {
7674 lea(rscratch1, src);
7675 Assembler::movss(dst, Address(rscratch1, 0));
7676 }
7677 }
7679 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
7680 if (reachable(src)) {
7681 Assembler::mulsd(dst, as_Address(src));
7682 } else {
7683 lea(rscratch1, src);
7684 Assembler::mulsd(dst, Address(rscratch1, 0));
7685 }
7686 }
7688 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
7689 if (reachable(src)) {
7690 Assembler::mulss(dst, as_Address(src));
7691 } else {
7692 lea(rscratch1, src);
7693 Assembler::mulss(dst, Address(rscratch1, 0));
7694 }
7695 }
7697 void MacroAssembler::null_check(Register reg, int offset) {
7698 if (needs_explicit_null_check(offset)) {
7699 // provoke OS NULL exception if reg = NULL by
7700 // accessing M[reg] w/o changing any (non-CC) registers
7701 // NOTE: cmpl is plenty here to provoke a segv
7702 cmpptr(rax, Address(reg, 0));
7703 // Note: should probably use testl(rax, Address(reg, 0));
7704 // may be shorter code (however, this version of
7705 // testl needs to be implemented first)
7706 } else {
7707 // nothing to do, (later) access of M[reg + offset]
7708 // will provoke OS NULL exception if reg = NULL
7709 }
7710 }
7712 void MacroAssembler::os_breakpoint() {
7713 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
7714 // (e.g., MSVC can't call ps() otherwise)
7715 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
7716 }
7718 void MacroAssembler::pop_CPU_state() {
7719 pop_FPU_state();
7720 pop_IU_state();
7721 }
7723 void MacroAssembler::pop_FPU_state() {
7724 NOT_LP64(frstor(Address(rsp, 0));)
7725 LP64_ONLY(fxrstor(Address(rsp, 0));)
7726 addptr(rsp, FPUStateSizeInWords * wordSize);
7727 }
7729 void MacroAssembler::pop_IU_state() {
7730 popa();
7731 LP64_ONLY(addq(rsp, 8));
7732 popf();
7733 }
7735 // Save Integer and Float state
7736 // Warning: Stack must be 16 byte aligned (64bit)
7737 void MacroAssembler::push_CPU_state() {
7738 push_IU_state();
7739 push_FPU_state();
7740 }
7742 void MacroAssembler::push_FPU_state() {
7743 subptr(rsp, FPUStateSizeInWords * wordSize);
7744 #ifndef _LP64
7745 fnsave(Address(rsp, 0));
7746 fwait();
7747 #else
7748 fxsave(Address(rsp, 0));
7749 #endif // LP64
7750 }
7752 void MacroAssembler::push_IU_state() {
7753 // Push flags first because pusha kills them
7754 pushf();
7755 // Make sure rsp stays 16-byte aligned
7756 LP64_ONLY(subq(rsp, 8));
7757 pusha();
7758 }
7760 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
7761 // determine java_thread register
7762 if (!java_thread->is_valid()) {
7763 java_thread = rdi;
7764 get_thread(java_thread);
7765 }
7766 // we must set sp to zero to clear frame
7767 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
7768 if (clear_fp) {
7769 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
7770 }
7772 if (clear_pc)
7773 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
7775 }
7777 void MacroAssembler::restore_rax(Register tmp) {
7778 if (tmp == noreg) pop(rax);
7779 else if (tmp != rax) mov(rax, tmp);
7780 }
7782 void MacroAssembler::round_to(Register reg, int modulus) {
7783 addptr(reg, modulus - 1);
7784 andptr(reg, -modulus);
7785 }
7787 void MacroAssembler::save_rax(Register tmp) {
7788 if (tmp == noreg) push(rax);
7789 else if (tmp != rax) mov(tmp, rax);
7790 }
7792 // Write serialization page so VM thread can do a pseudo remote membar.
7793 // We use the current thread pointer to calculate a thread specific
7794 // offset to write to within the page. This minimizes bus traffic
7795 // due to cache line collision.
7796 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
7797 movl(tmp, thread);
7798 shrl(tmp, os::get_serialize_page_shift_count());
7799 andl(tmp, (os::vm_page_size() - sizeof(int)));
7801 Address index(noreg, tmp, Address::times_1);
7802 ExternalAddress page(os::get_memory_serialize_page());
7804 // Size of store must match masking code above
7805 movl(as_Address(ArrayAddress(page, index)), tmp);
7806 }
7808 // Calls to C land
7809 //
7810 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
7811 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
7812 // has to be reset to 0. This is required to allow proper stack traversal.
7813 void MacroAssembler::set_last_Java_frame(Register java_thread,
7814 Register last_java_sp,
7815 Register last_java_fp,
7816 address last_java_pc) {
7817 // determine java_thread register
7818 if (!java_thread->is_valid()) {
7819 java_thread = rdi;
7820 get_thread(java_thread);
7821 }
7822 // determine last_java_sp register
7823 if (!last_java_sp->is_valid()) {
7824 last_java_sp = rsp;
7825 }
7827 // last_java_fp is optional
7829 if (last_java_fp->is_valid()) {
7830 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
7831 }
7833 // last_java_pc is optional
7835 if (last_java_pc != NULL) {
7836 lea(Address(java_thread,
7837 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
7838 InternalAddress(last_java_pc));
7840 }
7841 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
7842 }
7844 void MacroAssembler::shlptr(Register dst, int imm8) {
7845 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
7846 }
7848 void MacroAssembler::shrptr(Register dst, int imm8) {
7849 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
7850 }
7852 void MacroAssembler::sign_extend_byte(Register reg) {
7853 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
7854 movsbl(reg, reg); // movsxb
7855 } else {
7856 shll(reg, 24);
7857 sarl(reg, 24);
7858 }
7859 }
7861 void MacroAssembler::sign_extend_short(Register reg) {
7862 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
7863 movswl(reg, reg); // movsxw
7864 } else {
7865 shll(reg, 16);
7866 sarl(reg, 16);
7867 }
7868 }
7870 void MacroAssembler::testl(Register dst, AddressLiteral src) {
7871 assert(reachable(src), "Address should be reachable");
7872 testl(dst, as_Address(src));
7873 }
7875 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
7876 if (reachable(src)) {
7877 Assembler::sqrtsd(dst, as_Address(src));
7878 } else {
7879 lea(rscratch1, src);
7880 Assembler::sqrtsd(dst, Address(rscratch1, 0));
7881 }
7882 }
7884 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
7885 if (reachable(src)) {
7886 Assembler::sqrtss(dst, as_Address(src));
7887 } else {
7888 lea(rscratch1, src);
7889 Assembler::sqrtss(dst, Address(rscratch1, 0));
7890 }
7891 }
7893 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
7894 if (reachable(src)) {
7895 Assembler::subsd(dst, as_Address(src));
7896 } else {
7897 lea(rscratch1, src);
7898 Assembler::subsd(dst, Address(rscratch1, 0));
7899 }
7900 }
7902 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
7903 if (reachable(src)) {
7904 Assembler::subss(dst, as_Address(src));
7905 } else {
7906 lea(rscratch1, src);
7907 Assembler::subss(dst, Address(rscratch1, 0));
7908 }
7909 }
7911 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
7912 if (reachable(src)) {
7913 Assembler::ucomisd(dst, as_Address(src));
7914 } else {
7915 lea(rscratch1, src);
7916 Assembler::ucomisd(dst, Address(rscratch1, 0));
7917 }
7918 }
7920 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
7921 if (reachable(src)) {
7922 Assembler::ucomiss(dst, as_Address(src));
7923 } else {
7924 lea(rscratch1, src);
7925 Assembler::ucomiss(dst, Address(rscratch1, 0));
7926 }
7927 }
7929 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
7930 // Used in sign-bit flipping with aligned address.
7931 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
7932 if (reachable(src)) {
7933 Assembler::xorpd(dst, as_Address(src));
7934 } else {
7935 lea(rscratch1, src);
7936 Assembler::xorpd(dst, Address(rscratch1, 0));
7937 }
7938 }
7940 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
7941 // Used in sign-bit flipping with aligned address.
7942 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
7943 if (reachable(src)) {
7944 Assembler::xorps(dst, as_Address(src));
7945 } else {
7946 lea(rscratch1, src);
7947 Assembler::xorps(dst, Address(rscratch1, 0));
7948 }
7949 }
7951 // AVX 3-operands instructions
7953 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7954 if (reachable(src)) {
7955 vaddsd(dst, nds, as_Address(src));
7956 } else {
7957 lea(rscratch1, src);
7958 vaddsd(dst, nds, Address(rscratch1, 0));
7959 }
7960 }
7962 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7963 if (reachable(src)) {
7964 vaddss(dst, nds, as_Address(src));
7965 } else {
7966 lea(rscratch1, src);
7967 vaddss(dst, nds, Address(rscratch1, 0));
7968 }
7969 }
7971 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7972 if (reachable(src)) {
7973 vandpd(dst, nds, as_Address(src));
7974 } else {
7975 lea(rscratch1, src);
7976 vandpd(dst, nds, Address(rscratch1, 0));
7977 }
7978 }
7980 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7981 if (reachable(src)) {
7982 vandps(dst, nds, as_Address(src));
7983 } else {
7984 lea(rscratch1, src);
7985 vandps(dst, nds, Address(rscratch1, 0));
7986 }
7987 }
7989 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7990 if (reachable(src)) {
7991 vdivsd(dst, nds, as_Address(src));
7992 } else {
7993 lea(rscratch1, src);
7994 vdivsd(dst, nds, Address(rscratch1, 0));
7995 }
7996 }
7998 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7999 if (reachable(src)) {
8000 vdivss(dst, nds, as_Address(src));
8001 } else {
8002 lea(rscratch1, src);
8003 vdivss(dst, nds, Address(rscratch1, 0));
8004 }
8005 }
8007 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
8008 if (reachable(src)) {
8009 vmulsd(dst, nds, as_Address(src));
8010 } else {
8011 lea(rscratch1, src);
8012 vmulsd(dst, nds, Address(rscratch1, 0));
8013 }
8014 }
8016 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
8017 if (reachable(src)) {
8018 vmulss(dst, nds, as_Address(src));
8019 } else {
8020 lea(rscratch1, src);
8021 vmulss(dst, nds, Address(rscratch1, 0));
8022 }
8023 }
8025 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
8026 if (reachable(src)) {
8027 vsubsd(dst, nds, as_Address(src));
8028 } else {
8029 lea(rscratch1, src);
8030 vsubsd(dst, nds, Address(rscratch1, 0));
8031 }
8032 }
8034 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
8035 if (reachable(src)) {
8036 vsubss(dst, nds, as_Address(src));
8037 } else {
8038 lea(rscratch1, src);
8039 vsubss(dst, nds, Address(rscratch1, 0));
8040 }
8041 }
8043 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
8044 if (reachable(src)) {
8045 vxorpd(dst, nds, as_Address(src));
8046 } else {
8047 lea(rscratch1, src);
8048 vxorpd(dst, nds, Address(rscratch1, 0));
8049 }
8050 }
8052 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
8053 if (reachable(src)) {
8054 vxorps(dst, nds, as_Address(src));
8055 } else {
8056 lea(rscratch1, src);
8057 vxorps(dst, nds, Address(rscratch1, 0));
8058 }
8059 }
8062 //////////////////////////////////////////////////////////////////////////////////
8063 #ifndef SERIALGC
8065 void MacroAssembler::g1_write_barrier_pre(Register obj,
8066 Register pre_val,
8067 Register thread,
8068 Register tmp,
8069 bool tosca_live,
8070 bool expand_call) {
8072 // If expand_call is true then we expand the call_VM_leaf macro
8073 // directly to skip generating the check by
8074 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
8076 #ifdef _LP64
8077 assert(thread == r15_thread, "must be");
8078 #endif // _LP64
8080 Label done;
8081 Label runtime;
8083 assert(pre_val != noreg, "check this code");
8085 if (obj != noreg) {
8086 assert_different_registers(obj, pre_val, tmp);
8087 assert(pre_val != rax, "check this code");
8088 }
8090 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
8091 PtrQueue::byte_offset_of_active()));
8092 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
8093 PtrQueue::byte_offset_of_index()));
8094 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
8095 PtrQueue::byte_offset_of_buf()));
8098 // Is marking active?
8099 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
8100 cmpl(in_progress, 0);
8101 } else {
8102 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
8103 cmpb(in_progress, 0);
8104 }
8105 jcc(Assembler::equal, done);
8107 // Do we need to load the previous value?
8108 if (obj != noreg) {
8109 load_heap_oop(pre_val, Address(obj, 0));
8110 }
8112 // Is the previous value null?
8113 cmpptr(pre_val, (int32_t) NULL_WORD);
8114 jcc(Assembler::equal, done);
8116 // Can we store original value in the thread's buffer?
8117 // Is index == 0?
8118 // (The index field is typed as size_t.)
8120 movptr(tmp, index); // tmp := *index_adr
8121 cmpptr(tmp, 0); // tmp == 0?
8122 jcc(Assembler::equal, runtime); // If yes, goto runtime
8124 subptr(tmp, wordSize); // tmp := tmp - wordSize
8125 movptr(index, tmp); // *index_adr := tmp
8126 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
8128 // Record the previous value
8129 movptr(Address(tmp, 0), pre_val);
8130 jmp(done);
8132 bind(runtime);
8133 // save the live input values
8134 if(tosca_live) push(rax);
8136 if (obj != noreg && obj != rax)
8137 push(obj);
8139 if (pre_val != rax)
8140 push(pre_val);
8142 // Calling the runtime using the regular call_VM_leaf mechanism generates
8143 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
8144 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
8145 //
8146 // If we care generating the pre-barrier without a frame (e.g. in the
8147 // intrinsified Reference.get() routine) then ebp might be pointing to
8148 // the caller frame and so this check will most likely fail at runtime.
8149 //
8150 // Expanding the call directly bypasses the generation of the check.
8151 // So when we do not have have a full interpreter frame on the stack
8152 // expand_call should be passed true.
8154 NOT_LP64( push(thread); )
8156 if (expand_call) {
8157 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
8158 pass_arg1(this, thread);
8159 pass_arg0(this, pre_val);
8160 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
8161 } else {
8162 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
8163 }
8165 NOT_LP64( pop(thread); )
8167 // save the live input values
8168 if (pre_val != rax)
8169 pop(pre_val);
8171 if (obj != noreg && obj != rax)
8172 pop(obj);
8174 if(tosca_live) pop(rax);
8176 bind(done);
8177 }
8179 void MacroAssembler::g1_write_barrier_post(Register store_addr,
8180 Register new_val,
8181 Register thread,
8182 Register tmp,
8183 Register tmp2) {
8184 #ifdef _LP64
8185 assert(thread == r15_thread, "must be");
8186 #endif // _LP64
8188 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
8189 PtrQueue::byte_offset_of_index()));
8190 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
8191 PtrQueue::byte_offset_of_buf()));
8193 BarrierSet* bs = Universe::heap()->barrier_set();
8194 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
8195 Label done;
8196 Label runtime;
8198 // Does store cross heap regions?
8200 movptr(tmp, store_addr);
8201 xorptr(tmp, new_val);
8202 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
8203 jcc(Assembler::equal, done);
8205 // crosses regions, storing NULL?
8207 cmpptr(new_val, (int32_t) NULL_WORD);
8208 jcc(Assembler::equal, done);
8210 // storing region crossing non-NULL, is card already dirty?
8212 ExternalAddress cardtable((address) ct->byte_map_base);
8213 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
8214 #ifdef _LP64
8215 const Register card_addr = tmp;
8217 movq(card_addr, store_addr);
8218 shrq(card_addr, CardTableModRefBS::card_shift);
8220 lea(tmp2, cardtable);
8222 // get the address of the card
8223 addq(card_addr, tmp2);
8224 #else
8225 const Register card_index = tmp;
8227 movl(card_index, store_addr);
8228 shrl(card_index, CardTableModRefBS::card_shift);
8230 Address index(noreg, card_index, Address::times_1);
8231 const Register card_addr = tmp;
8232 lea(card_addr, as_Address(ArrayAddress(cardtable, index)));
8233 #endif
8234 cmpb(Address(card_addr, 0), 0);
8235 jcc(Assembler::equal, done);
8237 // storing a region crossing, non-NULL oop, card is clean.
8238 // dirty card and log.
8240 movb(Address(card_addr, 0), 0);
8242 cmpl(queue_index, 0);
8243 jcc(Assembler::equal, runtime);
8244 subl(queue_index, wordSize);
8245 movptr(tmp2, buffer);
8246 #ifdef _LP64
8247 movslq(rscratch1, queue_index);
8248 addq(tmp2, rscratch1);
8249 movq(Address(tmp2, 0), card_addr);
8250 #else
8251 addl(tmp2, queue_index);
8252 movl(Address(tmp2, 0), card_index);
8253 #endif
8254 jmp(done);
8256 bind(runtime);
8257 // save the live input values
8258 push(store_addr);
8259 push(new_val);
8260 #ifdef _LP64
8261 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
8262 #else
8263 push(thread);
8264 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
8265 pop(thread);
8266 #endif
8267 pop(new_val);
8268 pop(store_addr);
8270 bind(done);
8271 }
8273 #endif // SERIALGC
8274 //////////////////////////////////////////////////////////////////////////////////
8277 void MacroAssembler::store_check(Register obj) {
8278 // Does a store check for the oop in register obj. The content of
8279 // register obj is destroyed afterwards.
8280 store_check_part_1(obj);
8281 store_check_part_2(obj);
8282 }
8284 void MacroAssembler::store_check(Register obj, Address dst) {
8285 store_check(obj);
8286 }
8289 // split the store check operation so that other instructions can be scheduled inbetween
8290 void MacroAssembler::store_check_part_1(Register obj) {
8291 BarrierSet* bs = Universe::heap()->barrier_set();
8292 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
8293 shrptr(obj, CardTableModRefBS::card_shift);
8294 }
8296 void MacroAssembler::store_check_part_2(Register obj) {
8297 BarrierSet* bs = Universe::heap()->barrier_set();
8298 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
8299 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
8300 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
8302 // The calculation for byte_map_base is as follows:
8303 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
8304 // So this essentially converts an address to a displacement and
8305 // it will never need to be relocated. On 64bit however the value may be too
8306 // large for a 32bit displacement
8308 intptr_t disp = (intptr_t) ct->byte_map_base;
8309 if (is_simm32(disp)) {
8310 Address cardtable(noreg, obj, Address::times_1, disp);
8311 movb(cardtable, 0);
8312 } else {
8313 // By doing it as an ExternalAddress disp could be converted to a rip-relative
8314 // displacement and done in a single instruction given favorable mapping and
8315 // a smarter version of as_Address. Worst case it is two instructions which
8316 // is no worse off then loading disp into a register and doing as a simple
8317 // Address() as above.
8318 // We can't do as ExternalAddress as the only style since if disp == 0 we'll
8319 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case
8320 // in some cases we'll get a single instruction version.
8322 ExternalAddress cardtable((address)disp);
8323 Address index(noreg, obj, Address::times_1);
8324 movb(as_Address(ArrayAddress(cardtable, index)), 0);
8325 }
8326 }
8328 void MacroAssembler::subptr(Register dst, int32_t imm32) {
8329 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
8330 }
8332 // Force generation of a 4 byte immediate value even if it fits into 8bit
8333 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
8334 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
8335 }
8337 void MacroAssembler::subptr(Register dst, Register src) {
8338 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
8339 }
8341 // C++ bool manipulation
8342 void MacroAssembler::testbool(Register dst) {
8343 if(sizeof(bool) == 1)
8344 testb(dst, 0xff);
8345 else if(sizeof(bool) == 2) {
8346 // testw implementation needed for two byte bools
8347 ShouldNotReachHere();
8348 } else if(sizeof(bool) == 4)
8349 testl(dst, dst);
8350 else
8351 // unsupported
8352 ShouldNotReachHere();
8353 }
8355 void MacroAssembler::testptr(Register dst, Register src) {
8356 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
8357 }
8359 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
8360 void MacroAssembler::tlab_allocate(Register obj,
8361 Register var_size_in_bytes,
8362 int con_size_in_bytes,
8363 Register t1,
8364 Register t2,
8365 Label& slow_case) {
8366 assert_different_registers(obj, t1, t2);
8367 assert_different_registers(obj, var_size_in_bytes, t1);
8368 Register end = t2;
8369 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
8371 verify_tlab();
8373 NOT_LP64(get_thread(thread));
8375 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
8376 if (var_size_in_bytes == noreg) {
8377 lea(end, Address(obj, con_size_in_bytes));
8378 } else {
8379 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
8380 }
8381 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
8382 jcc(Assembler::above, slow_case);
8384 // update the tlab top pointer
8385 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
8387 // recover var_size_in_bytes if necessary
8388 if (var_size_in_bytes == end) {
8389 subptr(var_size_in_bytes, obj);
8390 }
8391 verify_tlab();
8392 }
8394 // Preserves rbx, and rdx.
8395 Register MacroAssembler::tlab_refill(Label& retry,
8396 Label& try_eden,
8397 Label& slow_case) {
8398 Register top = rax;
8399 Register t1 = rcx;
8400 Register t2 = rsi;
8401 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
8402 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
8403 Label do_refill, discard_tlab;
8405 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
8406 // No allocation in the shared eden.
8407 jmp(slow_case);
8408 }
8410 NOT_LP64(get_thread(thread_reg));
8412 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
8413 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
8415 // calculate amount of free space
8416 subptr(t1, top);
8417 shrptr(t1, LogHeapWordSize);
8419 // Retain tlab and allocate object in shared space if
8420 // the amount free in the tlab is too large to discard.
8421 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
8422 jcc(Assembler::lessEqual, discard_tlab);
8424 // Retain
8425 // %%% yuck as movptr...
8426 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
8427 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
8428 if (TLABStats) {
8429 // increment number of slow_allocations
8430 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
8431 }
8432 jmp(try_eden);
8434 bind(discard_tlab);
8435 if (TLABStats) {
8436 // increment number of refills
8437 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
8438 // accumulate wastage -- t1 is amount free in tlab
8439 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
8440 }
8442 // if tlab is currently allocated (top or end != null) then
8443 // fill [top, end + alignment_reserve) with array object
8444 testptr(top, top);
8445 jcc(Assembler::zero, do_refill);
8447 // set up the mark word
8448 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
8449 // set the length to the remaining space
8450 subptr(t1, typeArrayOopDesc::header_size(T_INT));
8451 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
8452 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
8453 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
8454 // set klass to intArrayKlass
8455 // dubious reloc why not an oop reloc?
8456 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
8457 // store klass last. concurrent gcs assumes klass length is valid if
8458 // klass field is not null.
8459 store_klass(top, t1);
8461 movptr(t1, top);
8462 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
8463 incr_allocated_bytes(thread_reg, t1, 0);
8465 // refill the tlab with an eden allocation
8466 bind(do_refill);
8467 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
8468 shlptr(t1, LogHeapWordSize);
8469 // allocate new tlab, address returned in top
8470 eden_allocate(top, t1, 0, t2, slow_case);
8472 // Check that t1 was preserved in eden_allocate.
8473 #ifdef ASSERT
8474 if (UseTLAB) {
8475 Label ok;
8476 Register tsize = rsi;
8477 assert_different_registers(tsize, thread_reg, t1);
8478 push(tsize);
8479 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
8480 shlptr(tsize, LogHeapWordSize);
8481 cmpptr(t1, tsize);
8482 jcc(Assembler::equal, ok);
8483 STOP("assert(t1 != tlab size)");
8484 should_not_reach_here();
8486 bind(ok);
8487 pop(tsize);
8488 }
8489 #endif
8490 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
8491 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
8492 addptr(top, t1);
8493 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
8494 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
8495 verify_tlab();
8496 jmp(retry);
8498 return thread_reg; // for use by caller
8499 }
8501 void MacroAssembler::incr_allocated_bytes(Register thread,
8502 Register var_size_in_bytes,
8503 int con_size_in_bytes,
8504 Register t1) {
8505 if (!thread->is_valid()) {
8506 #ifdef _LP64
8507 thread = r15_thread;
8508 #else
8509 assert(t1->is_valid(), "need temp reg");
8510 thread = t1;
8511 get_thread(thread);
8512 #endif
8513 }
8515 #ifdef _LP64
8516 if (var_size_in_bytes->is_valid()) {
8517 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
8518 } else {
8519 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
8520 }
8521 #else
8522 if (var_size_in_bytes->is_valid()) {
8523 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
8524 } else {
8525 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
8526 }
8527 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
8528 #endif
8529 }
8531 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) {
8532 pusha();
8534 // if we are coming from c1, xmm registers may be live
8535 if (UseSSE >= 1) {
8536 subptr(rsp, sizeof(jdouble)* LP64_ONLY(16) NOT_LP64(8));
8537 }
8538 int off = 0;
8539 if (UseSSE == 1) {
8540 movflt(Address(rsp,off++*sizeof(jdouble)),xmm0);
8541 movflt(Address(rsp,off++*sizeof(jdouble)),xmm1);
8542 movflt(Address(rsp,off++*sizeof(jdouble)),xmm2);
8543 movflt(Address(rsp,off++*sizeof(jdouble)),xmm3);
8544 movflt(Address(rsp,off++*sizeof(jdouble)),xmm4);
8545 movflt(Address(rsp,off++*sizeof(jdouble)),xmm5);
8546 movflt(Address(rsp,off++*sizeof(jdouble)),xmm6);
8547 movflt(Address(rsp,off++*sizeof(jdouble)),xmm7);
8548 } else if (UseSSE >= 2) {
8549 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm0);
8550 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm1);
8551 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm2);
8552 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm3);
8553 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm4);
8554 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm5);
8555 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm6);
8556 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm7);
8557 #ifdef _LP64
8558 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm8);
8559 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm9);
8560 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm10);
8561 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm11);
8562 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm12);
8563 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm13);
8564 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm14);
8565 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm15);
8566 #endif
8567 }
8569 // Preserve registers across runtime call
8570 int incoming_argument_and_return_value_offset = -1;
8571 if (num_fpu_regs_in_use > 1) {
8572 // Must preserve all other FPU regs (could alternatively convert
8573 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash
8574 // FPU state, but can not trust C compiler)
8575 NEEDS_CLEANUP;
8576 // NOTE that in this case we also push the incoming argument(s) to
8577 // the stack and restore it later; we also use this stack slot to
8578 // hold the return value from dsin, dcos etc.
8579 for (int i = 0; i < num_fpu_regs_in_use; i++) {
8580 subptr(rsp, sizeof(jdouble));
8581 fstp_d(Address(rsp, 0));
8582 }
8583 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
8584 for (int i = nb_args-1; i >= 0; i--) {
8585 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble)));
8586 }
8587 }
8589 subptr(rsp, nb_args*sizeof(jdouble));
8590 for (int i = 0; i < nb_args; i++) {
8591 fstp_d(Address(rsp, i*sizeof(jdouble)));
8592 }
8594 #ifdef _LP64
8595 if (nb_args > 0) {
8596 movdbl(xmm0, Address(rsp, 0));
8597 }
8598 if (nb_args > 1) {
8599 movdbl(xmm1, Address(rsp, sizeof(jdouble)));
8600 }
8601 assert(nb_args <= 2, "unsupported number of args");
8602 #endif // _LP64
8604 // NOTE: we must not use call_VM_leaf here because that requires a
8605 // complete interpreter frame in debug mode -- same bug as 4387334
8606 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
8607 // do proper 64bit abi
8609 NEEDS_CLEANUP;
8610 // Need to add stack banging before this runtime call if it needs to
8611 // be taken; however, there is no generic stack banging routine at
8612 // the MacroAssembler level
8614 MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
8616 #ifdef _LP64
8617 movsd(Address(rsp, 0), xmm0);
8618 fld_d(Address(rsp, 0));
8619 #endif // _LP64
8620 addptr(rsp, sizeof(jdouble) * nb_args);
8621 if (num_fpu_regs_in_use > 1) {
8622 // Must save return value to stack and then restore entire FPU
8623 // stack except incoming arguments
8624 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
8625 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) {
8626 fld_d(Address(rsp, 0));
8627 addptr(rsp, sizeof(jdouble));
8628 }
8629 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble)));
8630 addptr(rsp, sizeof(jdouble) * nb_args);
8631 }
8633 off = 0;
8634 if (UseSSE == 1) {
8635 movflt(xmm0, Address(rsp,off++*sizeof(jdouble)));
8636 movflt(xmm1, Address(rsp,off++*sizeof(jdouble)));
8637 movflt(xmm2, Address(rsp,off++*sizeof(jdouble)));
8638 movflt(xmm3, Address(rsp,off++*sizeof(jdouble)));
8639 movflt(xmm4, Address(rsp,off++*sizeof(jdouble)));
8640 movflt(xmm5, Address(rsp,off++*sizeof(jdouble)));
8641 movflt(xmm6, Address(rsp,off++*sizeof(jdouble)));
8642 movflt(xmm7, Address(rsp,off++*sizeof(jdouble)));
8643 } else if (UseSSE >= 2) {
8644 movdbl(xmm0, Address(rsp,off++*sizeof(jdouble)));
8645 movdbl(xmm1, Address(rsp,off++*sizeof(jdouble)));
8646 movdbl(xmm2, Address(rsp,off++*sizeof(jdouble)));
8647 movdbl(xmm3, Address(rsp,off++*sizeof(jdouble)));
8648 movdbl(xmm4, Address(rsp,off++*sizeof(jdouble)));
8649 movdbl(xmm5, Address(rsp,off++*sizeof(jdouble)));
8650 movdbl(xmm6, Address(rsp,off++*sizeof(jdouble)));
8651 movdbl(xmm7, Address(rsp,off++*sizeof(jdouble)));
8652 #ifdef _LP64
8653 movdbl(xmm8, Address(rsp,off++*sizeof(jdouble)));
8654 movdbl(xmm9, Address(rsp,off++*sizeof(jdouble)));
8655 movdbl(xmm10, Address(rsp,off++*sizeof(jdouble)));
8656 movdbl(xmm11, Address(rsp,off++*sizeof(jdouble)));
8657 movdbl(xmm12, Address(rsp,off++*sizeof(jdouble)));
8658 movdbl(xmm13, Address(rsp,off++*sizeof(jdouble)));
8659 movdbl(xmm14, Address(rsp,off++*sizeof(jdouble)));
8660 movdbl(xmm15, Address(rsp,off++*sizeof(jdouble)));
8661 #endif
8662 }
8663 if (UseSSE >= 1) {
8664 addptr(rsp, sizeof(jdouble)* LP64_ONLY(16) NOT_LP64(8));
8665 }
8666 popa();
8667 }
8669 static const double pi_4 = 0.7853981633974483;
8671 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
8672 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
8673 // was attempted in this code; unfortunately it appears that the
8674 // switch to 80-bit precision and back causes this to be
8675 // unprofitable compared with simply performing a runtime call if
8676 // the argument is out of the (-pi/4, pi/4) range.
8678 Register tmp = noreg;
8679 if (!VM_Version::supports_cmov()) {
8680 // fcmp needs a temporary so preserve rbx,
8681 tmp = rbx;
8682 push(tmp);
8683 }
8685 Label slow_case, done;
8687 ExternalAddress pi4_adr = (address)&pi_4;
8688 if (reachable(pi4_adr)) {
8689 // x ?<= pi/4
8690 fld_d(pi4_adr);
8691 fld_s(1); // Stack: X PI/4 X
8692 fabs(); // Stack: |X| PI/4 X
8693 fcmp(tmp);
8694 jcc(Assembler::above, slow_case);
8696 // fastest case: -pi/4 <= x <= pi/4
8697 switch(trig) {
8698 case 's':
8699 fsin();
8700 break;
8701 case 'c':
8702 fcos();
8703 break;
8704 case 't':
8705 ftan();
8706 break;
8707 default:
8708 assert(false, "bad intrinsic");
8709 break;
8710 }
8711 jmp(done);
8712 }
8714 // slow case: runtime call
8715 bind(slow_case);
8717 switch(trig) {
8718 case 's':
8719 {
8720 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use);
8721 }
8722 break;
8723 case 'c':
8724 {
8725 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use);
8726 }
8727 break;
8728 case 't':
8729 {
8730 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use);
8731 }
8732 break;
8733 default:
8734 assert(false, "bad intrinsic");
8735 break;
8736 }
8738 // Come here with result in F-TOS
8739 bind(done);
8741 if (tmp != noreg) {
8742 pop(tmp);
8743 }
8744 }
8747 // Look up the method for a megamorphic invokeinterface call.
8748 // The target method is determined by <intf_klass, itable_index>.
8749 // The receiver klass is in recv_klass.
8750 // On success, the result will be in method_result, and execution falls through.
8751 // On failure, execution transfers to the given label.
8752 void MacroAssembler::lookup_interface_method(Register recv_klass,
8753 Register intf_klass,
8754 RegisterOrConstant itable_index,
8755 Register method_result,
8756 Register scan_temp,
8757 Label& L_no_such_interface) {
8758 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
8759 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
8760 "caller must use same register for non-constant itable index as for method");
8762 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
8763 int vtable_base = instanceKlass::vtable_start_offset() * wordSize;
8764 int itentry_off = itableMethodEntry::method_offset_in_bytes();
8765 int scan_step = itableOffsetEntry::size() * wordSize;
8766 int vte_size = vtableEntry::size() * wordSize;
8767 Address::ScaleFactor times_vte_scale = Address::times_ptr;
8768 assert(vte_size == wordSize, "else adjust times_vte_scale");
8770 movl(scan_temp, Address(recv_klass, instanceKlass::vtable_length_offset() * wordSize));
8772 // %%% Could store the aligned, prescaled offset in the klassoop.
8773 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
8774 if (HeapWordsPerLong > 1) {
8775 // Round up to align_object_offset boundary
8776 // see code for instanceKlass::start_of_itable!
8777 round_to(scan_temp, BytesPerLong);
8778 }
8780 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
8781 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
8782 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
8784 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
8785 // if (scan->interface() == intf) {
8786 // result = (klass + scan->offset() + itable_index);
8787 // }
8788 // }
8789 Label search, found_method;
8791 for (int peel = 1; peel >= 0; peel--) {
8792 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
8793 cmpptr(intf_klass, method_result);
8795 if (peel) {
8796 jccb(Assembler::equal, found_method);
8797 } else {
8798 jccb(Assembler::notEqual, search);
8799 // (invert the test to fall through to found_method...)
8800 }
8802 if (!peel) break;
8804 bind(search);
8806 // Check that the previous entry is non-null. A null entry means that
8807 // the receiver class doesn't implement the interface, and wasn't the
8808 // same as when the caller was compiled.
8809 testptr(method_result, method_result);
8810 jcc(Assembler::zero, L_no_such_interface);
8811 addptr(scan_temp, scan_step);
8812 }
8814 bind(found_method);
8816 // Got a hit.
8817 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
8818 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
8819 }
8822 // virtual method calling
8823 void MacroAssembler::lookup_virtual_method(Register recv_klass,
8824 RegisterOrConstant vtable_index,
8825 Register method_result) {
8826 const int base = instanceKlass::vtable_start_offset() * wordSize;
8827 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
8828 Address vtable_entry_addr(recv_klass,
8829 vtable_index, Address::times_ptr,
8830 base + vtableEntry::method_offset_in_bytes());
8831 movptr(method_result, vtable_entry_addr);
8832 }
8835 void MacroAssembler::check_klass_subtype(Register sub_klass,
8836 Register super_klass,
8837 Register temp_reg,
8838 Label& L_success) {
8839 Label L_failure;
8840 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
8841 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
8842 bind(L_failure);
8843 }
8846 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
8847 Register super_klass,
8848 Register temp_reg,
8849 Label* L_success,
8850 Label* L_failure,
8851 Label* L_slow_path,
8852 RegisterOrConstant super_check_offset) {
8853 assert_different_registers(sub_klass, super_klass, temp_reg);
8854 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
8855 if (super_check_offset.is_register()) {
8856 assert_different_registers(sub_klass, super_klass,
8857 super_check_offset.as_register());
8858 } else if (must_load_sco) {
8859 assert(temp_reg != noreg, "supply either a temp or a register offset");
8860 }
8862 Label L_fallthrough;
8863 int label_nulls = 0;
8864 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
8865 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
8866 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
8867 assert(label_nulls <= 1, "at most one NULL in the batch");
8869 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
8870 int sco_offset = in_bytes(Klass::super_check_offset_offset());
8871 Address super_check_offset_addr(super_klass, sco_offset);
8873 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
8874 // range of a jccb. If this routine grows larger, reconsider at
8875 // least some of these.
8876 #define local_jcc(assembler_cond, label) \
8877 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
8878 else jcc( assembler_cond, label) /*omit semi*/
8880 // Hacked jmp, which may only be used just before L_fallthrough.
8881 #define final_jmp(label) \
8882 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
8883 else jmp(label) /*omit semi*/
8885 // If the pointers are equal, we are done (e.g., String[] elements).
8886 // This self-check enables sharing of secondary supertype arrays among
8887 // non-primary types such as array-of-interface. Otherwise, each such
8888 // type would need its own customized SSA.
8889 // We move this check to the front of the fast path because many
8890 // type checks are in fact trivially successful in this manner,
8891 // so we get a nicely predicted branch right at the start of the check.
8892 cmpptr(sub_klass, super_klass);
8893 local_jcc(Assembler::equal, *L_success);
8895 // Check the supertype display:
8896 if (must_load_sco) {
8897 // Positive movl does right thing on LP64.
8898 movl(temp_reg, super_check_offset_addr);
8899 super_check_offset = RegisterOrConstant(temp_reg);
8900 }
8901 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
8902 cmpptr(super_klass, super_check_addr); // load displayed supertype
8904 // This check has worked decisively for primary supers.
8905 // Secondary supers are sought in the super_cache ('super_cache_addr').
8906 // (Secondary supers are interfaces and very deeply nested subtypes.)
8907 // This works in the same check above because of a tricky aliasing
8908 // between the super_cache and the primary super display elements.
8909 // (The 'super_check_addr' can address either, as the case requires.)
8910 // Note that the cache is updated below if it does not help us find
8911 // what we need immediately.
8912 // So if it was a primary super, we can just fail immediately.
8913 // Otherwise, it's the slow path for us (no success at this point).
8915 if (super_check_offset.is_register()) {
8916 local_jcc(Assembler::equal, *L_success);
8917 cmpl(super_check_offset.as_register(), sc_offset);
8918 if (L_failure == &L_fallthrough) {
8919 local_jcc(Assembler::equal, *L_slow_path);
8920 } else {
8921 local_jcc(Assembler::notEqual, *L_failure);
8922 final_jmp(*L_slow_path);
8923 }
8924 } else if (super_check_offset.as_constant() == sc_offset) {
8925 // Need a slow path; fast failure is impossible.
8926 if (L_slow_path == &L_fallthrough) {
8927 local_jcc(Assembler::equal, *L_success);
8928 } else {
8929 local_jcc(Assembler::notEqual, *L_slow_path);
8930 final_jmp(*L_success);
8931 }
8932 } else {
8933 // No slow path; it's a fast decision.
8934 if (L_failure == &L_fallthrough) {
8935 local_jcc(Assembler::equal, *L_success);
8936 } else {
8937 local_jcc(Assembler::notEqual, *L_failure);
8938 final_jmp(*L_success);
8939 }
8940 }
8942 bind(L_fallthrough);
8944 #undef local_jcc
8945 #undef final_jmp
8946 }
8949 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
8950 Register super_klass,
8951 Register temp_reg,
8952 Register temp2_reg,
8953 Label* L_success,
8954 Label* L_failure,
8955 bool set_cond_codes) {
8956 assert_different_registers(sub_klass, super_klass, temp_reg);
8957 if (temp2_reg != noreg)
8958 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
8959 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
8961 Label L_fallthrough;
8962 int label_nulls = 0;
8963 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
8964 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
8965 assert(label_nulls <= 1, "at most one NULL in the batch");
8967 // a couple of useful fields in sub_klass:
8968 int ss_offset = in_bytes(Klass::secondary_supers_offset());
8969 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
8970 Address secondary_supers_addr(sub_klass, ss_offset);
8971 Address super_cache_addr( sub_klass, sc_offset);
8973 // Do a linear scan of the secondary super-klass chain.
8974 // This code is rarely used, so simplicity is a virtue here.
8975 // The repne_scan instruction uses fixed registers, which we must spill.
8976 // Don't worry too much about pre-existing connections with the input regs.
8978 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
8979 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
8981 // Get super_klass value into rax (even if it was in rdi or rcx).
8982 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
8983 if (super_klass != rax || UseCompressedOops) {
8984 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
8985 mov(rax, super_klass);
8986 }
8987 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
8988 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
8990 #ifndef PRODUCT
8991 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
8992 ExternalAddress pst_counter_addr((address) pst_counter);
8993 NOT_LP64( incrementl(pst_counter_addr) );
8994 LP64_ONLY( lea(rcx, pst_counter_addr) );
8995 LP64_ONLY( incrementl(Address(rcx, 0)) );
8996 #endif //PRODUCT
8998 // We will consult the secondary-super array.
8999 movptr(rdi, secondary_supers_addr);
9000 // Load the array length. (Positive movl does right thing on LP64.)
9001 movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
9002 // Skip to start of data.
9003 addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
9005 // Scan RCX words at [RDI] for an occurrence of RAX.
9006 // Set NZ/Z based on last compare.
9007 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
9008 // not change flags (only scas instruction which is repeated sets flags).
9009 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
9010 #ifdef _LP64
9011 // This part is tricky, as values in supers array could be 32 or 64 bit wide
9012 // and we store values in objArrays always encoded, thus we need to encode
9013 // the value of rax before repne. Note that rax is dead after the repne.
9014 if (UseCompressedOops) {
9015 encode_heap_oop_not_null(rax); // Changes flags.
9016 // The superclass is never null; it would be a basic system error if a null
9017 // pointer were to sneak in here. Note that we have already loaded the
9018 // Klass::super_check_offset from the super_klass in the fast path,
9019 // so if there is a null in that register, we are already in the afterlife.
9020 testl(rax,rax); // Set Z = 0
9021 repne_scanl();
9022 } else
9023 #endif // _LP64
9024 {
9025 testptr(rax,rax); // Set Z = 0
9026 repne_scan();
9027 }
9028 // Unspill the temp. registers:
9029 if (pushed_rdi) pop(rdi);
9030 if (pushed_rcx) pop(rcx);
9031 if (pushed_rax) pop(rax);
9033 if (set_cond_codes) {
9034 // Special hack for the AD files: rdi is guaranteed non-zero.
9035 assert(!pushed_rdi, "rdi must be left non-NULL");
9036 // Also, the condition codes are properly set Z/NZ on succeed/failure.
9037 }
9039 if (L_failure == &L_fallthrough)
9040 jccb(Assembler::notEqual, *L_failure);
9041 else jcc(Assembler::notEqual, *L_failure);
9043 // Success. Cache the super we found and proceed in triumph.
9044 movptr(super_cache_addr, super_klass);
9046 if (L_success != &L_fallthrough) {
9047 jmp(*L_success);
9048 }
9050 #undef IS_A_TEMP
9052 bind(L_fallthrough);
9053 }
9056 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
9057 if (VM_Version::supports_cmov()) {
9058 cmovl(cc, dst, src);
9059 } else {
9060 Label L;
9061 jccb(negate_condition(cc), L);
9062 movl(dst, src);
9063 bind(L);
9064 }
9065 }
9067 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
9068 if (VM_Version::supports_cmov()) {
9069 cmovl(cc, dst, src);
9070 } else {
9071 Label L;
9072 jccb(negate_condition(cc), L);
9073 movl(dst, src);
9074 bind(L);
9075 }
9076 }
9078 void MacroAssembler::verify_oop(Register reg, const char* s) {
9079 if (!VerifyOops) return;
9081 // Pass register number to verify_oop_subroutine
9082 char* b = new char[strlen(s) + 50];
9083 sprintf(b, "verify_oop: %s: %s", reg->name(), s);
9084 BLOCK_COMMENT("verify_oop {");
9085 #ifdef _LP64
9086 push(rscratch1); // save r10, trashed by movptr()
9087 #endif
9088 push(rax); // save rax,
9089 push(reg); // pass register argument
9090 ExternalAddress buffer((address) b);
9091 // avoid using pushptr, as it modifies scratch registers
9092 // and our contract is not to modify anything
9093 movptr(rax, buffer.addr());
9094 push(rax);
9095 // call indirectly to solve generation ordering problem
9096 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
9097 call(rax);
9098 // Caller pops the arguments (oop, message) and restores rax, r10
9099 BLOCK_COMMENT("} verify_oop");
9100 }
9103 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
9104 Register tmp,
9105 int offset) {
9106 intptr_t value = *delayed_value_addr;
9107 if (value != 0)
9108 return RegisterOrConstant(value + offset);
9110 // load indirectly to solve generation ordering problem
9111 movptr(tmp, ExternalAddress((address) delayed_value_addr));
9113 #ifdef ASSERT
9114 { Label L;
9115 testptr(tmp, tmp);
9116 if (WizardMode) {
9117 jcc(Assembler::notZero, L);
9118 char* buf = new char[40];
9119 sprintf(buf, "DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]);
9120 STOP(buf);
9121 } else {
9122 jccb(Assembler::notZero, L);
9123 hlt();
9124 }
9125 bind(L);
9126 }
9127 #endif
9129 if (offset != 0)
9130 addptr(tmp, offset);
9132 return RegisterOrConstant(tmp);
9133 }
9136 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
9137 int extra_slot_offset) {
9138 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
9139 int stackElementSize = Interpreter::stackElementSize;
9140 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
9141 #ifdef ASSERT
9142 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
9143 assert(offset1 - offset == stackElementSize, "correct arithmetic");
9144 #endif
9145 Register scale_reg = noreg;
9146 Address::ScaleFactor scale_factor = Address::no_scale;
9147 if (arg_slot.is_constant()) {
9148 offset += arg_slot.as_constant() * stackElementSize;
9149 } else {
9150 scale_reg = arg_slot.as_register();
9151 scale_factor = Address::times(stackElementSize);
9152 }
9153 offset += wordSize; // return PC is on stack
9154 return Address(rsp, scale_reg, scale_factor, offset);
9155 }
9158 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
9159 if (!VerifyOops) return;
9161 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
9162 // Pass register number to verify_oop_subroutine
9163 char* b = new char[strlen(s) + 50];
9164 sprintf(b, "verify_oop_addr: %s", s);
9166 #ifdef _LP64
9167 push(rscratch1); // save r10, trashed by movptr()
9168 #endif
9169 push(rax); // save rax,
9170 // addr may contain rsp so we will have to adjust it based on the push
9171 // we just did (and on 64 bit we do two pushes)
9172 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
9173 // stores rax into addr which is backwards of what was intended.
9174 if (addr.uses(rsp)) {
9175 lea(rax, addr);
9176 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
9177 } else {
9178 pushptr(addr);
9179 }
9181 ExternalAddress buffer((address) b);
9182 // pass msg argument
9183 // avoid using pushptr, as it modifies scratch registers
9184 // and our contract is not to modify anything
9185 movptr(rax, buffer.addr());
9186 push(rax);
9188 // call indirectly to solve generation ordering problem
9189 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
9190 call(rax);
9191 // Caller pops the arguments (addr, message) and restores rax, r10.
9192 }
9194 void MacroAssembler::verify_tlab() {
9195 #ifdef ASSERT
9196 if (UseTLAB && VerifyOops) {
9197 Label next, ok;
9198 Register t1 = rsi;
9199 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
9201 push(t1);
9202 NOT_LP64(push(thread_reg));
9203 NOT_LP64(get_thread(thread_reg));
9205 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
9206 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
9207 jcc(Assembler::aboveEqual, next);
9208 STOP("assert(top >= start)");
9209 should_not_reach_here();
9211 bind(next);
9212 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
9213 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
9214 jcc(Assembler::aboveEqual, ok);
9215 STOP("assert(top <= end)");
9216 should_not_reach_here();
9218 bind(ok);
9219 NOT_LP64(pop(thread_reg));
9220 pop(t1);
9221 }
9222 #endif
9223 }
9225 class ControlWord {
9226 public:
9227 int32_t _value;
9229 int rounding_control() const { return (_value >> 10) & 3 ; }
9230 int precision_control() const { return (_value >> 8) & 3 ; }
9231 bool precision() const { return ((_value >> 5) & 1) != 0; }
9232 bool underflow() const { return ((_value >> 4) & 1) != 0; }
9233 bool overflow() const { return ((_value >> 3) & 1) != 0; }
9234 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
9235 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
9236 bool invalid() const { return ((_value >> 0) & 1) != 0; }
9238 void print() const {
9239 // rounding control
9240 const char* rc;
9241 switch (rounding_control()) {
9242 case 0: rc = "round near"; break;
9243 case 1: rc = "round down"; break;
9244 case 2: rc = "round up "; break;
9245 case 3: rc = "chop "; break;
9246 };
9247 // precision control
9248 const char* pc;
9249 switch (precision_control()) {
9250 case 0: pc = "24 bits "; break;
9251 case 1: pc = "reserved"; break;
9252 case 2: pc = "53 bits "; break;
9253 case 3: pc = "64 bits "; break;
9254 };
9255 // flags
9256 char f[9];
9257 f[0] = ' ';
9258 f[1] = ' ';
9259 f[2] = (precision ()) ? 'P' : 'p';
9260 f[3] = (underflow ()) ? 'U' : 'u';
9261 f[4] = (overflow ()) ? 'O' : 'o';
9262 f[5] = (zero_divide ()) ? 'Z' : 'z';
9263 f[6] = (denormalized()) ? 'D' : 'd';
9264 f[7] = (invalid ()) ? 'I' : 'i';
9265 f[8] = '\x0';
9266 // output
9267 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
9268 }
9270 };
9272 class StatusWord {
9273 public:
9274 int32_t _value;
9276 bool busy() const { return ((_value >> 15) & 1) != 0; }
9277 bool C3() const { return ((_value >> 14) & 1) != 0; }
9278 bool C2() const { return ((_value >> 10) & 1) != 0; }
9279 bool C1() const { return ((_value >> 9) & 1) != 0; }
9280 bool C0() const { return ((_value >> 8) & 1) != 0; }
9281 int top() const { return (_value >> 11) & 7 ; }
9282 bool error_status() const { return ((_value >> 7) & 1) != 0; }
9283 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
9284 bool precision() const { return ((_value >> 5) & 1) != 0; }
9285 bool underflow() const { return ((_value >> 4) & 1) != 0; }
9286 bool overflow() const { return ((_value >> 3) & 1) != 0; }
9287 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
9288 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
9289 bool invalid() const { return ((_value >> 0) & 1) != 0; }
9291 void print() const {
9292 // condition codes
9293 char c[5];
9294 c[0] = (C3()) ? '3' : '-';
9295 c[1] = (C2()) ? '2' : '-';
9296 c[2] = (C1()) ? '1' : '-';
9297 c[3] = (C0()) ? '0' : '-';
9298 c[4] = '\x0';
9299 // flags
9300 char f[9];
9301 f[0] = (error_status()) ? 'E' : '-';
9302 f[1] = (stack_fault ()) ? 'S' : '-';
9303 f[2] = (precision ()) ? 'P' : '-';
9304 f[3] = (underflow ()) ? 'U' : '-';
9305 f[4] = (overflow ()) ? 'O' : '-';
9306 f[5] = (zero_divide ()) ? 'Z' : '-';
9307 f[6] = (denormalized()) ? 'D' : '-';
9308 f[7] = (invalid ()) ? 'I' : '-';
9309 f[8] = '\x0';
9310 // output
9311 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
9312 }
9314 };
9316 class TagWord {
9317 public:
9318 int32_t _value;
9320 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
9322 void print() const {
9323 printf("%04x", _value & 0xFFFF);
9324 }
9326 };
9328 class FPU_Register {
9329 public:
9330 int32_t _m0;
9331 int32_t _m1;
9332 int16_t _ex;
9334 bool is_indefinite() const {
9335 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
9336 }
9338 void print() const {
9339 char sign = (_ex < 0) ? '-' : '+';
9340 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
9341 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
9342 };
9344 };
9346 class FPU_State {
9347 public:
9348 enum {
9349 register_size = 10,
9350 number_of_registers = 8,
9351 register_mask = 7
9352 };
9354 ControlWord _control_word;
9355 StatusWord _status_word;
9356 TagWord _tag_word;
9357 int32_t _error_offset;
9358 int32_t _error_selector;
9359 int32_t _data_offset;
9360 int32_t _data_selector;
9361 int8_t _register[register_size * number_of_registers];
9363 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
9364 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
9366 const char* tag_as_string(int tag) const {
9367 switch (tag) {
9368 case 0: return "valid";
9369 case 1: return "zero";
9370 case 2: return "special";
9371 case 3: return "empty";
9372 }
9373 ShouldNotReachHere();
9374 return NULL;
9375 }
9377 void print() const {
9378 // print computation registers
9379 { int t = _status_word.top();
9380 for (int i = 0; i < number_of_registers; i++) {
9381 int j = (i - t) & register_mask;
9382 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
9383 st(j)->print();
9384 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
9385 }
9386 }
9387 printf("\n");
9388 // print control registers
9389 printf("ctrl = "); _control_word.print(); printf("\n");
9390 printf("stat = "); _status_word .print(); printf("\n");
9391 printf("tags = "); _tag_word .print(); printf("\n");
9392 }
9394 };
9396 class Flag_Register {
9397 public:
9398 int32_t _value;
9400 bool overflow() const { return ((_value >> 11) & 1) != 0; }
9401 bool direction() const { return ((_value >> 10) & 1) != 0; }
9402 bool sign() const { return ((_value >> 7) & 1) != 0; }
9403 bool zero() const { return ((_value >> 6) & 1) != 0; }
9404 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
9405 bool parity() const { return ((_value >> 2) & 1) != 0; }
9406 bool carry() const { return ((_value >> 0) & 1) != 0; }
9408 void print() const {
9409 // flags
9410 char f[8];
9411 f[0] = (overflow ()) ? 'O' : '-';
9412 f[1] = (direction ()) ? 'D' : '-';
9413 f[2] = (sign ()) ? 'S' : '-';
9414 f[3] = (zero ()) ? 'Z' : '-';
9415 f[4] = (auxiliary_carry()) ? 'A' : '-';
9416 f[5] = (parity ()) ? 'P' : '-';
9417 f[6] = (carry ()) ? 'C' : '-';
9418 f[7] = '\x0';
9419 // output
9420 printf("%08x flags = %s", _value, f);
9421 }
9423 };
9425 class IU_Register {
9426 public:
9427 int32_t _value;
9429 void print() const {
9430 printf("%08x %11d", _value, _value);
9431 }
9433 };
9435 class IU_State {
9436 public:
9437 Flag_Register _eflags;
9438 IU_Register _rdi;
9439 IU_Register _rsi;
9440 IU_Register _rbp;
9441 IU_Register _rsp;
9442 IU_Register _rbx;
9443 IU_Register _rdx;
9444 IU_Register _rcx;
9445 IU_Register _rax;
9447 void print() const {
9448 // computation registers
9449 printf("rax, = "); _rax.print(); printf("\n");
9450 printf("rbx, = "); _rbx.print(); printf("\n");
9451 printf("rcx = "); _rcx.print(); printf("\n");
9452 printf("rdx = "); _rdx.print(); printf("\n");
9453 printf("rdi = "); _rdi.print(); printf("\n");
9454 printf("rsi = "); _rsi.print(); printf("\n");
9455 printf("rbp, = "); _rbp.print(); printf("\n");
9456 printf("rsp = "); _rsp.print(); printf("\n");
9457 printf("\n");
9458 // control registers
9459 printf("flgs = "); _eflags.print(); printf("\n");
9460 }
9461 };
9464 class CPU_State {
9465 public:
9466 FPU_State _fpu_state;
9467 IU_State _iu_state;
9469 void print() const {
9470 printf("--------------------------------------------------\n");
9471 _iu_state .print();
9472 printf("\n");
9473 _fpu_state.print();
9474 printf("--------------------------------------------------\n");
9475 }
9477 };
9480 static void _print_CPU_state(CPU_State* state) {
9481 state->print();
9482 };
9485 void MacroAssembler::print_CPU_state() {
9486 push_CPU_state();
9487 push(rsp); // pass CPU state
9488 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
9489 addptr(rsp, wordSize); // discard argument
9490 pop_CPU_state();
9491 }
9494 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
9495 static int counter = 0;
9496 FPU_State* fs = &state->_fpu_state;
9497 counter++;
9498 // For leaf calls, only verify that the top few elements remain empty.
9499 // We only need 1 empty at the top for C2 code.
9500 if( stack_depth < 0 ) {
9501 if( fs->tag_for_st(7) != 3 ) {
9502 printf("FPR7 not empty\n");
9503 state->print();
9504 assert(false, "error");
9505 return false;
9506 }
9507 return true; // All other stack states do not matter
9508 }
9510 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
9511 "bad FPU control word");
9513 // compute stack depth
9514 int i = 0;
9515 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
9516 int d = i;
9517 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
9518 // verify findings
9519 if (i != FPU_State::number_of_registers) {
9520 // stack not contiguous
9521 printf("%s: stack not contiguous at ST%d\n", s, i);
9522 state->print();
9523 assert(false, "error");
9524 return false;
9525 }
9526 // check if computed stack depth corresponds to expected stack depth
9527 if (stack_depth < 0) {
9528 // expected stack depth is -stack_depth or less
9529 if (d > -stack_depth) {
9530 // too many elements on the stack
9531 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
9532 state->print();
9533 assert(false, "error");
9534 return false;
9535 }
9536 } else {
9537 // expected stack depth is stack_depth
9538 if (d != stack_depth) {
9539 // wrong stack depth
9540 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
9541 state->print();
9542 assert(false, "error");
9543 return false;
9544 }
9545 }
9546 // everything is cool
9547 return true;
9548 }
9551 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
9552 if (!VerifyFPU) return;
9553 push_CPU_state();
9554 push(rsp); // pass CPU state
9555 ExternalAddress msg((address) s);
9556 // pass message string s
9557 pushptr(msg.addr());
9558 push(stack_depth); // pass stack depth
9559 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
9560 addptr(rsp, 3 * wordSize); // discard arguments
9561 // check for error
9562 { Label L;
9563 testl(rax, rax);
9564 jcc(Assembler::notZero, L);
9565 int3(); // break if error condition
9566 bind(L);
9567 }
9568 pop_CPU_state();
9569 }
9571 void MacroAssembler::load_klass(Register dst, Register src) {
9572 #ifdef _LP64
9573 if (UseCompressedOops) {
9574 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
9575 decode_heap_oop_not_null(dst);
9576 } else
9577 #endif
9578 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
9579 }
9581 void MacroAssembler::load_prototype_header(Register dst, Register src) {
9582 #ifdef _LP64
9583 if (UseCompressedOops) {
9584 assert (Universe::heap() != NULL, "java heap should be initialized");
9585 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
9586 if (Universe::narrow_oop_shift() != 0) {
9587 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
9588 if (LogMinObjAlignmentInBytes == Address::times_8) {
9589 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset()));
9590 } else {
9591 // OK to use shift since we don't need to preserve flags.
9592 shlq(dst, LogMinObjAlignmentInBytes);
9593 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset()));
9594 }
9595 } else {
9596 movq(dst, Address(dst, Klass::prototype_header_offset()));
9597 }
9598 } else
9599 #endif
9600 {
9601 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
9602 movptr(dst, Address(dst, Klass::prototype_header_offset()));
9603 }
9604 }
9606 void MacroAssembler::store_klass(Register dst, Register src) {
9607 #ifdef _LP64
9608 if (UseCompressedOops) {
9609 encode_heap_oop_not_null(src);
9610 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
9611 } else
9612 #endif
9613 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
9614 }
9616 void MacroAssembler::load_heap_oop(Register dst, Address src) {
9617 #ifdef _LP64
9618 if (UseCompressedOops) {
9619 movl(dst, src);
9620 decode_heap_oop(dst);
9621 } else
9622 #endif
9623 movptr(dst, src);
9624 }
9626 // Doesn't do verfication, generates fixed size code
9627 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
9628 #ifdef _LP64
9629 if (UseCompressedOops) {
9630 movl(dst, src);
9631 decode_heap_oop_not_null(dst);
9632 } else
9633 #endif
9634 movptr(dst, src);
9635 }
9637 void MacroAssembler::store_heap_oop(Address dst, Register src) {
9638 #ifdef _LP64
9639 if (UseCompressedOops) {
9640 assert(!dst.uses(src), "not enough registers");
9641 encode_heap_oop(src);
9642 movl(dst, src);
9643 } else
9644 #endif
9645 movptr(dst, src);
9646 }
9648 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
9649 assert_different_registers(src1, tmp);
9650 #ifdef _LP64
9651 if (UseCompressedOops) {
9652 bool did_push = false;
9653 if (tmp == noreg) {
9654 tmp = rax;
9655 push(tmp);
9656 did_push = true;
9657 assert(!src2.uses(rsp), "can't push");
9658 }
9659 load_heap_oop(tmp, src2);
9660 cmpptr(src1, tmp);
9661 if (did_push) pop(tmp);
9662 } else
9663 #endif
9664 cmpptr(src1, src2);
9665 }
9667 // Used for storing NULLs.
9668 void MacroAssembler::store_heap_oop_null(Address dst) {
9669 #ifdef _LP64
9670 if (UseCompressedOops) {
9671 movl(dst, (int32_t)NULL_WORD);
9672 } else {
9673 movslq(dst, (int32_t)NULL_WORD);
9674 }
9675 #else
9676 movl(dst, (int32_t)NULL_WORD);
9677 #endif
9678 }
9680 #ifdef _LP64
9681 void MacroAssembler::store_klass_gap(Register dst, Register src) {
9682 if (UseCompressedOops) {
9683 // Store to klass gap in destination
9684 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
9685 }
9686 }
9688 #ifdef ASSERT
9689 void MacroAssembler::verify_heapbase(const char* msg) {
9690 assert (UseCompressedOops, "should be compressed");
9691 assert (Universe::heap() != NULL, "java heap should be initialized");
9692 if (CheckCompressedOops) {
9693 Label ok;
9694 push(rscratch1); // cmpptr trashes rscratch1
9695 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr()));
9696 jcc(Assembler::equal, ok);
9697 STOP(msg);
9698 bind(ok);
9699 pop(rscratch1);
9700 }
9701 }
9702 #endif
9704 // Algorithm must match oop.inline.hpp encode_heap_oop.
9705 void MacroAssembler::encode_heap_oop(Register r) {
9706 #ifdef ASSERT
9707 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
9708 #endif
9709 verify_oop(r, "broken oop in encode_heap_oop");
9710 if (Universe::narrow_oop_base() == NULL) {
9711 if (Universe::narrow_oop_shift() != 0) {
9712 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
9713 shrq(r, LogMinObjAlignmentInBytes);
9714 }
9715 return;
9716 }
9717 testq(r, r);
9718 cmovq(Assembler::equal, r, r12_heapbase);
9719 subq(r, r12_heapbase);
9720 shrq(r, LogMinObjAlignmentInBytes);
9721 }
9723 void MacroAssembler::encode_heap_oop_not_null(Register r) {
9724 #ifdef ASSERT
9725 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
9726 if (CheckCompressedOops) {
9727 Label ok;
9728 testq(r, r);
9729 jcc(Assembler::notEqual, ok);
9730 STOP("null oop passed to encode_heap_oop_not_null");
9731 bind(ok);
9732 }
9733 #endif
9734 verify_oop(r, "broken oop in encode_heap_oop_not_null");
9735 if (Universe::narrow_oop_base() != NULL) {
9736 subq(r, r12_heapbase);
9737 }
9738 if (Universe::narrow_oop_shift() != 0) {
9739 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
9740 shrq(r, LogMinObjAlignmentInBytes);
9741 }
9742 }
9744 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
9745 #ifdef ASSERT
9746 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
9747 if (CheckCompressedOops) {
9748 Label ok;
9749 testq(src, src);
9750 jcc(Assembler::notEqual, ok);
9751 STOP("null oop passed to encode_heap_oop_not_null2");
9752 bind(ok);
9753 }
9754 #endif
9755 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
9756 if (dst != src) {
9757 movq(dst, src);
9758 }
9759 if (Universe::narrow_oop_base() != NULL) {
9760 subq(dst, r12_heapbase);
9761 }
9762 if (Universe::narrow_oop_shift() != 0) {
9763 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
9764 shrq(dst, LogMinObjAlignmentInBytes);
9765 }
9766 }
9768 void MacroAssembler::decode_heap_oop(Register r) {
9769 #ifdef ASSERT
9770 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
9771 #endif
9772 if (Universe::narrow_oop_base() == NULL) {
9773 if (Universe::narrow_oop_shift() != 0) {
9774 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
9775 shlq(r, LogMinObjAlignmentInBytes);
9776 }
9777 } else {
9778 Label done;
9779 shlq(r, LogMinObjAlignmentInBytes);
9780 jccb(Assembler::equal, done);
9781 addq(r, r12_heapbase);
9782 bind(done);
9783 }
9784 verify_oop(r, "broken oop in decode_heap_oop");
9785 }
9787 void MacroAssembler::decode_heap_oop_not_null(Register r) {
9788 // Note: it will change flags
9789 assert (UseCompressedOops, "should only be used for compressed headers");
9790 assert (Universe::heap() != NULL, "java heap should be initialized");
9791 // Cannot assert, unverified entry point counts instructions (see .ad file)
9792 // vtableStubs also counts instructions in pd_code_size_limit.
9793 // Also do not verify_oop as this is called by verify_oop.
9794 if (Universe::narrow_oop_shift() != 0) {
9795 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
9796 shlq(r, LogMinObjAlignmentInBytes);
9797 if (Universe::narrow_oop_base() != NULL) {
9798 addq(r, r12_heapbase);
9799 }
9800 } else {
9801 assert (Universe::narrow_oop_base() == NULL, "sanity");
9802 }
9803 }
9805 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
9806 // Note: it will change flags
9807 assert (UseCompressedOops, "should only be used for compressed headers");
9808 assert (Universe::heap() != NULL, "java heap should be initialized");
9809 // Cannot assert, unverified entry point counts instructions (see .ad file)
9810 // vtableStubs also counts instructions in pd_code_size_limit.
9811 // Also do not verify_oop as this is called by verify_oop.
9812 if (Universe::narrow_oop_shift() != 0) {
9813 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
9814 if (LogMinObjAlignmentInBytes == Address::times_8) {
9815 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
9816 } else {
9817 if (dst != src) {
9818 movq(dst, src);
9819 }
9820 shlq(dst, LogMinObjAlignmentInBytes);
9821 if (Universe::narrow_oop_base() != NULL) {
9822 addq(dst, r12_heapbase);
9823 }
9824 }
9825 } else {
9826 assert (Universe::narrow_oop_base() == NULL, "sanity");
9827 if (dst != src) {
9828 movq(dst, src);
9829 }
9830 }
9831 }
9833 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
9834 assert (UseCompressedOops, "should only be used for compressed headers");
9835 assert (Universe::heap() != NULL, "java heap should be initialized");
9836 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
9837 int oop_index = oop_recorder()->find_index(obj);
9838 RelocationHolder rspec = oop_Relocation::spec(oop_index);
9839 mov_narrow_oop(dst, oop_index, rspec);
9840 }
9842 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
9843 assert (UseCompressedOops, "should only be used for compressed headers");
9844 assert (Universe::heap() != NULL, "java heap should be initialized");
9845 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
9846 int oop_index = oop_recorder()->find_index(obj);
9847 RelocationHolder rspec = oop_Relocation::spec(oop_index);
9848 mov_narrow_oop(dst, oop_index, rspec);
9849 }
9851 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
9852 assert (UseCompressedOops, "should only be used for compressed headers");
9853 assert (Universe::heap() != NULL, "java heap should be initialized");
9854 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
9855 int oop_index = oop_recorder()->find_index(obj);
9856 RelocationHolder rspec = oop_Relocation::spec(oop_index);
9857 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
9858 }
9860 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
9861 assert (UseCompressedOops, "should only be used for compressed headers");
9862 assert (Universe::heap() != NULL, "java heap should be initialized");
9863 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
9864 int oop_index = oop_recorder()->find_index(obj);
9865 RelocationHolder rspec = oop_Relocation::spec(oop_index);
9866 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
9867 }
9869 void MacroAssembler::reinit_heapbase() {
9870 if (UseCompressedOops) {
9871 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr()));
9872 }
9873 }
9874 #endif // _LP64
9877 // C2 compiled method's prolog code.
9878 void MacroAssembler::verified_entry(int framesize, bool stack_bang, bool fp_mode_24b) {
9880 // WARNING: Initial instruction MUST be 5 bytes or longer so that
9881 // NativeJump::patch_verified_entry will be able to patch out the entry
9882 // code safely. The push to verify stack depth is ok at 5 bytes,
9883 // the frame allocation can be either 3 or 6 bytes. So if we don't do
9884 // stack bang then we must use the 6 byte frame allocation even if
9885 // we have no frame. :-(
9887 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
9888 // Remove word for return addr
9889 framesize -= wordSize;
9891 // Calls to C2R adapters often do not accept exceptional returns.
9892 // We require that their callers must bang for them. But be careful, because
9893 // some VM calls (such as call site linkage) can use several kilobytes of
9894 // stack. But the stack safety zone should account for that.
9895 // See bugs 4446381, 4468289, 4497237.
9896 if (stack_bang) {
9897 generate_stack_overflow_check(framesize);
9899 // We always push rbp, so that on return to interpreter rbp, will be
9900 // restored correctly and we can correct the stack.
9901 push(rbp);
9902 // Remove word for ebp
9903 framesize -= wordSize;
9905 // Create frame
9906 if (framesize) {
9907 subptr(rsp, framesize);
9908 }
9909 } else {
9910 // Create frame (force generation of a 4 byte immediate value)
9911 subptr_imm32(rsp, framesize);
9913 // Save RBP register now.
9914 framesize -= wordSize;
9915 movptr(Address(rsp, framesize), rbp);
9916 }
9918 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
9919 framesize -= wordSize;
9920 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
9921 }
9923 #ifndef _LP64
9924 // If method sets FPU control word do it now
9925 if (fp_mode_24b) {
9926 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
9927 }
9928 if (UseSSE >= 2 && VerifyFPU) {
9929 verify_FPU(0, "FPU stack must be clean on entry");
9930 }
9931 #endif
9933 #ifdef ASSERT
9934 if (VerifyStackAtCalls) {
9935 Label L;
9936 push(rax);
9937 mov(rax, rsp);
9938 andptr(rax, StackAlignmentInBytes-1);
9939 cmpptr(rax, StackAlignmentInBytes-wordSize);
9940 pop(rax);
9941 jcc(Assembler::equal, L);
9942 STOP("Stack is not properly aligned!");
9943 bind(L);
9944 }
9945 #endif
9947 }
9950 // IndexOf for constant substrings with size >= 8 chars
9951 // which don't need to be loaded through stack.
9952 void MacroAssembler::string_indexofC8(Register str1, Register str2,
9953 Register cnt1, Register cnt2,
9954 int int_cnt2, Register result,
9955 XMMRegister vec, Register tmp) {
9956 ShortBranchVerifier sbv(this);
9957 assert(UseSSE42Intrinsics, "SSE4.2 is required");
9959 // This method uses pcmpestri inxtruction with bound registers
9960 // inputs:
9961 // xmm - substring
9962 // rax - substring length (elements count)
9963 // mem - scanned string
9964 // rdx - string length (elements count)
9965 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
9966 // outputs:
9967 // rcx - matched index in string
9968 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
9970 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
9971 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
9972 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
9974 // Note, inline_string_indexOf() generates checks:
9975 // if (substr.count > string.count) return -1;
9976 // if (substr.count == 0) return 0;
9977 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars");
9979 // Load substring.
9980 movdqu(vec, Address(str2, 0));
9981 movl(cnt2, int_cnt2);
9982 movptr(result, str1); // string addr
9984 if (int_cnt2 > 8) {
9985 jmpb(SCAN_TO_SUBSTR);
9987 // Reload substr for rescan, this code
9988 // is executed only for large substrings (> 8 chars)
9989 bind(RELOAD_SUBSTR);
9990 movdqu(vec, Address(str2, 0));
9991 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
9993 bind(RELOAD_STR);
9994 // We came here after the beginning of the substring was
9995 // matched but the rest of it was not so we need to search
9996 // again. Start from the next element after the previous match.
9998 // cnt2 is number of substring reminding elements and
9999 // cnt1 is number of string reminding elements when cmp failed.
10000 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
10001 subl(cnt1, cnt2);
10002 addl(cnt1, int_cnt2);
10003 movl(cnt2, int_cnt2); // Now restore cnt2
10005 decrementl(cnt1); // Shift to next element
10006 cmpl(cnt1, cnt2);
10007 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
10009 addptr(result, 2);
10011 } // (int_cnt2 > 8)
10013 // Scan string for start of substr in 16-byte vectors
10014 bind(SCAN_TO_SUBSTR);
10015 pcmpestri(vec, Address(result, 0), 0x0d);
10016 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
10017 subl(cnt1, 8);
10018 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
10019 cmpl(cnt1, cnt2);
10020 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
10021 addptr(result, 16);
10022 jmpb(SCAN_TO_SUBSTR);
10024 // Found a potential substr
10025 bind(FOUND_CANDIDATE);
10026 // Matched whole vector if first element matched (tmp(rcx) == 0).
10027 if (int_cnt2 == 8) {
10028 jccb(Assembler::overflow, RET_FOUND); // OF == 1
10029 } else { // int_cnt2 > 8
10030 jccb(Assembler::overflow, FOUND_SUBSTR);
10031 }
10032 // After pcmpestri tmp(rcx) contains matched element index
10033 // Compute start addr of substr
10034 lea(result, Address(result, tmp, Address::times_2));
10036 // Make sure string is still long enough
10037 subl(cnt1, tmp);
10038 cmpl(cnt1, cnt2);
10039 if (int_cnt2 == 8) {
10040 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
10041 } else { // int_cnt2 > 8
10042 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
10043 }
10044 // Left less then substring.
10046 bind(RET_NOT_FOUND);
10047 movl(result, -1);
10048 jmpb(EXIT);
10050 if (int_cnt2 > 8) {
10051 // This code is optimized for the case when whole substring
10052 // is matched if its head is matched.
10053 bind(MATCH_SUBSTR_HEAD);
10054 pcmpestri(vec, Address(result, 0), 0x0d);
10055 // Reload only string if does not match
10056 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0
10058 Label CONT_SCAN_SUBSTR;
10059 // Compare the rest of substring (> 8 chars).
10060 bind(FOUND_SUBSTR);
10061 // First 8 chars are already matched.
10062 negptr(cnt2);
10063 addptr(cnt2, 8);
10065 bind(SCAN_SUBSTR);
10066 subl(cnt1, 8);
10067 cmpl(cnt2, -8); // Do not read beyond substring
10068 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
10069 // Back-up strings to avoid reading beyond substring:
10070 // cnt1 = cnt1 - cnt2 + 8
10071 addl(cnt1, cnt2); // cnt2 is negative
10072 addl(cnt1, 8);
10073 movl(cnt2, 8); negptr(cnt2);
10074 bind(CONT_SCAN_SUBSTR);
10075 if (int_cnt2 < (int)G) {
10076 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2));
10077 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d);
10078 } else {
10079 // calculate index in register to avoid integer overflow (int_cnt2*2)
10080 movl(tmp, int_cnt2);
10081 addptr(tmp, cnt2);
10082 movdqu(vec, Address(str2, tmp, Address::times_2, 0));
10083 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d);
10084 }
10085 // Need to reload strings pointers if not matched whole vector
10086 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
10087 addptr(cnt2, 8);
10088 jcc(Assembler::negative, SCAN_SUBSTR);
10089 // Fall through if found full substring
10091 } // (int_cnt2 > 8)
10093 bind(RET_FOUND);
10094 // Found result if we matched full small substring.
10095 // Compute substr offset
10096 subptr(result, str1);
10097 shrl(result, 1); // index
10098 bind(EXIT);
10100 } // string_indexofC8
10102 // Small strings are loaded through stack if they cross page boundary.
10103 void MacroAssembler::string_indexof(Register str1, Register str2,
10104 Register cnt1, Register cnt2,
10105 int int_cnt2, Register result,
10106 XMMRegister vec, Register tmp) {
10107 ShortBranchVerifier sbv(this);
10108 assert(UseSSE42Intrinsics, "SSE4.2 is required");
10109 //
10110 // int_cnt2 is length of small (< 8 chars) constant substring
10111 // or (-1) for non constant substring in which case its length
10112 // is in cnt2 register.
10113 //
10114 // Note, inline_string_indexOf() generates checks:
10115 // if (substr.count > string.count) return -1;
10116 // if (substr.count == 0) return 0;
10117 //
10118 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0");
10120 // This method uses pcmpestri inxtruction with bound registers
10121 // inputs:
10122 // xmm - substring
10123 // rax - substring length (elements count)
10124 // mem - scanned string
10125 // rdx - string length (elements count)
10126 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
10127 // outputs:
10128 // rcx - matched index in string
10129 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
10131 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
10132 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
10133 FOUND_CANDIDATE;
10135 { //========================================================
10136 // We don't know where these strings are located
10137 // and we can't read beyond them. Load them through stack.
10138 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
10140 movptr(tmp, rsp); // save old SP
10142 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
10143 if (int_cnt2 == 1) { // One char
10144 load_unsigned_short(result, Address(str2, 0));
10145 movdl(vec, result); // move 32 bits
10146 } else if (int_cnt2 == 2) { // Two chars
10147 movdl(vec, Address(str2, 0)); // move 32 bits
10148 } else if (int_cnt2 == 4) { // Four chars
10149 movq(vec, Address(str2, 0)); // move 64 bits
10150 } else { // cnt2 = { 3, 5, 6, 7 }
10151 // Array header size is 12 bytes in 32-bit VM
10152 // + 6 bytes for 3 chars == 18 bytes,
10153 // enough space to load vec and shift.
10154 assert(HeapWordSize*typeArrayKlass::header_size() >= 12,"sanity");
10155 movdqu(vec, Address(str2, (int_cnt2*2)-16));
10156 psrldq(vec, 16-(int_cnt2*2));
10157 }
10158 } else { // not constant substring
10159 cmpl(cnt2, 8);
10160 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
10162 // We can read beyond string if srt+16 does not cross page boundary
10163 // since heaps are aligned and mapped by pages.
10164 assert(os::vm_page_size() < (int)G, "default page should be small");
10165 movl(result, str2); // We need only low 32 bits
10166 andl(result, (os::vm_page_size()-1));
10167 cmpl(result, (os::vm_page_size()-16));
10168 jccb(Assembler::belowEqual, CHECK_STR);
10170 // Move small strings to stack to allow load 16 bytes into vec.
10171 subptr(rsp, 16);
10172 int stk_offset = wordSize-2;
10173 push(cnt2);
10175 bind(COPY_SUBSTR);
10176 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2));
10177 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
10178 decrement(cnt2);
10179 jccb(Assembler::notZero, COPY_SUBSTR);
10181 pop(cnt2);
10182 movptr(str2, rsp); // New substring address
10183 } // non constant
10185 bind(CHECK_STR);
10186 cmpl(cnt1, 8);
10187 jccb(Assembler::aboveEqual, BIG_STRINGS);
10189 // Check cross page boundary.
10190 movl(result, str1); // We need only low 32 bits
10191 andl(result, (os::vm_page_size()-1));
10192 cmpl(result, (os::vm_page_size()-16));
10193 jccb(Assembler::belowEqual, BIG_STRINGS);
10195 subptr(rsp, 16);
10196 int stk_offset = -2;
10197 if (int_cnt2 < 0) { // not constant
10198 push(cnt2);
10199 stk_offset += wordSize;
10200 }
10201 movl(cnt2, cnt1);
10203 bind(COPY_STR);
10204 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2));
10205 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
10206 decrement(cnt2);
10207 jccb(Assembler::notZero, COPY_STR);
10209 if (int_cnt2 < 0) { // not constant
10210 pop(cnt2);
10211 }
10212 movptr(str1, rsp); // New string address
10214 bind(BIG_STRINGS);
10215 // Load substring.
10216 if (int_cnt2 < 0) { // -1
10217 movdqu(vec, Address(str2, 0));
10218 push(cnt2); // substr count
10219 push(str2); // substr addr
10220 push(str1); // string addr
10221 } else {
10222 // Small (< 8 chars) constant substrings are loaded already.
10223 movl(cnt2, int_cnt2);
10224 }
10225 push(tmp); // original SP
10227 } // Finished loading
10229 //========================================================
10230 // Start search
10231 //
10233 movptr(result, str1); // string addr
10235 if (int_cnt2 < 0) { // Only for non constant substring
10236 jmpb(SCAN_TO_SUBSTR);
10238 // SP saved at sp+0
10239 // String saved at sp+1*wordSize
10240 // Substr saved at sp+2*wordSize
10241 // Substr count saved at sp+3*wordSize
10243 // Reload substr for rescan, this code
10244 // is executed only for large substrings (> 8 chars)
10245 bind(RELOAD_SUBSTR);
10246 movptr(str2, Address(rsp, 2*wordSize));
10247 movl(cnt2, Address(rsp, 3*wordSize));
10248 movdqu(vec, Address(str2, 0));
10249 // We came here after the beginning of the substring was
10250 // matched but the rest of it was not so we need to search
10251 // again. Start from the next element after the previous match.
10252 subptr(str1, result); // Restore counter
10253 shrl(str1, 1);
10254 addl(cnt1, str1);
10255 decrementl(cnt1); // Shift to next element
10256 cmpl(cnt1, cnt2);
10257 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
10259 addptr(result, 2);
10260 } // non constant
10262 // Scan string for start of substr in 16-byte vectors
10263 bind(SCAN_TO_SUBSTR);
10264 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
10265 pcmpestri(vec, Address(result, 0), 0x0d);
10266 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
10267 subl(cnt1, 8);
10268 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
10269 cmpl(cnt1, cnt2);
10270 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
10271 addptr(result, 16);
10273 bind(ADJUST_STR);
10274 cmpl(cnt1, 8); // Do not read beyond string
10275 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
10276 // Back-up string to avoid reading beyond string.
10277 lea(result, Address(result, cnt1, Address::times_2, -16));
10278 movl(cnt1, 8);
10279 jmpb(SCAN_TO_SUBSTR);
10281 // Found a potential substr
10282 bind(FOUND_CANDIDATE);
10283 // After pcmpestri tmp(rcx) contains matched element index
10285 // Make sure string is still long enough
10286 subl(cnt1, tmp);
10287 cmpl(cnt1, cnt2);
10288 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
10289 // Left less then substring.
10291 bind(RET_NOT_FOUND);
10292 movl(result, -1);
10293 jmpb(CLEANUP);
10295 bind(FOUND_SUBSTR);
10296 // Compute start addr of substr
10297 lea(result, Address(result, tmp, Address::times_2));
10299 if (int_cnt2 > 0) { // Constant substring
10300 // Repeat search for small substring (< 8 chars)
10301 // from new point without reloading substring.
10302 // Have to check that we don't read beyond string.
10303 cmpl(tmp, 8-int_cnt2);
10304 jccb(Assembler::greater, ADJUST_STR);
10305 // Fall through if matched whole substring.
10306 } else { // non constant
10307 assert(int_cnt2 == -1, "should be != 0");
10309 addl(tmp, cnt2);
10310 // Found result if we matched whole substring.
10311 cmpl(tmp, 8);
10312 jccb(Assembler::lessEqual, RET_FOUND);
10314 // Repeat search for small substring (<= 8 chars)
10315 // from new point 'str1' without reloading substring.
10316 cmpl(cnt2, 8);
10317 // Have to check that we don't read beyond string.
10318 jccb(Assembler::lessEqual, ADJUST_STR);
10320 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
10321 // Compare the rest of substring (> 8 chars).
10322 movptr(str1, result);
10324 cmpl(tmp, cnt2);
10325 // First 8 chars are already matched.
10326 jccb(Assembler::equal, CHECK_NEXT);
10328 bind(SCAN_SUBSTR);
10329 pcmpestri(vec, Address(str1, 0), 0x0d);
10330 // Need to reload strings pointers if not matched whole vector
10331 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
10333 bind(CHECK_NEXT);
10334 subl(cnt2, 8);
10335 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
10336 addptr(str1, 16);
10337 addptr(str2, 16);
10338 subl(cnt1, 8);
10339 cmpl(cnt2, 8); // Do not read beyond substring
10340 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
10341 // Back-up strings to avoid reading beyond substring.
10342 lea(str2, Address(str2, cnt2, Address::times_2, -16));
10343 lea(str1, Address(str1, cnt2, Address::times_2, -16));
10344 subl(cnt1, cnt2);
10345 movl(cnt2, 8);
10346 addl(cnt1, 8);
10347 bind(CONT_SCAN_SUBSTR);
10348 movdqu(vec, Address(str2, 0));
10349 jmpb(SCAN_SUBSTR);
10351 bind(RET_FOUND_LONG);
10352 movptr(str1, Address(rsp, wordSize));
10353 } // non constant
10355 bind(RET_FOUND);
10356 // Compute substr offset
10357 subptr(result, str1);
10358 shrl(result, 1); // index
10360 bind(CLEANUP);
10361 pop(rsp); // restore SP
10363 } // string_indexof
10365 // Compare strings.
10366 void MacroAssembler::string_compare(Register str1, Register str2,
10367 Register cnt1, Register cnt2, Register result,
10368 XMMRegister vec1) {
10369 ShortBranchVerifier sbv(this);
10370 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
10372 // Compute the minimum of the string lengths and the
10373 // difference of the string lengths (stack).
10374 // Do the conditional move stuff
10375 movl(result, cnt1);
10376 subl(cnt1, cnt2);
10377 push(cnt1);
10378 cmov32(Assembler::lessEqual, cnt2, result);
10380 // Is the minimum length zero?
10381 testl(cnt2, cnt2);
10382 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
10384 // Load first characters
10385 load_unsigned_short(result, Address(str1, 0));
10386 load_unsigned_short(cnt1, Address(str2, 0));
10388 // Compare first characters
10389 subl(result, cnt1);
10390 jcc(Assembler::notZero, POP_LABEL);
10391 decrementl(cnt2);
10392 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
10394 {
10395 // Check after comparing first character to see if strings are equivalent
10396 Label LSkip2;
10397 // Check if the strings start at same location
10398 cmpptr(str1, str2);
10399 jccb(Assembler::notEqual, LSkip2);
10401 // Check if the length difference is zero (from stack)
10402 cmpl(Address(rsp, 0), 0x0);
10403 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
10405 // Strings might not be equivalent
10406 bind(LSkip2);
10407 }
10409 Address::ScaleFactor scale = Address::times_2;
10410 int stride = 8;
10412 // Advance to next element
10413 addptr(str1, 16/stride);
10414 addptr(str2, 16/stride);
10416 if (UseSSE42Intrinsics) {
10417 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
10418 int pcmpmask = 0x19;
10419 // Setup to compare 16-byte vectors
10420 movl(result, cnt2);
10421 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
10422 jccb(Assembler::zero, COMPARE_TAIL);
10424 lea(str1, Address(str1, result, scale));
10425 lea(str2, Address(str2, result, scale));
10426 negptr(result);
10428 // pcmpestri
10429 // inputs:
10430 // vec1- substring
10431 // rax - negative string length (elements count)
10432 // mem - scaned string
10433 // rdx - string length (elements count)
10434 // pcmpmask - cmp mode: 11000 (string compare with negated result)
10435 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
10436 // outputs:
10437 // rcx - first mismatched element index
10438 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
10440 bind(COMPARE_WIDE_VECTORS);
10441 movdqu(vec1, Address(str1, result, scale));
10442 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
10443 // After pcmpestri cnt1(rcx) contains mismatched element index
10445 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
10446 addptr(result, stride);
10447 subptr(cnt2, stride);
10448 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
10450 // compare wide vectors tail
10451 testl(result, result);
10452 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
10454 movl(cnt2, stride);
10455 movl(result, stride);
10456 negptr(result);
10457 movdqu(vec1, Address(str1, result, scale));
10458 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
10459 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
10461 // Mismatched characters in the vectors
10462 bind(VECTOR_NOT_EQUAL);
10463 addptr(result, cnt1);
10464 movptr(cnt2, result);
10465 load_unsigned_short(result, Address(str1, cnt2, scale));
10466 load_unsigned_short(cnt1, Address(str2, cnt2, scale));
10467 subl(result, cnt1);
10468 jmpb(POP_LABEL);
10470 bind(COMPARE_TAIL); // limit is zero
10471 movl(cnt2, result);
10472 // Fallthru to tail compare
10473 }
10475 // Shift str2 and str1 to the end of the arrays, negate min
10476 lea(str1, Address(str1, cnt2, scale, 0));
10477 lea(str2, Address(str2, cnt2, scale, 0));
10478 negptr(cnt2);
10480 // Compare the rest of the elements
10481 bind(WHILE_HEAD_LABEL);
10482 load_unsigned_short(result, Address(str1, cnt2, scale, 0));
10483 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0));
10484 subl(result, cnt1);
10485 jccb(Assembler::notZero, POP_LABEL);
10486 increment(cnt2);
10487 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
10489 // Strings are equal up to min length. Return the length difference.
10490 bind(LENGTH_DIFF_LABEL);
10491 pop(result);
10492 jmpb(DONE_LABEL);
10494 // Discard the stored length difference
10495 bind(POP_LABEL);
10496 pop(cnt1);
10498 // That's it
10499 bind(DONE_LABEL);
10500 }
10502 // Compare char[] arrays aligned to 4 bytes or substrings.
10503 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
10504 Register limit, Register result, Register chr,
10505 XMMRegister vec1, XMMRegister vec2) {
10506 ShortBranchVerifier sbv(this);
10507 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
10509 int length_offset = arrayOopDesc::length_offset_in_bytes();
10510 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
10512 // Check the input args
10513 cmpptr(ary1, ary2);
10514 jcc(Assembler::equal, TRUE_LABEL);
10516 if (is_array_equ) {
10517 // Need additional checks for arrays_equals.
10518 testptr(ary1, ary1);
10519 jcc(Assembler::zero, FALSE_LABEL);
10520 testptr(ary2, ary2);
10521 jcc(Assembler::zero, FALSE_LABEL);
10523 // Check the lengths
10524 movl(limit, Address(ary1, length_offset));
10525 cmpl(limit, Address(ary2, length_offset));
10526 jcc(Assembler::notEqual, FALSE_LABEL);
10527 }
10529 // count == 0
10530 testl(limit, limit);
10531 jcc(Assembler::zero, TRUE_LABEL);
10533 if (is_array_equ) {
10534 // Load array address
10535 lea(ary1, Address(ary1, base_offset));
10536 lea(ary2, Address(ary2, base_offset));
10537 }
10539 shll(limit, 1); // byte count != 0
10540 movl(result, limit); // copy
10542 if (UseSSE42Intrinsics) {
10543 // With SSE4.2, use double quad vector compare
10544 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
10546 // Compare 16-byte vectors
10547 andl(result, 0x0000000e); // tail count (in bytes)
10548 andl(limit, 0xfffffff0); // vector count (in bytes)
10549 jccb(Assembler::zero, COMPARE_TAIL);
10551 lea(ary1, Address(ary1, limit, Address::times_1));
10552 lea(ary2, Address(ary2, limit, Address::times_1));
10553 negptr(limit);
10555 bind(COMPARE_WIDE_VECTORS);
10556 movdqu(vec1, Address(ary1, limit, Address::times_1));
10557 movdqu(vec2, Address(ary2, limit, Address::times_1));
10558 pxor(vec1, vec2);
10560 ptest(vec1, vec1);
10561 jccb(Assembler::notZero, FALSE_LABEL);
10562 addptr(limit, 16);
10563 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
10565 testl(result, result);
10566 jccb(Assembler::zero, TRUE_LABEL);
10568 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
10569 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
10570 pxor(vec1, vec2);
10572 ptest(vec1, vec1);
10573 jccb(Assembler::notZero, FALSE_LABEL);
10574 jmpb(TRUE_LABEL);
10576 bind(COMPARE_TAIL); // limit is zero
10577 movl(limit, result);
10578 // Fallthru to tail compare
10579 }
10581 // Compare 4-byte vectors
10582 andl(limit, 0xfffffffc); // vector count (in bytes)
10583 jccb(Assembler::zero, COMPARE_CHAR);
10585 lea(ary1, Address(ary1, limit, Address::times_1));
10586 lea(ary2, Address(ary2, limit, Address::times_1));
10587 negptr(limit);
10589 bind(COMPARE_VECTORS);
10590 movl(chr, Address(ary1, limit, Address::times_1));
10591 cmpl(chr, Address(ary2, limit, Address::times_1));
10592 jccb(Assembler::notEqual, FALSE_LABEL);
10593 addptr(limit, 4);
10594 jcc(Assembler::notZero, COMPARE_VECTORS);
10596 // Compare trailing char (final 2 bytes), if any
10597 bind(COMPARE_CHAR);
10598 testl(result, 0x2); // tail char
10599 jccb(Assembler::zero, TRUE_LABEL);
10600 load_unsigned_short(chr, Address(ary1, 0));
10601 load_unsigned_short(limit, Address(ary2, 0));
10602 cmpl(chr, limit);
10603 jccb(Assembler::notEqual, FALSE_LABEL);
10605 bind(TRUE_LABEL);
10606 movl(result, 1); // return true
10607 jmpb(DONE);
10609 bind(FALSE_LABEL);
10610 xorl(result, result); // return false
10612 // That's it
10613 bind(DONE);
10614 }
10616 void MacroAssembler::generate_fill(BasicType t, bool aligned,
10617 Register to, Register value, Register count,
10618 Register rtmp, XMMRegister xtmp) {
10619 ShortBranchVerifier sbv(this);
10620 assert_different_registers(to, value, count, rtmp);
10621 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
10622 Label L_fill_2_bytes, L_fill_4_bytes;
10624 int shift = -1;
10625 switch (t) {
10626 case T_BYTE:
10627 shift = 2;
10628 break;
10629 case T_SHORT:
10630 shift = 1;
10631 break;
10632 case T_INT:
10633 shift = 0;
10634 break;
10635 default: ShouldNotReachHere();
10636 }
10638 if (t == T_BYTE) {
10639 andl(value, 0xff);
10640 movl(rtmp, value);
10641 shll(rtmp, 8);
10642 orl(value, rtmp);
10643 }
10644 if (t == T_SHORT) {
10645 andl(value, 0xffff);
10646 }
10647 if (t == T_BYTE || t == T_SHORT) {
10648 movl(rtmp, value);
10649 shll(rtmp, 16);
10650 orl(value, rtmp);
10651 }
10653 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
10654 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
10655 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
10656 // align source address at 4 bytes address boundary
10657 if (t == T_BYTE) {
10658 // One byte misalignment happens only for byte arrays
10659 testptr(to, 1);
10660 jccb(Assembler::zero, L_skip_align1);
10661 movb(Address(to, 0), value);
10662 increment(to);
10663 decrement(count);
10664 BIND(L_skip_align1);
10665 }
10666 // Two bytes misalignment happens only for byte and short (char) arrays
10667 testptr(to, 2);
10668 jccb(Assembler::zero, L_skip_align2);
10669 movw(Address(to, 0), value);
10670 addptr(to, 2);
10671 subl(count, 1<<(shift-1));
10672 BIND(L_skip_align2);
10673 }
10674 if (UseSSE < 2) {
10675 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
10676 // Fill 32-byte chunks
10677 subl(count, 8 << shift);
10678 jcc(Assembler::less, L_check_fill_8_bytes);
10679 align(16);
10681 BIND(L_fill_32_bytes_loop);
10683 for (int i = 0; i < 32; i += 4) {
10684 movl(Address(to, i), value);
10685 }
10687 addptr(to, 32);
10688 subl(count, 8 << shift);
10689 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
10690 BIND(L_check_fill_8_bytes);
10691 addl(count, 8 << shift);
10692 jccb(Assembler::zero, L_exit);
10693 jmpb(L_fill_8_bytes);
10695 //
10696 // length is too short, just fill qwords
10697 //
10698 BIND(L_fill_8_bytes_loop);
10699 movl(Address(to, 0), value);
10700 movl(Address(to, 4), value);
10701 addptr(to, 8);
10702 BIND(L_fill_8_bytes);
10703 subl(count, 1 << (shift + 1));
10704 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
10705 // fall through to fill 4 bytes
10706 } else {
10707 Label L_fill_32_bytes;
10708 if (!UseUnalignedLoadStores) {
10709 // align to 8 bytes, we know we are 4 byte aligned to start
10710 testptr(to, 4);
10711 jccb(Assembler::zero, L_fill_32_bytes);
10712 movl(Address(to, 0), value);
10713 addptr(to, 4);
10714 subl(count, 1<<shift);
10715 }
10716 BIND(L_fill_32_bytes);
10717 {
10718 assert( UseSSE >= 2, "supported cpu only" );
10719 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
10720 // Fill 32-byte chunks
10721 movdl(xtmp, value);
10722 pshufd(xtmp, xtmp, 0);
10724 subl(count, 8 << shift);
10725 jcc(Assembler::less, L_check_fill_8_bytes);
10726 align(16);
10728 BIND(L_fill_32_bytes_loop);
10730 if (UseUnalignedLoadStores) {
10731 movdqu(Address(to, 0), xtmp);
10732 movdqu(Address(to, 16), xtmp);
10733 } else {
10734 movq(Address(to, 0), xtmp);
10735 movq(Address(to, 8), xtmp);
10736 movq(Address(to, 16), xtmp);
10737 movq(Address(to, 24), xtmp);
10738 }
10740 addptr(to, 32);
10741 subl(count, 8 << shift);
10742 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
10743 BIND(L_check_fill_8_bytes);
10744 addl(count, 8 << shift);
10745 jccb(Assembler::zero, L_exit);
10746 jmpb(L_fill_8_bytes);
10748 //
10749 // length is too short, just fill qwords
10750 //
10751 BIND(L_fill_8_bytes_loop);
10752 movq(Address(to, 0), xtmp);
10753 addptr(to, 8);
10754 BIND(L_fill_8_bytes);
10755 subl(count, 1 << (shift + 1));
10756 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
10757 }
10758 }
10759 // fill trailing 4 bytes
10760 BIND(L_fill_4_bytes);
10761 testl(count, 1<<shift);
10762 jccb(Assembler::zero, L_fill_2_bytes);
10763 movl(Address(to, 0), value);
10764 if (t == T_BYTE || t == T_SHORT) {
10765 addptr(to, 4);
10766 BIND(L_fill_2_bytes);
10767 // fill trailing 2 bytes
10768 testl(count, 1<<(shift-1));
10769 jccb(Assembler::zero, L_fill_byte);
10770 movw(Address(to, 0), value);
10771 if (t == T_BYTE) {
10772 addptr(to, 2);
10773 BIND(L_fill_byte);
10774 // fill trailing byte
10775 testl(count, 1);
10776 jccb(Assembler::zero, L_exit);
10777 movb(Address(to, 0), value);
10778 } else {
10779 BIND(L_fill_byte);
10780 }
10781 } else {
10782 BIND(L_fill_2_bytes);
10783 }
10784 BIND(L_exit);
10785 }
10786 #undef BIND
10787 #undef BLOCK_COMMENT
10790 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10791 switch (cond) {
10792 // Note some conditions are synonyms for others
10793 case Assembler::zero: return Assembler::notZero;
10794 case Assembler::notZero: return Assembler::zero;
10795 case Assembler::less: return Assembler::greaterEqual;
10796 case Assembler::lessEqual: return Assembler::greater;
10797 case Assembler::greater: return Assembler::lessEqual;
10798 case Assembler::greaterEqual: return Assembler::less;
10799 case Assembler::below: return Assembler::aboveEqual;
10800 case Assembler::belowEqual: return Assembler::above;
10801 case Assembler::above: return Assembler::belowEqual;
10802 case Assembler::aboveEqual: return Assembler::below;
10803 case Assembler::overflow: return Assembler::noOverflow;
10804 case Assembler::noOverflow: return Assembler::overflow;
10805 case Assembler::negative: return Assembler::positive;
10806 case Assembler::positive: return Assembler::negative;
10807 case Assembler::parity: return Assembler::noParity;
10808 case Assembler::noParity: return Assembler::parity;
10809 }
10810 ShouldNotReachHere(); return Assembler::overflow;
10811 }
10813 SkipIfEqual::SkipIfEqual(
10814 MacroAssembler* masm, const bool* flag_addr, bool value) {
10815 _masm = masm;
10816 _masm->cmp8(ExternalAddress((address)flag_addr), value);
10817 _masm->jcc(Assembler::equal, _label);
10818 }
10820 SkipIfEqual::~SkipIfEqual() {
10821 _masm->bind(_label);
10822 }