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src/share/vm/c1/c1_LIR.cpp@10ee2b297ccd
src/share/vm/c1/c1_LIR.cpp
Wed, 14 Sep 2011 10:40:13 +0200
- author
- bdelsart
- date
- Wed, 14 Sep 2011 10:40:13 +0200
- changeset 3141
- 10ee2b297ccd
- parent 2488
- e4fee0bdaa85
- child 3153
- 5cceda753a4a
- permissions
- -rw-r--r--
7057978: improve robustness of c1 ARM back-end wrt non encodable constants
Summary: ARM only, avoid assertion failures for huge constants generated by C1 shared code
Reviewed-by: never, vladidan
1 /*
2 * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "c1/c1_InstructionPrinter.hpp"
27 #include "c1/c1_LIR.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_ValueStack.hpp"
30 #include "ci/ciInstance.hpp"
31 #include "runtime/sharedRuntime.hpp"
33 Register LIR_OprDesc::as_register() const {
34 return FrameMap::cpu_rnr2reg(cpu_regnr());
35 }
37 Register LIR_OprDesc::as_register_lo() const {
38 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
39 }
41 Register LIR_OprDesc::as_register_hi() const {
42 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
43 }
45 #if defined(X86)
47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
48 return FrameMap::nr2xmmreg(xmm_regnr());
49 }
51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
53 return FrameMap::nr2xmmreg(xmm_regnrLo());
54 }
56 #endif // X86
58 #if defined(SPARC) || defined(PPC)
60 FloatRegister LIR_OprDesc::as_float_reg() const {
61 return FrameMap::nr2floatreg(fpu_regnr());
62 }
64 FloatRegister LIR_OprDesc::as_double_reg() const {
65 return FrameMap::nr2floatreg(fpu_regnrHi());
66 }
68 #endif
70 #ifdef ARM
72 FloatRegister LIR_OprDesc::as_float_reg() const {
73 return as_FloatRegister(fpu_regnr());
74 }
76 FloatRegister LIR_OprDesc::as_double_reg() const {
77 return as_FloatRegister(fpu_regnrLo());
78 }
80 #endif
83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
85 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
86 ValueTag tag = type->tag();
87 switch (tag) {
88 case objectTag : {
89 ClassConstant* c = type->as_ClassConstant();
90 if (c != NULL && !c->value()->is_loaded()) {
91 return LIR_OprFact::oopConst(NULL);
92 } else {
93 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
94 }
95 }
96 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
97 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
98 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
99 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
100 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
101 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
102 }
103 }
106 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
107 switch (type->tag()) {
108 case objectTag: return LIR_OprFact::oopConst(NULL);
109 case addressTag:return LIR_OprFact::addressConst(0);
110 case intTag: return LIR_OprFact::intConst(0);
111 case floatTag: return LIR_OprFact::floatConst(0.0);
112 case longTag: return LIR_OprFact::longConst(0);
113 case doubleTag: return LIR_OprFact::doubleConst(0.0);
114 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
115 }
116 return illegalOpr;
117 }
121 //---------------------------------------------------
124 LIR_Address::Scale LIR_Address::scale(BasicType type) {
125 int elem_size = type2aelembytes(type);
126 switch (elem_size) {
127 case 1: return LIR_Address::times_1;
128 case 2: return LIR_Address::times_2;
129 case 4: return LIR_Address::times_4;
130 case 8: return LIR_Address::times_8;
131 }
132 ShouldNotReachHere();
133 return LIR_Address::times_1;
134 }
137 #ifndef PRODUCT
138 void LIR_Address::verify() const {
139 #if defined(SPARC) || defined(PPC)
140 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
141 assert(disp() == 0 || index()->is_illegal(), "can't have both");
142 #endif
143 #ifdef ARM
144 assert(disp() == 0 || index()->is_illegal(), "can't have both");
145 // Note: offsets higher than 4096 must not be rejected here. They can
146 // be handled by the back-end or will be rejected if not.
147 #endif
148 #ifdef _LP64
149 assert(base()->is_cpu_register(), "wrong base operand");
150 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
151 assert(base()->type() == T_OBJECT || base()->type() == T_LONG,
152 "wrong type for addresses");
153 #else
154 assert(base()->is_single_cpu(), "wrong base operand");
155 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
156 assert(base()->type() == T_OBJECT || base()->type() == T_INT,
157 "wrong type for addresses");
158 #endif
159 }
160 #endif
163 //---------------------------------------------------
165 char LIR_OprDesc::type_char(BasicType t) {
166 switch (t) {
167 case T_ARRAY:
168 t = T_OBJECT;
169 case T_BOOLEAN:
170 case T_CHAR:
171 case T_FLOAT:
172 case T_DOUBLE:
173 case T_BYTE:
174 case T_SHORT:
175 case T_INT:
176 case T_LONG:
177 case T_OBJECT:
178 case T_ADDRESS:
179 case T_VOID:
180 return ::type2char(t);
182 case T_ILLEGAL:
183 return '?';
185 default:
186 ShouldNotReachHere();
187 return '?';
188 }
189 }
191 #ifndef PRODUCT
192 void LIR_OprDesc::validate_type() const {
194 #ifdef ASSERT
195 if (!is_pointer() && !is_illegal()) {
196 switch (as_BasicType(type_field())) {
197 case T_LONG:
198 assert((kind_field() == cpu_register || kind_field() == stack_value) &&
199 size_field() == double_size, "must match");
200 break;
201 case T_FLOAT:
202 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
203 assert((kind_field() == fpu_register || kind_field() == stack_value
204 ARM_ONLY(|| kind_field() == cpu_register)
205 PPC_ONLY(|| kind_field() == cpu_register) ) &&
206 size_field() == single_size, "must match");
207 break;
208 case T_DOUBLE:
209 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
210 assert((kind_field() == fpu_register || kind_field() == stack_value
211 ARM_ONLY(|| kind_field() == cpu_register)
212 PPC_ONLY(|| kind_field() == cpu_register) ) &&
213 size_field() == double_size, "must match");
214 break;
215 case T_BOOLEAN:
216 case T_CHAR:
217 case T_BYTE:
218 case T_SHORT:
219 case T_INT:
220 case T_ADDRESS:
221 case T_OBJECT:
222 case T_ARRAY:
223 assert((kind_field() == cpu_register || kind_field() == stack_value) &&
224 size_field() == single_size, "must match");
225 break;
227 case T_ILLEGAL:
228 // XXX TKR also means unknown right now
229 // assert(is_illegal(), "must match");
230 break;
232 default:
233 ShouldNotReachHere();
234 }
235 }
236 #endif
238 }
239 #endif // PRODUCT
242 bool LIR_OprDesc::is_oop() const {
243 if (is_pointer()) {
244 return pointer()->is_oop_pointer();
245 } else {
246 OprType t= type_field();
247 assert(t != unknown_type, "not set");
248 return t == object_type;
249 }
250 }
254 void LIR_Op2::verify() const {
255 #ifdef ASSERT
256 switch (code()) {
257 case lir_cmove:
258 break;
260 default:
261 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
262 "can't produce oops from arith");
263 }
265 if (TwoOperandLIRForm) {
266 switch (code()) {
267 case lir_add:
268 case lir_sub:
269 case lir_mul:
270 case lir_mul_strictfp:
271 case lir_div:
272 case lir_div_strictfp:
273 case lir_rem:
274 case lir_logic_and:
275 case lir_logic_or:
276 case lir_logic_xor:
277 case lir_shl:
278 case lir_shr:
279 assert(in_opr1() == result_opr(), "opr1 and result must match");
280 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
281 break;
283 // special handling for lir_ushr because of write barriers
284 case lir_ushr:
285 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
286 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
287 break;
289 }
290 }
291 #endif
292 }
295 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
296 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
297 , _cond(cond)
298 , _type(type)
299 , _label(block->label())
300 , _block(block)
301 , _ublock(NULL)
302 , _stub(NULL) {
303 }
305 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
306 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
307 , _cond(cond)
308 , _type(type)
309 , _label(stub->entry())
310 , _block(NULL)
311 , _ublock(NULL)
312 , _stub(stub) {
313 }
315 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
316 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
317 , _cond(cond)
318 , _type(type)
319 , _label(block->label())
320 , _block(block)
321 , _ublock(ublock)
322 , _stub(NULL)
323 {
324 }
326 void LIR_OpBranch::change_block(BlockBegin* b) {
327 assert(_block != NULL, "must have old block");
328 assert(_block->label() == label(), "must be equal");
330 _block = b;
331 _label = b->label();
332 }
334 void LIR_OpBranch::change_ublock(BlockBegin* b) {
335 assert(_ublock != NULL, "must have old block");
336 _ublock = b;
337 }
339 void LIR_OpBranch::negate_cond() {
340 switch (_cond) {
341 case lir_cond_equal: _cond = lir_cond_notEqual; break;
342 case lir_cond_notEqual: _cond = lir_cond_equal; break;
343 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
344 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
345 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
346 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
347 default: ShouldNotReachHere();
348 }
349 }
352 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
353 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
354 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
355 CodeStub* stub)
357 : LIR_Op(code, result, NULL)
358 , _object(object)
359 , _array(LIR_OprFact::illegalOpr)
360 , _klass(klass)
361 , _tmp1(tmp1)
362 , _tmp2(tmp2)
363 , _tmp3(tmp3)
364 , _fast_check(fast_check)
365 , _stub(stub)
366 , _info_for_patch(info_for_patch)
367 , _info_for_exception(info_for_exception)
368 , _profiled_method(NULL)
369 , _profiled_bci(-1)
370 , _should_profile(false)
371 {
372 if (code == lir_checkcast) {
373 assert(info_for_exception != NULL, "checkcast throws exceptions");
374 } else if (code == lir_instanceof) {
375 assert(info_for_exception == NULL, "instanceof throws no exceptions");
376 } else {
377 ShouldNotReachHere();
378 }
379 }
383 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
384 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
385 , _object(object)
386 , _array(array)
387 , _klass(NULL)
388 , _tmp1(tmp1)
389 , _tmp2(tmp2)
390 , _tmp3(tmp3)
391 , _fast_check(false)
392 , _stub(NULL)
393 , _info_for_patch(NULL)
394 , _info_for_exception(info_for_exception)
395 , _profiled_method(NULL)
396 , _profiled_bci(-1)
397 , _should_profile(false)
398 {
399 if (code == lir_store_check) {
400 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
401 assert(info_for_exception != NULL, "store_check throws exceptions");
402 } else {
403 ShouldNotReachHere();
404 }
405 }
408 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
409 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
410 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
411 , _tmp(tmp)
412 , _src(src)
413 , _src_pos(src_pos)
414 , _dst(dst)
415 , _dst_pos(dst_pos)
416 , _flags(flags)
417 , _expected_type(expected_type)
418 , _length(length) {
419 _stub = new ArrayCopyStub(this);
420 }
423 //-------------------verify--------------------------
425 void LIR_Op1::verify() const {
426 switch(code()) {
427 case lir_move:
428 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
429 break;
430 case lir_null_check:
431 assert(in_opr()->is_register(), "must be");
432 break;
433 case lir_return:
434 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
435 break;
436 }
437 }
439 void LIR_OpRTCall::verify() const {
440 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
441 }
443 //-------------------visits--------------------------
445 // complete rework of LIR instruction visitor.
446 // The virtual calls for each instruction type is replaced by a big
447 // switch that adds the operands for each instruction
449 void LIR_OpVisitState::visit(LIR_Op* op) {
450 // copy information from the LIR_Op
451 reset();
452 set_op(op);
454 switch (op->code()) {
456 // LIR_Op0
457 case lir_word_align: // result and info always invalid
458 case lir_backwardbranch_target: // result and info always invalid
459 case lir_build_frame: // result and info always invalid
460 case lir_fpop_raw: // result and info always invalid
461 case lir_24bit_FPU: // result and info always invalid
462 case lir_reset_FPU: // result and info always invalid
463 case lir_breakpoint: // result and info always invalid
464 case lir_membar: // result and info always invalid
465 case lir_membar_acquire: // result and info always invalid
466 case lir_membar_release: // result and info always invalid
467 {
468 assert(op->as_Op0() != NULL, "must be");
469 assert(op->_info == NULL, "info not used by this instruction");
470 assert(op->_result->is_illegal(), "not used");
471 break;
472 }
474 case lir_nop: // may have info, result always invalid
475 case lir_std_entry: // may have result, info always invalid
476 case lir_osr_entry: // may have result, info always invalid
477 case lir_get_thread: // may have result, info always invalid
478 {
479 assert(op->as_Op0() != NULL, "must be");
480 if (op->_info != NULL) do_info(op->_info);
481 if (op->_result->is_valid()) do_output(op->_result);
482 break;
483 }
486 // LIR_OpLabel
487 case lir_label: // result and info always invalid
488 {
489 assert(op->as_OpLabel() != NULL, "must be");
490 assert(op->_info == NULL, "info not used by this instruction");
491 assert(op->_result->is_illegal(), "not used");
492 break;
493 }
496 // LIR_Op1
497 case lir_fxch: // input always valid, result and info always invalid
498 case lir_fld: // input always valid, result and info always invalid
499 case lir_ffree: // input always valid, result and info always invalid
500 case lir_push: // input always valid, result and info always invalid
501 case lir_pop: // input always valid, result and info always invalid
502 case lir_return: // input always valid, result and info always invalid
503 case lir_leal: // input and result always valid, info always invalid
504 case lir_neg: // input and result always valid, info always invalid
505 case lir_monaddr: // input and result always valid, info always invalid
506 case lir_null_check: // input and info always valid, result always invalid
507 case lir_move: // input and result always valid, may have info
508 case lir_pack64: // input and result always valid
509 case lir_unpack64: // input and result always valid
510 case lir_prefetchr: // input always valid, result and info always invalid
511 case lir_prefetchw: // input always valid, result and info always invalid
512 {
513 assert(op->as_Op1() != NULL, "must be");
514 LIR_Op1* op1 = (LIR_Op1*)op;
516 if (op1->_info) do_info(op1->_info);
517 if (op1->_opr->is_valid()) do_input(op1->_opr);
518 if (op1->_result->is_valid()) do_output(op1->_result);
520 break;
521 }
523 case lir_safepoint:
524 {
525 assert(op->as_Op1() != NULL, "must be");
526 LIR_Op1* op1 = (LIR_Op1*)op;
528 assert(op1->_info != NULL, ""); do_info(op1->_info);
529 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
530 assert(op1->_result->is_illegal(), "safepoint does not produce value");
532 break;
533 }
535 // LIR_OpConvert;
536 case lir_convert: // input and result always valid, info always invalid
537 {
538 assert(op->as_OpConvert() != NULL, "must be");
539 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
541 assert(opConvert->_info == NULL, "must be");
542 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
543 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
544 #ifdef PPC
545 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
546 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
547 #endif
548 do_stub(opConvert->_stub);
550 break;
551 }
553 // LIR_OpBranch;
554 case lir_branch: // may have info, input and result register always invalid
555 case lir_cond_float_branch: // may have info, input and result register always invalid
556 {
557 assert(op->as_OpBranch() != NULL, "must be");
558 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
560 if (opBranch->_info != NULL) do_info(opBranch->_info);
561 assert(opBranch->_result->is_illegal(), "not used");
562 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
564 break;
565 }
568 // LIR_OpAllocObj
569 case lir_alloc_object:
570 {
571 assert(op->as_OpAllocObj() != NULL, "must be");
572 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
574 if (opAllocObj->_info) do_info(opAllocObj->_info);
575 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
576 do_temp(opAllocObj->_opr);
577 }
578 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
579 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
580 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
581 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
582 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
583 do_stub(opAllocObj->_stub);
584 break;
585 }
588 // LIR_OpRoundFP;
589 case lir_roundfp: {
590 assert(op->as_OpRoundFP() != NULL, "must be");
591 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
593 assert(op->_info == NULL, "info not used by this instruction");
594 assert(opRoundFP->_tmp->is_illegal(), "not used");
595 do_input(opRoundFP->_opr);
596 do_output(opRoundFP->_result);
598 break;
599 }
602 // LIR_Op2
603 case lir_cmp:
604 case lir_cmp_l2i:
605 case lir_ucmp_fd2i:
606 case lir_cmp_fd2i:
607 case lir_add:
608 case lir_sub:
609 case lir_mul:
610 case lir_div:
611 case lir_rem:
612 case lir_sqrt:
613 case lir_abs:
614 case lir_logic_and:
615 case lir_logic_or:
616 case lir_logic_xor:
617 case lir_shl:
618 case lir_shr:
619 case lir_ushr:
620 {
621 assert(op->as_Op2() != NULL, "must be");
622 LIR_Op2* op2 = (LIR_Op2*)op;
624 if (op2->_info) do_info(op2->_info);
625 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
626 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
627 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
628 if (op2->_result->is_valid()) do_output(op2->_result);
630 break;
631 }
633 // special handling for cmove: right input operand must not be equal
634 // to the result operand, otherwise the backend fails
635 case lir_cmove:
636 {
637 assert(op->as_Op2() != NULL, "must be");
638 LIR_Op2* op2 = (LIR_Op2*)op;
640 assert(op2->_info == NULL && op2->_tmp->is_illegal(), "not used");
641 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
643 do_input(op2->_opr1);
644 do_input(op2->_opr2);
645 do_temp(op2->_opr2);
646 do_output(op2->_result);
648 break;
649 }
651 // vspecial handling for strict operations: register input operands
652 // as temp to guarantee that they do not overlap with other
653 // registers
654 case lir_mul_strictfp:
655 case lir_div_strictfp:
656 {
657 assert(op->as_Op2() != NULL, "must be");
658 LIR_Op2* op2 = (LIR_Op2*)op;
660 assert(op2->_info == NULL, "not used");
661 assert(op2->_opr1->is_valid(), "used");
662 assert(op2->_opr2->is_valid(), "used");
663 assert(op2->_result->is_valid(), "used");
665 do_input(op2->_opr1); do_temp(op2->_opr1);
666 do_input(op2->_opr2); do_temp(op2->_opr2);
667 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
668 do_output(op2->_result);
670 break;
671 }
673 case lir_throw: {
674 assert(op->as_Op2() != NULL, "must be");
675 LIR_Op2* op2 = (LIR_Op2*)op;
677 if (op2->_info) do_info(op2->_info);
678 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
679 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
680 assert(op2->_result->is_illegal(), "no result");
682 break;
683 }
685 case lir_unwind: {
686 assert(op->as_Op1() != NULL, "must be");
687 LIR_Op1* op1 = (LIR_Op1*)op;
689 assert(op1->_info == NULL, "no info");
690 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
691 assert(op1->_result->is_illegal(), "no result");
693 break;
694 }
697 case lir_tan:
698 case lir_sin:
699 case lir_cos:
700 case lir_log:
701 case lir_log10: {
702 assert(op->as_Op2() != NULL, "must be");
703 LIR_Op2* op2 = (LIR_Op2*)op;
705 // On x86 tan/sin/cos need two temporary fpu stack slots and
706 // log/log10 need one so handle opr2 and tmp as temp inputs.
707 // Register input operand as temp to guarantee that it doesn't
708 // overlap with the input.
709 assert(op2->_info == NULL, "not used");
710 assert(op2->_opr1->is_valid(), "used");
711 do_input(op2->_opr1); do_temp(op2->_opr1);
713 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
714 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
715 if (op2->_result->is_valid()) do_output(op2->_result);
717 break;
718 }
721 // LIR_Op3
722 case lir_idiv:
723 case lir_irem: {
724 assert(op->as_Op3() != NULL, "must be");
725 LIR_Op3* op3= (LIR_Op3*)op;
727 if (op3->_info) do_info(op3->_info);
728 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
730 // second operand is input and temp, so ensure that second operand
731 // and third operand get not the same register
732 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
733 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
734 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
736 if (op3->_result->is_valid()) do_output(op3->_result);
738 break;
739 }
742 // LIR_OpJavaCall
743 case lir_static_call:
744 case lir_optvirtual_call:
745 case lir_icvirtual_call:
746 case lir_virtual_call:
747 case lir_dynamic_call: {
748 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
749 assert(opJavaCall != NULL, "must be");
751 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
753 // only visit register parameters
754 int n = opJavaCall->_arguments->length();
755 for (int i = 0; i < n; i++) {
756 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
757 do_input(*opJavaCall->_arguments->adr_at(i));
758 }
759 }
761 if (opJavaCall->_info) do_info(opJavaCall->_info);
762 if (opJavaCall->is_method_handle_invoke()) {
763 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
764 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
765 }
766 do_call();
767 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
769 break;
770 }
773 // LIR_OpRTCall
774 case lir_rtcall: {
775 assert(op->as_OpRTCall() != NULL, "must be");
776 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
778 // only visit register parameters
779 int n = opRTCall->_arguments->length();
780 for (int i = 0; i < n; i++) {
781 if (!opRTCall->_arguments->at(i)->is_pointer()) {
782 do_input(*opRTCall->_arguments->adr_at(i));
783 }
784 }
785 if (opRTCall->_info) do_info(opRTCall->_info);
786 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
787 do_call();
788 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
790 break;
791 }
794 // LIR_OpArrayCopy
795 case lir_arraycopy: {
796 assert(op->as_OpArrayCopy() != NULL, "must be");
797 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
799 assert(opArrayCopy->_result->is_illegal(), "unused");
800 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
801 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
802 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
803 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
804 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
805 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
806 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
808 // the implementation of arraycopy always has a call into the runtime
809 do_call();
811 break;
812 }
815 // LIR_OpLock
816 case lir_lock:
817 case lir_unlock: {
818 assert(op->as_OpLock() != NULL, "must be");
819 LIR_OpLock* opLock = (LIR_OpLock*)op;
821 if (opLock->_info) do_info(opLock->_info);
823 // TODO: check if these operands really have to be temp
824 // (or if input is sufficient). This may have influence on the oop map!
825 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
826 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
827 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
829 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
830 assert(opLock->_result->is_illegal(), "unused");
832 do_stub(opLock->_stub);
834 break;
835 }
838 // LIR_OpDelay
839 case lir_delay_slot: {
840 assert(op->as_OpDelay() != NULL, "must be");
841 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
843 visit(opDelay->delay_op());
844 break;
845 }
847 // LIR_OpTypeCheck
848 case lir_instanceof:
849 case lir_checkcast:
850 case lir_store_check: {
851 assert(op->as_OpTypeCheck() != NULL, "must be");
852 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
854 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
855 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
856 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
857 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
858 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
859 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
860 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
861 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
862 do_stub(opTypeCheck->_stub);
863 break;
864 }
866 // LIR_OpCompareAndSwap
867 case lir_cas_long:
868 case lir_cas_obj:
869 case lir_cas_int: {
870 assert(op->as_OpCompareAndSwap() != NULL, "must be");
871 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
873 assert(opCompareAndSwap->_addr->is_valid(), "used");
874 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
875 assert(opCompareAndSwap->_new_value->is_valid(), "used");
876 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
877 do_input(opCompareAndSwap->_addr);
878 do_temp(opCompareAndSwap->_addr);
879 do_input(opCompareAndSwap->_cmp_value);
880 do_temp(opCompareAndSwap->_cmp_value);
881 do_input(opCompareAndSwap->_new_value);
882 do_temp(opCompareAndSwap->_new_value);
883 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
884 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
885 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
887 break;
888 }
891 // LIR_OpAllocArray;
892 case lir_alloc_array: {
893 assert(op->as_OpAllocArray() != NULL, "must be");
894 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
896 if (opAllocArray->_info) do_info(opAllocArray->_info);
897 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
898 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
899 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
900 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
901 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
902 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
903 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
904 do_stub(opAllocArray->_stub);
905 break;
906 }
908 // LIR_OpProfileCall:
909 case lir_profile_call: {
910 assert(op->as_OpProfileCall() != NULL, "must be");
911 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
913 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
914 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
915 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
916 break;
917 }
918 default:
919 ShouldNotReachHere();
920 }
921 }
924 void LIR_OpVisitState::do_stub(CodeStub* stub) {
925 if (stub != NULL) {
926 stub->visit(this);
927 }
928 }
930 XHandlers* LIR_OpVisitState::all_xhandler() {
931 XHandlers* result = NULL;
933 int i;
934 for (i = 0; i < info_count(); i++) {
935 if (info_at(i)->exception_handlers() != NULL) {
936 result = info_at(i)->exception_handlers();
937 break;
938 }
939 }
941 #ifdef ASSERT
942 for (i = 0; i < info_count(); i++) {
943 assert(info_at(i)->exception_handlers() == NULL ||
944 info_at(i)->exception_handlers() == result,
945 "only one xhandler list allowed per LIR-operation");
946 }
947 #endif
949 if (result != NULL) {
950 return result;
951 } else {
952 return new XHandlers();
953 }
955 return result;
956 }
959 #ifdef ASSERT
960 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
961 visit(op);
963 return opr_count(inputMode) == 0 &&
964 opr_count(outputMode) == 0 &&
965 opr_count(tempMode) == 0 &&
966 info_count() == 0 &&
967 !has_call() &&
968 !has_slow_case();
969 }
970 #endif
972 //---------------------------------------------------
975 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
976 masm->emit_call(this);
977 }
979 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
980 masm->emit_rtcall(this);
981 }
983 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
984 masm->emit_opLabel(this);
985 }
987 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
988 masm->emit_arraycopy(this);
989 masm->emit_code_stub(stub());
990 }
992 void LIR_Op0::emit_code(LIR_Assembler* masm) {
993 masm->emit_op0(this);
994 }
996 void LIR_Op1::emit_code(LIR_Assembler* masm) {
997 masm->emit_op1(this);
998 }
1000 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1001 masm->emit_alloc_obj(this);
1002 masm->emit_code_stub(stub());
1003 }
1005 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1006 masm->emit_opBranch(this);
1007 if (stub()) {
1008 masm->emit_code_stub(stub());
1009 }
1010 }
1012 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1013 masm->emit_opConvert(this);
1014 if (stub() != NULL) {
1015 masm->emit_code_stub(stub());
1016 }
1017 }
1019 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1020 masm->emit_op2(this);
1021 }
1023 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1024 masm->emit_alloc_array(this);
1025 masm->emit_code_stub(stub());
1026 }
1028 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1029 masm->emit_opTypeCheck(this);
1030 if (stub()) {
1031 masm->emit_code_stub(stub());
1032 }
1033 }
1035 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1036 masm->emit_compare_and_swap(this);
1037 }
1039 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1040 masm->emit_op3(this);
1041 }
1043 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1044 masm->emit_lock(this);
1045 if (stub()) {
1046 masm->emit_code_stub(stub());
1047 }
1048 }
1051 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1052 masm->emit_delay(this);
1053 }
1055 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1056 masm->emit_profile_call(this);
1057 }
1059 // LIR_List
1060 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1061 : _operations(8)
1062 , _compilation(compilation)
1063 #ifndef PRODUCT
1064 , _block(block)
1065 #endif
1066 #ifdef ASSERT
1067 , _file(NULL)
1068 , _line(0)
1069 #endif
1070 { }
1073 #ifdef ASSERT
1074 void LIR_List::set_file_and_line(const char * file, int line) {
1075 const char * f = strrchr(file, '/');
1076 if (f == NULL) f = strrchr(file, '\\');
1077 if (f == NULL) {
1078 f = file;
1079 } else {
1080 f++;
1081 }
1082 _file = f;
1083 _line = line;
1084 }
1085 #endif
1088 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1089 assert(this == buffer->lir_list(), "wrong lir list");
1090 const int n = _operations.length();
1092 if (buffer->number_of_ops() > 0) {
1093 // increase size of instructions list
1094 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1095 // insert ops from buffer into instructions list
1096 int op_index = buffer->number_of_ops() - 1;
1097 int ip_index = buffer->number_of_insertion_points() - 1;
1098 int from_index = n - 1;
1099 int to_index = _operations.length() - 1;
1100 for (; ip_index >= 0; ip_index --) {
1101 int index = buffer->index_at(ip_index);
1102 // make room after insertion point
1103 while (index < from_index) {
1104 _operations.at_put(to_index --, _operations.at(from_index --));
1105 }
1106 // insert ops from buffer
1107 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1108 _operations.at_put(to_index --, buffer->op_at(op_index --));
1109 }
1110 }
1111 }
1113 buffer->finish();
1114 }
1117 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1118 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1119 }
1122 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1123 append(new LIR_Op1(
1124 lir_move,
1125 LIR_OprFact::address(addr),
1126 src,
1127 addr->type(),
1128 patch_code,
1129 info));
1130 }
1133 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1134 append(new LIR_Op1(
1135 lir_move,
1136 LIR_OprFact::address(address),
1137 dst,
1138 address->type(),
1139 patch_code,
1140 info, lir_move_volatile));
1141 }
1143 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1144 append(new LIR_Op1(
1145 lir_move,
1146 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1147 dst,
1148 type,
1149 patch_code,
1150 info, lir_move_volatile));
1151 }
1154 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1155 append(new LIR_Op1(
1156 is_store ? lir_prefetchw : lir_prefetchr,
1157 LIR_OprFact::address(addr)));
1158 }
1161 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1162 append(new LIR_Op1(
1163 lir_move,
1164 LIR_OprFact::intConst(v),
1165 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1166 type,
1167 patch_code,
1168 info));
1169 }
1172 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1173 append(new LIR_Op1(
1174 lir_move,
1175 LIR_OprFact::oopConst(o),
1176 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1177 type,
1178 patch_code,
1179 info));
1180 }
1183 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1184 append(new LIR_Op1(
1185 lir_move,
1186 src,
1187 LIR_OprFact::address(addr),
1188 addr->type(),
1189 patch_code,
1190 info));
1191 }
1194 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1195 append(new LIR_Op1(
1196 lir_move,
1197 src,
1198 LIR_OprFact::address(addr),
1199 addr->type(),
1200 patch_code,
1201 info,
1202 lir_move_volatile));
1203 }
1205 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1206 append(new LIR_Op1(
1207 lir_move,
1208 src,
1209 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1210 type,
1211 patch_code,
1212 info, lir_move_volatile));
1213 }
1216 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1217 append(new LIR_Op3(
1218 lir_idiv,
1219 left,
1220 right,
1221 tmp,
1222 res,
1223 info));
1224 }
1227 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1228 append(new LIR_Op3(
1229 lir_idiv,
1230 left,
1231 LIR_OprFact::intConst(right),
1232 tmp,
1233 res,
1234 info));
1235 }
1238 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1239 append(new LIR_Op3(
1240 lir_irem,
1241 left,
1242 right,
1243 tmp,
1244 res,
1245 info));
1246 }
1249 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1250 append(new LIR_Op3(
1251 lir_irem,
1252 left,
1253 LIR_OprFact::intConst(right),
1254 tmp,
1255 res,
1256 info));
1257 }
1260 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1261 append(new LIR_Op2(
1262 lir_cmp,
1263 condition,
1264 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1265 LIR_OprFact::intConst(c),
1266 info));
1267 }
1270 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1271 append(new LIR_Op2(
1272 lir_cmp,
1273 condition,
1274 reg,
1275 LIR_OprFact::address(addr),
1276 info));
1277 }
1279 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1280 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1281 append(new LIR_OpAllocObj(
1282 klass,
1283 dst,
1284 t1,
1285 t2,
1286 t3,
1287 t4,
1288 header_size,
1289 object_size,
1290 init_check,
1291 stub));
1292 }
1294 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1295 append(new LIR_OpAllocArray(
1296 klass,
1297 len,
1298 dst,
1299 t1,
1300 t2,
1301 t3,
1302 t4,
1303 type,
1304 stub));
1305 }
1307 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1308 append(new LIR_Op2(
1309 lir_shl,
1310 value,
1311 count,
1312 dst,
1313 tmp));
1314 }
1316 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1317 append(new LIR_Op2(
1318 lir_shr,
1319 value,
1320 count,
1321 dst,
1322 tmp));
1323 }
1326 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1327 append(new LIR_Op2(
1328 lir_ushr,
1329 value,
1330 count,
1331 dst,
1332 tmp));
1333 }
1335 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1336 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1337 left,
1338 right,
1339 dst));
1340 }
1342 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1343 append(new LIR_OpLock(
1344 lir_lock,
1345 hdr,
1346 obj,
1347 lock,
1348 scratch,
1349 stub,
1350 info));
1351 }
1353 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1354 append(new LIR_OpLock(
1355 lir_unlock,
1356 hdr,
1357 obj,
1358 lock,
1359 scratch,
1360 stub,
1361 NULL));
1362 }
1365 void check_LIR() {
1366 // cannot do the proper checking as PRODUCT and other modes return different results
1367 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1368 }
1372 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1373 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1374 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1375 ciMethod* profiled_method, int profiled_bci) {
1376 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1377 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1378 if (profiled_method != NULL) {
1379 c->set_profiled_method(profiled_method);
1380 c->set_profiled_bci(profiled_bci);
1381 c->set_should_profile(true);
1382 }
1383 append(c);
1384 }
1386 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1387 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1388 if (profiled_method != NULL) {
1389 c->set_profiled_method(profiled_method);
1390 c->set_profiled_bci(profiled_bci);
1391 c->set_should_profile(true);
1392 }
1393 append(c);
1394 }
1397 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) {
1398 append(new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception));
1399 }
1402 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1403 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1404 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1405 }
1407 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1408 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1409 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1410 }
1412 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1413 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1414 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1415 }
1418 #ifdef PRODUCT
1420 void print_LIR(BlockList* blocks) {
1421 }
1423 #else
1424 // LIR_OprDesc
1425 void LIR_OprDesc::print() const {
1426 print(tty);
1427 }
1429 void LIR_OprDesc::print(outputStream* out) const {
1430 if (is_illegal()) {
1431 return;
1432 }
1434 out->print("[");
1435 if (is_pointer()) {
1436 pointer()->print_value_on(out);
1437 } else if (is_single_stack()) {
1438 out->print("stack:%d", single_stack_ix());
1439 } else if (is_double_stack()) {
1440 out->print("dbl_stack:%d",double_stack_ix());
1441 } else if (is_virtual()) {
1442 out->print("R%d", vreg_number());
1443 } else if (is_single_cpu()) {
1444 out->print(as_register()->name());
1445 } else if (is_double_cpu()) {
1446 out->print(as_register_hi()->name());
1447 out->print(as_register_lo()->name());
1448 #if defined(X86)
1449 } else if (is_single_xmm()) {
1450 out->print(as_xmm_float_reg()->name());
1451 } else if (is_double_xmm()) {
1452 out->print(as_xmm_double_reg()->name());
1453 } else if (is_single_fpu()) {
1454 out->print("fpu%d", fpu_regnr());
1455 } else if (is_double_fpu()) {
1456 out->print("fpu%d", fpu_regnrLo());
1457 #elif defined(ARM)
1458 } else if (is_single_fpu()) {
1459 out->print("s%d", fpu_regnr());
1460 } else if (is_double_fpu()) {
1461 out->print("d%d", fpu_regnrLo() >> 1);
1462 #else
1463 } else if (is_single_fpu()) {
1464 out->print(as_float_reg()->name());
1465 } else if (is_double_fpu()) {
1466 out->print(as_double_reg()->name());
1467 #endif
1469 } else if (is_illegal()) {
1470 out->print("-");
1471 } else {
1472 out->print("Unknown Operand");
1473 }
1474 if (!is_illegal()) {
1475 out->print("|%c", type_char());
1476 }
1477 if (is_register() && is_last_use()) {
1478 out->print("(last_use)");
1479 }
1480 out->print("]");
1481 }
1484 // LIR_Address
1485 void LIR_Const::print_value_on(outputStream* out) const {
1486 switch (type()) {
1487 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1488 case T_INT: out->print("int:%d", as_jint()); break;
1489 case T_LONG: out->print("lng:%lld", as_jlong()); break;
1490 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1491 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1492 case T_OBJECT: out->print("obj:0x%x", as_jobject()); break;
1493 default: out->print("%3d:0x%x",type(), as_jdouble()); break;
1494 }
1495 }
1497 // LIR_Address
1498 void LIR_Address::print_value_on(outputStream* out) const {
1499 out->print("Base:"); _base->print(out);
1500 if (!_index->is_illegal()) {
1501 out->print(" Index:"); _index->print(out);
1502 switch (scale()) {
1503 case times_1: break;
1504 case times_2: out->print(" * 2"); break;
1505 case times_4: out->print(" * 4"); break;
1506 case times_8: out->print(" * 8"); break;
1507 }
1508 }
1509 out->print(" Disp: %d", _disp);
1510 }
1512 // debug output of block header without InstructionPrinter
1513 // (because phi functions are not necessary for LIR)
1514 static void print_block(BlockBegin* x) {
1515 // print block id
1516 BlockEnd* end = x->end();
1517 tty->print("B%d ", x->block_id());
1519 // print flags
1520 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1521 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1522 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1523 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1524 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1525 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1526 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1528 // print block bci range
1529 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1531 // print predecessors and successors
1532 if (x->number_of_preds() > 0) {
1533 tty->print("preds: ");
1534 for (int i = 0; i < x->number_of_preds(); i ++) {
1535 tty->print("B%d ", x->pred_at(i)->block_id());
1536 }
1537 }
1539 if (x->number_of_sux() > 0) {
1540 tty->print("sux: ");
1541 for (int i = 0; i < x->number_of_sux(); i ++) {
1542 tty->print("B%d ", x->sux_at(i)->block_id());
1543 }
1544 }
1546 // print exception handlers
1547 if (x->number_of_exception_handlers() > 0) {
1548 tty->print("xhandler: ");
1549 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1550 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1551 }
1552 }
1554 tty->cr();
1555 }
1557 void print_LIR(BlockList* blocks) {
1558 tty->print_cr("LIR:");
1559 int i;
1560 for (i = 0; i < blocks->length(); i++) {
1561 BlockBegin* bb = blocks->at(i);
1562 print_block(bb);
1563 tty->print("__id_Instruction___________________________________________"); tty->cr();
1564 bb->lir()->print_instructions();
1565 }
1566 }
1568 void LIR_List::print_instructions() {
1569 for (int i = 0; i < _operations.length(); i++) {
1570 _operations.at(i)->print(); tty->cr();
1571 }
1572 tty->cr();
1573 }
1575 // LIR_Ops printing routines
1576 // LIR_Op
1577 void LIR_Op::print_on(outputStream* out) const {
1578 if (id() != -1 || PrintCFGToFile) {
1579 out->print("%4d ", id());
1580 } else {
1581 out->print(" ");
1582 }
1583 out->print(name()); out->print(" ");
1584 print_instr(out);
1585 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1586 #ifdef ASSERT
1587 if (Verbose && _file != NULL) {
1588 out->print(" (%s:%d)", _file, _line);
1589 }
1590 #endif
1591 }
1593 const char * LIR_Op::name() const {
1594 const char* s = NULL;
1595 switch(code()) {
1596 // LIR_Op0
1597 case lir_membar: s = "membar"; break;
1598 case lir_membar_acquire: s = "membar_acquire"; break;
1599 case lir_membar_release: s = "membar_release"; break;
1600 case lir_word_align: s = "word_align"; break;
1601 case lir_label: s = "label"; break;
1602 case lir_nop: s = "nop"; break;
1603 case lir_backwardbranch_target: s = "backbranch"; break;
1604 case lir_std_entry: s = "std_entry"; break;
1605 case lir_osr_entry: s = "osr_entry"; break;
1606 case lir_build_frame: s = "build_frm"; break;
1607 case lir_fpop_raw: s = "fpop_raw"; break;
1608 case lir_24bit_FPU: s = "24bit_FPU"; break;
1609 case lir_reset_FPU: s = "reset_FPU"; break;
1610 case lir_breakpoint: s = "breakpoint"; break;
1611 case lir_get_thread: s = "get_thread"; break;
1612 // LIR_Op1
1613 case lir_fxch: s = "fxch"; break;
1614 case lir_fld: s = "fld"; break;
1615 case lir_ffree: s = "ffree"; break;
1616 case lir_push: s = "push"; break;
1617 case lir_pop: s = "pop"; break;
1618 case lir_null_check: s = "null_check"; break;
1619 case lir_return: s = "return"; break;
1620 case lir_safepoint: s = "safepoint"; break;
1621 case lir_neg: s = "neg"; break;
1622 case lir_leal: s = "leal"; break;
1623 case lir_branch: s = "branch"; break;
1624 case lir_cond_float_branch: s = "flt_cond_br"; break;
1625 case lir_move: s = "move"; break;
1626 case lir_roundfp: s = "roundfp"; break;
1627 case lir_rtcall: s = "rtcall"; break;
1628 case lir_throw: s = "throw"; break;
1629 case lir_unwind: s = "unwind"; break;
1630 case lir_convert: s = "convert"; break;
1631 case lir_alloc_object: s = "alloc_obj"; break;
1632 case lir_monaddr: s = "mon_addr"; break;
1633 case lir_pack64: s = "pack64"; break;
1634 case lir_unpack64: s = "unpack64"; break;
1635 // LIR_Op2
1636 case lir_cmp: s = "cmp"; break;
1637 case lir_cmp_l2i: s = "cmp_l2i"; break;
1638 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1639 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1640 case lir_cmove: s = "cmove"; break;
1641 case lir_add: s = "add"; break;
1642 case lir_sub: s = "sub"; break;
1643 case lir_mul: s = "mul"; break;
1644 case lir_mul_strictfp: s = "mul_strictfp"; break;
1645 case lir_div: s = "div"; break;
1646 case lir_div_strictfp: s = "div_strictfp"; break;
1647 case lir_rem: s = "rem"; break;
1648 case lir_abs: s = "abs"; break;
1649 case lir_sqrt: s = "sqrt"; break;
1650 case lir_sin: s = "sin"; break;
1651 case lir_cos: s = "cos"; break;
1652 case lir_tan: s = "tan"; break;
1653 case lir_log: s = "log"; break;
1654 case lir_log10: s = "log10"; break;
1655 case lir_logic_and: s = "logic_and"; break;
1656 case lir_logic_or: s = "logic_or"; break;
1657 case lir_logic_xor: s = "logic_xor"; break;
1658 case lir_shl: s = "shift_left"; break;
1659 case lir_shr: s = "shift_right"; break;
1660 case lir_ushr: s = "ushift_right"; break;
1661 case lir_alloc_array: s = "alloc_array"; break;
1662 // LIR_Op3
1663 case lir_idiv: s = "idiv"; break;
1664 case lir_irem: s = "irem"; break;
1665 // LIR_OpJavaCall
1666 case lir_static_call: s = "static"; break;
1667 case lir_optvirtual_call: s = "optvirtual"; break;
1668 case lir_icvirtual_call: s = "icvirtual"; break;
1669 case lir_virtual_call: s = "virtual"; break;
1670 case lir_dynamic_call: s = "dynamic"; break;
1671 // LIR_OpArrayCopy
1672 case lir_arraycopy: s = "arraycopy"; break;
1673 // LIR_OpLock
1674 case lir_lock: s = "lock"; break;
1675 case lir_unlock: s = "unlock"; break;
1676 // LIR_OpDelay
1677 case lir_delay_slot: s = "delay"; break;
1678 // LIR_OpTypeCheck
1679 case lir_instanceof: s = "instanceof"; break;
1680 case lir_checkcast: s = "checkcast"; break;
1681 case lir_store_check: s = "store_check"; break;
1682 // LIR_OpCompareAndSwap
1683 case lir_cas_long: s = "cas_long"; break;
1684 case lir_cas_obj: s = "cas_obj"; break;
1685 case lir_cas_int: s = "cas_int"; break;
1686 // LIR_OpProfileCall
1687 case lir_profile_call: s = "profile_call"; break;
1688 case lir_none: ShouldNotReachHere();break;
1689 default: s = "illegal_op"; break;
1690 }
1691 return s;
1692 }
1694 // LIR_OpJavaCall
1695 void LIR_OpJavaCall::print_instr(outputStream* out) const {
1696 out->print("call: ");
1697 out->print("[addr: 0x%x]", address());
1698 if (receiver()->is_valid()) {
1699 out->print(" [recv: "); receiver()->print(out); out->print("]");
1700 }
1701 if (result_opr()->is_valid()) {
1702 out->print(" [result: "); result_opr()->print(out); out->print("]");
1703 }
1704 }
1706 // LIR_OpLabel
1707 void LIR_OpLabel::print_instr(outputStream* out) const {
1708 out->print("[label:0x%x]", _label);
1709 }
1711 // LIR_OpArrayCopy
1712 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
1713 src()->print(out); out->print(" ");
1714 src_pos()->print(out); out->print(" ");
1715 dst()->print(out); out->print(" ");
1716 dst_pos()->print(out); out->print(" ");
1717 length()->print(out); out->print(" ");
1718 tmp()->print(out); out->print(" ");
1719 }
1721 // LIR_OpCompareAndSwap
1722 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
1723 addr()->print(out); out->print(" ");
1724 cmp_value()->print(out); out->print(" ");
1725 new_value()->print(out); out->print(" ");
1726 tmp1()->print(out); out->print(" ");
1727 tmp2()->print(out); out->print(" ");
1729 }
1731 // LIR_Op0
1732 void LIR_Op0::print_instr(outputStream* out) const {
1733 result_opr()->print(out);
1734 }
1736 // LIR_Op1
1737 const char * LIR_Op1::name() const {
1738 if (code() == lir_move) {
1739 switch (move_kind()) {
1740 case lir_move_normal:
1741 return "move";
1742 case lir_move_unaligned:
1743 return "unaligned move";
1744 case lir_move_volatile:
1745 return "volatile_move";
1746 case lir_move_wide:
1747 return "wide_move";
1748 default:
1749 ShouldNotReachHere();
1750 return "illegal_op";
1751 }
1752 } else {
1753 return LIR_Op::name();
1754 }
1755 }
1758 void LIR_Op1::print_instr(outputStream* out) const {
1759 _opr->print(out); out->print(" ");
1760 result_opr()->print(out); out->print(" ");
1761 print_patch_code(out, patch_code());
1762 }
1765 // LIR_Op1
1766 void LIR_OpRTCall::print_instr(outputStream* out) const {
1767 intx a = (intx)addr();
1768 out->print(Runtime1::name_for_address(addr()));
1769 out->print(" ");
1770 tmp()->print(out);
1771 }
1773 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1774 switch(code) {
1775 case lir_patch_none: break;
1776 case lir_patch_low: out->print("[patch_low]"); break;
1777 case lir_patch_high: out->print("[patch_high]"); break;
1778 case lir_patch_normal: out->print("[patch_normal]"); break;
1779 default: ShouldNotReachHere();
1780 }
1781 }
1783 // LIR_OpBranch
1784 void LIR_OpBranch::print_instr(outputStream* out) const {
1785 print_condition(out, cond()); out->print(" ");
1786 if (block() != NULL) {
1787 out->print("[B%d] ", block()->block_id());
1788 } else if (stub() != NULL) {
1789 out->print("[");
1790 stub()->print_name(out);
1791 out->print(": 0x%x]", stub());
1792 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1793 } else {
1794 out->print("[label:0x%x] ", label());
1795 }
1796 if (ublock() != NULL) {
1797 out->print("unordered: [B%d] ", ublock()->block_id());
1798 }
1799 }
1801 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1802 switch(cond) {
1803 case lir_cond_equal: out->print("[EQ]"); break;
1804 case lir_cond_notEqual: out->print("[NE]"); break;
1805 case lir_cond_less: out->print("[LT]"); break;
1806 case lir_cond_lessEqual: out->print("[LE]"); break;
1807 case lir_cond_greaterEqual: out->print("[GE]"); break;
1808 case lir_cond_greater: out->print("[GT]"); break;
1809 case lir_cond_belowEqual: out->print("[BE]"); break;
1810 case lir_cond_aboveEqual: out->print("[AE]"); break;
1811 case lir_cond_always: out->print("[AL]"); break;
1812 default: out->print("[%d]",cond); break;
1813 }
1814 }
1816 // LIR_OpConvert
1817 void LIR_OpConvert::print_instr(outputStream* out) const {
1818 print_bytecode(out, bytecode());
1819 in_opr()->print(out); out->print(" ");
1820 result_opr()->print(out); out->print(" ");
1821 #ifdef PPC
1822 if(tmp1()->is_valid()) {
1823 tmp1()->print(out); out->print(" ");
1824 tmp2()->print(out); out->print(" ");
1825 }
1826 #endif
1827 }
1829 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1830 switch(code) {
1831 case Bytecodes::_d2f: out->print("[d2f] "); break;
1832 case Bytecodes::_d2i: out->print("[d2i] "); break;
1833 case Bytecodes::_d2l: out->print("[d2l] "); break;
1834 case Bytecodes::_f2d: out->print("[f2d] "); break;
1835 case Bytecodes::_f2i: out->print("[f2i] "); break;
1836 case Bytecodes::_f2l: out->print("[f2l] "); break;
1837 case Bytecodes::_i2b: out->print("[i2b] "); break;
1838 case Bytecodes::_i2c: out->print("[i2c] "); break;
1839 case Bytecodes::_i2d: out->print("[i2d] "); break;
1840 case Bytecodes::_i2f: out->print("[i2f] "); break;
1841 case Bytecodes::_i2l: out->print("[i2l] "); break;
1842 case Bytecodes::_i2s: out->print("[i2s] "); break;
1843 case Bytecodes::_l2i: out->print("[l2i] "); break;
1844 case Bytecodes::_l2f: out->print("[l2f] "); break;
1845 case Bytecodes::_l2d: out->print("[l2d] "); break;
1846 default:
1847 out->print("[?%d]",code);
1848 break;
1849 }
1850 }
1852 void LIR_OpAllocObj::print_instr(outputStream* out) const {
1853 klass()->print(out); out->print(" ");
1854 obj()->print(out); out->print(" ");
1855 tmp1()->print(out); out->print(" ");
1856 tmp2()->print(out); out->print(" ");
1857 tmp3()->print(out); out->print(" ");
1858 tmp4()->print(out); out->print(" ");
1859 out->print("[hdr:%d]", header_size()); out->print(" ");
1860 out->print("[obj:%d]", object_size()); out->print(" ");
1861 out->print("[lbl:0x%x]", stub()->entry());
1862 }
1864 void LIR_OpRoundFP::print_instr(outputStream* out) const {
1865 _opr->print(out); out->print(" ");
1866 tmp()->print(out); out->print(" ");
1867 result_opr()->print(out); out->print(" ");
1868 }
1870 // LIR_Op2
1871 void LIR_Op2::print_instr(outputStream* out) const {
1872 if (code() == lir_cmove) {
1873 print_condition(out, condition()); out->print(" ");
1874 }
1875 in_opr1()->print(out); out->print(" ");
1876 in_opr2()->print(out); out->print(" ");
1877 if (tmp_opr()->is_valid()) { tmp_opr()->print(out); out->print(" "); }
1878 result_opr()->print(out);
1879 }
1881 void LIR_OpAllocArray::print_instr(outputStream* out) const {
1882 klass()->print(out); out->print(" ");
1883 len()->print(out); out->print(" ");
1884 obj()->print(out); out->print(" ");
1885 tmp1()->print(out); out->print(" ");
1886 tmp2()->print(out); out->print(" ");
1887 tmp3()->print(out); out->print(" ");
1888 tmp4()->print(out); out->print(" ");
1889 out->print("[type:0x%x]", type()); out->print(" ");
1890 out->print("[label:0x%x]", stub()->entry());
1891 }
1894 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
1895 object()->print(out); out->print(" ");
1896 if (code() == lir_store_check) {
1897 array()->print(out); out->print(" ");
1898 }
1899 if (code() != lir_store_check) {
1900 klass()->print_name_on(out); out->print(" ");
1901 if (fast_check()) out->print("fast_check ");
1902 }
1903 tmp1()->print(out); out->print(" ");
1904 tmp2()->print(out); out->print(" ");
1905 tmp3()->print(out); out->print(" ");
1906 result_opr()->print(out); out->print(" ");
1907 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
1908 }
1911 // LIR_Op3
1912 void LIR_Op3::print_instr(outputStream* out) const {
1913 in_opr1()->print(out); out->print(" ");
1914 in_opr2()->print(out); out->print(" ");
1915 in_opr3()->print(out); out->print(" ");
1916 result_opr()->print(out);
1917 }
1920 void LIR_OpLock::print_instr(outputStream* out) const {
1921 hdr_opr()->print(out); out->print(" ");
1922 obj_opr()->print(out); out->print(" ");
1923 lock_opr()->print(out); out->print(" ");
1924 if (_scratch->is_valid()) {
1925 _scratch->print(out); out->print(" ");
1926 }
1927 out->print("[lbl:0x%x]", stub()->entry());
1928 }
1931 void LIR_OpDelay::print_instr(outputStream* out) const {
1932 _op->print_on(out);
1933 }
1936 // LIR_OpProfileCall
1937 void LIR_OpProfileCall::print_instr(outputStream* out) const {
1938 profiled_method()->name()->print_symbol_on(out);
1939 out->print(".");
1940 profiled_method()->holder()->name()->print_symbol_on(out);
1941 out->print(" @ %d ", profiled_bci());
1942 mdo()->print(out); out->print(" ");
1943 recv()->print(out); out->print(" ");
1944 tmp1()->print(out); out->print(" ");
1945 }
1947 #endif // PRODUCT
1949 // Implementation of LIR_InsertionBuffer
1951 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
1952 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
1954 int i = number_of_insertion_points() - 1;
1955 if (i < 0 || index_at(i) < index) {
1956 append_new(index, 1);
1957 } else {
1958 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
1959 assert(count_at(i) > 0, "check");
1960 set_count_at(i, count_at(i) + 1);
1961 }
1962 _ops.push(op);
1964 DEBUG_ONLY(verify());
1965 }
1967 #ifdef ASSERT
1968 void LIR_InsertionBuffer::verify() {
1969 int sum = 0;
1970 int prev_idx = -1;
1972 for (int i = 0; i < number_of_insertion_points(); i++) {
1973 assert(prev_idx < index_at(i), "index must be ordered ascending");
1974 sum += count_at(i);
1975 }
1976 assert(sum == number_of_ops(), "wrong total sum");
1977 }
1978 #endif
