src/share/vm/c1/c1_LIR.cpp

changeset 3141
10ee2b297ccd
parent 2488
e4fee0bdaa85
child 3153
5cceda753a4a
equal deleted inserted replaced
3140:2209834ccb59 3141:10ee2b297ccd
140 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used"); 140 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
141 assert(disp() == 0 || index()->is_illegal(), "can't have both"); 141 assert(disp() == 0 || index()->is_illegal(), "can't have both");
142 #endif 142 #endif
143 #ifdef ARM 143 #ifdef ARM
144 assert(disp() == 0 || index()->is_illegal(), "can't have both"); 144 assert(disp() == 0 || index()->is_illegal(), "can't have both");
145 assert(-4096 < disp() && disp() < 4096, "architecture constraint"); 145 // Note: offsets higher than 4096 must not be rejected here. They can
146 // be handled by the back-end or will be rejected if not.
146 #endif 147 #endif
147 #ifdef _LP64 148 #ifdef _LP64
148 assert(base()->is_cpu_register(), "wrong base operand"); 149 assert(base()->is_cpu_register(), "wrong base operand");
149 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); 150 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
150 assert(base()->type() == T_OBJECT || base()->type() == T_LONG, 151 assert(base()->type() == T_OBJECT || base()->type() == T_LONG,

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