1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/share/vm/opto/regmask.hpp Wed Apr 27 01:25:04 2016 +0800
1.3 @@ -0,0 +1,337 @@
1.4 +/*
1.5 + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.7 + *
1.8 + * This code is free software; you can redistribute it and/or modify it
1.9 + * under the terms of the GNU General Public License version 2 only, as
1.10 + * published by the Free Software Foundation.
1.11 + *
1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.15 + * version 2 for more details (a copy is included in the LICENSE file that
1.16 + * accompanied this code).
1.17 + *
1.18 + * You should have received a copy of the GNU General Public License version
1.19 + * 2 along with this work; if not, write to the Free Software Foundation,
1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.21 + *
1.22 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1.23 + * or visit www.oracle.com if you need additional information or have any
1.24 + * questions.
1.25 + *
1.26 + */
1.27 +
1.28 +#ifndef SHARE_VM_OPTO_REGMASK_HPP
1.29 +#define SHARE_VM_OPTO_REGMASK_HPP
1.30 +
1.31 +#include "code/vmreg.hpp"
1.32 +#include "libadt/port.hpp"
1.33 +#include "opto/optoreg.hpp"
1.34 +#ifdef TARGET_ARCH_MODEL_x86_32
1.35 +# include "adfiles/adGlobals_x86_32.hpp"
1.36 +#endif
1.37 +#ifdef TARGET_ARCH_MODEL_x86_64
1.38 +# include "adfiles/adGlobals_x86_64.hpp"
1.39 +#endif
1.40 +#ifdef TARGET_ARCH_MODEL_sparc
1.41 +# include "adfiles/adGlobals_sparc.hpp"
1.42 +#endif
1.43 +#ifdef TARGET_ARCH_MODEL_zero
1.44 +# include "adfiles/adGlobals_zero.hpp"
1.45 +#endif
1.46 +#ifdef TARGET_ARCH_MODEL_arm
1.47 +# include "adfiles/adGlobals_arm.hpp"
1.48 +#endif
1.49 +#ifdef TARGET_ARCH_MODEL_ppc_32
1.50 +# include "adfiles/adGlobals_ppc_32.hpp"
1.51 +#endif
1.52 +#ifdef TARGET_ARCH_MODEL_ppc_64
1.53 +# include "adfiles/adGlobals_ppc_64.hpp"
1.54 +#endif
1.55 +
1.56 +// Some fun naming (textual) substitutions:
1.57 +//
1.58 +// RegMask::get_low_elem() ==> RegMask::find_first_elem()
1.59 +// RegMask::Special ==> RegMask::Empty
1.60 +// RegMask::_flags ==> RegMask::is_AllStack()
1.61 +// RegMask::operator<<=() ==> RegMask::Insert()
1.62 +// RegMask::operator>>=() ==> RegMask::Remove()
1.63 +// RegMask::Union() ==> RegMask::OR
1.64 +// RegMask::Inter() ==> RegMask::AND
1.65 +//
1.66 +// OptoRegister::RegName ==> OptoReg::Name
1.67 +//
1.68 +// OptoReg::stack0() ==> _last_Mach_Reg or ZERO in core version
1.69 +//
1.70 +// numregs in chaitin ==> proper degree in chaitin
1.71 +
1.72 +//-------------Non-zero bit search methods used by RegMask---------------------
1.73 +// Find lowest 1, or return 32 if empty
1.74 +int find_lowest_bit( uint32 mask );
1.75 +// Find highest 1, or return 32 if empty
1.76 +int find_hihghest_bit( uint32 mask );
1.77 +
1.78 +//------------------------------RegMask----------------------------------------
1.79 +// The ADL file describes how to print the machine-specific registers, as well
1.80 +// as any notion of register classes. We provide a register mask, which is
1.81 +// just a collection of Register numbers.
1.82 +
1.83 +// The ADLC defines 2 macros, RM_SIZE and FORALL_BODY.
1.84 +// RM_SIZE is the size of a register mask in words.
1.85 +// FORALL_BODY replicates a BODY macro once per word in the register mask.
1.86 +// The usage is somewhat clumsy and limited to the regmask.[h,c]pp files.
1.87 +// However, it means the ADLC can redefine the unroll macro and all loops
1.88 +// over register masks will be unrolled by the correct amount.
1.89 +
1.90 +class RegMask VALUE_OBJ_CLASS_SPEC {
1.91 + union {
1.92 + double _dummy_force_double_alignment[RM_SIZE>>1];
1.93 + // Array of Register Mask bits. This array is large enough to cover
1.94 + // all the machine registers and all parameters that need to be passed
1.95 + // on the stack (stack registers) up to some interesting limit. Methods
1.96 + // that need more parameters will NOT be compiled. On Intel, the limit
1.97 + // is something like 90+ parameters.
1.98 + int _A[RM_SIZE];
1.99 + };
1.100 +
1.101 + enum {
1.102 + _WordBits = BitsPerInt,
1.103 + _LogWordBits = LogBitsPerInt,
1.104 + _RM_SIZE = RM_SIZE // local constant, imported, then hidden by #undef
1.105 + };
1.106 +
1.107 +public:
1.108 + enum { CHUNK_SIZE = RM_SIZE*_WordBits };
1.109 +
1.110 + // SlotsPerLong is 2, since slots are 32 bits and longs are 64 bits.
1.111 + // Also, consider the maximum alignment size for a normally allocated
1.112 + // value. Since we allocate register pairs but not register quads (at
1.113 + // present), this alignment is SlotsPerLong (== 2). A normally
1.114 + // aligned allocated register is either a single register, or a pair
1.115 + // of adjacent registers, the lower-numbered being even.
1.116 + // See also is_aligned_Pairs() below, and the padding added before
1.117 + // Matcher::_new_SP to keep allocated pairs aligned properly.
1.118 + // If we ever go to quad-word allocations, SlotsPerQuad will become
1.119 + // the controlling alignment constraint. Note that this alignment
1.120 + // requirement is internal to the allocator, and independent of any
1.121 + // particular platform.
1.122 + enum { SlotsPerLong = 2,
1.123 + SlotsPerVecS = 1,
1.124 + SlotsPerVecD = 2,
1.125 + SlotsPerVecX = 4,
1.126 + SlotsPerVecY = 8 };
1.127 +
1.128 + // A constructor only used by the ADLC output. All mask fields are filled
1.129 + // in directly. Calls to this look something like RM(1,2,3,4);
1.130 + RegMask(
1.131 +# define BODY(I) int a##I,
1.132 + FORALL_BODY
1.133 +# undef BODY
1.134 + int dummy = 0 ) {
1.135 +# define BODY(I) _A[I] = a##I;
1.136 + FORALL_BODY
1.137 +# undef BODY
1.138 + }
1.139 +
1.140 + // Handy copying constructor
1.141 + RegMask( RegMask *rm ) {
1.142 +# define BODY(I) _A[I] = rm->_A[I];
1.143 + FORALL_BODY
1.144 +# undef BODY
1.145 + }
1.146 +
1.147 + // Construct an empty mask
1.148 + RegMask( ) { Clear(); }
1.149 +
1.150 + // Construct a mask with a single bit
1.151 + RegMask( OptoReg::Name reg ) { Clear(); Insert(reg); }
1.152 +
1.153 + // Check for register being in mask
1.154 + int Member( OptoReg::Name reg ) const {
1.155 + assert( reg < CHUNK_SIZE, "" );
1.156 + return _A[reg>>_LogWordBits] & (1<<(reg&(_WordBits-1)));
1.157 + }
1.158 +
1.159 + // The last bit in the register mask indicates that the mask should repeat
1.160 + // indefinitely with ONE bits. Returns TRUE if mask is infinite or
1.161 + // unbounded in size. Returns FALSE if mask is finite size.
1.162 + int is_AllStack() const { return _A[RM_SIZE-1] >> (_WordBits-1); }
1.163 +
1.164 + // Work around an -xO3 optimization problme in WS6U1. The old way:
1.165 + // void set_AllStack() { _A[RM_SIZE-1] |= (1<<(_WordBits-1)); }
1.166 + // will cause _A[RM_SIZE-1] to be clobbered, not updated when set_AllStack()
1.167 + // follows an Insert() loop, like the one found in init_spill_mask(). Using
1.168 + // Insert() instead works because the index into _A in computed instead of
1.169 + // constant. See bug 4665841.
1.170 + void set_AllStack() { Insert(OptoReg::Name(CHUNK_SIZE-1)); }
1.171 +
1.172 + // Test for being a not-empty mask.
1.173 + int is_NotEmpty( ) const {
1.174 + int tmp = 0;
1.175 +# define BODY(I) tmp |= _A[I];
1.176 + FORALL_BODY
1.177 +# undef BODY
1.178 + return tmp;
1.179 + }
1.180 +
1.181 + // Find lowest-numbered register from mask, or BAD if mask is empty.
1.182 + OptoReg::Name find_first_elem() const {
1.183 + int base, bits;
1.184 +# define BODY(I) if( (bits = _A[I]) != 0 ) base = I<<_LogWordBits; else
1.185 + FORALL_BODY
1.186 +# undef BODY
1.187 + { base = OptoReg::Bad; bits = 1<<0; }
1.188 + return OptoReg::Name(base + find_lowest_bit(bits));
1.189 + }
1.190 + // Get highest-numbered register from mask, or BAD if mask is empty.
1.191 + OptoReg::Name find_last_elem() const {
1.192 + int base, bits;
1.193 +# define BODY(I) if( (bits = _A[RM_SIZE-1-I]) != 0 ) base = (RM_SIZE-1-I)<<_LogWordBits; else
1.194 + FORALL_BODY
1.195 +# undef BODY
1.196 + { base = OptoReg::Bad; bits = 1<<0; }
1.197 + return OptoReg::Name(base + find_hihghest_bit(bits));
1.198 + }
1.199 +
1.200 + // Find the lowest-numbered register pair in the mask. Return the
1.201 + // HIGHEST register number in the pair, or BAD if no pairs.
1.202 + // Assert that the mask contains only bit pairs.
1.203 + OptoReg::Name find_first_pair() const;
1.204 +
1.205 + // Clear out partial bits; leave only aligned adjacent bit pairs.
1.206 + void clear_to_pairs();
1.207 + // Smear out partial bits; leave only aligned adjacent bit pairs.
1.208 + void smear_to_pairs();
1.209 + // Verify that the mask contains only aligned adjacent bit pairs
1.210 + void verify_pairs() const { assert( is_aligned_pairs(), "mask is not aligned, adjacent pairs" ); }
1.211 + // Test that the mask contains only aligned adjacent bit pairs
1.212 + bool is_aligned_pairs() const;
1.213 +
1.214 + // mask is a pair of misaligned registers
1.215 + bool is_misaligned_pair() const { return Size()==2 && !is_aligned_pairs(); }
1.216 + // Test for single register
1.217 + int is_bound1() const;
1.218 + // Test for a single adjacent pair
1.219 + int is_bound_pair() const;
1.220 + // Test for a single adjacent set of ideal register's size.
1.221 + int is_bound(uint ireg) const {
1.222 + if (is_vector(ireg)) {
1.223 + if (is_bound_set(num_registers(ireg)))
1.224 + return true;
1.225 + } else if (is_bound1() || is_bound_pair()) {
1.226 + return true;
1.227 + }
1.228 + return false;
1.229 + }
1.230 +
1.231 + // Find the lowest-numbered register set in the mask. Return the
1.232 + // HIGHEST register number in the set, or BAD if no sets.
1.233 + // Assert that the mask contains only bit sets.
1.234 + OptoReg::Name find_first_set(const int size) const;
1.235 +
1.236 + // Clear out partial bits; leave only aligned adjacent bit sets of size.
1.237 + void clear_to_sets(const int size);
1.238 + // Smear out partial bits to aligned adjacent bit sets.
1.239 + void smear_to_sets(const int size);
1.240 + // Verify that the mask contains only aligned adjacent bit sets
1.241 + void verify_sets(int size) const { assert(is_aligned_sets(size), "mask is not aligned, adjacent sets"); }
1.242 + // Test that the mask contains only aligned adjacent bit sets
1.243 + bool is_aligned_sets(const int size) const;
1.244 +
1.245 + // mask is a set of misaligned registers
1.246 + bool is_misaligned_set(int size) const { return (int)Size()==size && !is_aligned_sets(size);}
1.247 +
1.248 + // Test for a single adjacent set
1.249 + int is_bound_set(const int size) const;
1.250 +
1.251 + static bool is_vector(uint ireg);
1.252 + static int num_registers(uint ireg);
1.253 +
1.254 + // Fast overlap test. Non-zero if any registers in common.
1.255 + int overlap( const RegMask &rm ) const {
1.256 + return
1.257 +# define BODY(I) (_A[I] & rm._A[I]) |
1.258 + FORALL_BODY
1.259 +# undef BODY
1.260 + 0 ;
1.261 + }
1.262 +
1.263 + // Special test for register pressure based splitting
1.264 + // UP means register only, Register plus stack, or stack only is DOWN
1.265 + bool is_UP() const;
1.266 +
1.267 + // Clear a register mask
1.268 + void Clear( ) {
1.269 +# define BODY(I) _A[I] = 0;
1.270 + FORALL_BODY
1.271 +# undef BODY
1.272 + }
1.273 +
1.274 + // Fill a register mask with 1's
1.275 + void Set_All( ) {
1.276 +# define BODY(I) _A[I] = -1;
1.277 + FORALL_BODY
1.278 +# undef BODY
1.279 + }
1.280 +
1.281 + // Insert register into mask
1.282 + void Insert( OptoReg::Name reg ) {
1.283 + assert( reg < CHUNK_SIZE, "" );
1.284 + _A[reg>>_LogWordBits] |= (1<<(reg&(_WordBits-1)));
1.285 + }
1.286 +
1.287 + // Remove register from mask
1.288 + void Remove( OptoReg::Name reg ) {
1.289 + assert( reg < CHUNK_SIZE, "" );
1.290 + _A[reg>>_LogWordBits] &= ~(1<<(reg&(_WordBits-1)));
1.291 + }
1.292 +
1.293 + // OR 'rm' into 'this'
1.294 + void OR( const RegMask &rm ) {
1.295 +# define BODY(I) this->_A[I] |= rm._A[I];
1.296 + FORALL_BODY
1.297 +# undef BODY
1.298 + }
1.299 +
1.300 + // AND 'rm' into 'this'
1.301 + void AND( const RegMask &rm ) {
1.302 +# define BODY(I) this->_A[I] &= rm._A[I];
1.303 + FORALL_BODY
1.304 +# undef BODY
1.305 + }
1.306 +
1.307 + // Subtract 'rm' from 'this'
1.308 + void SUBTRACT( const RegMask &rm ) {
1.309 +# define BODY(I) _A[I] &= ~rm._A[I];
1.310 + FORALL_BODY
1.311 +# undef BODY
1.312 + }
1.313 +
1.314 + // Compute size of register mask: number of bits
1.315 + uint Size() const;
1.316 +
1.317 +#ifndef PRODUCT
1.318 + void print() const { dump(); }
1.319 + void dump(outputStream *st = tty) const; // Print a mask
1.320 +#endif
1.321 +
1.322 + static const RegMask Empty; // Common empty mask
1.323 +
1.324 + static bool can_represent(OptoReg::Name reg) {
1.325 + // NOTE: -1 in computation reflects the usage of the last
1.326 + // bit of the regmask as an infinite stack flag and
1.327 + // -7 is to keep mask aligned for largest value (VecY).
1.328 + return (int)reg < (int)(CHUNK_SIZE-1);
1.329 + }
1.330 + static bool can_represent_arg(OptoReg::Name reg) {
1.331 + // NOTE: -SlotsPerVecY in computation reflects the need
1.332 + // to keep mask aligned for largest value (VecY).
1.333 + return (int)reg < (int)(CHUNK_SIZE-SlotsPerVecY);
1.334 + }
1.335 +};
1.336 +
1.337 +// Do not use this constant directly in client code!
1.338 +#undef RM_SIZE
1.339 +
1.340 +#endif // SHARE_VM_OPTO_REGMASK_HPP
