1.1 --- a/src/cpu/mips/vm/mips_64.ad Tue Mar 28 16:09:10 2017 -0400
1.2 +++ b/src/cpu/mips/vm/mips_64.ad Thu Mar 30 08:45:59 2017 -0400
1.3 @@ -1704,15 +1704,55 @@
1.4 int disp = $mem$$disp;
1.5
1.6 if( index != 0 ) {
1.7 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.8 - __ gslbx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.9 + if( Assembler::is_simm16(disp) ) {
1.10 + if( UseLoongsonISA ) {
1.11 + if (scale == 0) {
1.12 + __ gslbx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.13 + } else {
1.14 + __ dsll(AT, as_Register(index), scale);
1.15 + __ gslbx(as_Register(dst), as_Register(base), AT, disp);
1.16 + }
1.17 + } else {
1.18 + if (scale == 0) {
1.19 + __ addu(AT, as_Register(base), as_Register(index));
1.20 + } else {
1.21 + __ dsll(AT, as_Register(index), scale);
1.22 + __ addu(AT, as_Register(base), AT);
1.23 + }
1.24 + __ lb(as_Register(dst), AT, disp);
1.25 + }
1.26 + } else {
1.27 + if (scale == 0) {
1.28 + __ addu(AT, as_Register(base), as_Register(index));
1.29 + } else {
1.30 + __ dsll(AT, as_Register(index), scale);
1.31 + __ addu(AT, as_Register(base), AT);
1.32 + }
1.33 + __ move(T9, disp);
1.34 + if( UseLoongsonISA ) {
1.35 + __ gslbx(as_Register(dst), AT, T9, 0);
1.36 + } else {
1.37 + __ addu(AT, AT, T9);
1.38 + __ lb(as_Register(dst), AT, 0);
1.39 + }
1.40 + }
1.41 } else {
1.42 - __ lb(as_Register(dst), as_Register(base), disp);
1.43 + if( Assembler::is_simm16(disp) ) {
1.44 + __ lb(as_Register(dst), as_Register(base), disp);
1.45 + } else {
1.46 + __ move(T9, disp);
1.47 + if( UseLoongsonISA ) {
1.48 + __ gslbx(as_Register(dst), as_Register(base), T9, 0);
1.49 + } else {
1.50 + __ addu(AT, as_Register(base), T9);
1.51 + __ lb(as_Register(dst), AT, 0);
1.52 + }
1.53 + }
1.54 }
1.55 %}
1.56
1.57 //Load byte unsigned
1.58 - enc_class load_UB_enc (mRegI dst, umemory mem) %{
1.59 + enc_class load_UB_enc (mRegI dst, memory mem) %{
1.60 MacroAssembler _masm(&cbuf);
1.61 int dst = $dst$$reg;
1.62 int base = $mem$$base;
1.63 @@ -1720,8 +1760,29 @@
1.64 int scale = $mem$$scale;
1.65 int disp = $mem$$disp;
1.66
1.67 - assert(index == 0, "no index");
1.68 - __ lbu(as_Register(dst), as_Register(base), disp);
1.69 + if( index != 0 ) {
1.70 + if (scale == 0) {
1.71 + __ daddu(AT, as_Register(base), as_Register(index));
1.72 + } else {
1.73 + __ dsll(AT, as_Register(index), scale);
1.74 + __ daddu(AT, as_Register(base), AT);
1.75 + }
1.76 + if( Assembler::is_simm16(disp) ) {
1.77 + __ lbu(as_Register(dst), AT, disp);
1.78 + } else {
1.79 + __ move(T9, disp);
1.80 + __ daddu(AT, AT, T9);
1.81 + __ lbu(as_Register(dst), AT, 0);
1.82 + }
1.83 + } else {
1.84 + if( Assembler::is_simm16(disp) ) {
1.85 + __ lbu(as_Register(dst), as_Register(base), disp);
1.86 + } else {
1.87 + __ move(T9, disp);
1.88 + __ daddu(AT, as_Register(base), T9);
1.89 + __ lbu(as_Register(dst), AT, 0);
1.90 + }
1.91 + }
1.92 %}
1.93
1.94 enc_class store_B_reg_enc (memory mem, mRegI src) %{
1.95 @@ -1733,58 +1794,334 @@
1.96 int disp = $mem$$disp;
1.97
1.98 if( index != 0 ) {
1.99 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.100 - __ gssbx(as_Register(src), as_Register(base), as_Register(index), disp);
1.101 + if (scale == 0) {
1.102 + if( Assembler::is_simm(disp, 8) ) {
1.103 + if (UseLoongsonISA) {
1.104 + __ gssbx(as_Register(src), as_Register(base), as_Register(index), disp);
1.105 + } else {
1.106 + __ addu(AT, as_Register(base), as_Register(index));
1.107 + __ sb(as_Register(src), AT, disp);
1.108 + }
1.109 + } else if( Assembler::is_simm16(disp) ) {
1.110 + __ addu(AT, as_Register(base), as_Register(index));
1.111 + __ sb(as_Register(src), AT, disp);
1.112 + } else {
1.113 + __ addu(AT, as_Register(base), as_Register(index));
1.114 + __ move(T9, disp);
1.115 + if (UseLoongsonISA) {
1.116 + __ gssbx(as_Register(src), AT, T9, 0);
1.117 + } else {
1.118 + __ addu(AT, AT, T9);
1.119 + __ sb(as_Register(src), AT, 0);
1.120 + }
1.121 + }
1.122 + } else {
1.123 + __ dsll(AT, as_Register(index), scale);
1.124 + if( Assembler::is_simm(disp, 8) ) {
1.125 + if (UseLoongsonISA) {
1.126 + __ gssbx(as_Register(src), AT, as_Register(base), disp);
1.127 + } else {
1.128 + __ addu(AT, as_Register(base), AT);
1.129 + __ sb(as_Register(src), AT, disp);
1.130 + }
1.131 + } else if( Assembler::is_simm16(disp) ) {
1.132 + __ addu(AT, as_Register(base), AT);
1.133 + __ sb(as_Register(src), AT, disp);
1.134 + } else {
1.135 + __ addu(AT, as_Register(base), AT);
1.136 + __ move(T9, disp);
1.137 + if (UseLoongsonISA) {
1.138 + __ gssbx(as_Register(src), AT, T9, 0);
1.139 + } else {
1.140 + __ addu(AT, AT, T9);
1.141 + __ sb(as_Register(src), AT, 0);
1.142 + }
1.143 + }
1.144 + }
1.145 } else {
1.146 - __ sb(as_Register(src), as_Register(base), disp);
1.147 + if( Assembler::is_simm16(disp) ) {
1.148 + __ sb(as_Register(src), as_Register(base), disp);
1.149 + } else {
1.150 + __ move(T9, disp);
1.151 + if (UseLoongsonISA) {
1.152 + __ gssbx(as_Register(src), as_Register(base), T9, 0);
1.153 + } else {
1.154 + __ addu(AT, as_Register(base), T9);
1.155 + __ sb(as_Register(src), AT, 0);
1.156 + }
1.157 + }
1.158 }
1.159 %}
1.160
1.161 - enc_class store_B0_enc (memory mem) %{
1.162 + enc_class store_B_immI_enc (memory mem, immI8 src) %{
1.163 MacroAssembler _masm(&cbuf);
1.164 int base = $mem$$base;
1.165 int index = $mem$$index;
1.166 int scale = $mem$$scale;
1.167 int disp = $mem$$disp;
1.168 + int value = $src$$constant;
1.169
1.170 if( index != 0 ) {
1.171 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.172 - __ gssbx(R0, as_Register(base), as_Register(index), disp);
1.173 + if (!UseLoongsonISA) {
1.174 + if (scale == 0) {
1.175 + __ daddu(AT, as_Register(base), as_Register(index));
1.176 + } else {
1.177 + __ dsll(AT, as_Register(index), scale);
1.178 + __ daddu(AT, as_Register(base), AT);
1.179 + }
1.180 + if( Assembler::is_simm16(disp) ) {
1.181 + if (value == 0) {
1.182 + __ sb(R0, AT, disp);
1.183 + } else {
1.184 + __ move(T9, value);
1.185 + __ sb(T9, AT, disp);
1.186 + }
1.187 + } else {
1.188 + if (value == 0) {
1.189 + __ move(T9, disp);
1.190 + __ daddu(AT, AT, T9);
1.191 + __ sb(R0, AT, 0);
1.192 + } else {
1.193 + __ move(T9, disp);
1.194 + __ daddu(AT, AT, T9);
1.195 + __ move(T9, value);
1.196 + __ sb(T9, AT, 0);
1.197 + }
1.198 + }
1.199 + } else {
1.200 +
1.201 + if (scale == 0) {
1.202 + if( Assembler::is_simm(disp, 8) ) {
1.203 + if (value == 0) {
1.204 + __ gssbx(R0, as_Register(base), as_Register(index), disp);
1.205 + } else {
1.206 + __ move(T9, value);
1.207 + __ gssbx(T9, as_Register(base), as_Register(index), disp);
1.208 + }
1.209 + } else if( Assembler::is_simm16(disp) ) {
1.210 + __ daddu(AT, as_Register(base), as_Register(index));
1.211 + if (value == 0) {
1.212 + __ sb(R0, AT, disp);
1.213 + } else {
1.214 + __ move(T9, value);
1.215 + __ sb(T9, AT, disp);
1.216 + }
1.217 + } else {
1.218 + if (value == 0) {
1.219 + __ daddu(AT, as_Register(base), as_Register(index));
1.220 + __ move(T9, disp);
1.221 + __ gssbx(R0, AT, T9, 0);
1.222 + } else {
1.223 + __ move(AT, disp);
1.224 + __ move(T9, value);
1.225 + __ daddu(AT, as_Register(base), AT);
1.226 + __ gssbx(T9, AT, as_Register(index), 0);
1.227 + }
1.228 + }
1.229 +
1.230 + } else {
1.231 +
1.232 + if( Assembler::is_simm(disp, 8) ) {
1.233 + __ dsll(AT, as_Register(index), scale);
1.234 + if (value == 0) {
1.235 + __ gssbx(R0, as_Register(base), AT, disp);
1.236 + } else {
1.237 + __ move(T9, value);
1.238 + __ gssbx(T9, as_Register(base), AT, disp);
1.239 + }
1.240 + } else if( Assembler::is_simm16(disp) ) {
1.241 + __ dsll(AT, as_Register(index), scale);
1.242 + __ daddu(AT, as_Register(base), AT);
1.243 + if (value == 0) {
1.244 + __ sb(R0, AT, disp);
1.245 + } else {
1.246 + __ move(T9, value);
1.247 + __ sb(T9, AT, disp);
1.248 + }
1.249 + } else {
1.250 + __ dsll(AT, as_Register(index), scale);
1.251 + if (value == 0) {
1.252 + __ daddu(AT, as_Register(base), AT);
1.253 + __ move(T9, disp);
1.254 + __ gssbx(R0, AT, T9, 0);
1.255 + } else {
1.256 + __ move(T9, disp);
1.257 + __ daddu(AT, AT, T9);
1.258 + __ move(T9, value);
1.259 + __ gssbx(T9, as_Register(base), AT, 0);
1.260 + }
1.261 + }
1.262 + }
1.263 + }
1.264 } else {
1.265 - __ sb(R0, as_Register(base), disp);
1.266 + if( Assembler::is_simm16(disp) ) {
1.267 + if (value == 0) {
1.268 + __ sb(R0, as_Register(base), disp);
1.269 + } else {
1.270 + __ move(AT, value);
1.271 + __ sb(AT, as_Register(base), disp);
1.272 + }
1.273 + } else {
1.274 + if (value == 0) {
1.275 + __ move(T9, disp);
1.276 + if (UseLoongsonISA) {
1.277 + __ gssbx(R0, as_Register(base), T9, 0);
1.278 + } else {
1.279 + __ daddu(AT, as_Register(base), T9);
1.280 + __ sb(R0, AT, 0);
1.281 + }
1.282 + } else {
1.283 + __ move(T9, disp);
1.284 + if (UseLoongsonISA) {
1.285 + __ move(AT, value);
1.286 + __ gssbx(AT, as_Register(base), T9, 0);
1.287 + } else {
1.288 + __ daddu(AT, as_Register(base), T9);
1.289 + __ move(T9, value);
1.290 + __ sb(T9, AT, 0);
1.291 + }
1.292 + }
1.293 + }
1.294 }
1.295 %}
1.296
1.297 - enc_class store_B_reg_sync_enc (memory mem, mRegI src) %{
1.298 - MacroAssembler _masm(&cbuf);
1.299 - int src = $src$$reg;
1.300 - int base = $mem$$base;
1.301 - int index = $mem$$index;
1.302 - int scale = $mem$$scale;
1.303 - int disp = $mem$$disp;
1.304 -
1.305 - if( index != 0 ) {
1.306 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.307 - __ gssbx(as_Register(src), as_Register(base), as_Register(index), disp);
1.308 - } else {
1.309 - __ sb(as_Register(src), as_Register(base), disp);
1.310 - }
1.311 - __ sync();
1.312 - %}
1.313 -
1.314 - enc_class store_B0_sync_enc (memory mem) %{
1.315 +
1.316 + enc_class store_B_immI_enc_sync (memory mem, immI8 src) %{
1.317 MacroAssembler _masm(&cbuf);
1.318 int base = $mem$$base;
1.319 int index = $mem$$index;
1.320 int scale = $mem$$scale;
1.321 int disp = $mem$$disp;
1.322 + int value = $src$$constant;
1.323
1.324 if( index != 0 ) {
1.325 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.326 - __ gssbx(R0, as_Register(base), as_Register(index), disp);
1.327 + if ( UseLoongsonISA ) {
1.328 + if ( Assembler::is_simm(disp,8) ) {
1.329 + if ( scale == 0 ) {
1.330 + if ( value == 0 ) {
1.331 + __ gssbx(R0, as_Register(base), as_Register(index), disp);
1.332 + } else {
1.333 + __ move(AT, value);
1.334 + __ gssbx(AT, as_Register(base), as_Register(index), disp);
1.335 + }
1.336 + } else {
1.337 + __ dsll(AT, as_Register(index), scale);
1.338 + if ( value == 0 ) {
1.339 + __ gssbx(R0, as_Register(base), AT, disp);
1.340 + } else {
1.341 + __ move(T9, value);
1.342 + __ gssbx(T9, as_Register(base), AT, disp);
1.343 + }
1.344 + }
1.345 + } else if ( Assembler::is_simm16(disp) ) {
1.346 + if ( scale == 0 ) {
1.347 + __ daddu(AT, as_Register(base), as_Register(index));
1.348 + if ( value == 0 ){
1.349 + __ sb(R0, AT, disp);
1.350 + } else {
1.351 + __ move(T9, value);
1.352 + __ sb(T9, AT, disp);
1.353 + }
1.354 + } else {
1.355 + __ dsll(AT, as_Register(index), scale);
1.356 + __ daddu(AT, as_Register(base), AT);
1.357 + if ( value == 0 ) {
1.358 + __ sb(R0, AT, disp);
1.359 + } else {
1.360 + __ move(T9, value);
1.361 + __ sb(T9, AT, disp);
1.362 + }
1.363 + }
1.364 + } else {
1.365 + if ( scale == 0 ) {
1.366 + __ move(AT, disp);
1.367 + __ daddu(AT, as_Register(index), AT);
1.368 + if ( value == 0 ) {
1.369 + __ gssbx(R0, as_Register(base), AT, 0);
1.370 + } else {
1.371 + __ move(T9, value);
1.372 + __ gssbx(T9, as_Register(base), AT, 0);
1.373 + }
1.374 + } else {
1.375 + __ dsll(AT, as_Register(index), scale);
1.376 + __ move(T9, disp);
1.377 + __ daddu(AT, AT, T9);
1.378 + if ( value == 0 ) {
1.379 + __ gssbx(R0, as_Register(base), AT, 0);
1.380 + } else {
1.381 + __ move(T9, value);
1.382 + __ gssbx(T9, as_Register(base), AT, 0);
1.383 + }
1.384 + }
1.385 + }
1.386 + } else { //not use loongson isa
1.387 + if (scale == 0) {
1.388 + __ daddu(AT, as_Register(base), as_Register(index));
1.389 + } else {
1.390 + __ dsll(AT, as_Register(index), scale);
1.391 + __ daddu(AT, as_Register(base), AT);
1.392 + }
1.393 + if( Assembler::is_simm16(disp) ) {
1.394 + if (value == 0) {
1.395 + __ sb(R0, AT, disp);
1.396 + } else {
1.397 + __ move(T9, value);
1.398 + __ sb(T9, AT, disp);
1.399 + }
1.400 + } else {
1.401 + if (value == 0) {
1.402 + __ move(T9, disp);
1.403 + __ daddu(AT, AT, T9);
1.404 + __ sb(R0, AT, 0);
1.405 + } else {
1.406 + __ move(T9, disp);
1.407 + __ daddu(AT, AT, T9);
1.408 + __ move(T9, value);
1.409 + __ sb(T9, AT, 0);
1.410 + }
1.411 + }
1.412 + }
1.413 } else {
1.414 - __ sb(R0, as_Register(base), disp);
1.415 + if ( UseLoongsonISA ){
1.416 + if ( Assembler::is_simm16(disp) ){
1.417 + if ( value == 0 ) {
1.418 + __ sb(R0, as_Register(base), disp);
1.419 + } else {
1.420 + __ move(AT, value);
1.421 + __ sb(AT, as_Register(base), disp);
1.422 + }
1.423 + } else {
1.424 + __ move(AT, disp);
1.425 + if ( value == 0 ) {
1.426 + __ gssbx(R0, as_Register(base), AT, 0);
1.427 + } else {
1.428 + __ move(T9, value);
1.429 + __ gssbx(T9, as_Register(base), AT, 0);
1.430 + }
1.431 + }
1.432 + } else {
1.433 + if( Assembler::is_simm16(disp) ) {
1.434 + if (value == 0) {
1.435 + __ sb(R0, as_Register(base), disp);
1.436 + } else {
1.437 + __ move(AT, value);
1.438 + __ sb(AT, as_Register(base), disp);
1.439 + }
1.440 + } else {
1.441 + if (value == 0) {
1.442 + __ move(T9, disp);
1.443 + __ daddu(AT, as_Register(base), T9);
1.444 + __ sb(R0, AT, 0);
1.445 + } else {
1.446 + __ move(T9, disp);
1.447 + __ daddu(AT, as_Register(base), T9);
1.448 + __ move(T9, value);
1.449 + __ sb(T9, AT, 0);
1.450 + }
1.451 + }
1.452 + }
1.453 }
1.454 +
1.455 __ sync();
1.456 %}
1.457
1.458 @@ -1798,15 +2135,72 @@
1.459 int disp = $mem$$disp;
1.460
1.461 if( index != 0 ) {
1.462 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.463 - __ gslhx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.464 - } else {
1.465 - __ lh(as_Register(dst), as_Register(base), disp);
1.466 + if ( UseLoongsonISA ) {
1.467 + if ( Assembler::is_simm(disp, 8) ) {
1.468 + if (scale == 0) {
1.469 + __ gslhx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.470 + } else {
1.471 + __ dsll(AT, as_Register(index), scale);
1.472 + __ gslhx(as_Register(dst), as_Register(base), AT, disp);
1.473 + }
1.474 + } else if ( Assembler::is_simm16(disp) ) {
1.475 + if (scale == 0) {
1.476 + __ daddu(AT, as_Register(base), as_Register(index));
1.477 + __ lh(as_Register(dst), AT, disp);
1.478 + } else {
1.479 + __ dsll(AT, as_Register(index), scale);
1.480 + __ daddu(AT, as_Register(base), AT);
1.481 + __ lh(as_Register(dst), AT, disp);
1.482 + }
1.483 + } else {
1.484 + if (scale == 0) {
1.485 + __ move(AT, disp);
1.486 + __ daddu(AT, as_Register(index), AT);
1.487 + __ gslhx(as_Register(dst), as_Register(base), AT, 0);
1.488 + } else {
1.489 + __ dsll(AT, as_Register(index), scale);
1.490 + __ move(T9, disp);
1.491 + __ daddu(AT, AT, T9);
1.492 + __ gslhx(as_Register(dst), as_Register(base), AT, 0);
1.493 + }
1.494 + }
1.495 + } else { // not use loongson isa
1.496 + if (scale == 0) {
1.497 + __ daddu(AT, as_Register(base), as_Register(index));
1.498 + } else {
1.499 + __ dsll(AT, as_Register(index), scale);
1.500 + __ daddu(AT, as_Register(base), AT);
1.501 + }
1.502 + if( Assembler::is_simm16(disp) ) {
1.503 + __ lh(as_Register(dst), AT, disp);
1.504 + } else {
1.505 + __ move(T9, disp);
1.506 + __ daddu(AT, AT, T9);
1.507 + __ lh(as_Register(dst), AT, 0);
1.508 + }
1.509 + }
1.510 + } else { // index is 0
1.511 + if ( UseLoongsonISA ) {
1.512 + if ( Assembler::is_simm16(disp) ) {
1.513 + __ lh(as_Register(dst), as_Register(base), disp);
1.514 + } else {
1.515 + __ move(T9, disp);
1.516 + __ gslhx(as_Register(dst), as_Register(base), T9, 0);
1.517 + }
1.518 + } else { //not use loongson isa
1.519 + if( Assembler::is_simm16(disp) ) {
1.520 + __ lh(as_Register(dst), as_Register(base), disp);
1.521 + } else {
1.522 + __ move(T9, disp);
1.523 + __ daddu(AT, as_Register(base), T9);
1.524 + __ lh(as_Register(dst), AT, 0);
1.525 + }
1.526 + }
1.527 }
1.528 %}
1.529
1.530 // Load Char (16bit unsigned)
1.531 - enc_class load_C_enc (mRegI dst, umemory mem) %{
1.532 + enc_class load_C_enc (mRegI dst, memory mem) %{
1.533 MacroAssembler _masm(&cbuf);
1.534 int dst = $dst$$reg;
1.535 int base = $mem$$base;
1.536 @@ -1814,8 +2208,29 @@
1.537 int scale = $mem$$scale;
1.538 int disp = $mem$$disp;
1.539
1.540 - assert(index == 0, "no index");
1.541 - __ lhu(as_Register(dst), as_Register(base), disp);
1.542 + if( index != 0 ) {
1.543 + if (scale == 0) {
1.544 + __ daddu(AT, as_Register(base), as_Register(index));
1.545 + } else {
1.546 + __ dsll(AT, as_Register(index), scale);
1.547 + __ daddu(AT, as_Register(base), AT);
1.548 + }
1.549 + if( Assembler::is_simm16(disp) ) {
1.550 + __ lhu(as_Register(dst), AT, disp);
1.551 + } else {
1.552 + __ move(T9, disp);
1.553 + __ addu(AT, AT, T9);
1.554 + __ lhu(as_Register(dst), AT, 0);
1.555 + }
1.556 + } else {
1.557 + if( Assembler::is_simm16(disp) ) {
1.558 + __ lhu(as_Register(dst), as_Register(base), disp);
1.559 + } else {
1.560 + __ move(T9, disp);
1.561 + __ daddu(AT, as_Register(base), T9);
1.562 + __ lhu(as_Register(dst), AT, 0);
1.563 + }
1.564 + }
1.565 %}
1.566
1.567 // Store Char (16bit unsigned)
1.568 @@ -1828,10 +2243,50 @@
1.569 int disp = $mem$$disp;
1.570
1.571 if( index != 0 ) {
1.572 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.573 - __ gsshx(as_Register(src), as_Register(base), as_Register(index), disp);
1.574 + if( Assembler::is_simm16(disp) ) {
1.575 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.576 + if (scale == 0) {
1.577 + __ gsshx(as_Register(src), as_Register(base), as_Register(index), disp);
1.578 + } else {
1.579 + __ dsll(AT, as_Register(index), scale);
1.580 + __ gsshx(as_Register(src), as_Register(base), AT, disp);
1.581 + }
1.582 + } else {
1.583 + if (scale == 0) {
1.584 + __ addu(AT, as_Register(base), as_Register(index));
1.585 + } else {
1.586 + __ dsll(AT, as_Register(index), scale);
1.587 + __ addu(AT, as_Register(base), AT);
1.588 + }
1.589 + __ sh(as_Register(src), AT, disp);
1.590 + }
1.591 + } else {
1.592 + if (scale == 0) {
1.593 + __ addu(AT, as_Register(base), as_Register(index));
1.594 + } else {
1.595 + __ dsll(AT, as_Register(index), scale);
1.596 + __ addu(AT, as_Register(base), AT);
1.597 + }
1.598 + __ move(T9, disp);
1.599 + if( UseLoongsonISA ) {
1.600 + __ gsshx(as_Register(src), AT, T9, 0);
1.601 + } else {
1.602 + __ addu(AT, AT, T9);
1.603 + __ sh(as_Register(src), AT, 0);
1.604 + }
1.605 + }
1.606 } else {
1.607 - __ sh(as_Register(src), as_Register(base), disp);
1.608 + if( Assembler::is_simm16(disp) ) {
1.609 + __ sh(as_Register(src), as_Register(base), disp);
1.610 + } else {
1.611 + __ move(T9, disp);
1.612 + if( UseLoongsonISA ) {
1.613 + __ gsshx(as_Register(src), as_Register(base), T9, 0);
1.614 + } else {
1.615 + __ addu(AT, as_Register(base), T9);
1.616 + __ sh(as_Register(src), AT, 0);
1.617 + }
1.618 + }
1.619 }
1.620 %}
1.621
1.622 @@ -1843,10 +2298,50 @@
1.623 int disp = $mem$$disp;
1.624
1.625 if( index != 0 ) {
1.626 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.627 - __ gsshx(R0, as_Register(base), as_Register(index), disp);
1.628 + if( Assembler::is_simm16(disp) ) {
1.629 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.630 + if (scale == 0) {
1.631 + __ gsshx(R0, as_Register(base), as_Register(index), disp);
1.632 + } else {
1.633 + __ dsll(AT, as_Register(index), scale);
1.634 + __ gsshx(R0, as_Register(base), AT, disp);
1.635 + }
1.636 + } else {
1.637 + if (scale == 0) {
1.638 + __ addu(AT, as_Register(base), as_Register(index));
1.639 + } else {
1.640 + __ dsll(AT, as_Register(index), scale);
1.641 + __ addu(AT, as_Register(base), AT);
1.642 + }
1.643 + __ sh(R0, AT, disp);
1.644 + }
1.645 + } else {
1.646 + if (scale == 0) {
1.647 + __ addu(AT, as_Register(base), as_Register(index));
1.648 + } else {
1.649 + __ dsll(AT, as_Register(index), scale);
1.650 + __ addu(AT, as_Register(base), AT);
1.651 + }
1.652 + __ move(T9, disp);
1.653 + if( UseLoongsonISA ) {
1.654 + __ gsshx(R0, AT, T9, 0);
1.655 + } else {
1.656 + __ addu(AT, AT, T9);
1.657 + __ sh(R0, AT, 0);
1.658 + }
1.659 + }
1.660 } else {
1.661 - __ sh(R0, as_Register(base), disp);
1.662 + if( Assembler::is_simm16(disp) ) {
1.663 + __ sh(R0, as_Register(base), disp);
1.664 + } else {
1.665 + __ move(T9, disp);
1.666 + if( UseLoongsonISA ) {
1.667 + __ gsshx(R0, as_Register(base), T9, 0);
1.668 + } else {
1.669 + __ addu(AT, as_Register(base), T9);
1.670 + __ sh(R0, AT, 0);
1.671 + }
1.672 + }
1.673 }
1.674 %}
1.675
1.676 @@ -1859,10 +2354,50 @@
1.677 int disp = $mem$$disp;
1.678
1.679 if( index != 0 ) {
1.680 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.681 - __ gslwx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.682 + if( Assembler::is_simm16(disp) ) {
1.683 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.684 + if (scale == 0) {
1.685 + __ gslwx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.686 + } else {
1.687 + __ dsll(AT, as_Register(index), scale);
1.688 + __ gslwx(as_Register(dst), as_Register(base), AT, disp);
1.689 + }
1.690 + } else {
1.691 + if (scale == 0) {
1.692 + __ addu(AT, as_Register(base), as_Register(index));
1.693 + } else {
1.694 + __ dsll(AT, as_Register(index), scale);
1.695 + __ addu(AT, as_Register(base), AT);
1.696 + }
1.697 + __ lw(as_Register(dst), AT, disp);
1.698 + }
1.699 + } else {
1.700 + if (scale == 0) {
1.701 + __ addu(AT, as_Register(base), as_Register(index));
1.702 + } else {
1.703 + __ dsll(AT, as_Register(index), scale);
1.704 + __ addu(AT, as_Register(base), AT);
1.705 + }
1.706 + __ move(T9, disp);
1.707 + if( UseLoongsonISA ) {
1.708 + __ gslwx(as_Register(dst), AT, T9, 0);
1.709 + } else {
1.710 + __ addu(AT, AT, T9);
1.711 + __ lw(as_Register(dst), AT, 0);
1.712 + }
1.713 + }
1.714 } else {
1.715 - __ lw(as_Register(dst), as_Register(base), disp);
1.716 + if( Assembler::is_simm16(disp) ) {
1.717 + __ lw(as_Register(dst), as_Register(base), disp);
1.718 + } else {
1.719 + __ move(T9, disp);
1.720 + if( UseLoongsonISA ) {
1.721 + __ gslwx(as_Register(dst), as_Register(base), T9, 0);
1.722 + } else {
1.723 + __ addu(AT, as_Register(base), T9);
1.724 + __ lw(as_Register(dst), AT, 0);
1.725 + }
1.726 + }
1.727 }
1.728 %}
1.729
1.730 @@ -1875,41 +2410,224 @@
1.731 int disp = $mem$$disp;
1.732
1.733 if( index != 0 ) {
1.734 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.735 - __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
1.736 + if( Assembler::is_simm16(disp) ) {
1.737 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.738 + if (scale == 0) {
1.739 + __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
1.740 + } else {
1.741 + __ dsll(AT, as_Register(index), scale);
1.742 + __ gsswx(as_Register(src), as_Register(base), AT, disp);
1.743 + }
1.744 + } else {
1.745 + if (scale == 0) {
1.746 + __ addu(AT, as_Register(base), as_Register(index));
1.747 + } else {
1.748 + __ dsll(AT, as_Register(index), scale);
1.749 + __ addu(AT, as_Register(base), AT);
1.750 + }
1.751 + __ sw(as_Register(src), AT, disp);
1.752 + }
1.753 + } else {
1.754 + if (scale == 0) {
1.755 + __ addu(AT, as_Register(base), as_Register(index));
1.756 + } else {
1.757 + __ dsll(AT, as_Register(index), scale);
1.758 + __ addu(AT, as_Register(base), AT);
1.759 + }
1.760 + __ move(T9, disp);
1.761 + if( UseLoongsonISA ) {
1.762 + __ gsswx(as_Register(src), AT, T9, 0);
1.763 + } else {
1.764 + __ addu(AT, AT, T9);
1.765 + __ sw(as_Register(src), AT, 0);
1.766 + }
1.767 + }
1.768 } else {
1.769 - __ sw(as_Register(src), as_Register(base), disp);
1.770 + if( Assembler::is_simm16(disp) ) {
1.771 + __ sw(as_Register(src), as_Register(base), disp);
1.772 + } else {
1.773 + __ move(T9, disp);
1.774 + if( UseLoongsonISA ) {
1.775 + __ gsswx(as_Register(src), as_Register(base), T9, 0);
1.776 + } else {
1.777 + __ addu(AT, as_Register(base), T9);
1.778 + __ sw(as_Register(src), AT, 0);
1.779 + }
1.780 + }
1.781 }
1.782 %}
1.783
1.784 - enc_class store_I_immI0_enc (memory mem) %{
1.785 + enc_class store_I_immI_enc (memory mem, immI src) %{
1.786 MacroAssembler _masm(&cbuf);
1.787 - int base = $mem$$base;
1.788 + int base = $mem$$base;
1.789 int index = $mem$$index;
1.790 int scale = $mem$$scale;
1.791 - int disp = $mem$$disp;
1.792 + int disp = $mem$$disp;
1.793 + int value = $src$$constant;
1.794
1.795 if( index != 0 ) {
1.796 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.797 - __ gsswx(R0, as_Register(base), as_Register(index), disp);
1.798 + if ( UseLoongsonISA ) {
1.799 + if ( Assembler::is_simm(disp, 8) ) {
1.800 + if ( scale == 0 ) {
1.801 + if ( value == 0 ) {
1.802 + __ gsswx(R0, as_Register(base), as_Register(index), disp);
1.803 + } else {
1.804 + __ move(T9, value);
1.805 + __ gsswx(T9, as_Register(base), as_Register(index), disp);
1.806 + }
1.807 + } else {
1.808 + __ dsll(AT, as_Register(index), scale);
1.809 + if ( value == 0 ) {
1.810 + __ gsswx(R0, as_Register(base), AT, disp);
1.811 + } else {
1.812 + __ move(T9, value);
1.813 + __ gsswx(T9, as_Register(base), AT, disp);
1.814 + }
1.815 + }
1.816 + } else if ( Assembler::is_simm16(disp) ) {
1.817 + if ( scale == 0 ) {
1.818 + __ daddu(AT, as_Register(base), as_Register(index));
1.819 + if ( value == 0 ) {
1.820 + __ sw(R0, AT, disp);
1.821 + } else {
1.822 + __ move(T9, value);
1.823 + __ sw(T9, AT, disp);
1.824 + }
1.825 + } else {
1.826 + __ dsll(AT, as_Register(index), scale);
1.827 + __ daddu(AT, as_Register(base), AT);
1.828 + if ( value == 0 ) {
1.829 + __ sw(R0, AT, disp);
1.830 + } else {
1.831 + __ move(T9, value);
1.832 + __ sw(T9, AT, disp);
1.833 + }
1.834 + }
1.835 + } else {
1.836 + if ( scale == 0 ) {
1.837 + __ move(T9, disp);
1.838 + __ daddu(AT, as_Register(index), T9);
1.839 + if ( value ==0 ) {
1.840 + __ gsswx(R0, as_Register(base), AT, 0);
1.841 + } else {
1.842 + __ move(T9, value);
1.843 + __ gsswx(T9, as_Register(base), AT, 0);
1.844 + }
1.845 + } else {
1.846 + __ dsll(AT, as_Register(index), scale);
1.847 + __ move(T9, disp);
1.848 + __ daddu(AT, AT, T9);
1.849 + if ( value == 0 ) {
1.850 + __ gsswx(R0, as_Register(base), AT, 0);
1.851 + } else {
1.852 + __ move(T9, value);
1.853 + __ gsswx(T9, as_Register(base), AT, 0);
1.854 + }
1.855 + }
1.856 + }
1.857 + } else { //not use loongson isa
1.858 + if (scale == 0) {
1.859 + __ daddu(AT, as_Register(base), as_Register(index));
1.860 + } else {
1.861 + __ dsll(AT, as_Register(index), scale);
1.862 + __ daddu(AT, as_Register(base), AT);
1.863 + }
1.864 + if( Assembler::is_simm16(disp) ) {
1.865 + if (value == 0) {
1.866 + __ sw(R0, AT, disp);
1.867 + } else {
1.868 + __ move(T9, value);
1.869 + __ sw(T9, AT, disp);
1.870 + }
1.871 + } else {
1.872 + if (value == 0) {
1.873 + __ move(T9, disp);
1.874 + __ daddu(AT, AT, T9);
1.875 + __ sw(R0, AT, 0);
1.876 + } else {
1.877 + __ move(T9, disp);
1.878 + __ daddu(AT, AT, T9);
1.879 + __ move(T9, value);
1.880 + __ sw(T9, AT, 0);
1.881 + }
1.882 + }
1.883 + }
1.884 } else {
1.885 - __ sw(R0, as_Register(base), disp);
1.886 + if ( UseLoongsonISA ) {
1.887 + if ( Assembler::is_simm16(disp) ) {
1.888 + if ( value == 0 ) {
1.889 + __ sw(R0, as_Register(base), disp);
1.890 + } else {
1.891 + __ move(AT, value);
1.892 + __ sw(AT, as_Register(base), disp);
1.893 + }
1.894 + } else {
1.895 + __ move(T9, disp);
1.896 + if ( value == 0 ) {
1.897 + __ gsswx(R0, as_Register(base), T9, 0);
1.898 + } else {
1.899 + __ move(AT, value);
1.900 + __ gsswx(AT, as_Register(base), T9, 0);
1.901 + }
1.902 + }
1.903 + } else {
1.904 + if( Assembler::is_simm16(disp) ) {
1.905 + if (value == 0) {
1.906 + __ sw(R0, as_Register(base), disp);
1.907 + } else {
1.908 + __ move(AT, value);
1.909 + __ sw(AT, as_Register(base), disp);
1.910 + }
1.911 + } else {
1.912 + if (value == 0) {
1.913 + __ move(T9, disp);
1.914 + __ daddu(AT, as_Register(base), T9);
1.915 + __ sw(R0, AT, 0);
1.916 + } else {
1.917 + __ move(T9, disp);
1.918 + __ daddu(AT, as_Register(base), T9);
1.919 + __ move(T9, value);
1.920 + __ sw(T9, AT, 0);
1.921 + }
1.922 + }
1.923 + }
1.924 }
1.925 %}
1.926
1.927 - enc_class load_N_enc (mRegN dst, umemory mem) %{
1.928 + enc_class load_N_enc (mRegN dst, memory mem) %{
1.929 MacroAssembler _masm(&cbuf);
1.930 int dst = $dst$$reg;
1.931 int base = $mem$$base;
1.932 int index = $mem$$index;
1.933 int scale = $mem$$scale;
1.934 int disp = $mem$$disp;
1.935 -
1.936 - relocInfo::relocType disp_reloc = $mem->disp_reloc();
1.937 - assert(disp_reloc == relocInfo::none, "cannot have disp");
1.938 -
1.939 - assert(index == 0, "no index");
1.940 - __ lwu(as_Register(dst), as_Register(base), disp);
1.941 + relocInfo::relocType disp_reloc = $mem->disp_reloc();
1.942 + assert(disp_reloc == relocInfo::none, "cannot have disp");
1.943 +
1.944 + if( index != 0 ) {
1.945 + if (scale == 0) {
1.946 + __ daddu(AT, as_Register(base), as_Register(index));
1.947 + } else {
1.948 + __ dsll(AT, as_Register(index), scale);
1.949 + __ daddu(AT, as_Register(base), AT);
1.950 + }
1.951 + if( Assembler::is_simm16(disp) ) {
1.952 + __ lwu(as_Register(dst), AT, disp);
1.953 + } else {
1.954 + __ set64(T9, disp);
1.955 + __ daddu(AT, AT, T9);
1.956 + __ lwu(as_Register(dst), AT, 0);
1.957 + }
1.958 + } else {
1.959 + if( Assembler::is_simm16(disp) ) {
1.960 + __ lwu(as_Register(dst), as_Register(base), disp);
1.961 + } else {
1.962 + __ set64(T9, disp);
1.963 + __ daddu(AT, as_Register(base), T9);
1.964 + __ lwu(as_Register(dst), AT, 0);
1.965 + }
1.966 + }
1.967 +
1.968 %}
1.969
1.970
1.971 @@ -1920,16 +2638,71 @@
1.972 int index = $mem$$index;
1.973 int scale = $mem$$scale;
1.974 int disp = $mem$$disp;
1.975 -
1.976 - relocInfo::relocType disp_reloc = $mem->disp_reloc();
1.977 - assert(disp_reloc == relocInfo::none, "cannot have disp");
1.978 + relocInfo::relocType disp_reloc = $mem->disp_reloc();
1.979 + assert(disp_reloc == relocInfo::none, "cannot have disp");
1.980
1.981 if( index != 0 ) {
1.982 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.983 - __ gsldx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.984 + if ( UseLoongsonISA ) {
1.985 + if ( Assembler::is_simm(disp, 8) ) {
1.986 + if ( scale != 0 ) {
1.987 + __ dsll(AT, as_Register(index), scale);
1.988 + __ gsldx(as_Register(dst), as_Register(base), AT, disp);
1.989 + } else {
1.990 + __ gsldx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.991 + }
1.992 + } else if ( Assembler::is_simm16(disp) ){
1.993 + if ( scale != 0 ) {
1.994 + __ dsll(AT, as_Register(index), scale);
1.995 + __ daddu(AT, AT, as_Register(base));
1.996 + } else {
1.997 + __ daddu(AT, as_Register(index), as_Register(base));
1.998 + }
1.999 + __ ld(as_Register(dst), AT, disp);
1.1000 + } else {
1.1001 + if ( scale != 0 ) {
1.1002 + __ dsll(AT, as_Register(index), scale);
1.1003 + __ move(T9, disp);
1.1004 + __ daddu(AT, AT, T9);
1.1005 + } else {
1.1006 + __ move(T9, disp);
1.1007 + __ daddu(AT, as_Register(index), T9);
1.1008 + }
1.1009 + __ gsldx(as_Register(dst), as_Register(base), AT, 0);
1.1010 + }
1.1011 + } else { //not use loongson isa
1.1012 + if (scale == 0) {
1.1013 + __ daddu(AT, as_Register(base), as_Register(index));
1.1014 + } else {
1.1015 + __ dsll(AT, as_Register(index), scale);
1.1016 + __ daddu(AT, as_Register(base), AT);
1.1017 + }
1.1018 + if( Assembler::is_simm16(disp) ) {
1.1019 + __ ld(as_Register(dst), AT, disp);
1.1020 + } else {
1.1021 + __ set64(T9, disp);
1.1022 + __ daddu(AT, AT, T9);
1.1023 + __ ld(as_Register(dst), AT, 0);
1.1024 + }
1.1025 + }
1.1026 } else {
1.1027 - __ ld(as_Register(dst), as_Register(base), disp);
1.1028 + if ( UseLoongsonISA ) {
1.1029 + if ( Assembler::is_simm16(disp) ){
1.1030 + __ ld(as_Register(dst), as_Register(base), disp);
1.1031 + } else {
1.1032 + __ set64(T9, disp);
1.1033 + __ gsldx(as_Register(dst), as_Register(base), T9, 0);
1.1034 + }
1.1035 + } else { //not use loongson isa
1.1036 + if( Assembler::is_simm16(disp) ) {
1.1037 + __ ld(as_Register(dst), as_Register(base), disp);
1.1038 + } else {
1.1039 + __ set64(T9, disp);
1.1040 + __ daddu(AT, as_Register(base), T9);
1.1041 + __ ld(as_Register(dst), AT, 0);
1.1042 + }
1.1043 + }
1.1044 }
1.1045 +// if( disp_reloc != relocInfo::none) __ ld(as_Register(dst), as_Register(dst), 0);
1.1046 %}
1.1047
1.1048 enc_class store_P_reg_enc (memory mem, mRegP src) %{
1.1049 @@ -1941,10 +2714,65 @@
1.1050 int disp = $mem$$disp;
1.1051
1.1052 if( index != 0 ) {
1.1053 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.1054 - __ gssdx(as_Register(src), as_Register(base), as_Register(index), disp);
1.1055 + if ( UseLoongsonISA ){
1.1056 + if ( Assembler::is_simm(disp, 8) ) {
1.1057 + if ( scale == 0 ) {
1.1058 + __ gssdx(as_Register(src), as_Register(base), as_Register(index), disp);
1.1059 + } else {
1.1060 + __ dsll(AT, as_Register(index), scale);
1.1061 + __ gssdx(as_Register(src), as_Register(base), AT, disp);
1.1062 + }
1.1063 + } else if ( Assembler::is_simm16(disp) ) {
1.1064 + if ( scale == 0 ) {
1.1065 + __ daddu(AT, as_Register(base), as_Register(index));
1.1066 + } else {
1.1067 + __ dsll(AT, as_Register(index), scale);
1.1068 + __ daddu(AT, as_Register(base), AT);
1.1069 + }
1.1070 + __ sd(as_Register(src), AT, disp);
1.1071 + } else {
1.1072 + if ( scale == 0 ) {
1.1073 + __ move(T9, disp);
1.1074 + __ daddu(AT, as_Register(index), T9);
1.1075 + } else {
1.1076 + __ dsll(AT, as_Register(index), scale);
1.1077 + __ move(T9, disp);
1.1078 + __ daddu(AT, AT, T9);
1.1079 + }
1.1080 + __ gssdx(as_Register(src), as_Register(base), AT, 0);
1.1081 + }
1.1082 + } else { //not use loongson isa
1.1083 + if (scale == 0) {
1.1084 + __ daddu(AT, as_Register(base), as_Register(index));
1.1085 + } else {
1.1086 + __ dsll(AT, as_Register(index), scale);
1.1087 + __ daddu(AT, as_Register(base), AT);
1.1088 + }
1.1089 + if( Assembler::is_simm16(disp) ) {
1.1090 + __ sd(as_Register(src), AT, disp);
1.1091 + } else {
1.1092 + __ move(T9, disp);
1.1093 + __ daddu(AT, AT, T9);
1.1094 + __ sd(as_Register(src), AT, 0);
1.1095 + }
1.1096 + }
1.1097 } else {
1.1098 - __ sd(as_Register(src), as_Register(base), disp);
1.1099 + if ( UseLoongsonISA ) {
1.1100 + if ( Assembler::is_simm16(disp) ) {
1.1101 + __ sd(as_Register(src), as_Register(base), disp);
1.1102 + } else {
1.1103 + __ move(T9, disp);
1.1104 + __ gssdx(as_Register(src), as_Register(base), T9, 0);
1.1105 + }
1.1106 + } else {
1.1107 + if( Assembler::is_simm16(disp) ) {
1.1108 + __ sd(as_Register(src), as_Register(base), disp);
1.1109 + } else {
1.1110 + __ move(T9, disp);
1.1111 + __ daddu(AT, as_Register(base), T9);
1.1112 + __ sd(as_Register(src), AT, 0);
1.1113 + }
1.1114 + }
1.1115 }
1.1116 %}
1.1117
1.1118 @@ -1957,10 +2785,65 @@
1.1119 int disp = $mem$$disp;
1.1120
1.1121 if( index != 0 ) {
1.1122 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.1123 - __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
1.1124 + if ( UseLoongsonISA ){
1.1125 + if ( Assembler::is_simm(disp, 8) ) {
1.1126 + if ( scale == 0 ) {
1.1127 + __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
1.1128 + } else {
1.1129 + __ dsll(AT, as_Register(index), scale);
1.1130 + __ gsswx(as_Register(src), as_Register(base), AT, disp);
1.1131 + }
1.1132 + } else if ( Assembler::is_simm16(disp) ) {
1.1133 + if ( scale == 0 ) {
1.1134 + __ daddu(AT, as_Register(base), as_Register(index));
1.1135 + } else {
1.1136 + __ dsll(AT, as_Register(index), scale);
1.1137 + __ daddu(AT, as_Register(base), AT);
1.1138 + }
1.1139 + __ sw(as_Register(src), AT, disp);
1.1140 + } else {
1.1141 + if ( scale == 0 ) {
1.1142 + __ move(T9, disp);
1.1143 + __ daddu(AT, as_Register(index), T9);
1.1144 + } else {
1.1145 + __ dsll(AT, as_Register(index), scale);
1.1146 + __ move(T9, disp);
1.1147 + __ daddu(AT, AT, T9);
1.1148 + }
1.1149 + __ gsswx(as_Register(src), as_Register(base), AT, 0);
1.1150 + }
1.1151 + } else { //not use loongson isa
1.1152 + if (scale == 0) {
1.1153 + __ daddu(AT, as_Register(base), as_Register(index));
1.1154 + } else {
1.1155 + __ dsll(AT, as_Register(index), scale);
1.1156 + __ daddu(AT, as_Register(base), AT);
1.1157 + }
1.1158 + if( Assembler::is_simm16(disp) ) {
1.1159 + __ sw(as_Register(src), AT, disp);
1.1160 + } else {
1.1161 + __ move(T9, disp);
1.1162 + __ daddu(AT, AT, T9);
1.1163 + __ sw(as_Register(src), AT, 0);
1.1164 + }
1.1165 + }
1.1166 } else {
1.1167 - __ sw(as_Register(src), as_Register(base), disp);
1.1168 + if ( UseLoongsonISA ) {
1.1169 + if ( Assembler::is_simm16(disp) ) {
1.1170 + __ sw(as_Register(src), as_Register(base), disp);
1.1171 + } else {
1.1172 + __ move(T9, disp);
1.1173 + __ gsswx(as_Register(src), as_Register(base), T9, 0);
1.1174 + }
1.1175 + } else {
1.1176 + if( Assembler::is_simm16(disp) ) {
1.1177 + __ sw(as_Register(src), as_Register(base), disp);
1.1178 + } else {
1.1179 + __ move(T9, disp);
1.1180 + __ daddu(AT, as_Register(base), T9);
1.1181 + __ sw(as_Register(src), AT, 0);
1.1182 + }
1.1183 + }
1.1184 }
1.1185 %}
1.1186
1.1187 @@ -1972,29 +2855,303 @@
1.1188 int disp = $mem$$disp;
1.1189
1.1190 if( index != 0 ) {
1.1191 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.1192 - __ gssdx(R0, as_Register(base), as_Register(index), disp);
1.1193 + if (scale == 0) {
1.1194 + if( Assembler::is_simm16(disp) ) {
1.1195 + if (UseLoongsonISA && Assembler::is_simm(disp, 8)) {
1.1196 + __ gssdx(R0, as_Register(base), as_Register(index), disp);
1.1197 + } else {
1.1198 + __ daddu(AT, as_Register(base), as_Register(index));
1.1199 + __ sd(R0, AT, disp);
1.1200 + }
1.1201 + } else {
1.1202 + __ daddu(AT, as_Register(base), as_Register(index));
1.1203 + __ move(T9, disp);
1.1204 + if(UseLoongsonISA) {
1.1205 + __ gssdx(R0, AT, T9, 0);
1.1206 + } else {
1.1207 + __ daddu(AT, AT, T9);
1.1208 + __ sd(R0, AT, 0);
1.1209 + }
1.1210 + }
1.1211 + } else {
1.1212 + __ dsll(AT, as_Register(index), scale);
1.1213 + if( Assembler::is_simm16(disp) ) {
1.1214 + if (UseLoongsonISA && Assembler::is_simm(disp, 8)) {
1.1215 + __ gssdx(R0, as_Register(base), AT, disp);
1.1216 + } else {
1.1217 + __ daddu(AT, as_Register(base), AT);
1.1218 + __ sd(R0, AT, disp);
1.1219 + }
1.1220 + } else {
1.1221 + __ daddu(AT, as_Register(base), AT);
1.1222 + __ move(T9, disp);
1.1223 + if (UseLoongsonISA) {
1.1224 + __ gssdx(R0, AT, T9, 0);
1.1225 + } else {
1.1226 + __ daddu(AT, AT, T9);
1.1227 + __ sd(R0, AT, 0);
1.1228 + }
1.1229 + }
1.1230 + }
1.1231 } else {
1.1232 - __ sd(R0, as_Register(base), disp);
1.1233 + if( Assembler::is_simm16(disp) ) {
1.1234 + __ sd(R0, as_Register(base), disp);
1.1235 + } else {
1.1236 + __ move(T9, disp);
1.1237 + if (UseLoongsonISA) {
1.1238 + __ gssdx(R0, as_Register(base), T9, 0);
1.1239 + } else {
1.1240 + __ daddu(AT, as_Register(base), T9);
1.1241 + __ sd(R0, AT, 0);
1.1242 + }
1.1243 + }
1.1244 }
1.1245 %}
1.1246
1.1247 -
1.1248 - enc_class storeImmN0_enc(memory mem) %{
1.1249 + enc_class store_P_immP_enc (memory mem, immP31 src) %{
1.1250 MacroAssembler _masm(&cbuf);
1.1251 int base = $mem$$base;
1.1252 int index = $mem$$index;
1.1253 int scale = $mem$$scale;
1.1254 int disp = $mem$$disp;
1.1255 -
1.1256 - if(index != 0){
1.1257 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.1258 - __ gsswx(R0, as_Register(base), as_Register(index), disp);
1.1259 + long value = $src$$constant;
1.1260 +
1.1261 + if( index != 0 ) {
1.1262 + if (scale == 0) {
1.1263 + __ daddu(AT, as_Register(base), as_Register(index));
1.1264 + } else {
1.1265 + __ dsll(AT, as_Register(index), scale);
1.1266 + __ daddu(AT, as_Register(base), AT);
1.1267 + }
1.1268 + if( Assembler::is_simm16(disp) ) {
1.1269 + if (value == 0) {
1.1270 + __ sd(R0, AT, disp);
1.1271 + } else {
1.1272 + __ move(T9, value);
1.1273 + __ sd(T9, AT, disp);
1.1274 + }
1.1275 + } else {
1.1276 + if (value == 0) {
1.1277 + __ move(T9, disp);
1.1278 + __ daddu(AT, AT, T9);
1.1279 + __ sd(R0, AT, 0);
1.1280 + } else {
1.1281 + __ move(T9, disp);
1.1282 + __ daddu(AT, AT, T9);
1.1283 + __ move(T9, value);
1.1284 + __ sd(T9, AT, 0);
1.1285 + }
1.1286 + }
1.1287 } else {
1.1288 - __ sw(R0, as_Register(base), disp);
1.1289 + if( Assembler::is_simm16(disp) ) {
1.1290 + if (value == 0) {
1.1291 + __ sd(R0, as_Register(base), disp);
1.1292 + } else {
1.1293 + __ move(AT, value);
1.1294 + __ sd(AT, as_Register(base), disp);
1.1295 + }
1.1296 + } else {
1.1297 + if (value == 0) {
1.1298 + __ move(T9, disp);
1.1299 + __ daddu(AT, as_Register(base), T9);
1.1300 + __ sd(R0, AT, 0);
1.1301 + } else {
1.1302 + __ move(T9, disp);
1.1303 + __ daddu(AT, as_Register(base), T9);
1.1304 + __ move(T9, value);
1.1305 + __ sd(T9, AT, 0);
1.1306 + }
1.1307 + }
1.1308 }
1.1309 + %}
1.1310 +
1.1311 + enc_class storeImmN0_enc(memory mem, ImmN0 src) %{
1.1312 + MacroAssembler _masm(&cbuf);
1.1313 + int base = $mem$$base;
1.1314 + int index = $mem$$index;
1.1315 + int scale = $mem$$scale;
1.1316 + int disp = $mem$$disp;
1.1317 +
1.1318 + if(index!=0){
1.1319 + if (scale == 0) {
1.1320 + __ daddu(AT, as_Register(base), as_Register(index));
1.1321 + } else {
1.1322 + __ dsll(AT, as_Register(index), scale);
1.1323 + __ daddu(AT, as_Register(base), AT);
1.1324 + }
1.1325 +
1.1326 + if( Assembler::is_simm16(disp) ) {
1.1327 + __ sw(R0, AT, disp);
1.1328 + } else {
1.1329 + __ move(T9, disp);
1.1330 + __ daddu(AT, AT, T9);
1.1331 + __ sw(R0, AT, 0);
1.1332 + }
1.1333 + }
1.1334 + else {
1.1335 + if( Assembler::is_simm16(disp) ) {
1.1336 + __ sw(R0, as_Register(base), disp);
1.1337 + } else {
1.1338 + __ move(T9, disp);
1.1339 + __ daddu(AT, as_Register(base), T9);
1.1340 + __ sw(R0, AT, 0);
1.1341 + }
1.1342 + }
1.1343 %}
1.1344
1.1345 + enc_class storeImmN_enc (memory mem, immN src) %{
1.1346 + MacroAssembler _masm(&cbuf);
1.1347 + int base = $mem$$base;
1.1348 + int index = $mem$$index;
1.1349 + int scale = $mem$$scale;
1.1350 + int disp = $mem$$disp;
1.1351 + long * value = (long *)$src$$constant;
1.1352 +
1.1353 + if (value == NULL) {
1.1354 + guarantee(Assembler::is_simm16(disp), "FIXME: disp is not simm16!");
1.1355 + if (index == 0) {
1.1356 + __ sw(R0, as_Register(base), disp);
1.1357 + } else {
1.1358 + if (scale == 0) {
1.1359 + __ daddu(AT, as_Register(base), as_Register(index));
1.1360 + } else {
1.1361 + __ dsll(AT, as_Register(index), scale);
1.1362 + __ daddu(AT, as_Register(base), AT);
1.1363 + }
1.1364 + __ sw(R0, AT, disp);
1.1365 + }
1.1366 +
1.1367 + return;
1.1368 + }
1.1369 +
1.1370 + int oop_index = __ oop_recorder()->find_index((jobject)value);
1.1371 + RelocationHolder rspec = oop_Relocation::spec(oop_index);
1.1372 +
1.1373 + guarantee(scale == 0, "FIXME: scale is not zero !");
1.1374 + guarantee(value != 0, "FIXME: value is zero !");
1.1375 +
1.1376 + if (index != 0) {
1.1377 + if (scale == 0) {
1.1378 + __ daddu(AT, as_Register(base), as_Register(index));
1.1379 + } else {
1.1380 + __ dsll(AT, as_Register(index), scale);
1.1381 + __ daddu(AT, as_Register(base), AT);
1.1382 + }
1.1383 + if( Assembler::is_simm16(disp) ) {
1.1384 + if(rspec.type() != relocInfo::none) {
1.1385 + __ relocate(rspec, Assembler::narrow_oop_operand);
1.1386 + __ patchable_set48(T9, oop_index);
1.1387 + } else {
1.1388 + __ set64(T9, oop_index);
1.1389 + }
1.1390 + __ sw(T9, AT, disp);
1.1391 + } else {
1.1392 + __ move(T9, disp);
1.1393 + __ addu(AT, AT, T9);
1.1394 +
1.1395 + if(rspec.type() != relocInfo::none) {
1.1396 + __ relocate(rspec, Assembler::narrow_oop_operand);
1.1397 + __ patchable_set48(T9, oop_index);
1.1398 + } else {
1.1399 + __ set64(T9, oop_index);
1.1400 + }
1.1401 + __ sw(T9, AT, 0);
1.1402 + }
1.1403 + }
1.1404 + else {
1.1405 + if( Assembler::is_simm16(disp) ) {
1.1406 + if($src->constant_reloc() != relocInfo::none) {
1.1407 + __ relocate(rspec, Assembler::narrow_oop_operand);
1.1408 + __ patchable_set48(T9, oop_index);
1.1409 + } else {
1.1410 + __ set64(T9, oop_index);
1.1411 + }
1.1412 + __ sw(T9, as_Register(base), disp);
1.1413 + } else {
1.1414 + __ move(T9, disp);
1.1415 + __ daddu(AT, as_Register(base), T9);
1.1416 +
1.1417 + if($src->constant_reloc() != relocInfo::none){
1.1418 + __ relocate(rspec, Assembler::narrow_oop_operand);
1.1419 + __ patchable_set48(T9, oop_index);
1.1420 + } else {
1.1421 + __ set64(T9, oop_index);
1.1422 + }
1.1423 + __ sw(T9, AT, 0);
1.1424 + }
1.1425 + }
1.1426 + %}
1.1427 +
1.1428 + enc_class storeImmNKlass_enc (memory mem, immNKlass src) %{
1.1429 + MacroAssembler _masm(&cbuf);
1.1430 +
1.1431 + assert (UseCompressedOops, "should only be used for compressed headers");
1.1432 + assert (__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
1.1433 +
1.1434 + int base = $mem$$base;
1.1435 + int index = $mem$$index;
1.1436 + int scale = $mem$$scale;
1.1437 + int disp = $mem$$disp;
1.1438 + long value = $src$$constant;
1.1439 +
1.1440 + int klass_index = __ oop_recorder()->find_index((Klass*)value);
1.1441 + RelocationHolder rspec = metadata_Relocation::spec(klass_index);
1.1442 + long narrowp = Klass::encode_klass((Klass*)value);
1.1443 +
1.1444 + if(index!=0){
1.1445 + if (scale == 0) {
1.1446 + __ daddu(AT, as_Register(base), as_Register(index));
1.1447 + } else {
1.1448 + __ dsll(AT, as_Register(index), scale);
1.1449 + __ daddu(AT, as_Register(base), AT);
1.1450 + }
1.1451 +
1.1452 + if( Assembler::is_simm16(disp) ) {
1.1453 + if(rspec.type() != relocInfo::none){
1.1454 + __ relocate(rspec, Assembler::narrow_oop_operand);
1.1455 + __ patchable_set48(T9, narrowp);
1.1456 + } else {
1.1457 + __ set64(T9, narrowp);
1.1458 + }
1.1459 + __ sw(T9, AT, disp);
1.1460 + } else {
1.1461 + __ move(T9, disp);
1.1462 + __ daddu(AT, AT, T9);
1.1463 +
1.1464 + if(rspec.type() != relocInfo::none){
1.1465 + __ relocate(rspec, Assembler::narrow_oop_operand);
1.1466 + __ patchable_set48(T9, narrowp);
1.1467 + } else {
1.1468 + __ set64(T9, narrowp);
1.1469 + }
1.1470 +
1.1471 + __ sw(T9, AT, 0);
1.1472 + }
1.1473 + } else {
1.1474 + if( Assembler::is_simm16(disp) ) {
1.1475 + if(rspec.type() != relocInfo::none){
1.1476 + __ relocate(rspec, Assembler::narrow_oop_operand);
1.1477 + __ patchable_set48(T9, narrowp);
1.1478 + }
1.1479 + else {
1.1480 + __ set64(T9, narrowp);
1.1481 + }
1.1482 + __ sw(T9, as_Register(base), disp);
1.1483 + } else {
1.1484 + __ move(T9, disp);
1.1485 + __ daddu(AT, as_Register(base), T9);
1.1486 +
1.1487 + if(rspec.type() != relocInfo::none){
1.1488 + __ relocate(rspec, Assembler::narrow_oop_operand);
1.1489 + __ patchable_set48(T9, narrowp);
1.1490 + } else {
1.1491 + __ set64(T9, narrowp);
1.1492 + }
1.1493 + __ sw(T9, AT, 0);
1.1494 + }
1.1495 + }
1.1496 + %}
1.1497 +
1.1498 enc_class load_L_enc (mRegL dst, memory mem) %{
1.1499 MacroAssembler _masm(&cbuf);
1.1500 int base = $mem$$base;
1.1501 @@ -2003,11 +3160,31 @@
1.1502 int disp = $mem$$disp;
1.1503 Register dst_reg = as_Register($dst$$reg);
1.1504
1.1505 + // For implicit null check
1.1506 + __ lb(AT, as_Register(base), 0);
1.1507 +
1.1508 if( index != 0 ) {
1.1509 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.1510 - __ gsldx(dst_reg, as_Register(base), as_Register(index), disp);
1.1511 + if (scale == 0) {
1.1512 + __ daddu(AT, as_Register(base), as_Register(index));
1.1513 + } else {
1.1514 + __ dsll(AT, as_Register(index), scale);
1.1515 + __ daddu(AT, as_Register(base), AT);
1.1516 + }
1.1517 + if( Assembler::is_simm16(disp) ) {
1.1518 + __ ld(dst_reg, AT, disp);
1.1519 + } else {
1.1520 + __ move(T9, disp);
1.1521 + __ daddu(AT, AT, T9);
1.1522 + __ ld(dst_reg, AT, 0);
1.1523 + }
1.1524 } else {
1.1525 - __ ld(dst_reg, as_Register(base), disp);
1.1526 + if( Assembler::is_simm16(disp) ) {
1.1527 + __ ld(dst_reg, as_Register(base), disp);
1.1528 + } else {
1.1529 + __ move(T9, disp);
1.1530 + __ daddu(AT, as_Register(base), T9);
1.1531 + __ ld(dst_reg, AT, 0);
1.1532 + }
1.1533 }
1.1534 %}
1.1535
1.1536 @@ -2020,14 +3197,31 @@
1.1537 Register src_reg = as_Register($src$$reg);
1.1538
1.1539 if( index != 0 ) {
1.1540 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.1541 - __ gssdx(src_reg, as_Register(base), as_Register(index), disp);
1.1542 + if (scale == 0) {
1.1543 + __ daddu(AT, as_Register(base), as_Register(index));
1.1544 + } else {
1.1545 + __ dsll(AT, as_Register(index), scale);
1.1546 + __ daddu(AT, as_Register(base), AT);
1.1547 + }
1.1548 + if( Assembler::is_simm16(disp) ) {
1.1549 + __ sd(src_reg, AT, disp);
1.1550 + } else {
1.1551 + __ move(T9, disp);
1.1552 + __ daddu(AT, AT, T9);
1.1553 + __ sd(src_reg, AT, 0);
1.1554 + }
1.1555 } else {
1.1556 - __ sd(src_reg, as_Register(base), disp);
1.1557 + if( Assembler::is_simm16(disp) ) {
1.1558 + __ sd(src_reg, as_Register(base), disp);
1.1559 + } else {
1.1560 + __ move(T9, disp);
1.1561 + __ daddu(AT, as_Register(base), T9);
1.1562 + __ sd(src_reg, AT, 0);
1.1563 + }
1.1564 }
1.1565 %}
1.1566
1.1567 - enc_class store_L_immL0_enc (memory mem) %{
1.1568 + enc_class store_L_immL0_enc (memory mem, immL0 src) %{
1.1569 MacroAssembler _masm(&cbuf);
1.1570 int base = $mem$$base;
1.1571 int index = $mem$$index;
1.1572 @@ -2035,10 +3229,68 @@
1.1573 int disp = $mem$$disp;
1.1574
1.1575 if( index != 0 ) {
1.1576 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.1577 - __ gssdx(R0, as_Register(base), as_Register(index), disp);
1.1578 + // For implicit null check
1.1579 + __ lb(AT, as_Register(base), 0);
1.1580 +
1.1581 + if (scale == 0) {
1.1582 + __ daddu(AT, as_Register(base), as_Register(index));
1.1583 + } else {
1.1584 + __ dsll(AT, as_Register(index), scale);
1.1585 + __ daddu(AT, as_Register(base), AT);
1.1586 + }
1.1587 + if( Assembler::is_simm16(disp) ) {
1.1588 + __ sd(R0, AT, disp);
1.1589 + } else {
1.1590 + __ move(T9, disp);
1.1591 + __ addu(AT, AT, T9);
1.1592 + __ sd(R0, AT, 0);
1.1593 + }
1.1594 } else {
1.1595 - __ sd(R0, as_Register(base), disp);
1.1596 + if( Assembler::is_simm16(disp) ) {
1.1597 + __ sd(R0, as_Register(base), disp);
1.1598 + } else {
1.1599 + __ move(T9, disp);
1.1600 + __ addu(AT, as_Register(base), T9);
1.1601 + __ sd(R0, AT, 0);
1.1602 + }
1.1603 + }
1.1604 + %}
1.1605 +
1.1606 + enc_class store_L_immL_enc (memory mem, immL src) %{
1.1607 + MacroAssembler _masm(&cbuf);
1.1608 + int base = $mem$$base;
1.1609 + int index = $mem$$index;
1.1610 + int scale = $mem$$scale;
1.1611 + int disp = $mem$$disp;
1.1612 + long imm = $src$$constant;
1.1613 +
1.1614 + if( index != 0 ) {
1.1615 + if (scale == 0) {
1.1616 + __ daddu(AT, as_Register(base), as_Register(index));
1.1617 + } else {
1.1618 + __ dsll(AT, as_Register(index), scale);
1.1619 + __ daddu(AT, as_Register(base), AT);
1.1620 + }
1.1621 + if( Assembler::is_simm16(disp) ) {
1.1622 + __ set64(T9, imm);
1.1623 + __ sd(T9, AT, disp);
1.1624 + } else {
1.1625 + __ move(T9, disp);
1.1626 + __ addu(AT, AT, T9);
1.1627 + __ set64(T9, imm);
1.1628 + __ sd(T9, AT, 0);
1.1629 + }
1.1630 + } else {
1.1631 + if( Assembler::is_simm16(disp) ) {
1.1632 + __ move(AT, as_Register(base));
1.1633 + __ set64(T9, imm);
1.1634 + __ sd(T9, AT, disp);
1.1635 + } else {
1.1636 + __ move(T9, disp);
1.1637 + __ addu(AT, as_Register(base), T9);
1.1638 + __ set64(T9, imm);
1.1639 + __ sd(T9, AT, 0);
1.1640 + }
1.1641 }
1.1642 %}
1.1643
1.1644 @@ -2051,10 +3303,50 @@
1.1645 FloatRegister dst = $dst$$FloatRegister;
1.1646
1.1647 if( index != 0 ) {
1.1648 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.1649 - __ gslwxc1(dst, as_Register(base), as_Register(index), disp);
1.1650 + if( Assembler::is_simm16(disp) ) {
1.1651 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.1652 + if (scale == 0) {
1.1653 + __ gslwxc1(dst, as_Register(base), as_Register(index), disp);
1.1654 + } else {
1.1655 + __ dsll(AT, as_Register(index), scale);
1.1656 + __ gslwxc1(dst, as_Register(base), AT, disp);
1.1657 + }
1.1658 + } else {
1.1659 + if (scale == 0) {
1.1660 + __ daddu(AT, as_Register(base), as_Register(index));
1.1661 + } else {
1.1662 + __ dsll(AT, as_Register(index), scale);
1.1663 + __ daddu(AT, as_Register(base), AT);
1.1664 + }
1.1665 + __ lwc1(dst, AT, disp);
1.1666 + }
1.1667 + } else {
1.1668 + if (scale == 0) {
1.1669 + __ daddu(AT, as_Register(base), as_Register(index));
1.1670 + } else {
1.1671 + __ dsll(AT, as_Register(index), scale);
1.1672 + __ daddu(AT, as_Register(base), AT);
1.1673 + }
1.1674 + __ move(T9, disp);
1.1675 + if( UseLoongsonISA ) {
1.1676 + __ gslwxc1(dst, AT, T9, 0);
1.1677 + } else {
1.1678 + __ daddu(AT, AT, T9);
1.1679 + __ lwc1(dst, AT, 0);
1.1680 + }
1.1681 + }
1.1682 } else {
1.1683 - __ lwc1(dst, as_Register(base), disp);
1.1684 + if( Assembler::is_simm16(disp) ) {
1.1685 + __ lwc1(dst, as_Register(base), disp);
1.1686 + } else {
1.1687 + __ move(T9, disp);
1.1688 + if( UseLoongsonISA ) {
1.1689 + __ gslwxc1(dst, as_Register(base), T9, 0);
1.1690 + } else {
1.1691 + __ daddu(AT, as_Register(base), T9);
1.1692 + __ lwc1(dst, AT, 0);
1.1693 + }
1.1694 + }
1.1695 }
1.1696 %}
1.1697
1.1698 @@ -2067,10 +3359,50 @@
1.1699 FloatRegister src = $src$$FloatRegister;
1.1700
1.1701 if( index != 0 ) {
1.1702 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.1703 - __ gsswxc1(src, as_Register(base), as_Register(index), disp);
1.1704 + if( Assembler::is_simm16(disp) ) {
1.1705 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.1706 + if (scale == 0) {
1.1707 + __ gsswxc1(src, as_Register(base), as_Register(index), disp);
1.1708 + } else {
1.1709 + __ dsll(AT, as_Register(index), scale);
1.1710 + __ gsswxc1(src, as_Register(base), AT, disp);
1.1711 + }
1.1712 + } else {
1.1713 + if (scale == 0) {
1.1714 + __ daddu(AT, as_Register(base), as_Register(index));
1.1715 + } else {
1.1716 + __ dsll(AT, as_Register(index), scale);
1.1717 + __ daddu(AT, as_Register(base), AT);
1.1718 + }
1.1719 + __ swc1(src, AT, disp);
1.1720 + }
1.1721 + } else {
1.1722 + if (scale == 0) {
1.1723 + __ daddu(AT, as_Register(base), as_Register(index));
1.1724 + } else {
1.1725 + __ dsll(AT, as_Register(index), scale);
1.1726 + __ daddu(AT, as_Register(base), AT);
1.1727 + }
1.1728 + __ move(T9, disp);
1.1729 + if( UseLoongsonISA ) {
1.1730 + __ gsswxc1(src, AT, T9, 0);
1.1731 + } else {
1.1732 + __ daddu(AT, AT, T9);
1.1733 + __ swc1(src, AT, 0);
1.1734 + }
1.1735 + }
1.1736 } else {
1.1737 - __ swc1(src, as_Register(base), disp);
1.1738 + if( Assembler::is_simm16(disp) ) {
1.1739 + __ swc1(src, as_Register(base), disp);
1.1740 + } else {
1.1741 + __ move(T9, disp);
1.1742 + if( UseLoongsonISA ) {
1.1743 + __ gslwxc1(src, as_Register(base), T9, 0);
1.1744 + } else {
1.1745 + __ daddu(AT, as_Register(base), T9);
1.1746 + __ swc1(src, AT, 0);
1.1747 + }
1.1748 + }
1.1749 }
1.1750 %}
1.1751
1.1752 @@ -2083,26 +3415,106 @@
1.1753 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
1.1754
1.1755 if( index != 0 ) {
1.1756 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.1757 - __ gsldxc1(dst_reg, as_Register(base), as_Register(index), disp);
1.1758 + if( Assembler::is_simm16(disp) ) {
1.1759 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.1760 + if (scale == 0) {
1.1761 + __ gsldxc1(dst_reg, as_Register(base), as_Register(index), disp);
1.1762 + } else {
1.1763 + __ dsll(AT, as_Register(index), scale);
1.1764 + __ gsldxc1(dst_reg, as_Register(base), AT, disp);
1.1765 + }
1.1766 + } else {
1.1767 + if (scale == 0) {
1.1768 + __ daddu(AT, as_Register(base), as_Register(index));
1.1769 + } else {
1.1770 + __ dsll(AT, as_Register(index), scale);
1.1771 + __ daddu(AT, as_Register(base), AT);
1.1772 + }
1.1773 + __ ldc1(dst_reg, AT, disp);
1.1774 + }
1.1775 + } else {
1.1776 + if (scale == 0) {
1.1777 + __ daddu(AT, as_Register(base), as_Register(index));
1.1778 + } else {
1.1779 + __ dsll(AT, as_Register(index), scale);
1.1780 + __ daddu(AT, as_Register(base), AT);
1.1781 + }
1.1782 + __ move(T9, disp);
1.1783 + if( UseLoongsonISA ) {
1.1784 + __ gsldxc1(dst_reg, AT, T9, 0);
1.1785 + } else {
1.1786 + __ addu(AT, AT, T9);
1.1787 + __ ldc1(dst_reg, AT, 0);
1.1788 + }
1.1789 + }
1.1790 } else {
1.1791 - __ ldc1(dst_reg, as_Register(base), disp);
1.1792 + if( Assembler::is_simm16(disp) ) {
1.1793 + __ ldc1(dst_reg, as_Register(base), disp);
1.1794 + } else {
1.1795 + __ move(T9, disp);
1.1796 + if( UseLoongsonISA ) {
1.1797 + __ gsldxc1(dst_reg, as_Register(base), T9, 0);
1.1798 + } else {
1.1799 + __ addu(AT, as_Register(base), T9);
1.1800 + __ ldc1(dst_reg, AT, 0);
1.1801 + }
1.1802 + }
1.1803 }
1.1804 %}
1.1805
1.1806 enc_class store_D_reg_enc (memory mem, regD src) %{
1.1807 MacroAssembler _masm(&cbuf);
1.1808 - int base = $mem$$base;
1.1809 + int base = $mem$$base;
1.1810 int index = $mem$$index;
1.1811 int scale = $mem$$scale;
1.1812 - int disp = $mem$$disp;
1.1813 + int disp = $mem$$disp;
1.1814 FloatRegister src_reg = as_FloatRegister($src$$reg);
1.1815
1.1816 if( index != 0 ) {
1.1817 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.1818 - __ gssdxc1(src_reg, as_Register(base), as_Register(index), disp);
1.1819 + if( Assembler::is_simm16(disp) ) {
1.1820 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.1821 + if (scale == 0) {
1.1822 + __ gssdxc1(src_reg, as_Register(base), as_Register(index), disp);
1.1823 + } else {
1.1824 + __ dsll(AT, as_Register(index), scale);
1.1825 + __ gssdxc1(src_reg, as_Register(base), AT, disp);
1.1826 + }
1.1827 + } else {
1.1828 + if (scale == 0) {
1.1829 + __ daddu(AT, as_Register(base), as_Register(index));
1.1830 + } else {
1.1831 + __ dsll(AT, as_Register(index), scale);
1.1832 + __ daddu(AT, as_Register(base), AT);
1.1833 + }
1.1834 + __ sdc1(src_reg, AT, disp);
1.1835 + }
1.1836 + } else {
1.1837 + if (scale == 0) {
1.1838 + __ daddu(AT, as_Register(base), as_Register(index));
1.1839 + } else {
1.1840 + __ dsll(AT, as_Register(index), scale);
1.1841 + __ daddu(AT, as_Register(base), AT);
1.1842 + }
1.1843 + __ move(T9, disp);
1.1844 + if( UseLoongsonISA ) {
1.1845 + __ gssdxc1(src_reg, AT, T9, 0);
1.1846 + } else {
1.1847 + __ addu(AT, AT, T9);
1.1848 + __ sdc1(src_reg, AT, 0);
1.1849 + }
1.1850 + }
1.1851 } else {
1.1852 - __ sdc1(src_reg, as_Register(base), disp);
1.1853 + if( Assembler::is_simm16(disp) ) {
1.1854 + __ sdc1(src_reg, as_Register(base), disp);
1.1855 + } else {
1.1856 + __ move(T9, disp);
1.1857 + if( UseLoongsonISA ) {
1.1858 + __ gssdxc1(src_reg, as_Register(base), T9, 0);
1.1859 + } else {
1.1860 + __ addu(AT, as_Register(base), T9);
1.1861 + __ sdc1(src_reg, AT, 0);
1.1862 + }
1.1863 + }
1.1864 }
1.1865 %}
1.1866
1.1867 @@ -2663,6 +4075,17 @@
1.1868 interface(CONST_INTER);
1.1869 %}
1.1870
1.1871 +operand immP31()
1.1872 +%{
1.1873 + predicate(n->as_Type()->type()->reloc() == relocInfo::none
1.1874 + && (n->get_ptr() >> 31) == 0);
1.1875 + match(ConP);
1.1876 +
1.1877 + op_cost(5);
1.1878 + format %{ %}
1.1879 + interface(CONST_INTER);
1.1880 +%}
1.1881 +
1.1882 // NULL Pointer Immediate
1.1883 operand immP0() %{
1.1884 predicate( n->get_ptr() == 0 );
1.1885 @@ -3933,13 +5356,223 @@
1.1886 %}
1.1887
1.1888 //----------Memory Operands----------------------------------------------------
1.1889 -operand baseOffset16(mRegP reg, immL16 off)
1.1890 +// Indirect Memory Operand
1.1891 +operand indirect(mRegP reg) %{
1.1892 + constraint(ALLOC_IN_RC(p_reg));
1.1893 + match(reg);
1.1894 +
1.1895 + format %{ "[$reg] @ indirect" %}
1.1896 + interface(MEMORY_INTER) %{
1.1897 + base($reg);
1.1898 + index(0x0); /* NO_INDEX */
1.1899 + scale(0x0);
1.1900 + disp(0x0);
1.1901 + %}
1.1902 +%}
1.1903 +
1.1904 +// Indirect Memory Plus Short Offset Operand
1.1905 +operand indOffset8(mRegP reg, immL8 off)
1.1906 %{
1.1907 constraint(ALLOC_IN_RC(p_reg));
1.1908 match(AddP reg off);
1.1909
1.1910 + op_cost(10);
1.1911 + format %{ "[$reg + $off (8-bit)] @ indOffset8" %}
1.1912 + interface(MEMORY_INTER) %{
1.1913 + base($reg);
1.1914 + index(0x0); /* NO_INDEX */
1.1915 + scale(0x0);
1.1916 + disp($off);
1.1917 + %}
1.1918 +%}
1.1919 +
1.1920 +// Indirect Memory Times Scale Plus Index Register
1.1921 +operand indIndexScale(mRegP reg, mRegL lreg, immI2 scale)
1.1922 +%{
1.1923 + constraint(ALLOC_IN_RC(p_reg));
1.1924 + match(AddP reg (LShiftL lreg scale));
1.1925 +
1.1926 + op_cost(10);
1.1927 + format %{"[$reg + $lreg << $scale] @ indIndexScale" %}
1.1928 + interface(MEMORY_INTER) %{
1.1929 + base($reg);
1.1930 + index($lreg);
1.1931 + scale($scale);
1.1932 + disp(0x0);
1.1933 + %}
1.1934 +%}
1.1935 +
1.1936 +
1.1937 +// [base + index + offset]
1.1938 +operand baseIndexOffset8(mRegP base, mRegL index, immL8 off)
1.1939 +%{
1.1940 + constraint(ALLOC_IN_RC(p_reg));
1.1941 op_cost(5);
1.1942 - format %{ "[$reg + $off (16-bit)] @ baseOffset16" %}
1.1943 + match(AddP (AddP base index) off);
1.1944 +
1.1945 + format %{ "[$base + $index + $off (8-bit)] @ baseIndexOffset8" %}
1.1946 + interface(MEMORY_INTER) %{
1.1947 + base($base);
1.1948 + index($index);
1.1949 + scale(0x0);
1.1950 + disp($off);
1.1951 + %}
1.1952 +%}
1.1953 +
1.1954 +// [base + index + offset]
1.1955 +operand baseIndexOffset8_convI2L(mRegP base, mRegI index, immL8 off)
1.1956 +%{
1.1957 + constraint(ALLOC_IN_RC(p_reg));
1.1958 + op_cost(5);
1.1959 + match(AddP (AddP base (ConvI2L index)) off);
1.1960 +
1.1961 + format %{ "[$base + $index + $off (8-bit)] @ baseIndexOffset8_convI2L" %}
1.1962 + interface(MEMORY_INTER) %{
1.1963 + base($base);
1.1964 + index($index);
1.1965 + scale(0x0);
1.1966 + disp($off);
1.1967 + %}
1.1968 +%}
1.1969 +
1.1970 +// Indirect Memory Times Scale Plus Index Register Plus Offset Operand
1.1971 +operand indIndexScaleOffset8(mRegP reg, immL8 off, mRegL lreg, immI2 scale)
1.1972 +%{
1.1973 + constraint(ALLOC_IN_RC(p_reg));
1.1974 + match(AddP (AddP reg (LShiftL lreg scale)) off);
1.1975 +
1.1976 + op_cost(10);
1.1977 + format %{"[$reg + $off + $lreg << $scale] @ indIndexScaleOffset8" %}
1.1978 + interface(MEMORY_INTER) %{
1.1979 + base($reg);
1.1980 + index($lreg);
1.1981 + scale($scale);
1.1982 + disp($off);
1.1983 + %}
1.1984 +%}
1.1985 +
1.1986 +operand indIndexScaleOffset8_convI2L(mRegP reg, immL8 off, mRegI ireg, immI2 scale)
1.1987 +%{
1.1988 + constraint(ALLOC_IN_RC(p_reg));
1.1989 + match(AddP (AddP reg (LShiftL (ConvI2L ireg) scale)) off);
1.1990 +
1.1991 + op_cost(10);
1.1992 + format %{"[$reg + $off + $ireg << $scale] @ indIndexScaleOffset8_convI2L" %}
1.1993 + interface(MEMORY_INTER) %{
1.1994 + base($reg);
1.1995 + index($ireg);
1.1996 + scale($scale);
1.1997 + disp($off);
1.1998 + %}
1.1999 +%}
1.2000 +
1.2001 +// [base + index<<scale + offset]
1.2002 +operand basePosIndexScaleOffset8(mRegP base, mRegI index, immL8 off, immI_0_31 scale)
1.2003 +%{
1.2004 + constraint(ALLOC_IN_RC(p_reg));
1.2005 + //predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
1.2006 + op_cost(10);
1.2007 + match(AddP (AddP base (LShiftL (ConvI2L index) scale)) off);
1.2008 +
1.2009 + format %{ "[$base + $index << $scale + $off (8-bit)] @ basePosIndexScaleOffset8" %}
1.2010 + interface(MEMORY_INTER) %{
1.2011 + base($base);
1.2012 + index($index);
1.2013 + scale($scale);
1.2014 + disp($off);
1.2015 + %}
1.2016 +%}
1.2017 +
1.2018 +// Indirect Memory Times Scale Plus Index Register Plus Offset Operand
1.2019 +operand indIndexScaleOffsetNarrow(mRegN reg, immL8 off, mRegL lreg, immI2 scale)
1.2020 +%{
1.2021 + predicate(Universe::narrow_oop_shift() == 0);
1.2022 + constraint(ALLOC_IN_RC(p_reg));
1.2023 + match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
1.2024 +
1.2025 + op_cost(10);
1.2026 + format %{"[$reg + $off + $lreg << $scale] @ indIndexScaleOffsetNarrow" %}
1.2027 + interface(MEMORY_INTER) %{
1.2028 + base($reg);
1.2029 + index($lreg);
1.2030 + scale($scale);
1.2031 + disp($off);
1.2032 + %}
1.2033 +%}
1.2034 +
1.2035 +// [base + index<<scale + offset] for compressd Oops
1.2036 +operand indPosIndexI2LScaleOffset8Narrow(mRegN base, mRegI index, immL8 off, immI_0_31 scale)
1.2037 +%{
1.2038 + constraint(ALLOC_IN_RC(p_reg));
1.2039 + //predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
1.2040 + predicate(Universe::narrow_oop_shift() == 0);
1.2041 + op_cost(10);
1.2042 + match(AddP (AddP (DecodeN base) (LShiftL (ConvI2L index) scale)) off);
1.2043 +
1.2044 + format %{ "[$base + $index << $scale + $off (8-bit)] @ indPosIndexI2LScaleOffset8Narrow" %}
1.2045 + interface(MEMORY_INTER) %{
1.2046 + base($base);
1.2047 + index($index);
1.2048 + scale($scale);
1.2049 + disp($off);
1.2050 + %}
1.2051 +%}
1.2052 +
1.2053 +//FIXME: I think it's better to limit the immI to be 16-bit at most!
1.2054 +// Indirect Memory Plus Long Offset Operand
1.2055 +operand indOffset32(mRegP reg, immL32 off) %{
1.2056 + constraint(ALLOC_IN_RC(p_reg));
1.2057 + op_cost(20);
1.2058 + match(AddP reg off);
1.2059 +
1.2060 + format %{ "[$reg + $off (32-bit)] @ indOffset32" %}
1.2061 + interface(MEMORY_INTER) %{
1.2062 + base($reg);
1.2063 + index(0x0); /* NO_INDEX */
1.2064 + scale(0x0);
1.2065 + disp($off);
1.2066 + %}
1.2067 +%}
1.2068 +
1.2069 +// Indirect Memory Plus Index Register
1.2070 +operand indIndex(mRegP addr, mRegL index) %{
1.2071 + constraint(ALLOC_IN_RC(p_reg));
1.2072 + match(AddP addr index);
1.2073 +
1.2074 + op_cost(20);
1.2075 + format %{"[$addr + $index] @ indIndex" %}
1.2076 + interface(MEMORY_INTER) %{
1.2077 + base($addr);
1.2078 + index($index);
1.2079 + scale(0x0);
1.2080 + disp(0x0);
1.2081 + %}
1.2082 +%}
1.2083 +
1.2084 +operand indirectNarrowKlass(mRegN reg)
1.2085 +%{
1.2086 + predicate(Universe::narrow_klass_shift() == 0);
1.2087 + constraint(ALLOC_IN_RC(p_reg));
1.2088 + op_cost(10);
1.2089 + match(DecodeNKlass reg);
1.2090 +
1.2091 + format %{ "[$reg] @ indirectNarrowKlass" %}
1.2092 + interface(MEMORY_INTER) %{
1.2093 + base($reg);
1.2094 + index(0x0);
1.2095 + scale(0x0);
1.2096 + disp(0x0);
1.2097 + %}
1.2098 +%}
1.2099 +
1.2100 +operand indOffset8NarrowKlass(mRegN reg, immL8 off)
1.2101 +%{
1.2102 + predicate(Universe::narrow_klass_shift() == 0);
1.2103 + constraint(ALLOC_IN_RC(p_reg));
1.2104 + op_cost(10);
1.2105 + match(AddP (DecodeNKlass reg) off);
1.2106 +
1.2107 + format %{ "[$reg + $off (8-bit)] @ indOffset8NarrowKlass" %}
1.2108 interface(MEMORY_INTER) %{
1.2109 base($reg);
1.2110 index(0x0);
1.2111 @@ -3948,59 +5581,63 @@
1.2112 %}
1.2113 %}
1.2114
1.2115 -operand gsBaseIndexOffset8(mRegP base, mRegL index, immL8 off)
1.2116 -%{
1.2117 - predicate(UseLoongsonISA);
1.2118 +operand indOffset32NarrowKlass(mRegN reg, immL32 off)
1.2119 +%{
1.2120 + predicate(Universe::narrow_klass_shift() == 0);
1.2121 constraint(ALLOC_IN_RC(p_reg));
1.2122 - match(AddP (AddP base index) off);
1.2123 -
1.2124 - op_cost(5);
1.2125 - format %{ "[$base + $index + $off (8-bit)] @ gsBaseIndexOffset8" %}
1.2126 + op_cost(10);
1.2127 + match(AddP (DecodeNKlass reg) off);
1.2128 +
1.2129 + format %{ "[$reg + $off (32-bit)] @ indOffset32NarrowKlass" %}
1.2130 interface(MEMORY_INTER) %{
1.2131 - base($base);
1.2132 - index($index);
1.2133 + base($reg);
1.2134 + index(0x0);
1.2135 scale(0x0);
1.2136 disp($off);
1.2137 %}
1.2138 %}
1.2139
1.2140 -operand gsBaseIndexI2LOffset8(mRegP base, mRegI index, immL8 off)
1.2141 -%{
1.2142 - predicate(UseLoongsonISA);
1.2143 +operand indIndexOffsetNarrowKlass(mRegN reg, mRegL lreg, immL32 off)
1.2144 +%{
1.2145 + predicate(Universe::narrow_klass_shift() == 0);
1.2146 constraint(ALLOC_IN_RC(p_reg));
1.2147 - match(AddP (AddP base (ConvI2L index)) off);
1.2148 -
1.2149 - op_cost(5);
1.2150 - format %{ "[$base + $index + $off (8-bit)] @ gsBaseIndexI2LOffset8" %}
1.2151 + match(AddP (AddP (DecodeNKlass reg) lreg) off);
1.2152 +
1.2153 + op_cost(10);
1.2154 + format %{"[$reg + $off + $lreg] @ indIndexOffsetNarrowKlass" %}
1.2155 interface(MEMORY_INTER) %{
1.2156 - base($base);
1.2157 - index($index);
1.2158 + base($reg);
1.2159 + index($lreg);
1.2160 scale(0x0);
1.2161 disp($off);
1.2162 %}
1.2163 %}
1.2164
1.2165 -operand gsBaseIndexOffset0(mRegP addr, mRegL index) %{
1.2166 - predicate(UseLoongsonISA);
1.2167 +operand indIndexNarrowKlass(mRegN reg, mRegL lreg)
1.2168 +%{
1.2169 + predicate(Universe::narrow_klass_shift() == 0);
1.2170 constraint(ALLOC_IN_RC(p_reg));
1.2171 - match(AddP addr index);
1.2172 + match(AddP (DecodeNKlass reg) lreg);
1.2173
1.2174 op_cost(10);
1.2175 - format %{"[$addr + $index] @ gsBaseIndexOffset0" %}
1.2176 + format %{"[$reg + $lreg] @ indIndexNarrowKlass" %}
1.2177 interface(MEMORY_INTER) %{
1.2178 - base($addr);
1.2179 - index($index);
1.2180 + base($reg);
1.2181 + index($lreg);
1.2182 scale(0x0);
1.2183 disp(0x0);
1.2184 %}
1.2185 %}
1.2186
1.2187 -operand baseOffset0(mRegP reg) %{
1.2188 +// Indirect Memory Operand
1.2189 +operand indirectNarrow(mRegN reg)
1.2190 +%{
1.2191 + predicate(Universe::narrow_oop_shift() == 0);
1.2192 constraint(ALLOC_IN_RC(p_reg));
1.2193 op_cost(10);
1.2194 - match(reg);
1.2195 -
1.2196 - format %{ "[$reg] @ baseOffset0" %}
1.2197 + match(DecodeN reg);
1.2198 +
1.2199 + format %{ "[$reg] @ indirectNarrow" %}
1.2200 interface(MEMORY_INTER) %{
1.2201 base($reg);
1.2202 index(0x0);
1.2203 @@ -4009,14 +5646,15 @@
1.2204 %}
1.2205 %}
1.2206
1.2207 -operand baseOffset16Narrow(mRegN reg, immL16 off)
1.2208 -%{
1.2209 - predicate(Universe::narrow_oop_base() == 0 && Universe::narrow_oop_shift() == 0);
1.2210 +// Indirect Memory Plus Short Offset Operand
1.2211 +operand indOffset8Narrow(mRegN reg, immL8 off)
1.2212 +%{
1.2213 + predicate(Universe::narrow_oop_shift() == 0);
1.2214 constraint(ALLOC_IN_RC(p_reg));
1.2215 + op_cost(10);
1.2216 match(AddP (DecodeN reg) off);
1.2217
1.2218 - op_cost(5);
1.2219 - format %{ "[$reg + $off (16-bit)] @ baseOffset16Narrow" %}
1.2220 + format %{ "[$reg + $off (8-bit)] @ indOffset8Narrow" %}
1.2221 interface(MEMORY_INTER) %{
1.2222 base($reg);
1.2223 index(0x0);
1.2224 @@ -4025,14 +5663,15 @@
1.2225 %}
1.2226 %}
1.2227
1.2228 -operand gsBaseIndexOffset8Narrow(mRegN reg, mRegL lreg, immL8 off)
1.2229 -%{
1.2230 - predicate(UseLoongsonISA && Universe::narrow_oop_base() == 0 && Universe::narrow_oop_shift() == 0);
1.2231 +// Indirect Memory Plus Index Register Plus Offset Operand
1.2232 +operand indIndexOffset8Narrow(mRegN reg, mRegL lreg, immL8 off)
1.2233 +%{
1.2234 + predicate(Universe::narrow_oop_shift() == 0);
1.2235 constraint(ALLOC_IN_RC(p_reg));
1.2236 match(AddP (AddP (DecodeN reg) lreg) off);
1.2237
1.2238 - op_cost(5);
1.2239 - format %{"[$reg + $off + $lreg] @ gsBaseIndexOffset8Narrow" %}
1.2240 + op_cost(10);
1.2241 + format %{"[$reg + $off + $lreg] @ indIndexOffset8Narrow" %}
1.2242 interface(MEMORY_INTER) %{
1.2243 base($reg);
1.2244 index($lreg);
1.2245 @@ -4041,14 +5680,29 @@
1.2246 %}
1.2247 %}
1.2248
1.2249 -operand baseOffset0Narrow(mRegN reg)
1.2250 -%{
1.2251 - predicate(Universe::narrow_oop_base() == 0 && Universe::narrow_oop_shift() == 0);
1.2252 +//----------Load Long Memory Operands------------------------------------------
1.2253 +// The load-long idiom will use it's address expression again after loading
1.2254 +// the first word of the long. If the load-long destination overlaps with
1.2255 +// registers used in the addressing expression, the 2nd half will be loaded
1.2256 +// from a clobbered address. Fix this by requiring that load-long use
1.2257 +// address registers that do not overlap with the load-long target.
1.2258 +
1.2259 +// load-long support
1.2260 +operand load_long_RegP() %{
1.2261 constraint(ALLOC_IN_RC(p_reg));
1.2262 - match(DecodeN reg);
1.2263 -
1.2264 - op_cost(10);
1.2265 - format %{ "[$reg] @ baseOffset0Narrow" %}
1.2266 + match(RegP);
1.2267 + match(mRegP);
1.2268 + op_cost(100);
1.2269 + format %{ %}
1.2270 + interface(REG_INTER);
1.2271 +%}
1.2272 +
1.2273 +// Indirect Memory Operand Long
1.2274 +operand load_long_indirect(load_long_RegP reg) %{
1.2275 + constraint(ALLOC_IN_RC(p_reg));
1.2276 + match(reg);
1.2277 +
1.2278 + format %{ "[$reg]" %}
1.2279 interface(MEMORY_INTER) %{
1.2280 base($reg);
1.2281 index(0x0);
1.2282 @@ -4057,14 +5711,11 @@
1.2283 %}
1.2284 %}
1.2285
1.2286 -operand baseOffset16NarrowKlass(mRegN reg, immL16 off)
1.2287 -%{
1.2288 - predicate(Universe::narrow_klass_base() == 0 && Universe::narrow_klass_shift() == 0);
1.2289 - constraint(ALLOC_IN_RC(p_reg));
1.2290 - match(AddP (DecodeNKlass reg) off);
1.2291 -
1.2292 - op_cost(5);
1.2293 - format %{ "[$reg + $off (16-bit)] @ baseOffset16NarrowKlass" %}
1.2294 +// Indirect Memory Plus Long Offset Operand
1.2295 +operand load_long_indOffset32(load_long_RegP reg, immL32 off) %{
1.2296 + match(AddP reg off);
1.2297 +
1.2298 + format %{ "[$reg + $off]" %}
1.2299 interface(MEMORY_INTER) %{
1.2300 base($reg);
1.2301 index(0x0);
1.2302 @@ -4073,87 +5724,6 @@
1.2303 %}
1.2304 %}
1.2305
1.2306 -operand baseOffset0NarrowKlass(mRegN reg)
1.2307 -%{
1.2308 - predicate(Universe::narrow_klass_base() == 0 && Universe::narrow_klass_shift() == 0);
1.2309 - constraint(ALLOC_IN_RC(p_reg));
1.2310 - match(DecodeNKlass reg);
1.2311 -
1.2312 - op_cost(10);
1.2313 - format %{ "[$reg] @ baseOffset0NarrowKlass" %}
1.2314 - interface(MEMORY_INTER) %{
1.2315 - base($reg);
1.2316 - index(0x0);
1.2317 - scale(0x0);
1.2318 - disp(0x0);
1.2319 - %}
1.2320 -%}
1.2321 -
1.2322 -operand gsBaseIndexOffset8NarrowKlass(mRegN reg, mRegL lreg, immL8 off)
1.2323 -%{
1.2324 - predicate(UseLoongsonISA && Universe::narrow_klass_base() == 0 && Universe::narrow_klass_shift() == 0);
1.2325 - constraint(ALLOC_IN_RC(p_reg));
1.2326 - match(AddP (AddP (DecodeNKlass reg) lreg) off);
1.2327 -
1.2328 - op_cost(5);
1.2329 - format %{"[$reg + $off + $lreg] @ gsBaseIndexOffset8NarrowKlass" %}
1.2330 - interface(MEMORY_INTER) %{
1.2331 - base($reg);
1.2332 - index($lreg);
1.2333 - scale(0x0);
1.2334 - disp($off);
1.2335 - %}
1.2336 -%}
1.2337 -
1.2338 -operand gsBaseIndexOffset0NarrowKlass(mRegN reg, mRegL lreg)
1.2339 -%{
1.2340 - predicate(UseLoongsonISA && Universe::narrow_klass_base() == 0 && Universe::narrow_klass_shift() == 0);
1.2341 - constraint(ALLOC_IN_RC(p_reg));
1.2342 - match(AddP (DecodeNKlass reg) lreg);
1.2343 -
1.2344 - op_cost(10);
1.2345 - format %{"[$reg + $lreg] @ gsBaseIndexOffset0NarrowKlass" %}
1.2346 - interface(MEMORY_INTER) %{
1.2347 - base($reg);
1.2348 - index($lreg);
1.2349 - scale(0x0);
1.2350 - disp(0x0);
1.2351 - %}
1.2352 -%}
1.2353 -
1.2354 -
1.2355 -//------------------------OPERAND CLASSES--------------------------------------
1.2356 -opclass memory(
1.2357 - baseOffset16,
1.2358 - gsBaseIndexOffset8,
1.2359 - gsBaseIndexI2LOffset8,
1.2360 - gsBaseIndexOffset0,
1.2361 - baseOffset0,
1.2362 -
1.2363 - baseOffset16Narrow,
1.2364 - gsBaseIndexOffset8Narrow,
1.2365 - baseOffset0Narrow,
1.2366 -
1.2367 - baseOffset16NarrowKlass,
1.2368 - baseOffset0NarrowKlass,
1.2369 - gsBaseIndexOffset8NarrowKlass,
1.2370 - gsBaseIndexOffset0NarrowKlass
1.2371 -);
1.2372 -
1.2373 -// For loading unsigned values
1.2374 -// umemory --> unsigned memory
1.2375 -opclass umemory(
1.2376 - baseOffset16,
1.2377 - baseOffset0,
1.2378 -
1.2379 - baseOffset16Narrow,
1.2380 - baseOffset0Narrow,
1.2381 -
1.2382 - baseOffset16NarrowKlass,
1.2383 - baseOffset0NarrowKlass
1.2384 -);
1.2385 -
1.2386 -
1.2387 //----------Conditional Branch Operands----------------------------------------
1.2388 // Comparison Op - This is the operation of the comparison, and is limited to
1.2389 // the following set of codes:
1.2390 @@ -4206,6 +5776,55 @@
1.2391 %}
1.2392 %}
1.2393
1.2394 +/*
1.2395 +// Comparison Code, unsigned compare. Used by FP also, with
1.2396 +// C2 (unordered) turned into GT or LT already. The other bits
1.2397 +// C0 and C3 are turned into Carry & Zero flags.
1.2398 +operand cmpOpU() %{
1.2399 + match(Bool);
1.2400 +
1.2401 + format %{ "" %}
1.2402 + interface(COND_INTER) %{
1.2403 + equal(0x4);
1.2404 + not_equal(0x5);
1.2405 + less(0x2);
1.2406 + greater_equal(0x3);
1.2407 + less_equal(0x6);
1.2408 + greater(0x7);
1.2409 + %}
1.2410 +%}
1.2411 +*/
1.2412 +/*
1.2413 +// Comparison Code for FP conditional move
1.2414 +operand cmpOp_fcmov() %{
1.2415 + match(Bool);
1.2416 +
1.2417 + format %{ "" %}
1.2418 + interface(COND_INTER) %{
1.2419 + equal (0x01);
1.2420 + not_equal (0x02);
1.2421 + greater (0x03);
1.2422 + greater_equal(0x04);
1.2423 + less (0x05);
1.2424 + less_equal (0x06);
1.2425 + %}
1.2426 +%}
1.2427 +
1.2428 +// Comparision Code used in long compares
1.2429 +operand cmpOp_commute() %{
1.2430 + match(Bool);
1.2431 +
1.2432 + format %{ "" %}
1.2433 + interface(COND_INTER) %{
1.2434 + equal(0x4);
1.2435 + not_equal(0x5);
1.2436 + less(0xF);
1.2437 + greater_equal(0xE);
1.2438 + less_equal(0xD);
1.2439 + greater(0xC);
1.2440 + %}
1.2441 +%}
1.2442 +*/
1.2443
1.2444 //----------Special Memory Operands--------------------------------------------
1.2445 // Stack Slot Operand - This operand is used for loading and storing temporary
1.2446 @@ -4275,6 +5894,12 @@
1.2447 disp($reg); // Stack Offset
1.2448 %}
1.2449 %}
1.2450 +
1.2451 +
1.2452 +//------------------------OPERAND CLASSES--------------------------------------
1.2453 +//opclass memory( direct, indirect, indOffset16, indOffset32, indOffset32X, indIndexOffset );
1.2454 +opclass memory( indirect, indirectNarrow, indOffset8, indOffset32, indIndex, indIndexScale, load_long_indirect, load_long_indOffset32, baseIndexOffset8, baseIndexOffset8_convI2L, indIndexScaleOffset8, indIndexScaleOffset8_convI2L, basePosIndexScaleOffset8, indIndexScaleOffsetNarrow, indPosIndexI2LScaleOffset8Narrow, indOffset8Narrow, indIndexOffset8Narrow);
1.2455 +
1.2456
1.2457 //----------PIPELINE-----------------------------------------------------------
1.2458 // Rules which define the behavior of the target architectures pipeline.
1.2459 @@ -4628,7 +6253,7 @@
1.2460 %}
1.2461
1.2462 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
1.2463 -instruct loadI2UB(mRegI dst, umemory mem, immI_255 mask) %{
1.2464 +instruct loadI2UB(mRegI dst, memory mem, immI_255 mask) %{
1.2465 match(Set dst (AndI (LoadI mem) mask));
1.2466
1.2467 ins_cost(125);
1.2468 @@ -4648,7 +6273,7 @@
1.2469 %}
1.2470
1.2471 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
1.2472 -instruct loadI2US(mRegI dst, umemory mem, immI_65535 mask) %{
1.2473 +instruct loadI2US(mRegI dst, memory mem, immI_65535 mask) %{
1.2474 match(Set dst (AndI (LoadI mem) mask));
1.2475
1.2476 ins_cost(125);
1.2477 @@ -4689,18 +6314,26 @@
1.2478 ins_pipe( ialu_storeL );
1.2479 %}
1.2480
1.2481 -
1.2482 instruct storeL_immL0(memory mem, immL0 zero) %{
1.2483 match(Set mem (StoreL mem zero));
1.2484
1.2485 ins_cost(180);
1.2486 - format %{ "sd $mem, zero #@storeL_immL0" %}
1.2487 - ins_encode(store_L_immL0_enc(mem));
1.2488 + format %{ "sd zero, $mem #@storeL_immL0" %}
1.2489 + ins_encode(store_L_immL0_enc(mem, zero));
1.2490 ins_pipe( ialu_storeL );
1.2491 %}
1.2492
1.2493 +instruct storeL_imm(memory mem, immL src) %{
1.2494 + match(Set mem (StoreL mem src));
1.2495 +
1.2496 + ins_cost(200);
1.2497 + format %{ "sd $src, $mem #@storeL_imm" %}
1.2498 + ins_encode(store_L_immL_enc(mem, src));
1.2499 + ins_pipe( ialu_storeL );
1.2500 +%}
1.2501 +
1.2502 // Load Compressed Pointer
1.2503 -instruct loadN(mRegN dst, umemory mem)
1.2504 +instruct loadN(mRegN dst, memory mem)
1.2505 %{
1.2506 match(Set dst (LoadN mem));
1.2507
1.2508 @@ -4710,7 +6343,7 @@
1.2509 ins_pipe( ialu_loadI ); // XXX
1.2510 %}
1.2511
1.2512 -instruct loadN2P(mRegP dst, umemory mem)
1.2513 +instruct loadN2P(mRegP dst, memory mem)
1.2514 %{
1.2515 match(Set dst (DecodeN (LoadN mem)));
1.2516 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0);
1.2517 @@ -4742,7 +6375,7 @@
1.2518 %}
1.2519
1.2520 // Load narrow Klass Pointer
1.2521 -instruct loadNKlass(mRegN dst, umemory mem)
1.2522 +instruct loadNKlass(mRegN dst, memory mem)
1.2523 %{
1.2524 match(Set dst (LoadNKlass mem));
1.2525
1.2526 @@ -4752,7 +6385,7 @@
1.2527 ins_pipe( ialu_loadI ); // XXX
1.2528 %}
1.2529
1.2530 -instruct loadN2PKlass(mRegP dst, umemory mem)
1.2531 +instruct loadN2PKlass(mRegP dst, memory mem)
1.2532 %{
1.2533 match(Set dst (DecodeNKlass (LoadNKlass mem)));
1.2534 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
1.2535 @@ -4867,6 +6500,26 @@
1.2536 ins_pipe( ialu_storeI );
1.2537 %}
1.2538
1.2539 +// Store NULL Pointer, mark word, or other simple pointer constant.
1.2540 +instruct storeImmP(memory mem, immP31 src) %{
1.2541 + match(Set mem (StoreP mem src));
1.2542 +
1.2543 + ins_cost(150);
1.2544 + format %{ "mov $mem, $src #@storeImmP" %}
1.2545 + ins_encode(store_P_immP_enc(mem, src));
1.2546 + ins_pipe( ialu_storeI );
1.2547 +%}
1.2548 +
1.2549 +// Store Byte Immediate
1.2550 +instruct storeImmB(memory mem, immI8 src) %{
1.2551 + match(Set mem (StoreB mem src));
1.2552 +
1.2553 + ins_cost(150);
1.2554 + format %{ "movb $mem, $src #@storeImmB" %}
1.2555 + ins_encode(store_B_immI_enc(mem, src));
1.2556 + ins_pipe( ialu_storeI );
1.2557 +%}
1.2558 +
1.2559 // Store Compressed Pointer
1.2560 instruct storeN(memory mem, mRegN src)
1.2561 %{
1.2562 @@ -4915,8 +6568,28 @@
1.2563 match(Set mem (StoreN mem zero));
1.2564
1.2565 ins_cost(125); // XXX
1.2566 - format %{ "storeN0 $mem, R12\t# compressed ptr" %}
1.2567 - ins_encode(storeImmN0_enc(mem));
1.2568 + format %{ "storeN0 zero, $mem\t# compressed ptr" %}
1.2569 + ins_encode(storeImmN0_enc(mem, zero));
1.2570 + ins_pipe( ialu_storeI );
1.2571 +%}
1.2572 +
1.2573 +instruct storeImmN(memory mem, immN src)
1.2574 +%{
1.2575 + match(Set mem (StoreN mem src));
1.2576 +
1.2577 + ins_cost(150);
1.2578 + format %{ "storeImmN $mem, $src\t# compressed ptr @ storeImmN" %}
1.2579 + ins_encode(storeImmN_enc(mem, src));
1.2580 + ins_pipe( ialu_storeI );
1.2581 +%}
1.2582 +
1.2583 +instruct storeImmNKlass(memory mem, immNKlass src)
1.2584 +%{
1.2585 + match(Set mem (StoreNKlass mem src));
1.2586 +
1.2587 + ins_cost(150); // XXX
1.2588 + format %{ "sw $mem, $src\t# compressed klass ptr @ storeImmNKlass" %}
1.2589 + ins_encode(storeImmNKlass_enc(mem, src));
1.2590 ins_pipe( ialu_storeI );
1.2591 %}
1.2592
1.2593 @@ -4930,15 +6603,6 @@
1.2594 ins_pipe( ialu_storeI );
1.2595 %}
1.2596
1.2597 -instruct storeB0(memory mem, immI0 zero) %{
1.2598 - match(Set mem (StoreB mem zero));
1.2599 -
1.2600 - ins_cost(100);
1.2601 - format %{ "sb $zero, $mem #@storeB0" %}
1.2602 - ins_encode(store_B0_enc(mem));
1.2603 - ins_pipe( ialu_storeI );
1.2604 -%}
1.2605 -
1.2606 instruct storeB_convL2I(memory mem, mRegL src) %{
1.2607 match(Set mem (StoreB mem (ConvL2I src)));
1.2608
1.2609 @@ -4968,7 +6632,7 @@
1.2610 %}
1.2611
1.2612 // Load Byte (8bit UNsigned)
1.2613 -instruct loadUB(mRegI dst, umemory mem) %{
1.2614 +instruct loadUB(mRegI dst, memory mem) %{
1.2615 match(Set dst (LoadUB mem));
1.2616
1.2617 ins_cost(125);
1.2618 @@ -4977,7 +6641,7 @@
1.2619 ins_pipe( ialu_loadI );
1.2620 %}
1.2621
1.2622 -instruct loadUB_convI2L(mRegL dst, umemory mem) %{
1.2623 +instruct loadUB_convI2L(mRegL dst, memory mem) %{
1.2624 match(Set dst (ConvI2L (LoadUB mem)));
1.2625
1.2626 ins_cost(125);
1.2627 @@ -5016,12 +6680,12 @@
1.2628 %}
1.2629
1.2630 // Store Integer Immediate
1.2631 -instruct storeI0(memory mem, immI0 zero) %{
1.2632 - match(Set mem (StoreI mem zero));
1.2633 -
1.2634 - ins_cost(100);
1.2635 - format %{ "sw $mem, $zero #@storeI0" %}
1.2636 - ins_encode(store_I_immI0_enc(mem));
1.2637 +instruct storeImmI(memory mem, immI src) %{
1.2638 + match(Set mem (StoreI mem src));
1.2639 +
1.2640 + ins_cost(150);
1.2641 + format %{ "mov $mem, $src #@storeImmI" %}
1.2642 + ins_encode(store_I_immI_enc(mem, src));
1.2643 ins_pipe( ialu_storeI );
1.2644 %}
1.2645
1.2646 @@ -9047,20 +10711,20 @@
1.2647 %}
1.2648 */
1.2649
1.2650 -instruct lbu_and_lmask(mRegI dst, umemory mem, immI_255 mask) %{
1.2651 +instruct lbu_and_lmask(mRegI dst, memory mem, immI_255 mask) %{
1.2652 match(Set dst (AndI mask (LoadB mem)));
1.2653 ins_cost(60);
1.2654
1.2655 - format %{ "lbu $dst, $mem #@lbu_and_lmask" %}
1.2656 + format %{ "lhu $dst, $mem #@lbu_and_lmask" %}
1.2657 ins_encode(load_UB_enc(dst, mem));
1.2658 ins_pipe( ialu_loadI );
1.2659 %}
1.2660
1.2661 -instruct lbu_and_rmask(mRegI dst, umemory mem, immI_255 mask) %{
1.2662 +instruct lbu_and_rmask(mRegI dst, memory mem, immI_255 mask) %{
1.2663 match(Set dst (AndI (LoadB mem) mask));
1.2664 ins_cost(60);
1.2665
1.2666 - format %{ "lbu $dst, $mem #@lbu_and_rmask" %}
1.2667 + format %{ "lhu $dst, $mem #@lbu_and_rmask" %}
1.2668 ins_encode(load_UB_enc(dst, mem));
1.2669 ins_pipe( ialu_loadI );
1.2670 %}
1.2671 @@ -10704,7 +12368,7 @@
1.2672
1.2673 // Prefetch instructions.
1.2674
1.2675 -instruct prefetchrNTA( umemory mem ) %{
1.2676 +instruct prefetchrNTA( memory mem ) %{
1.2677 match(PrefetchRead mem);
1.2678 ins_cost(125);
1.2679
1.2680 @@ -10715,14 +12379,29 @@
1.2681 int scale = $mem$$scale;
1.2682 int disp = $mem$$disp;
1.2683
1.2684 - assert(index == 0, "no index");
1.2685 - __ daddiu(AT, as_Register(base), disp);
1.2686 + if( index != 0 ) {
1.2687 + if (scale == 0) {
1.2688 + __ daddu(AT, as_Register(base), as_Register(index));
1.2689 + } else {
1.2690 + __ dsll(AT, as_Register(index), scale);
1.2691 + __ daddu(AT, as_Register(base), AT);
1.2692 + }
1.2693 + } else {
1.2694 + __ move(AT, as_Register(base));
1.2695 + }
1.2696 + if( Assembler::is_simm16(disp) ) {
1.2697 + __ daddiu(AT, as_Register(base), disp);
1.2698 + __ daddiu(AT, AT, disp);
1.2699 + } else {
1.2700 + __ move(T9, disp);
1.2701 + __ daddu(AT, as_Register(base), T9);
1.2702 + }
1.2703 __ pref(0, AT, 0); //hint: 0:load
1.2704 %}
1.2705 ins_pipe(pipe_slow);
1.2706 %}
1.2707
1.2708 -instruct prefetchwNTA( umemory mem ) %{
1.2709 +instruct prefetchwNTA( memory mem ) %{
1.2710 match(PrefetchWrite mem);
1.2711 ins_cost(125);
1.2712 format %{ "pref $mem\t# Prefetch to non-temporal cache for write @ prefetchwNTA" %}
1.2713 @@ -10732,9 +12411,24 @@
1.2714 int scale = $mem$$scale;
1.2715 int disp = $mem$$disp;
1.2716
1.2717 - assert(index == 0, "no index");
1.2718 - __ daddiu(AT, as_Register(base), disp);
1.2719 - __ pref(1, AT, 0); //hint: 1:store
1.2720 + if( index != 0 ) {
1.2721 + if (scale == 0) {
1.2722 + __ daddu(AT, as_Register(base), as_Register(index));
1.2723 + } else {
1.2724 + __ dsll(AT, as_Register(index), scale);
1.2725 + __ daddu(AT, as_Register(base), AT);
1.2726 + }
1.2727 + } else {
1.2728 + __ move(AT, as_Register(base));
1.2729 + }
1.2730 + if( Assembler::is_simm16(disp) ) {
1.2731 + __ daddiu(AT, as_Register(base), disp);
1.2732 + __ daddiu(AT, AT, disp);
1.2733 + } else {
1.2734 + __ move(T9, disp);
1.2735 + __ daddu(AT, as_Register(base), T9);
1.2736 + }
1.2737 + __ pref(1, AT, 0); //hint: 1:store
1.2738 %}
1.2739 ins_pipe(pipe_slow);
1.2740 %}
1.2741 @@ -10754,10 +12448,50 @@
1.2742 Register dst = R0;
1.2743
1.2744 if( index != 0 ) {
1.2745 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.2746 - __ gslbx(dst, as_Register(base), as_Register(index), disp);
1.2747 + if( Assembler::is_simm16(disp) ) {
1.2748 + if( UseLoongsonISA ) {
1.2749 + if (scale == 0) {
1.2750 + __ gslbx(dst, as_Register(base), as_Register(index), disp);
1.2751 + } else {
1.2752 + __ dsll(AT, as_Register(index), scale);
1.2753 + __ gslbx(dst, as_Register(base), AT, disp);
1.2754 + }
1.2755 + } else {
1.2756 + if (scale == 0) {
1.2757 + __ addu(AT, as_Register(base), as_Register(index));
1.2758 + } else {
1.2759 + __ dsll(AT, as_Register(index), scale);
1.2760 + __ addu(AT, as_Register(base), AT);
1.2761 + }
1.2762 + __ lb(dst, AT, disp);
1.2763 + }
1.2764 + } else {
1.2765 + if (scale == 0) {
1.2766 + __ addu(AT, as_Register(base), as_Register(index));
1.2767 + } else {
1.2768 + __ dsll(AT, as_Register(index), scale);
1.2769 + __ addu(AT, as_Register(base), AT);
1.2770 + }
1.2771 + __ move(T9, disp);
1.2772 + if( UseLoongsonISA ) {
1.2773 + __ gslbx(dst, AT, T9, 0);
1.2774 + } else {
1.2775 + __ addu(AT, AT, T9);
1.2776 + __ lb(dst, AT, 0);
1.2777 + }
1.2778 + }
1.2779 } else {
1.2780 - __ lb(dst, as_Register(base), disp);
1.2781 + if( Assembler::is_simm16(disp) ) {
1.2782 + __ lb(dst, as_Register(base), disp);
1.2783 + } else {
1.2784 + __ move(T9, disp);
1.2785 + if( UseLoongsonISA ) {
1.2786 + __ gslbx(dst, as_Register(base), T9, 0);
1.2787 + } else {
1.2788 + __ addu(AT, as_Register(base), T9);
1.2789 + __ lb(dst, AT, 0);
1.2790 + }
1.2791 + }
1.2792 }
1.2793 %}
1.2794 ins_pipe(pipe_slow);
1.2795 @@ -10778,7 +12512,7 @@
1.2796 %}
1.2797
1.2798 // Load Char (16bit unsigned)
1.2799 -instruct loadUS(mRegI dst, umemory mem) %{
1.2800 +instruct loadUS(mRegI dst, memory mem) %{
1.2801 match(Set dst (LoadUS mem));
1.2802
1.2803 ins_cost(125);
1.2804 @@ -10787,7 +12521,7 @@
1.2805 ins_pipe( ialu_loadI );
1.2806 %}
1.2807
1.2808 -instruct loadUS_convI2L(mRegL dst, umemory mem) %{
1.2809 +instruct loadUS_convI2L(mRegL dst, memory mem) %{
1.2810 match(Set dst (ConvI2L (LoadUS mem)));
1.2811
1.2812 ins_cost(125);
1.2813 @@ -10862,7 +12596,7 @@
1.2814 ins_encode %{
1.2815 FloatRegister dst = as_FloatRegister($dst$$reg);
1.2816
1.2817 - __ dmtc1(R0, dst);
1.2818 + __ dmtc1(R0, dst);
1.2819 %}
1.2820 ins_pipe( fpu_loadF );
1.2821 %}
1.2822 @@ -10912,10 +12646,66 @@
1.2823 int disp = $mem$$disp;
1.2824
1.2825 if( index != 0 ) {
1.2826 - assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.2827 - __ gsswx(R0, as_Register(base), as_Register(index), disp);
1.2828 - } else {
1.2829 - __ sw(R0, as_Register(base), disp);
1.2830 + if ( UseLoongsonISA ) {
1.2831 + if ( Assembler::is_simm(disp, 8) ) {
1.2832 + if ( scale == 0 ) {
1.2833 + __ gsswx(R0, as_Register(base), as_Register(index), disp);
1.2834 + } else {
1.2835 + __ dsll(T9, as_Register(index), scale);
1.2836 + __ gsswx(R0, as_Register(base), T9, disp);
1.2837 + }
1.2838 + } else if ( Assembler::is_simm16(disp) ) {
1.2839 + if ( scale == 0 ) {
1.2840 + __ daddu(AT, as_Register(base), as_Register(index));
1.2841 + } else {
1.2842 + __ dsll(T9, as_Register(index), scale);
1.2843 + __ daddu(AT, as_Register(base), T9);
1.2844 + }
1.2845 + __ sw(R0, AT, disp);
1.2846 + } else {
1.2847 + if ( scale == 0 ) {
1.2848 + __ move(T9, disp);
1.2849 + __ daddu(AT, as_Register(index), T9);
1.2850 + __ gsswx(R0, as_Register(base), AT, 0);
1.2851 + } else {
1.2852 + __ dsll(T9, as_Register(index), scale);
1.2853 + __ move(AT, disp);
1.2854 + __ daddu(AT, AT, T9);
1.2855 + __ gsswx(R0, as_Register(base), AT, 0);
1.2856 + }
1.2857 + }
1.2858 + } else { //not use loongson isa
1.2859 + if(scale != 0) {
1.2860 + __ dsll(T9, as_Register(index), scale);
1.2861 + __ daddu(AT, as_Register(base), T9);
1.2862 + } else {
1.2863 + __ daddu(AT, as_Register(base), as_Register(index));
1.2864 + }
1.2865 + if( Assembler::is_simm16(disp) ) {
1.2866 + __ sw(R0, AT, disp);
1.2867 + } else {
1.2868 + __ move(T9, disp);
1.2869 + __ daddu(AT, AT, T9);
1.2870 + __ sw(R0, AT, 0);
1.2871 + }
1.2872 + }
1.2873 + } else { //index is 0
1.2874 + if ( UseLoongsonISA ) {
1.2875 + if ( Assembler::is_simm16(disp) ) {
1.2876 + __ sw(R0, as_Register(base), disp);
1.2877 + } else {
1.2878 + __ move(T9, disp);
1.2879 + __ gsswx(R0, as_Register(base), T9, 0);
1.2880 + }
1.2881 + } else {
1.2882 + if( Assembler::is_simm16(disp) ) {
1.2883 + __ sw(R0, as_Register(base), disp);
1.2884 + } else {
1.2885 + __ move(T9, disp);
1.2886 + __ daddu(AT, as_Register(base), T9);
1.2887 + __ sw(R0, AT, 0);
1.2888 + }
1.2889 + }
1.2890 }
1.2891 %}
1.2892 ins_pipe( ialu_storeI );
1.2893 @@ -10950,6 +12740,87 @@
1.2894 ins_pipe( fpu_storeF );
1.2895 %}
1.2896
1.2897 +instruct storeD_imm0( memory mem, immD0 zero) %{
1.2898 + match(Set mem (StoreD mem zero));
1.2899 +
1.2900 + ins_cost(40);
1.2901 + format %{ "store $mem, zero\t# store float @ storeD_imm0" %}
1.2902 + ins_encode %{
1.2903 + int base = $mem$$base;
1.2904 + int index = $mem$$index;
1.2905 + int scale = $mem$$scale;
1.2906 + int disp = $mem$$disp;
1.2907 +
1.2908 + __ mtc1(R0, F30);
1.2909 + __ cvt_d_w(F30, F30);
1.2910 +
1.2911 + if( index != 0 ) {
1.2912 + if ( UseLoongsonISA ) {
1.2913 + if ( Assembler::is_simm(disp, 8) ) {
1.2914 + if (scale == 0) {
1.2915 + __ gssdxc1(F30, as_Register(base), as_Register(index), disp);
1.2916 + } else {
1.2917 + __ dsll(T9, as_Register(index), scale);
1.2918 + __ gssdxc1(F30, as_Register(base), T9, disp);
1.2919 + }
1.2920 + } else if ( Assembler::is_simm16(disp) ) {
1.2921 + if (scale == 0) {
1.2922 + __ daddu(AT, as_Register(base), as_Register(index));
1.2923 + __ sdc1(F30, AT, disp);
1.2924 + } else {
1.2925 + __ dsll(T9, as_Register(index), scale);
1.2926 + __ daddu(AT, as_Register(base), T9);
1.2927 + __ sdc1(F30, AT, disp);
1.2928 + }
1.2929 + } else {
1.2930 + if (scale == 0) {
1.2931 + __ move(T9, disp);
1.2932 + __ daddu(AT, as_Register(index), T9);
1.2933 + __ gssdxc1(F30, as_Register(base), AT, 0);
1.2934 + } else {
1.2935 + __ move(T9, disp);
1.2936 + __ dsll(AT, as_Register(index), scale);
1.2937 + __ daddu(AT, AT, T9);
1.2938 + __ gssdxc1(F30, as_Register(base), AT, 0);
1.2939 + }
1.2940 + }
1.2941 + } else { // not use loongson isa
1.2942 + if(scale != 0) {
1.2943 + __ dsll(T9, as_Register(index), scale);
1.2944 + __ daddu(AT, as_Register(base), T9);
1.2945 + } else {
1.2946 + __ daddu(AT, as_Register(base), as_Register(index));
1.2947 + }
1.2948 + if( Assembler::is_simm16(disp) ) {
1.2949 + __ sdc1(F30, AT, disp);
1.2950 + } else {
1.2951 + __ move(T9, disp);
1.2952 + __ daddu(AT, AT, T9);
1.2953 + __ sdc1(F30, AT, 0);
1.2954 + }
1.2955 + }
1.2956 + } else {// index is 0
1.2957 + if ( UseLoongsonISA ) {
1.2958 + if ( Assembler::is_simm16(disp) ) {
1.2959 + __ sdc1(F30, as_Register(base), disp);
1.2960 + } else {
1.2961 + __ move(T9, disp);
1.2962 + __ gssdxc1(F30, as_Register(base), T9, 0);
1.2963 + }
1.2964 + } else {
1.2965 + if( Assembler::is_simm16(disp) ) {
1.2966 + __ sdc1(F30, as_Register(base), disp);
1.2967 + } else {
1.2968 + __ move(T9, disp);
1.2969 + __ daddu(AT, as_Register(base), T9);
1.2970 + __ sdc1(F30, AT, 0);
1.2971 + }
1.2972 + }
1.2973 + }
1.2974 + %}
1.2975 + ins_pipe( ialu_storeI );
1.2976 +%}
1.2977 +
1.2978 instruct loadSSI(mRegI dst, stackSlotI src)
1.2979 %{
1.2980 match(Set dst src);
1.2981 @@ -11108,21 +12979,13 @@
1.2982 %}
1.2983
1.2984 // Store CMS card-mark Immediate
1.2985 -instruct storeImmCM(memory mem, mRegI src) %{
1.2986 +instruct storeImmCM(memory mem, immI8 src) %{
1.2987 match(Set mem (StoreCM mem src));
1.2988
1.2989 - ins_cost(500);
1.2990 - format %{ "sb $src, $mem (CMS card-mark) @ storeImmCM" %}
1.2991 - ins_encode(store_B_reg_sync_enc(mem, src));
1.2992 - ins_pipe( ialu_storeI );
1.2993 -%}
1.2994 -
1.2995 -instruct storeI0CM(memory mem, immI0 zero) %{
1.2996 - match(Set mem (StoreCM mem zero));
1.2997 -
1.2998 - ins_cost(450);
1.2999 - format %{ "sb $zero, $mem (CMS card-mark) @ storeI0CM" %}
1.3000 - ins_encode(store_B0_sync_enc(mem));
1.3001 + ins_cost(150);
1.3002 + format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
1.3003 +// opcode(0xC6);
1.3004 + ins_encode(store_B_immI_enc_sync(mem, src));
1.3005 ins_pipe( ialu_storeI );
1.3006 %}
1.3007
1.3008 @@ -11143,6 +13006,72 @@
1.3009 ins_pipe( pipe_jump );
1.3010 %}
1.3011
1.3012 +instruct leaP8Narrow(mRegP dst, indOffset8Narrow mem)
1.3013 +%{
1.3014 + predicate(Universe::narrow_oop_shift() == 0);
1.3015 + match(Set dst mem);
1.3016 +
1.3017 + ins_cost(110);
1.3018 + format %{ "leaq $dst, $mem\t# ptr off8narrow @ leaP8Narrow" %}
1.3019 + ins_encode %{
1.3020 + Register dst = $dst$$Register;
1.3021 + Register base = as_Register($mem$$base);
1.3022 + int disp = $mem$$disp;
1.3023 +
1.3024 + __ daddiu(dst, base, disp);
1.3025 + %}
1.3026 + ins_pipe( ialu_regI_imm16 );
1.3027 +%}
1.3028 +
1.3029 +instruct leaPPosIdxScaleOff8(mRegP dst, basePosIndexScaleOffset8 mem)
1.3030 +%{
1.3031 + match(Set dst mem);
1.3032 +
1.3033 + ins_cost(110);
1.3034 + format %{ "leaq $dst, $mem\t# @ PosIdxScaleOff8" %}
1.3035 + ins_encode %{
1.3036 + Register dst = $dst$$Register;
1.3037 + Register base = as_Register($mem$$base);
1.3038 + Register index = as_Register($mem$$index);
1.3039 + int scale = $mem$$scale;
1.3040 + int disp = $mem$$disp;
1.3041 +
1.3042 + if (scale == 0) {
1.3043 + __ daddu(AT, base, index);
1.3044 + __ daddiu(dst, AT, disp);
1.3045 + } else {
1.3046 + __ dsll(AT, index, scale);
1.3047 + __ daddu(AT, base, AT);
1.3048 + __ daddiu(dst, AT, disp);
1.3049 + }
1.3050 + %}
1.3051 +
1.3052 + ins_pipe( ialu_regI_imm16 );
1.3053 +%}
1.3054 +
1.3055 +instruct leaPIdxScale(mRegP dst, indIndexScale mem)
1.3056 +%{
1.3057 + match(Set dst mem);
1.3058 +
1.3059 + ins_cost(110);
1.3060 + format %{ "leaq $dst, $mem\t# @ leaPIdxScale" %}
1.3061 + ins_encode %{
1.3062 + Register dst = $dst$$Register;
1.3063 + Register base = as_Register($mem$$base);
1.3064 + Register index = as_Register($mem$$index);
1.3065 + int scale = $mem$$scale;
1.3066 +
1.3067 + if (scale == 0) {
1.3068 + __ daddu(dst, base, index);
1.3069 + } else {
1.3070 + __ dsll(AT, index, scale);
1.3071 + __ daddu(dst, base, AT);
1.3072 + }
1.3073 + %}
1.3074 +
1.3075 + ins_pipe( ialu_regI_imm16 );
1.3076 +%}
1.3077 +
1.3078 // Jump Direct Conditional - Label defines a relative address from Jcc+1
1.3079 instruct jmpLoopEnd(cmpOp cop, mRegI src1, mRegI src2, label labl) %{
1.3080 match(CountedLoopEnd cop (CmpI src1 src2));
1.3081 @@ -11658,7 +13587,7 @@
1.3082
1.3083 // Match loading integer and casting it to unsigned int in long register.
1.3084 // LoadI + ConvI2L + AndL 0xffffffff.
1.3085 -instruct loadUI2L_rmask(mRegL dst, umemory mem, immL_32bits mask) %{
1.3086 +instruct loadUI2L_rmask(mRegL dst, memory mem, immL_32bits mask) %{
1.3087 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
1.3088
1.3089 format %{ "lwu $dst, $mem \t// zero-extend to long @ loadUI2L_rmask" %}
1.3090 @@ -11666,7 +13595,7 @@
1.3091 ins_pipe(ialu_loadI);
1.3092 %}
1.3093
1.3094 -instruct loadUI2L_lmask(mRegL dst, umemory mem, immL_32bits mask) %{
1.3095 +instruct loadUI2L_lmask(mRegL dst, memory mem, immL_32bits mask) %{
1.3096 match(Set dst (AndL mask (ConvI2L (LoadI mem))));
1.3097
1.3098 format %{ "lwu $dst, $mem \t// zero-extend to long @ loadUI2L_lmask" %}
