src/cpu/mips/vm/mips_64.ad

changeset 391
910b77f150c4
parent 390
d3aefa77da6c
child 394
61b347fb2a89
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Thu Mar 30 08:45:59 2017 -0400
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Fri Mar 31 12:43:02 2017 -0400
     1.3 @@ -12089,10 +12089,8 @@
     1.4    ins_encode %{
     1.5      Register src = $src$$Register;
     1.6      Register dst = $dst$$Register;
     1.7 -    if (src != dst) {
     1.8 -      __ move(dst, src);
     1.9 -    }
    1.10 -    __ encode_heap_oop(dst);
    1.11 +
    1.12 +    __ encode_heap_oop(dst, src);
    1.13    %}
    1.14    ins_pipe( ialu_regL_regL );
    1.15  %}
    1.16 @@ -12115,10 +12113,8 @@
    1.17    ins_encode %{
    1.18      Register s = $src$$Register;
    1.19      Register d = $dst$$Register;
    1.20 -    if (s != d) {
    1.21 -      __ move(d, s);
    1.22 -    }
    1.23 -    __ decode_heap_oop(d);
    1.24 +
    1.25 +    __ decode_heap_oop(d, s);
    1.26    %}
    1.27    ins_pipe( ialu_regL_regL );
    1.28  %}

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