jdk8-mips64-public/hotspot: comparison src/cpu/mips/vm/mips

-:76857a2c3534
+:d3aefa77da6c
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if( Assembler::is_simm16(disp) ) {
-__ gslbx(as_Register(dst), as_Register(base), as_Register(index), disp);
+if( UseLoongsonISA ) {
+if (scale == 0) {
+__ gslbx(as_Register(dst), as_Register(base), as_Register(index), disp);
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ gslbx(as_Register(dst), as_Register(base), AT, disp);
+}
+} else {
+if (scale == 0) {
+__ addu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ addu(AT, as_Register(base), AT);
+}
+__ lb(as_Register(dst), AT, disp);
+}
+} else {
+if (scale == 0) {
+__ addu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ addu(AT, as_Register(base), AT);
+}
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gslbx(as_Register(dst), AT, T9, 0);
+} else {
+__ addu(AT, AT, T9);
+__ lb(as_Register(dst), AT, 0);
+}
+}
 } else {
-__ lb(as_Register(dst), as_Register(base), disp);
+if( Assembler::is_simm16(disp) ) {
+__ lb(as_Register(dst), as_Register(base), disp);
+} else {
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gslbx(as_Register(dst), as_Register(base), T9, 0);
+} else {
+__ addu(AT, as_Register(base), T9);
+__ lb(as_Register(dst), AT, 0);
+}
+}
 }
 %}
 //Load byte unsigned
-enc_class load_UB_enc (mRegI dst, umemory mem) %{
+enc_class load_UB_enc (mRegI dst, memory mem) %{
 MacroAssembler _masm(&cbuf);
 int  dst = $dst$$reg;
 int  base = $mem$$base;
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
-assert(index == 0, "no index");
+if( index != 0 ) {
-__ lbu(as_Register(dst), as_Register(base), disp);
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+if( Assembler::is_simm16(disp) ) {
+__ lbu(as_Register(dst), AT, disp);
+} else {
+__ move(T9, disp);
+__ daddu(AT, AT, T9);
+__ lbu(as_Register(dst), AT, 0);
+}
+} else {
+if( Assembler::is_simm16(disp) ) {
+__ lbu(as_Register(dst), as_Register(base), disp);
+} else {
+__ move(T9, disp);
+__ daddu(AT, as_Register(base), T9);
+__ lbu(as_Register(dst), AT, 0);
+}
+}
 %}
 enc_class store_B_reg_enc (memory mem, mRegI src) %{
 MacroAssembler _masm(&cbuf);
 int  src = $src$$reg;
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if (scale == 0) {
-__ gssbx(as_Register(src), as_Register(base), as_Register(index), disp);
+if( Assembler::is_simm(disp, 8) ) {
+if (UseLoongsonISA) {
+__ gssbx(as_Register(src), as_Register(base), as_Register(index), disp);
+} else {
+__ addu(AT, as_Register(base), as_Register(index));
+__ sb(as_Register(src), AT, disp);
+}
+} else if( Assembler::is_simm16(disp) ) {
+__ addu(AT, as_Register(base), as_Register(index));
+__ sb(as_Register(src), AT, disp);
+} else {
+__ addu(AT, as_Register(base), as_Register(index));
+__ move(T9, disp);
+if (UseLoongsonISA) {
+__ gssbx(as_Register(src), AT, T9, 0);
+} else {
+__ addu(AT, AT, T9);
+__ sb(as_Register(src), AT, 0);
+}
+}
+} else {
+__ dsll(AT, as_Register(index), scale);
+if( Assembler::is_simm(disp, 8) ) {
+if (UseLoongsonISA) {
+__ gssbx(as_Register(src), AT, as_Register(base), disp);
+} else {
+__ addu(AT, as_Register(base), AT);
+__ sb(as_Register(src), AT, disp);
+}
+} else if( Assembler::is_simm16(disp) ) {
+__ addu(AT, as_Register(base), AT);
+__ sb(as_Register(src), AT, disp);
+} else {
+__ addu(AT, as_Register(base), AT);
+__ move(T9, disp);
+if (UseLoongsonISA) {
+__ gssbx(as_Register(src), AT, T9, 0);
+} else {
+__ addu(AT, AT, T9);
+__ sb(as_Register(src), AT, 0);
+}
+}
+}
 } else {
-__ sb(as_Register(src), as_Register(base), disp);
+if( Assembler::is_simm16(disp) ) {
+__ sb(as_Register(src), as_Register(base), disp);
+} else {
+__ move(T9, disp);
+if (UseLoongsonISA) {
+__ gssbx(as_Register(src), as_Register(base), T9, 0);
+} else {
+__ addu(AT, as_Register(base), T9);
+__ sb(as_Register(src), AT, 0);
+}
+}
 }
 %}
-enc_class store_B0_enc (memory mem) %{
+enc_class store_B_immI_enc (memory mem, immI8 src) %{
 MacroAssembler _masm(&cbuf);
 int  base = $mem$$base;
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
+int value = $src$$constant;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if (!UseLoongsonISA) {
-__ gssbx(R0, as_Register(base), as_Register(index), disp);
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+if( Assembler::is_simm16(disp) ) {
+if (value == 0) {
+__ sb(R0, AT, disp);
+} else {
+__ move(T9, value);
+__ sb(T9, AT, disp);
+}
+} else {
+if (value == 0) {
+__ move(T9, disp);
+__ daddu(AT, AT, T9);
+__ sb(R0, AT, 0);
+} else {
+__ move(T9, disp);
+__ daddu(AT, AT, T9);
+__ move(T9, value);
+__ sb(T9, AT, 0);
+}
+}
+} else {
+if (scale == 0) {
+if( Assembler::is_simm(disp, 8) ) {
+if (value == 0) {
+__ gssbx(R0, as_Register(base), as_Register(index), disp);
+} else {
+__ move(T9, value);
+__ gssbx(T9, as_Register(base), as_Register(index), disp);
+}
+} else if( Assembler::is_simm16(disp) ) {
+__ daddu(AT, as_Register(base), as_Register(index));
+if (value == 0) {
+__ sb(R0, AT, disp);
+} else {
+__ move(T9, value);
+__ sb(T9, AT, disp);
+}
+} else {
+if (value == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+__ move(T9, disp);
+__ gssbx(R0, AT, T9, 0);
+} else {
+__ move(AT, disp);
+__ move(T9, value);
+__ daddu(AT, as_Register(base), AT);
+__ gssbx(T9, AT, as_Register(index), 0);
+}
+}
+} else {
+if( Assembler::is_simm(disp, 8) ) {
+__ dsll(AT, as_Register(index), scale);
+if (value == 0) {
+__ gssbx(R0, as_Register(base), AT, disp);
+} else {
+__ move(T9, value);
+__ gssbx(T9, as_Register(base), AT, disp);
+}
+} else if( Assembler::is_simm16(disp) ) {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+if (value == 0) {
+__ sb(R0, AT, disp);
+} else {
+__ move(T9, value);
+__ sb(T9, AT, disp);
+}
+} else {
+__ dsll(AT, as_Register(index), scale);
+if (value == 0) {
+__ daddu(AT, as_Register(base), AT);
+__ move(T9, disp);
+__ gssbx(R0, AT, T9, 0);
+} else {
+__ move(T9, disp);
+__ daddu(AT, AT, T9);
+__ move(T9, value);
+__ gssbx(T9, as_Register(base), AT, 0);
+}
+}
+}
+}
 } else {
-__ sb(R0, as_Register(base), disp);
+if( Assembler::is_simm16(disp) ) {
+if (value == 0) {
+__ sb(R0, as_Register(base), disp);
+} else {
+__ move(AT, value);
+__ sb(AT, as_Register(base), disp);
+}
+} else {
+if (value == 0) {
+__ move(T9, disp);
+if (UseLoongsonISA) {
+__ gssbx(R0, as_Register(base), T9, 0);
+} else {
+__ daddu(AT, as_Register(base), T9);
+__ sb(R0, AT, 0);
+}
+} else {
+__ move(T9, disp);
+if (UseLoongsonISA) {
+__ move(AT, value);
+__ gssbx(AT, as_Register(base), T9, 0);
+} else {
+__ daddu(AT, as_Register(base), T9);
+__ move(T9, value);
+__ sb(T9, AT, 0);
+}
+}
+}
 }
 %}
-enc_class store_B_reg_sync_enc (memory mem, mRegI src) %{
-MacroAssembler _masm(&cbuf);
+enc_class store_B_immI_enc_sync (memory mem, immI8 src) %{
-int  src = $src$$reg;
-int  base = $mem$$base;
-int  index = $mem$$index;
-int  scale = $mem$$scale;
-int  disp = $mem$$disp;
-if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
-__ gssbx(as_Register(src), as_Register(base), as_Register(index), disp);
-} else {
-__ sb(as_Register(src), as_Register(base), disp);
-}
-__ sync();
-%}
-enc_class store_B0_sync_enc (memory mem) %{
 MacroAssembler _masm(&cbuf);
 int  base = $mem$$base;
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
+int value = $src$$constant;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+		 if ( UseLoongsonISA ) {
-__ gssbx(R0, as_Register(base), as_Register(index), disp);
+			if ( Assembler::is_simm(disp,8) ) {
+				if ( scale == 0 ) {
+					if ( value == 0 ) {
+						__ gssbx(R0, as_Register(base), as_Register(index), disp);
+					} else {
+						__ move(AT, value);
+						__ gssbx(AT, as_Register(base), as_Register(index), disp);
+					}
+				} else {
+					__ dsll(AT, as_Register(index), scale);
+					if ( value == 0 ) {
+						__ gssbx(R0, as_Register(base), AT, disp);
+					} else {
+						__ move(T9, value);
+						__ gssbx(T9, as_Register(base), AT, disp);
+					}
+				}
+			} else if ( Assembler::is_simm16(disp) ) {
+				if ( scale == 0 ) {
+					__ daddu(AT, as_Register(base), as_Register(index));
+					if ( value == 0 ){
+						__ sb(R0, AT, disp);
+					} else {
+						__ move(T9, value);
+						__ sb(T9, AT, disp);
+					}
+				} else {
+					__ dsll(AT, as_Register(index), scale);
+					__ daddu(AT, as_Register(base), AT);
+					if ( value == 0 ) {
+						__ sb(R0, AT, disp);
+					} else {
+						__ move(T9, value);
+						__ sb(T9, AT, disp);
+					}
+				}
+			} else {
+				if ( scale == 0 ) {
+					__ move(AT, disp);
+					__ daddu(AT, as_Register(index), AT);
+					if ( value == 0 ) {
+						__ gssbx(R0, as_Register(base), AT, 0);
+					} else {
+						__ move(T9, value);
+						__ gssbx(T9, as_Register(base), AT, 0);
+					}
+				} else {
+					__ dsll(AT, as_Register(index), scale);
+					__ move(T9, disp);
+					__ daddu(AT, AT, T9);
+					if ( value == 0 ) {
+						__ gssbx(R0, as_Register(base), AT, 0);
+					} else {
+						__ move(T9, value);
+						__ gssbx(T9, as_Register(base), AT, 0);
+					}
+				}
+			}
+		 } else { //not use loongson isa
+		    if (scale == 0) {
+			   __ daddu(AT, as_Register(base), as_Register(index));
+		    } else {
+			   __ dsll(AT, as_Register(index), scale);
+			   __ daddu(AT, as_Register(base), AT);
+		    }
+		    if( Assembler::is_simm16(disp) ) {
+			   if (value == 0) {
+			      __ sb(R0, AT, disp);
+			   } else {
+		          __ move(T9, value);
+				  __ sb(T9, AT, disp);
+			  }
+			} else {
+		       if (value == 0) {
+	              __ move(T9, disp);
+				  __ daddu(AT, AT, T9);
+			      __ sb(R0, AT, 0);
+		       } else {
+	              __ move(T9, disp);
+				  __ daddu(AT, AT, T9);
+			      __ move(T9, value);
+		          __ sb(T9, AT, 0);
+	           }
+			}
+		}
 } else {
-__ sb(R0, as_Register(base), disp);
+		 if ( UseLoongsonISA ){
+			if ( Assembler::is_simm16(disp) ){
+				if ( value == 0 ) {
+					__ sb(R0, as_Register(base), disp);
+				} else {
+					__ move(AT, value);
+					__ sb(AT, as_Register(base), disp);
+				}
+			} else {
+				__ move(AT, disp);
+				if ( value == 0 ) {
+					__ gssbx(R0, as_Register(base), AT, 0);
+				} else {
+					__ move(T9, value);
+					__ gssbx(T9, as_Register(base), AT, 0);
+				}
+			}
+		 } else {
+		    if( Assembler::is_simm16(disp) ) {
+	           if (value == 0) {
+			      __ sb(R0, as_Register(base), disp);
+		       } else {
+	              __ move(AT, value);
+				  __ sb(AT, as_Register(base), disp);
+			   }
+		    } else {
+	           if (value == 0) {
+				  __ move(T9, disp);
+			      __ daddu(AT, as_Register(base), T9);
+		          __ sb(R0, AT, 0);
+	           } else {
+				  __ move(T9, disp);
+			      __ daddu(AT, as_Register(base), T9);
+		          __ move(T9, value);
+	              __ sb(T9, AT, 0);
+			   }
+		    }
+		}
 }
 __ sync();
 %}
 // Load Short (16bit signed)
 enc_class load_S_enc (mRegI dst, memory mem) %{
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+		 if ( UseLoongsonISA ) {
-	__ gslhx(as_Register(dst), as_Register(base), as_Register(index), disp);
+			if ( Assembler::is_simm(disp, 8) ) {
-} else {
+				if (scale == 0) {
-__ lh(as_Register(dst), as_Register(base), disp);
+					__ gslhx(as_Register(dst), as_Register(base), as_Register(index), disp);
+				} else {
+					__ dsll(AT, as_Register(index), scale);
+					__ gslhx(as_Register(dst), as_Register(base), AT, disp);
+				}
+			} else if ( Assembler::is_simm16(disp) ) {
+				if (scale == 0) {
+					__ daddu(AT, as_Register(base), as_Register(index));
+					__ lh(as_Register(dst), AT, disp);
+				} else {
+					__ dsll(AT, as_Register(index), scale);
+					__ daddu(AT, as_Register(base), AT);
+					__ lh(as_Register(dst), AT, disp);
+				}
+			} else {
+				if (scale == 0) {
+					__ move(AT, disp);
+					__ daddu(AT, as_Register(index), AT);
+					__ gslhx(as_Register(dst), as_Register(base), AT, 0);
+				} else {
+					__ dsll(AT, as_Register(index), scale);
+					__ move(T9, disp);
+					__ daddu(AT, AT, T9);
+					__ gslhx(as_Register(dst), as_Register(base), AT, 0);
+				}
+			}
+		 } else { // not use loongson isa
+		    if (scale == 0) {
+			   __ daddu(AT, as_Register(base), as_Register(index));
+		    } else {
+			   __ dsll(AT, as_Register(index), scale);
+		       __ daddu(AT, as_Register(base), AT);
+			}
+		    if( Assembler::is_simm16(disp) ) {
+		       __ lh(as_Register(dst), AT, disp);
+	        } else {
+	           __ move(T9, disp);
+			   __ daddu(AT, AT, T9);
+		       __ lh(as_Register(dst), AT, 0);
+	        }
+		}
+} else { // index is 0
+		 if ( UseLoongsonISA ) {
+			if ( Assembler::is_simm16(disp) ) {
+				__ lh(as_Register(dst), as_Register(base), disp);
+			} else {
+				__ move(T9, disp);
+				__ gslhx(as_Register(dst), as_Register(base), T9, 0);
+			}
+		 } else { //not use loongson isa
+		    if( Assembler::is_simm16(disp) ) {
+			   __ lh(as_Register(dst), as_Register(base), disp);
+		    } else {
+	           __ move(T9, disp);
+			   __ daddu(AT, as_Register(base), T9);
+		       __ lh(as_Register(dst), AT, 0);
+	        }
+		 }
 }
 %}
 // Load Char (16bit unsigned)
-enc_class load_C_enc (mRegI dst, umemory mem) %{
+enc_class load_C_enc (mRegI dst, memory mem) %{
 MacroAssembler _masm(&cbuf);
 int  dst = $dst$$reg;
 int  base = $mem$$base;
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
-assert(index == 0, "no index");
+if( index != 0 ) {
-__ lhu(as_Register(dst), as_Register(base), disp);
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+if( Assembler::is_simm16(disp) ) {
+__ lhu(as_Register(dst), AT, disp);
+} else {
+__ move(T9, disp);
+__ addu(AT, AT, T9);
+__ lhu(as_Register(dst), AT, 0);
+}
+} else {
+if( Assembler::is_simm16(disp) ) {
+__ lhu(as_Register(dst), as_Register(base), disp);
+} else {
+__ move(T9, disp);
+__ daddu(AT, as_Register(base), T9);
+__ lhu(as_Register(dst), AT, 0);
+}
+}
 %}
 // Store Char (16bit unsigned)
 enc_class store_C_reg_enc (memory mem, mRegI src) %{
 MacroAssembler _masm(&cbuf);
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if( Assembler::is_simm16(disp) ) {
-__ gsshx(as_Register(src), as_Register(base), as_Register(index), disp);
+if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
+if (scale == 0) {
+__ gsshx(as_Register(src), as_Register(base), as_Register(index), disp);
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ gsshx(as_Register(src), as_Register(base), AT, disp);
+}
+} else {
+if (scale == 0) {
+__ addu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ addu(AT, as_Register(base), AT);
+}
+__ sh(as_Register(src), AT, disp);
+}
+} else {
+if (scale == 0) {
+__ addu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ addu(AT, as_Register(base), AT);
+}
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gsshx(as_Register(src), AT, T9, 0);
+} else {
+__ addu(AT, AT, T9);
+__ sh(as_Register(src), AT, 0);
+}
+}
 } else {
-__ sh(as_Register(src), as_Register(base), disp);
+if( Assembler::is_simm16(disp) ) {
+__ sh(as_Register(src), as_Register(base), disp);
+} else {
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gsshx(as_Register(src), as_Register(base), T9, 0);
+} else {
+__ addu(AT, as_Register(base), T9);
+__ sh(as_Register(src), AT, 0);
+}
+}
 }
 %}
 enc_class store_C0_enc (memory mem) %{
 MacroAssembler _masm(&cbuf);
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if( Assembler::is_simm16(disp) ) {
-__ gsshx(R0, as_Register(base), as_Register(index), disp);
+if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
+if (scale == 0) {
+__ gsshx(R0, as_Register(base), as_Register(index), disp);
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ gsshx(R0, as_Register(base), AT, disp);
+}
+} else {
+if (scale == 0) {
+__ addu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ addu(AT, as_Register(base), AT);
+}
+__ sh(R0, AT, disp);
+}
+} else {
+if (scale == 0) {
+__ addu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ addu(AT, as_Register(base), AT);
+}
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gsshx(R0, AT, T9, 0);
+} else {
+__ addu(AT, AT, T9);
+__ sh(R0, AT, 0);
+}
+}
 } else {
-__ sh(R0, as_Register(base), disp);
+if( Assembler::is_simm16(disp) ) {
+__ sh(R0, as_Register(base), disp);
+} else {
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gsshx(R0, as_Register(base), T9, 0);
+} else {
+__ addu(AT, as_Register(base), T9);
+__ sh(R0, AT, 0);
+}
+}
 }
 %}
 enc_class load_I_enc (mRegI dst, memory mem) %{
 MacroAssembler _masm(&cbuf);
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if( Assembler::is_simm16(disp) ) {
-__ gslwx(as_Register(dst), as_Register(base), as_Register(index), disp);
+if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
+if (scale == 0) {
+__ gslwx(as_Register(dst), as_Register(base), as_Register(index), disp);
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ gslwx(as_Register(dst), as_Register(base), AT, disp);
+}
+} else {
+if (scale == 0) {
+__ addu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ addu(AT, as_Register(base), AT);
+}
+__ lw(as_Register(dst), AT, disp);
+}
+} else {
+if (scale == 0) {
+__ addu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ addu(AT, as_Register(base), AT);
+}
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gslwx(as_Register(dst), AT, T9, 0);
+} else {
+__ addu(AT, AT, T9);
+__ lw(as_Register(dst), AT, 0);
+}
+}
 } else {
-__ lw(as_Register(dst), as_Register(base), disp);
+if( Assembler::is_simm16(disp) ) {
+__ lw(as_Register(dst), as_Register(base), disp);
+} else {
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gslwx(as_Register(dst), as_Register(base), T9, 0);
+} else {
+__ addu(AT, as_Register(base), T9);
+__ lw(as_Register(dst), AT, 0);
+}
+}
 }
 %}
 enc_class store_I_reg_enc (memory mem, mRegI src) %{
 MacroAssembler _masm(&cbuf);
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if( Assembler::is_simm16(disp) ) {
-__ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
+if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
+if (scale == 0) {
+__ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ gsswx(as_Register(src), as_Register(base), AT, disp);
+}
+} else {
+if (scale == 0) {
+__ addu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ addu(AT, as_Register(base), AT);
+}
+__ sw(as_Register(src), AT, disp);
+}
+} else {
+if (scale == 0) {
+__ addu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ addu(AT, as_Register(base), AT);
+}
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gsswx(as_Register(src), AT, T9, 0);
+} else {
+__ addu(AT, AT, T9);
+__ sw(as_Register(src), AT, 0);
+}
+}
 } else {
-__ sw(as_Register(src), as_Register(base), disp);
+if( Assembler::is_simm16(disp) ) {
+__ sw(as_Register(src), as_Register(base), disp);
+} else {
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gsswx(as_Register(src), as_Register(base), T9, 0);
+} else {
+__ addu(AT, as_Register(base), T9);
+__ sw(as_Register(src), AT, 0);
+}
+}
 }
 %}
-enc_class store_I_immI0_enc (memory mem) %{
+enc_class store_I_immI_enc (memory mem, immI src) %{
 MacroAssembler _masm(&cbuf);
-int  base  = $mem$$base;
+int  base = $mem$$base;
 int  index = $mem$$index;
 int  scale = $mem$$scale;
-int  disp  = $mem$$disp;
+int  disp = $mem$$disp;
+int value = $src$$constant;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if ( UseLoongsonISA ) {
-__ gsswx(R0, as_Register(base), as_Register(index), disp);
+if ( Assembler::is_simm(disp, 8) ) {
+if ( scale == 0 ) {
+if ( value == 0 ) {
+__ gsswx(R0, as_Register(base), as_Register(index), disp);
+} else {
+__ move(T9, value);
+__ gsswx(T9, as_Register(base), as_Register(index), disp);
+}
+} else {
+__ dsll(AT, as_Register(index), scale);
+if ( value == 0 ) {
+__ gsswx(R0, as_Register(base), AT, disp);
+} else {
+__ move(T9, value);
+__ gsswx(T9, as_Register(base), AT, disp);
+}
+}
+} else if ( Assembler::is_simm16(disp) ) {
+if ( scale == 0 ) {
+__ daddu(AT, as_Register(base), as_Register(index));
+if ( value == 0 ) {
+__ sw(R0, AT, disp);
+} else {
+__ move(T9, value);
+					  __ sw(T9, AT, disp);
+}
+} else {
+				   __ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+if ( value == 0 ) {
+__ sw(R0, AT, disp);
+} else {
+__ move(T9, value);
+__ sw(T9, AT, disp);
+				   }
+				}
+			} else {
+if ( scale == 0 ) {
+__ move(T9, disp);
+__ daddu(AT, as_Register(index), T9);
+if ( value ==0 ) {
+__ gsswx(R0, as_Register(base), AT, 0);
+} else {
+__ move(T9, value);
+__ gsswx(T9, as_Register(base), AT, 0);
+					}
+} else {
+__ dsll(AT, as_Register(index), scale);
+					  __ move(T9, disp);
+					  __ daddu(AT, AT, T9);
+if ( value == 0 ) {
+__ gsswx(R0, as_Register(base), AT, 0);
+					  } else {
+						 __ move(T9, value);
+						 __ gsswx(T9, as_Register(base), AT, 0);
+					  }
+				 }
+			}
+		} else { //not use loongson isa
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+			    __ daddu(AT, as_Register(base), AT);
+		     }
+	         if( Assembler::is_simm16(disp) ) {
+if (value == 0) {
+__ sw(R0, AT, disp);
+} else {
+		           __ move(T9, value);
+			       __ sw(T9, AT, disp);
+			    }
+		     } else {
+if (value == 0) {
+				   __ move(T9, disp);
+			       __ daddu(AT, AT, T9);
+			       __ sw(R0, AT, 0);
+			    } else {
+			       __ move(T9, disp);
+			       __ daddu(AT, AT, T9);
+			       __ move(T9, value);
+			       __ sw(T9, AT, 0);
+			    }
+			 }
+		}
 } else {
-__ sw(R0, as_Register(base), disp);
+		 if ( UseLoongsonISA ) {
+			if ( Assembler::is_simm16(disp) ) {
+				if ( value == 0 ) {
+					__ sw(R0, as_Register(base), disp);
+				} else {
+					__ move(AT, value);
+					__ sw(AT, as_Register(base), disp);
+				}
+			} else {
+				__ move(T9, disp);
+				if ( value == 0 ) {
+					__ gsswx(R0, as_Register(base), T9, 0);
+				} else {
+					__ move(AT, value);
+					__ gsswx(AT, as_Register(base), T9, 0);
+				}
+			}
+		 } else {
+		    if( Assembler::is_simm16(disp) ) {
+			   if (value == 0) {
+		          __ sw(R0, as_Register(base), disp);
+	           } else {
+	              __ move(AT, value);
+				  __ sw(AT, as_Register(base), disp);
+			   }
+		    } else {
+	           if (value == 0) {
+	              __ move(T9, disp);
+				  __ daddu(AT, as_Register(base), T9);
+			      __ sw(R0, AT, 0);
+		      } else {
+			      __ move(T9, disp);
+		          __ daddu(AT, as_Register(base), T9);
+				  __ move(T9, value);
+			      __ sw(T9, AT, 0);
+		       }
+	        }
+		}
 }
 %}
-enc_class load_N_enc (mRegN dst, umemory mem) %{
+enc_class load_N_enc (mRegN dst, memory mem) %{
 MacroAssembler _masm(&cbuf);
 int  dst = $dst$$reg;
 int  base = $mem$$base;
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
+	 relocInfo::relocType disp_reloc = $mem->disp_reloc();
-relocInfo::relocType disp_reloc = $mem->disp_reloc();
+	 assert(disp_reloc == relocInfo::none, "cannot have disp");
-assert(disp_reloc == relocInfo::none, "cannot have disp");
+if( index != 0 ) {
-assert(index == 0, "no index");
+if (scale == 0) {
-__ lwu(as_Register(dst), as_Register(base), disp);
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+if( Assembler::is_simm16(disp) ) {
+__ lwu(as_Register(dst), AT, disp);
+} else {
+__ set64(T9, disp);
+__ daddu(AT, AT, T9);
+__ lwu(as_Register(dst), AT, 0);
+}
+} else {
+if( Assembler::is_simm16(disp) ) {
+__ lwu(as_Register(dst), as_Register(base), disp);
+} else {
+__ set64(T9, disp);
+__ daddu(AT, as_Register(base), T9);
+__ lwu(as_Register(dst), AT, 0);
+}
+}
 %}
 enc_class load_P_enc (mRegP dst, memory mem) %{
 MacroAssembler _masm(&cbuf);
 int  dst = $dst$$reg;
 int  base = $mem$$base;
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
+	 relocInfo::relocType disp_reloc = $mem->disp_reloc();
-relocInfo::relocType disp_reloc = $mem->disp_reloc();
+	 assert(disp_reloc == relocInfo::none, "cannot have disp");
-assert(disp_reloc == relocInfo::none, "cannot have disp");
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if ( UseLoongsonISA ) {
-__ gsldx(as_Register(dst), as_Register(base), as_Register(index), disp);
+if ( Assembler::is_simm(disp, 8) ) {
+if ( scale != 0 ) {
+__ dsll(AT, as_Register(index), scale);
+__ gsldx(as_Register(dst), as_Register(base), AT, disp);
+} else {
+__ gsldx(as_Register(dst), as_Register(base), as_Register(index), disp);
+}
+} else if ( Assembler::is_simm16(disp) ){
+if ( scale != 0 ) {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, AT, as_Register(base));
+} else {
+__ daddu(AT, as_Register(index), as_Register(base));
+}
+__ ld(as_Register(dst), AT, disp);
+} else {
+if ( scale != 0 ) {
+__ dsll(AT, as_Register(index), scale);
+__ move(T9, disp);
+__ daddu(AT, AT, T9);
+} else {
+__ move(T9, disp);
+__ daddu(AT, as_Register(index), T9);
+}
+__ gsldx(as_Register(dst), as_Register(base), AT, 0);
+}
+	    } else { //not use loongson isa
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+if( Assembler::is_simm16(disp) ) {
+__ ld(as_Register(dst), AT, disp);
+} else {
+__ set64(T9, disp);
+__ daddu(AT, AT, T9);
+__ ld(as_Register(dst), AT, 0);
+}
+	    }
 } else {
-__ ld(as_Register(dst), as_Register(base), disp);
+	      if ( UseLoongsonISA ) {
+	         if ( Assembler::is_simm16(disp) ){
+	            __ ld(as_Register(dst), as_Register(base), disp);
+	         } else {
+	            __ set64(T9, disp);
+	            __ gsldx(as_Register(dst), as_Register(base), T9, 0);
+	         }
+	      } else { //not use loongson isa
+	         if( Assembler::is_simm16(disp) ) {
+__ ld(as_Register(dst), as_Register(base), disp);
+} else {
+__ set64(T9, disp);
+__ daddu(AT, as_Register(base), T9);
+__ ld(as_Register(dst), AT, 0);
+}
+	      }
 }
+//     if( disp_reloc != relocInfo::none) __ ld(as_Register(dst), as_Register(dst), 0);
 %}
 enc_class store_P_reg_enc (memory mem, mRegP src) %{
 MacroAssembler _masm(&cbuf);
 int  src = $src$$reg;
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+	    if ( UseLoongsonISA ){
-__ gssdx(as_Register(src), as_Register(base), as_Register(index), disp);
+	       if ( Assembler::is_simm(disp, 8) ) {
+	          if ( scale == 0 ) {
+		         __ gssdx(as_Register(src), as_Register(base), as_Register(index), disp);
+	          } else {
+		         __ dsll(AT, as_Register(index), scale);
+	     __ gssdx(as_Register(src), as_Register(base), AT, disp);
+	          }
+	       } else if ( Assembler::is_simm16(disp) ) {
+	          if ( scale == 0 ) {
+		         __ daddu(AT, as_Register(base), as_Register(index));
+	          } else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+	          }
+__ sd(as_Register(src), AT, disp);
+	       } else {
+	          if ( scale == 0 ) {
+__ move(T9, disp);
+__ daddu(AT, as_Register(index), T9);
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ move(T9, disp);
+__ daddu(AT, AT, T9);
+}
+__ gssdx(as_Register(src), as_Register(base), AT, 0);
+}
+	    } else { //not use loongson isa
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+if( Assembler::is_simm16(disp) ) {
+__ sd(as_Register(src), AT, disp);
+} else {
+__ move(T9, disp);
+__ daddu(AT, AT, T9);
+__ sd(as_Register(src), AT, 0);
+}
+	    }
 } else {
-__ sd(as_Register(src), as_Register(base), disp);
+if ( UseLoongsonISA ) {
+if ( Assembler::is_simm16(disp) ) {
+	            __ sd(as_Register(src), as_Register(base), disp);
+	         } else {
+	            __ move(T9, disp);
+__ gssdx(as_Register(src), as_Register(base), T9, 0);
+	         }
+	      } else {
+if( Assembler::is_simm16(disp) ) {
+__ sd(as_Register(src), as_Register(base), disp);
+} else {
+__ move(T9, disp);
+__ daddu(AT, as_Register(base), T9);
+__ sd(as_Register(src), AT, 0);
+}
+	      }
 }
 %}
 enc_class store_N_reg_enc (memory mem, mRegN src) %{
 MacroAssembler _masm(&cbuf);
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if ( UseLoongsonISA ){
-__ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
+	       if ( Assembler::is_simm(disp, 8) ) {
+if ( scale == 0 ) {
+	             __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
+	          } else {
+__ dsll(AT, as_Register(index), scale);
+__ gsswx(as_Register(src), as_Register(base), AT, disp);
+	          }
+	       } else if ( Assembler::is_simm16(disp) ) {
+if ( scale == 0 ) {
+__ daddu(AT, as_Register(base), as_Register(index));
+	          } else {
+		         __ dsll(AT, as_Register(index), scale);
+		         __ daddu(AT, as_Register(base), AT);
+	          }
+	          __ sw(as_Register(src), AT, disp);
+	       } else {
+	          if ( scale == 0 ) {
+	             __ move(T9, disp);
+__ daddu(AT, as_Register(index), T9);
+	          } else {
+__ dsll(AT, as_Register(index), scale);
+	 	         __ move(T9, disp);
+__ daddu(AT, AT, T9);
+	          }
+	          __ gsswx(as_Register(src), as_Register(base), AT, 0);
+	       }
+	    } else { //not use loongson isa
+	       if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+if( Assembler::is_simm16(disp) ) {
+__ sw(as_Register(src), AT, disp);
+} else {
+__ move(T9, disp);
+__ daddu(AT, AT, T9);
+__ sw(as_Register(src), AT, 0);
+}
+	    }
 } else {
-	__ sw(as_Register(src), as_Register(base), disp);
+if ( UseLoongsonISA ) {
+if ( Assembler::is_simm16(disp) ) {
+	          __ sw(as_Register(src), as_Register(base), disp);
+	       } else {
+	          __ move(T9, disp);
+	          __ gsswx(as_Register(src), as_Register(base), T9, 0);
+	       }
+	    } else {
+if( Assembler::is_simm16(disp) ) {
+__ sw(as_Register(src), as_Register(base), disp);
+} else {
+__ move(T9, disp);
+__ daddu(AT, as_Register(base), T9);
+__ sw(as_Register(src), AT, 0);
+}
+	    }
 }
 %}
 enc_class store_P_immP0_enc (memory mem) %{
 MacroAssembler _masm(&cbuf);
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if (scale == 0) {
-__ gssdx(R0, as_Register(base), as_Register(index), disp);
+if( Assembler::is_simm16(disp) ) {
+if (UseLoongsonISA && Assembler::is_simm(disp, 8)) {
+__ gssdx(R0, as_Register(base), as_Register(index), disp);
+} else {
+__ daddu(AT, as_Register(base), as_Register(index));
+__ sd(R0, AT, disp);
+}
+} else {
+__ daddu(AT, as_Register(base), as_Register(index));
+__ move(T9, disp);
+if(UseLoongsonISA) {
+__ gssdx(R0, AT, T9, 0);
+} else {
+__ daddu(AT, AT, T9);
+__ sd(R0, AT, 0);
+}
+}
+} else {
+__ dsll(AT, as_Register(index), scale);
+if( Assembler::is_simm16(disp) ) {
+if (UseLoongsonISA && Assembler::is_simm(disp, 8)) {
+__ gssdx(R0, as_Register(base), AT, disp);
+} else {
+__ daddu(AT, as_Register(base), AT);
+__ sd(R0, AT, disp);
+}
+} else {
+__ daddu(AT, as_Register(base), AT);
+__ move(T9, disp);
+if (UseLoongsonISA) {
+__ gssdx(R0, AT, T9, 0);
+} else {
+__ daddu(AT, AT, T9);
+__ sd(R0, AT, 0);
+}
+}
+}
 } else {
-__ sd(R0, as_Register(base), disp);
+if( Assembler::is_simm16(disp) ) {
+__ sd(R0, as_Register(base), disp);
+} else {
+__ move(T9, disp);
+if (UseLoongsonISA) {
+__ gssdx(R0, as_Register(base), T9, 0);
+} else {
+__ daddu(AT, as_Register(base), T9);
+__ sd(R0, AT, 0);
+}
+}
 }
 %}
+enc_class store_P_immP_enc (memory mem, immP31 src) %{
-enc_class storeImmN0_enc(memory mem) %{
 MacroAssembler _masm(&cbuf);
 int  base = $mem$$base;
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
+long value = $src$$constant;
-if(index != 0){
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if( index != 0 ) {
-__ gsswx(R0, as_Register(base), as_Register(index), disp);
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+if( Assembler::is_simm16(disp) ) {
+if (value == 0) {
+__ sd(R0, AT, disp);
+} else {
+__ move(T9, value);
+__ sd(T9, AT, disp);
+}
+} else {
+if (value == 0) {
+__ move(T9, disp);
+__ daddu(AT, AT, T9);
+__ sd(R0, AT, 0);
+} else {
+__ move(T9, disp);
+__ daddu(AT, AT, T9);
+__ move(T9, value);
+__ sd(T9, AT, 0);
+}
+}
 } else {
-__ sw(R0, as_Register(base), disp);
+if( Assembler::is_simm16(disp) ) {
+if (value == 0) {
+__ sd(R0, as_Register(base), disp);
+} else {
+__ move(AT, value);
+__ sd(AT, as_Register(base), disp);
+}
+} else {
+if (value == 0) {
+__ move(T9, disp);
+__ daddu(AT, as_Register(base), T9);
+__ sd(R0, AT, 0);
+} else {
+__ move(T9, disp);
+__ daddu(AT, as_Register(base), T9);
+__ move(T9, value);
+__ sd(T9, AT, 0);
+}
+}
 }
+%}
+enc_class storeImmN0_enc(memory mem, ImmN0 src) %{
+MacroAssembler _masm(&cbuf);
+int  base = $mem$$base;
+int  index = $mem$$index;
+int  scale = $mem$$scale;
+int  disp = $mem$$disp;
+	 if(index!=0){
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+		 if( Assembler::is_simm16(disp) ) {
+			 __ sw(R0, AT, disp);
+		 } else {
+			 __ move(T9, disp);
+			 __ daddu(AT, AT, T9);
+			 __ sw(R0, AT, 0);
+		 }
+	 }
+else {
+		 if( Assembler::is_simm16(disp) ) {
+			 __ sw(R0, as_Register(base), disp);
+		 } else {
+			 __ move(T9, disp);
+			 __ daddu(AT, as_Register(base), T9);
+			 __ sw(R0, AT, 0);
+		 }
+	 }
 %}
+enc_class storeImmN_enc (memory mem, immN src) %{
+MacroAssembler _masm(&cbuf);
+int  base = $mem$$base;
+int  index = $mem$$index;
+int  scale = $mem$$scale;
+int  disp = $mem$$disp;
+long * value = (long *)$src$$constant;
+if (value == NULL) {
+guarantee(Assembler::is_simm16(disp), "FIXME: disp is not simm16!");
+if (index == 0) {
+__ sw(R0, as_Register(base), disp);
+} else {
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+__ sw(R0, AT, disp);
+}
+return;
+}
+int oop_index = __ oop_recorder()->find_index((jobject)value);
+RelocationHolder rspec = oop_Relocation::spec(oop_index);
+guarantee(scale == 0, "FIXME: scale is not zero !");
+guarantee(value != 0, "FIXME: value is zero !");
+if (index != 0) {
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+if( Assembler::is_simm16(disp) ) {
+if(rspec.type() != relocInfo::none) {
+__ relocate(rspec, Assembler::narrow_oop_operand);
+__ patchable_set48(T9, oop_index);
+} else {
+__ set64(T9, oop_index);
+}
+__ sw(T9, AT, disp);
+} else {
+__ move(T9, disp);
+__ addu(AT, AT, T9);
+if(rspec.type() != relocInfo::none) {
+__ relocate(rspec, Assembler::narrow_oop_operand);
+__ patchable_set48(T9, oop_index);
+} else {
+__ set64(T9, oop_index);
+}
+__ sw(T9, AT, 0);
+}
+}
+else {
+if( Assembler::is_simm16(disp) ) {
+if($src->constant_reloc() != relocInfo::none) {
+__ relocate(rspec, Assembler::narrow_oop_operand);
+__ patchable_set48(T9, oop_index);
+} else {
+__ set64(T9, oop_index);
+}
+__ sw(T9, as_Register(base), disp);
+} else {
+__ move(T9, disp);
+__ daddu(AT, as_Register(base), T9);
+if($src->constant_reloc() != relocInfo::none){
+__ relocate(rspec, Assembler::narrow_oop_operand);
+__ patchable_set48(T9, oop_index);
+} else {
+__ set64(T9, oop_index);
+}
+__ sw(T9, AT, 0);
+}
+}
+%}
+enc_class storeImmNKlass_enc (memory mem, immNKlass src) %{
+MacroAssembler _masm(&cbuf);
+assert (UseCompressedOops, "should only be used for compressed headers");
+assert (__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
+int  base = $mem$$base;
+int  index = $mem$$index;
+int  scale = $mem$$scale;
+int  disp = $mem$$disp;
+long value = $src$$constant;
+int klass_index = __ oop_recorder()->find_index((Klass*)value);
+RelocationHolder rspec = metadata_Relocation::spec(klass_index);
+long narrowp = Klass::encode_klass((Klass*)value);
+if(index!=0){
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+if( Assembler::is_simm16(disp) ) {
+if(rspec.type() != relocInfo::none){
+__ relocate(rspec, Assembler::narrow_oop_operand);
+__ patchable_set48(T9, narrowp);
+} else {
+__ set64(T9, narrowp);
+}
+__ sw(T9, AT, disp);
+} else {
+__ move(T9, disp);
+__ daddu(AT, AT, T9);
+if(rspec.type() != relocInfo::none){
+__ relocate(rspec, Assembler::narrow_oop_operand);
+__ patchable_set48(T9, narrowp);
+} else {
+__ set64(T9, narrowp);
+}
+__ sw(T9, AT, 0);
+}
+} else {
+if( Assembler::is_simm16(disp) ) {
+if(rspec.type() != relocInfo::none){
+__ relocate(rspec, Assembler::narrow_oop_operand);
+__ patchable_set48(T9, narrowp);
+}
+else {
+__ set64(T9, narrowp);
+}
+__ sw(T9, as_Register(base), disp);
+} else {
+__ move(T9, disp);
+__ daddu(AT, as_Register(base), T9);
+if(rspec.type() != relocInfo::none){
+__ relocate(rspec, Assembler::narrow_oop_operand);
+__ patchable_set48(T9, narrowp);
+} else {
+__ set64(T9, narrowp);
+}
+__ sw(T9, AT, 0);
+}
+}
+%}
 enc_class load_L_enc (mRegL dst, memory mem) %{
 MacroAssembler _masm(&cbuf);
 int  base = $mem$$base;
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
 Register  dst_reg = as_Register($dst$$reg);
+// For implicit null check
+__ lb(AT, as_Register(base), 0);
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if (scale == 0) {
-__ gsldx(dst_reg, as_Register(base), as_Register(index), disp);
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+if( Assembler::is_simm16(disp) ) {
+__ ld(dst_reg, AT, disp);
+} else {
+__ move(T9, disp);
+__ daddu(AT, AT, T9);
+__ ld(dst_reg, AT, 0);
+}
 } else {
-__ ld(dst_reg, as_Register(base), disp);
+if( Assembler::is_simm16(disp) ) {
+__ ld(dst_reg, as_Register(base), disp);
+} else {
+__ move(T9, disp);
+__ daddu(AT, as_Register(base), T9);
+__ ld(dst_reg, AT, 0);
+}
 }
 %}
 enc_class store_L_reg_enc (memory mem, mRegL src) %{
 MacroAssembler _masm(&cbuf);
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
 Register  src_reg = as_Register($src$$reg);
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if (scale == 0) {
-__ gssdx(src_reg, as_Register(base), as_Register(index), disp);
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+if( Assembler::is_simm16(disp) ) {
+__ sd(src_reg, AT, disp);
+} else {
+__ move(T9, disp);
+__ daddu(AT, AT, T9);
+__ sd(src_reg, AT, 0);
+}
 } else {
-__ sd(src_reg, as_Register(base), disp);
+if( Assembler::is_simm16(disp) ) {
+__ sd(src_reg, as_Register(base), disp);
+} else {
+__ move(T9, disp);
+__ daddu(AT, as_Register(base), T9);
+__ sd(src_reg, AT, 0);
+}
 }
 %}
-enc_class store_L_immL0_enc (memory mem) %{
+enc_class store_L_immL0_enc (memory mem, immL0 src) %{
 MacroAssembler _masm(&cbuf);
 int  base = $mem$$base;
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+// For implicit null check
-__ gssdx(R0, as_Register(base), as_Register(index), disp);
+__ lb(AT, as_Register(base), 0);
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+if( Assembler::is_simm16(disp) ) {
+__ sd(R0, AT, disp);
+} else {
+__ move(T9, disp);
+__ addu(AT, AT, T9);
+__ sd(R0, AT, 0);
+}
 } else {
-__ sd(R0, as_Register(base), disp);
+if( Assembler::is_simm16(disp) ) {
+__ sd(R0, as_Register(base), disp);
+} else {
+__ move(T9, disp);
+__ addu(AT, as_Register(base), T9);
+__ sd(R0, AT, 0);
+}
+}
+%}
+enc_class store_L_immL_enc (memory mem, immL src) %{
+MacroAssembler _masm(&cbuf);
+int  base = $mem$$base;
+int  index = $mem$$index;
+int  scale = $mem$$scale;
+int  disp = $mem$$disp;
+long  imm = $src$$constant;
+if( index != 0 ) {
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+if( Assembler::is_simm16(disp) ) {
+__ set64(T9, imm);
+__ sd(T9, AT, disp);
+} else {
+__ move(T9, disp);
+__ addu(AT, AT, T9);
+__ set64(T9, imm);
+__ sd(T9, AT, 0);
+}
+} else {
+if( Assembler::is_simm16(disp) ) {
+__ move(AT, as_Register(base));
+__ set64(T9, imm);
+__ sd(T9, AT, disp);
+} else {
+__ move(T9, disp);
+__ addu(AT, as_Register(base), T9);
+__ set64(T9, imm);
+__ sd(T9, AT, 0);
+}
 }
 %}
 enc_class load_F_enc (regF dst, memory mem) %{
 MacroAssembler _masm(&cbuf);
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
 FloatRegister dst = $dst$$FloatRegister;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if( Assembler::is_simm16(disp) ) {
-__ gslwxc1(dst, as_Register(base), as_Register(index), disp);
+if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
+if (scale == 0) {
+__ gslwxc1(dst, as_Register(base), as_Register(index), disp);
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ gslwxc1(dst, as_Register(base), AT, disp);
+}
+} else {
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+__ lwc1(dst, AT, disp);
+}
+} else {
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gslwxc1(dst, AT, T9, 0);
+} else {
+__ daddu(AT, AT, T9);
+__ lwc1(dst, AT, 0);
+}
+}
 } else {
-__ lwc1(dst, as_Register(base), disp);
+if( Assembler::is_simm16(disp) ) {
+__ lwc1(dst, as_Register(base), disp);
+} else {
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gslwxc1(dst, as_Register(base), T9, 0);
+} else {
+__ daddu(AT, as_Register(base), T9);
+__ lwc1(dst, AT, 0);
+}
+}
 }
 %}
 enc_class store_F_reg_enc (memory mem, regF src) %{
 MacroAssembler _masm(&cbuf);
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
 FloatRegister src = $src$$FloatRegister;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if( Assembler::is_simm16(disp) ) {
-__ gsswxc1(src, as_Register(base), as_Register(index), disp);
+if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
+if (scale == 0) {
+__ gsswxc1(src, as_Register(base), as_Register(index), disp);
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ gsswxc1(src, as_Register(base), AT, disp);
+}
+} else {
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+__ swc1(src, AT, disp);
+}
+} else {
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gsswxc1(src, AT, T9, 0);
+} else {
+__ daddu(AT, AT, T9);
+__ swc1(src, AT, 0);
+}
+}
 } else {
-__ swc1(src, as_Register(base), disp);
+if( Assembler::is_simm16(disp) ) {
+__ swc1(src, as_Register(base), disp);
+} else {
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gslwxc1(src, as_Register(base), T9, 0);
+} else {
+__ daddu(AT, as_Register(base), T9);
+__ swc1(src, AT, 0);
+}
+}
 }
 %}
 enc_class load_D_enc (regD dst, memory mem) %{
 MacroAssembler _masm(&cbuf);
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if( Assembler::is_simm16(disp) ) {
-__ gsldxc1(dst_reg, as_Register(base), as_Register(index), disp);
+if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
+if (scale == 0) {
+__ gsldxc1(dst_reg, as_Register(base), as_Register(index), disp);
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ gsldxc1(dst_reg, as_Register(base), AT, disp);
+}
+} else {
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+__ ldc1(dst_reg, AT, disp);
+}
+} else {
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gsldxc1(dst_reg, AT, T9, 0);
+} else {
+__ addu(AT, AT, T9);
+__ ldc1(dst_reg, AT, 0);
+}
+}
 } else {
-__ ldc1(dst_reg, as_Register(base), disp);
+if( Assembler::is_simm16(disp) ) {
+__ ldc1(dst_reg, as_Register(base), disp);
+} else {
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gsldxc1(dst_reg, as_Register(base), T9, 0);
+} else {
+__ addu(AT, as_Register(base), T9);
+__ ldc1(dst_reg, AT, 0);
+}
+}
 }
 %}
 enc_class store_D_reg_enc (memory mem, regD src) %{
 MacroAssembler _masm(&cbuf);
-int  base  = $mem$$base;
+int  base = $mem$$base;
 int  index = $mem$$index;
 int  scale = $mem$$scale;
-int  disp  = $mem$$disp;
+int  disp = $mem$$disp;
 FloatRegister src_reg = as_FloatRegister($src$$reg);
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if( Assembler::is_simm16(disp) ) {
-__ gssdxc1(src_reg, as_Register(base), as_Register(index), disp);
+if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
+if (scale == 0) {
+__ gssdxc1(src_reg, as_Register(base), as_Register(index), disp);
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ gssdxc1(src_reg, as_Register(base), AT, disp);
+}
+} else {
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+__ sdc1(src_reg, AT, disp);
+}
+} else {
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gssdxc1(src_reg, AT, T9, 0);
+} else {
+__ addu(AT, AT, T9);
+__ sdc1(src_reg, AT, 0);
+}
+}
 } else {
-__ sdc1(src_reg, as_Register(base), disp);
+if( Assembler::is_simm16(disp) ) {
+__ sdc1(src_reg, as_Register(base), disp);
+} else {
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gssdxc1(src_reg, as_Register(base), T9, 0);
+} else {
+__ addu(AT, as_Register(base), T9);
+__ sdc1(src_reg, AT, 0);
+}
+}
 }
 %}
 enc_class Java_To_Runtime (method meth) %{    // CALL Java_To_Runtime, Java_To_Runtime_Leaf
 MacroAssembler _masm(&cbuf);
 op_cost(10);
 format %{ %}
 interface(CONST_INTER);
 %}
+operand immP31()
+%{
+predicate(n->as_Type()->type()->reloc() == relocInfo::none
+&& (n->get_ptr() >> 31) == 0);
+match(ConP);
+op_cost(5);
+format %{ %}
+interface(CONST_INTER);
+%}
 // NULL Pointer Immediate
 operand immP0() %{
 predicate( n->get_ptr() == 0 );
 match(ConP);
 op_cost(0);
 format %{ %}
 interface(REG_INTER);
 %}
 //----------Memory Operands----------------------------------------------------
-operand baseOffset16(mRegP reg, immL16 off)
+// Indirect Memory Operand
+operand indirect(mRegP reg) %{
+constraint(ALLOC_IN_RC(p_reg));
+match(reg);
+format %{ "[$reg] @ indirect" %}
+interface(MEMORY_INTER) %{
+base($reg);
+index(0x0);	/* NO_INDEX */
+scale(0x0);
+disp(0x0);
+%}
+%}
+// Indirect Memory Plus Short Offset Operand
+operand indOffset8(mRegP reg, immL8 off)
 %{
 constraint(ALLOC_IN_RC(p_reg));
 match(AddP reg off);
+op_cost(10);
+format %{ "[$reg + $off (8-bit)] @ indOffset8" %}
+interface(MEMORY_INTER) %{
+base($reg);
+index(0x0); /* NO_INDEX */
+scale(0x0);
+disp($off);
+%}
+%}
+// Indirect Memory Times Scale Plus Index Register
+operand indIndexScale(mRegP reg, mRegL lreg, immI2 scale)
+%{
+constraint(ALLOC_IN_RC(p_reg));
+match(AddP reg (LShiftL lreg scale));
+op_cost(10);
+format %{"[$reg + $lreg << $scale] @ indIndexScale" %}
+interface(MEMORY_INTER) %{
+base($reg);
+index($lreg);
+scale($scale);
+disp(0x0);
+%}
+%}
+// [base + index + offset]
+operand baseIndexOffset8(mRegP base, mRegL index, immL8 off)
+%{
+constraint(ALLOC_IN_RC(p_reg));
 op_cost(5);
-format %{ "[$reg + $off (16-bit)] @ baseOffset16" %}
+match(AddP (AddP base index) off);
+format %{ "[$base + $index + $off (8-bit)] @ baseIndexOffset8" %}
+interface(MEMORY_INTER) %{
+base($base);
+index($index);
+scale(0x0);
+disp($off);
+%}
+%}
+// [base + index + offset]
+operand baseIndexOffset8_convI2L(mRegP base, mRegI index, immL8 off)
+%{
+constraint(ALLOC_IN_RC(p_reg));
+op_cost(5);
+match(AddP (AddP base (ConvI2L index)) off);
+format %{ "[$base + $index + $off (8-bit)] @ baseIndexOffset8_convI2L" %}
+interface(MEMORY_INTER) %{
+base($base);
+index($index);
+scale(0x0);
+disp($off);
+%}
+%}
+// Indirect Memory Times Scale Plus Index Register Plus Offset Operand
+operand indIndexScaleOffset8(mRegP reg, immL8 off, mRegL lreg, immI2 scale)
+%{
+constraint(ALLOC_IN_RC(p_reg));
+match(AddP (AddP reg (LShiftL lreg scale)) off);
+op_cost(10);
+format %{"[$reg + $off + $lreg << $scale] @ indIndexScaleOffset8" %}
+interface(MEMORY_INTER) %{
+base($reg);
+index($lreg);
+scale($scale);
+disp($off);
+%}
+%}
+operand indIndexScaleOffset8_convI2L(mRegP reg, immL8 off, mRegI ireg, immI2 scale)
+%{
+constraint(ALLOC_IN_RC(p_reg));
+match(AddP (AddP reg (LShiftL (ConvI2L ireg) scale)) off);
+op_cost(10);
+format %{"[$reg + $off + $ireg << $scale] @ indIndexScaleOffset8_convI2L" %}
+interface(MEMORY_INTER) %{
+base($reg);
+index($ireg);
+scale($scale);
+disp($off);
+%}
+%}
+// [base + index<<scale + offset]
+operand basePosIndexScaleOffset8(mRegP base, mRegI index, immL8 off, immI_0_31 scale)
+%{
+constraint(ALLOC_IN_RC(p_reg));
+//predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
+op_cost(10);
+match(AddP (AddP base (LShiftL (ConvI2L index) scale)) off);
+format %{ "[$base + $index << $scale + $off (8-bit)] @ basePosIndexScaleOffset8" %}
+interface(MEMORY_INTER) %{
+base($base);
+index($index);
+scale($scale);
+disp($off);
+%}
+%}
+// Indirect Memory Times Scale Plus Index Register Plus Offset Operand
+operand indIndexScaleOffsetNarrow(mRegN reg, immL8 off, mRegL lreg, immI2 scale)
+%{
+predicate(Universe::narrow_oop_shift() == 0);
+constraint(ALLOC_IN_RC(p_reg));
+match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
+op_cost(10);
+format %{"[$reg + $off + $lreg << $scale] @ indIndexScaleOffsetNarrow" %}
+interface(MEMORY_INTER) %{
+base($reg);
+index($lreg);
+scale($scale);
+disp($off);
+%}
+%}
+// [base + index<<scale + offset] for compressd Oops
+operand indPosIndexI2LScaleOffset8Narrow(mRegN base, mRegI index, immL8 off, immI_0_31 scale)
+%{
+constraint(ALLOC_IN_RC(p_reg));
+//predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
+predicate(Universe::narrow_oop_shift() == 0);
+op_cost(10);
+match(AddP (AddP (DecodeN base) (LShiftL (ConvI2L index) scale)) off);
+format %{ "[$base + $index << $scale + $off (8-bit)] @ indPosIndexI2LScaleOffset8Narrow" %}
+interface(MEMORY_INTER) %{
+base($base);
+index($index);
+scale($scale);
+disp($off);
+%}
+%}
+//FIXME: I think it's better to limit the immI to be 16-bit at most!
+// Indirect Memory Plus Long Offset Operand
+operand indOffset32(mRegP reg, immL32 off) %{
+constraint(ALLOC_IN_RC(p_reg));
+op_cost(20);
+match(AddP reg off);
+format %{ "[$reg + $off (32-bit)] @ indOffset32" %}
+interface(MEMORY_INTER) %{
+base($reg);
+index(0x0); 	/* NO_INDEX */
+scale(0x0);
+disp($off);
+%}
+%}
+// Indirect Memory Plus Index Register
+operand indIndex(mRegP addr, mRegL index) %{
+constraint(ALLOC_IN_RC(p_reg));
+match(AddP addr index);
+op_cost(20);
+format %{"[$addr + $index] @ indIndex" %}
+interface(MEMORY_INTER) %{
+base($addr);
+index($index);
+scale(0x0);
+disp(0x0);
+%}
+%}
+operand indirectNarrowKlass(mRegN reg)
+%{
+predicate(Universe::narrow_klass_shift() == 0);
+constraint(ALLOC_IN_RC(p_reg));
+op_cost(10);
+match(DecodeNKlass reg);
+format %{ "[$reg] @ indirectNarrowKlass" %}
+interface(MEMORY_INTER) %{
+base($reg);
+index(0x0);
+scale(0x0);
+disp(0x0);
+%}
+%}
+operand indOffset8NarrowKlass(mRegN reg, immL8 off)
+%{
+predicate(Universe::narrow_klass_shift() == 0);
+constraint(ALLOC_IN_RC(p_reg));
+op_cost(10);
+match(AddP (DecodeNKlass reg) off);
+format %{ "[$reg + $off (8-bit)] @ indOffset8NarrowKlass" %}
 interface(MEMORY_INTER) %{
 base($reg);
 index(0x0);
 scale(0x0);
 disp($off);
 %}
 %}
-operand gsBaseIndexOffset8(mRegP base, mRegL index, immL8 off)
+operand indOffset32NarrowKlass(mRegN reg, immL32 off)
 %{
-predicate(UseLoongsonISA);
+predicate(Universe::narrow_klass_shift() == 0);
 constraint(ALLOC_IN_RC(p_reg));
-match(AddP (AddP base index) off);
+op_cost(10);
+match(AddP (DecodeNKlass reg) off);
-op_cost(5);
-format %{ "[$base + $index + $off (8-bit)] @ gsBaseIndexOffset8" %}
+format %{ "[$reg + $off (32-bit)] @ indOffset32NarrowKlass" %}
 interface(MEMORY_INTER) %{
-base($base);
+base($reg);
-index($index);
+index(0x0);
 scale(0x0);
 disp($off);
 %}
 %}
-operand gsBaseIndexI2LOffset8(mRegP base, mRegI index, immL8 off)
+operand indIndexOffsetNarrowKlass(mRegN reg, mRegL lreg, immL32 off)
 %{
-predicate(UseLoongsonISA);
+predicate(Universe::narrow_klass_shift() == 0);
 constraint(ALLOC_IN_RC(p_reg));
-match(AddP (AddP base (ConvI2L index)) off);
+match(AddP (AddP (DecodeNKlass reg) lreg) off);
-op_cost(5);
+op_cost(10);
-format %{ "[$base + $index + $off (8-bit)] @ gsBaseIndexI2LOffset8" %}
+format %{"[$reg + $off + $lreg] @ indIndexOffsetNarrowKlass" %}
 interface(MEMORY_INTER) %{
-base($base);
+base($reg);
-index($index);
+index($lreg);
 scale(0x0);
 disp($off);
 %}
 %}
-operand gsBaseIndexOffset0(mRegP addr, mRegL index) %{
+operand indIndexNarrowKlass(mRegN reg, mRegL lreg)
-predicate(UseLoongsonISA);
+%{
+predicate(Universe::narrow_klass_shift() == 0);
 constraint(ALLOC_IN_RC(p_reg));
-match(AddP addr index);
+match(AddP (DecodeNKlass reg) lreg);
 op_cost(10);
-format %{"[$addr + $index] @ gsBaseIndexOffset0" %}
+format %{"[$reg + $lreg] @ indIndexNarrowKlass" %}
 interface(MEMORY_INTER) %{
-base($addr);
+base($reg);
-index($index);
+index($lreg);
 scale(0x0);
 disp(0x0);
 %}
 %}
-operand baseOffset0(mRegP reg) %{
+// Indirect Memory Operand
+operand indirectNarrow(mRegN reg)
+%{
+predicate(Universe::narrow_oop_shift() == 0);
 constraint(ALLOC_IN_RC(p_reg));
 op_cost(10);
-match(reg);
+match(DecodeN reg);
-format %{ "[$reg] @ baseOffset0" %}
+format %{ "[$reg] @ indirectNarrow" %}
 interface(MEMORY_INTER) %{
 base($reg);
 index(0x0);
 scale(0x0);
 disp(0x0);
 %}
 %}
-operand baseOffset16Narrow(mRegN reg, immL16 off)
+// Indirect Memory Plus Short Offset Operand
+operand indOffset8Narrow(mRegN reg, immL8 off)
 %{
-predicate(Universe::narrow_oop_base() == 0 && Universe::narrow_oop_shift() == 0);
+predicate(Universe::narrow_oop_shift() == 0);
 constraint(ALLOC_IN_RC(p_reg));
+op_cost(10);
 match(AddP (DecodeN reg) off);
-op_cost(5);
+format %{ "[$reg + $off (8-bit)] @ indOffset8Narrow" %}
-format %{ "[$reg + $off (16-bit)] @ baseOffset16Narrow" %}
 interface(MEMORY_INTER) %{
 base($reg);
 index(0x0);
 scale(0x0);
 disp($off);
 %}
 %}
-operand gsBaseIndexOffset8Narrow(mRegN reg, mRegL lreg, immL8 off)
+// Indirect Memory Plus Index Register Plus Offset Operand
+operand indIndexOffset8Narrow(mRegN reg, mRegL lreg, immL8 off)
 %{
-predicate(UseLoongsonISA && Universe::narrow_oop_base() == 0 && Universe::narrow_oop_shift() == 0);
+predicate(Universe::narrow_oop_shift() == 0);
 constraint(ALLOC_IN_RC(p_reg));
 match(AddP (AddP (DecodeN reg) lreg) off);
-op_cost(5);
+op_cost(10);
-format %{"[$reg + $off + $lreg] @ gsBaseIndexOffset8Narrow" %}
+format %{"[$reg + $off + $lreg] @ indIndexOffset8Narrow" %}
 interface(MEMORY_INTER) %{
 base($reg);
 index($lreg);
 scale(0x0);
 disp($off);
 %}
 %}
-operand baseOffset0Narrow(mRegN reg)
+//----------Load Long Memory Operands------------------------------------------
-%{
+// The load-long idiom will use it's address expression again after loading
-predicate(Universe::narrow_oop_base() == 0 && Universe::narrow_oop_shift() == 0);
+// the first word of the long.  If the load-long destination overlaps with
+// registers used in the addressing expression, the 2nd half will be loaded
+// from a clobbered address.  Fix this by requiring that load-long use
+// address registers that do not overlap with the load-long target.
+// load-long support
+operand load_long_RegP() %{
 constraint(ALLOC_IN_RC(p_reg));
-match(DecodeN reg);
+match(RegP);
+match(mRegP);
-op_cost(10);
+op_cost(100);
-format %{ "[$reg] @ baseOffset0Narrow" %}
+format %{  %}
+interface(REG_INTER);
+%}
+// Indirect Memory Operand Long
+operand load_long_indirect(load_long_RegP reg) %{
+constraint(ALLOC_IN_RC(p_reg));
+match(reg);
+format %{ "[$reg]" %}
 interface(MEMORY_INTER) %{
 base($reg);
 index(0x0);
 scale(0x0);
 disp(0x0);
 %}
 %}
-operand baseOffset16NarrowKlass(mRegN reg, immL16 off)
+// Indirect Memory Plus Long Offset Operand
-%{
+operand load_long_indOffset32(load_long_RegP reg, immL32 off) %{
-predicate(Universe::narrow_klass_base() == 0 && Universe::narrow_klass_shift() == 0);
+match(AddP reg off);
-constraint(ALLOC_IN_RC(p_reg));
-match(AddP (DecodeNKlass reg) off);
+format %{ "[$reg + $off]" %}
-op_cost(5);
-format %{ "[$reg + $off (16-bit)] @ baseOffset16NarrowKlass" %}
 interface(MEMORY_INTER) %{
 base($reg);
 index(0x0);
 scale(0x0);
 disp($off);
 %}
 %}
-operand baseOffset0NarrowKlass(mRegN reg)
-%{
-predicate(Universe::narrow_klass_base() == 0 && Universe::narrow_klass_shift() == 0);
-constraint(ALLOC_IN_RC(p_reg));
-match(DecodeNKlass reg);
-op_cost(10);
-format %{ "[$reg] @ baseOffset0NarrowKlass" %}
-interface(MEMORY_INTER) %{
-base($reg);
-index(0x0);
-scale(0x0);
-disp(0x0);
-%}
-%}
-operand gsBaseIndexOffset8NarrowKlass(mRegN reg, mRegL lreg, immL8 off)
-%{
-predicate(UseLoongsonISA && Universe::narrow_klass_base() == 0 && Universe::narrow_klass_shift() == 0);
-constraint(ALLOC_IN_RC(p_reg));
-match(AddP (AddP (DecodeNKlass reg) lreg) off);
-op_cost(5);
-format %{"[$reg + $off + $lreg] @ gsBaseIndexOffset8NarrowKlass" %}
-interface(MEMORY_INTER) %{
-base($reg);
-index($lreg);
-scale(0x0);
-disp($off);
-%}
-%}
-operand gsBaseIndexOffset0NarrowKlass(mRegN reg, mRegL lreg)
-%{
-predicate(UseLoongsonISA && Universe::narrow_klass_base() == 0 && Universe::narrow_klass_shift() == 0);
-constraint(ALLOC_IN_RC(p_reg));
-match(AddP (DecodeNKlass reg) lreg);
-op_cost(10);
-format %{"[$reg + $lreg] @ gsBaseIndexOffset0NarrowKlass" %}
-interface(MEMORY_INTER) %{
-base($reg);
-index($lreg);
-scale(0x0);
-disp(0x0);
-%}
-%}
-//------------------------OPERAND CLASSES--------------------------------------
-opclass memory(
-baseOffset16,
-gsBaseIndexOffset8,
-gsBaseIndexI2LOffset8,
-gsBaseIndexOffset0,
-baseOffset0,
-baseOffset16Narrow,
-gsBaseIndexOffset8Narrow,
-baseOffset0Narrow,
-baseOffset16NarrowKlass,
-baseOffset0NarrowKlass,
-gsBaseIndexOffset8NarrowKlass,
-gsBaseIndexOffset0NarrowKlass
-);
-// For loading unsigned values
-// umemory --> unsigned memory
-opclass umemory(
-baseOffset16,
-baseOffset0,
-baseOffset16Narrow,
-baseOffset0Narrow,
-baseOffset16NarrowKlass,
-baseOffset0NarrowKlass
-);
 //----------Conditional Branch Operands----------------------------------------
 // Comparison Op  - This is the operation of the comparison, and is limited to
 //                  the following set of codes:
 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
 overflow(0x7);
 no_overflow(0x8);
 %}
 %}
+/*
+// Comparison Code, unsigned compare.  Used by FP also, with
+// C2 (unordered) turned into GT or LT already.  The other bits
+// C0 and C3 are turned into Carry & Zero flags.
+operand cmpOpU() %{
+match(Bool);
+format %{ "" %}
+interface(COND_INTER) %{
+equal(0x4);
+not_equal(0x5);
+less(0x2);
+greater_equal(0x3);
+less_equal(0x6);
+greater(0x7);
+%}
+%}
+*/
+/*
+// Comparison Code for FP conditional move
+operand cmpOp_fcmov() %{
+match(Bool);
+format %{ "" %}
+interface(COND_INTER) %{
+equal        (0x01);
+not_equal    (0x02);
+greater      (0x03);
+greater_equal(0x04);
+less         (0x05);
+less_equal   (0x06);
+%}
+%}
+// Comparision Code used in long compares
+operand cmpOp_commute() %{
+match(Bool);
+format %{ "" %}
+interface(COND_INTER) %{
+equal(0x4);
+not_equal(0x5);
+less(0xF);
+greater_equal(0xE);
+less_equal(0xD);
+greater(0xC);
+%}
+%}
+*/
 //----------Special Memory Operands--------------------------------------------
 // Stack Slot Operand - This operand is used for loading and storing temporary
 //                      values on the stack where a match requires a value to
 //                      flow through memory.
 index(0x0);  // No Index
 scale(0x0);  // No Scale
 disp($reg);  // Stack Offset
 %}
 %}
+//------------------------OPERAND CLASSES--------------------------------------
+//opclass memory( direct, indirect, indOffset16, indOffset32, indOffset32X, indIndexOffset );
+opclass memory( indirect, indirectNarrow, indOffset8, indOffset32, indIndex, indIndexScale, load_long_indirect, load_long_indOffset32, baseIndexOffset8, baseIndexOffset8_convI2L, indIndexScaleOffset8, indIndexScaleOffset8_convI2L, basePosIndexScaleOffset8, indIndexScaleOffsetNarrow, indPosIndexI2LScaleOffset8Narrow, indOffset8Narrow, indIndexOffset8Narrow);
 //----------PIPELINE-----------------------------------------------------------
 // Rules which define the behavior of the target architectures pipeline.
 pipeline %{
 ins_encode(load_B_enc(dst, mem));
 ins_pipe(ialu_loadI);
 %}
 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
-instruct loadI2UB(mRegI dst, umemory mem, immI_255 mask) %{
+instruct loadI2UB(mRegI dst, memory mem, immI_255 mask) %{
 match(Set dst (AndI (LoadI mem) mask));
 ins_cost(125);
 format %{ "lbu  $dst, $mem\t# int -> ubyte #@loadI2UB" %}
 ins_encode(load_UB_enc(dst, mem));
 ins_encode(load_S_enc(dst, mem));
 ins_pipe(ialu_loadI);
 %}
 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
-instruct loadI2US(mRegI dst, umemory mem, immI_65535 mask) %{
+instruct loadI2US(mRegI dst, memory mem, immI_65535 mask) %{
 match(Set dst (AndI (LoadI mem) mask));
 ins_cost(125);
 format %{ "lhu  $dst, $mem\t# int -> ushort/char #@loadI2US" %}
 ins_encode(load_C_enc(dst, mem));
 format %{ "sd    $mem,   $src #@storeL_reg\n" %}
 ins_encode(store_L_reg_enc(mem, src));
 ins_pipe( ialu_storeL );
 %}
 instruct storeL_immL0(memory mem, immL0 zero) %{
 match(Set mem (StoreL mem zero));
 ins_cost(180);
-format %{ "sd    $mem,   zero #@storeL_immL0" %}
+format %{ "sd    zero, $mem #@storeL_immL0" %}
-ins_encode(store_L_immL0_enc(mem));
+ins_encode(store_L_immL0_enc(mem, zero));
 ins_pipe( ialu_storeL );
 %}
+instruct storeL_imm(memory mem, immL src) %{
+match(Set mem (StoreL mem src));
+ins_cost(200);
+format %{ "sd    $src, $mem #@storeL_imm" %}
+ins_encode(store_L_immL_enc(mem, src));
+ins_pipe( ialu_storeL );
+%}
 // Load Compressed Pointer
-instruct loadN(mRegN dst, umemory mem)
+instruct loadN(mRegN dst, memory mem)
 %{
 match(Set dst (LoadN mem));
 ins_cost(125); // XXX
 format %{ "lwu    $dst, $mem\t# compressed ptr @ loadN" %}
 ins_encode (load_N_enc(dst, mem));
 ins_pipe( ialu_loadI ); // XXX
 %}
-instruct loadN2P(mRegP dst, umemory mem)
+instruct loadN2P(mRegP dst, memory mem)
 %{
 match(Set dst (DecodeN (LoadN mem)));
 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0);
 ins_cost(125); // XXX
 ins_encode (load_P_enc(dst, mem));
 ins_pipe( ialu_loadI );
 %}
 // Load narrow Klass Pointer
-instruct loadNKlass(mRegN dst, umemory mem)
+instruct loadNKlass(mRegN dst, memory mem)
 %{
 match(Set dst (LoadNKlass mem));
 ins_cost(125); // XXX
 format %{ "lwu    $dst, $mem\t# compressed klass ptr @ loadNKlass" %}
 ins_encode (load_N_enc(dst, mem));
 ins_pipe( ialu_loadI ); // XXX
 %}
-instruct loadN2PKlass(mRegP dst, umemory mem)
+instruct loadN2PKlass(mRegP dst, memory mem)
 %{
 match(Set dst (DecodeNKlass (LoadNKlass mem)));
 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
 ins_cost(125); // XXX
 format %{ "mov    $mem, $zero #@storeImmP0" %}
 ins_encode(store_P_immP0_enc(mem));
 ins_pipe( ialu_storeI );
 %}
+// Store NULL Pointer, mark word, or other simple pointer constant.
+instruct storeImmP(memory mem, immP31 src) %{
+match(Set mem (StoreP mem src));
+ins_cost(150);
+format %{ "mov    $mem, $src #@storeImmP" %}
+ins_encode(store_P_immP_enc(mem, src));
+ins_pipe( ialu_storeI );
+%}
+// Store Byte Immediate
+instruct storeImmB(memory mem, immI8 src) %{
+match(Set mem (StoreB mem src));
+ins_cost(150);
+format %{ "movb   $mem, $src #@storeImmB" %}
+ins_encode(store_B_immI_enc(mem, src));
+ins_pipe( ialu_storeI );
+%}
 // Store Compressed Pointer
 instruct storeN(memory mem, mRegN src)
 %{
 match(Set mem (StoreN mem src));
 instruct storeImmN0(memory mem, immN0 zero)
 %{
 match(Set mem (StoreN mem zero));
 ins_cost(125); // XXX
-format %{ "storeN0    $mem, R12\t# compressed ptr" %}
+format %{ "storeN0    zero, $mem\t# compressed ptr" %}
-ins_encode(storeImmN0_enc(mem));
+ins_encode(storeImmN0_enc(mem, zero));
+ins_pipe( ialu_storeI );
+%}
+instruct storeImmN(memory mem, immN src)
+%{
+match(Set mem (StoreN mem src));
+ins_cost(150);
+format %{ "storeImmN    $mem, $src\t# compressed ptr @ storeImmN" %}
+ins_encode(storeImmN_enc(mem, src));
+ins_pipe( ialu_storeI );
+%}
+instruct storeImmNKlass(memory mem, immNKlass src)
+%{
+match(Set mem (StoreNKlass mem src));
+ins_cost(150); // XXX
+format %{ "sw    $mem, $src\t# compressed klass ptr @ storeImmNKlass" %}
+ins_encode(storeImmNKlass_enc(mem, src));
 ins_pipe( ialu_storeI );
 %}
 // Store Byte
 instruct storeB(memory mem, mRegI src) %{
 format %{ "sb    $src, $mem #@storeB" %}
 ins_encode(store_B_reg_enc(mem, src));
 ins_pipe( ialu_storeI );
 %}
-instruct storeB0(memory mem, immI0 zero) %{
-match(Set mem (StoreB mem zero));
-ins_cost(100);
-format %{ "sb    $zero, $mem #@storeB0" %}
-ins_encode(store_B0_enc(mem));
-ins_pipe( ialu_storeI );
-%}
 instruct storeB_convL2I(memory mem, mRegL src) %{
 match(Set mem (StoreB mem (ConvL2I src)));
 ins_cost(125);
 format %{ "sb    $src, $mem #@storeB_convL2I" %}
 ins_encode(load_B_enc(dst, mem));
 ins_pipe( ialu_loadI );
 %}
 // Load Byte (8bit UNsigned)
-instruct loadUB(mRegI dst, umemory mem) %{
+instruct loadUB(mRegI dst, memory mem) %{
 match(Set dst (LoadUB mem));
 ins_cost(125);
 format %{ "lbu   $dst, $mem #@loadUB" %}
 ins_encode(load_UB_enc(dst, mem));
 ins_pipe( ialu_loadI );
 %}
-instruct loadUB_convI2L(mRegL dst, umemory mem) %{
+instruct loadUB_convI2L(mRegL dst, memory mem) %{
 match(Set dst (ConvI2L (LoadUB mem)));
 ins_cost(125);
 format %{ "lbu   $dst, $mem #@loadUB_convI2L" %}
 ins_encode(load_UB_enc(dst, mem));
 ins_encode(load_S_enc(dst, mem));
 ins_pipe( ialu_loadI );
 %}
 // Store Integer Immediate
-instruct storeI0(memory mem, immI0 zero) %{
+instruct storeImmI(memory mem, immI src) %{
-match(Set mem (StoreI mem zero));
+match(Set mem (StoreI mem src));
-ins_cost(100);
+ins_cost(150);
-format %{ "sw    $mem, $zero #@storeI0" %}
+format %{ "mov    $mem, $src #@storeImmI" %}
-ins_encode(store_I_immI0_enc(mem));
+ins_encode(store_I_immI_enc(mem, src));
 ins_pipe( ialu_storeI );
 %}
 // Store Integer
 instruct storeI(memory mem, mRegI src) %{
 %}
 ins_pipe( ialu_regI_regI );
 %}
 */
-instruct lbu_and_lmask(mRegI dst, umemory mem,  immI_255 mask) %{
+instruct lbu_and_lmask(mRegI dst, memory mem,  immI_255 mask) %{
 match(Set dst (AndI mask (LoadB mem)));
 ins_cost(60);
-format %{ "lbu  $dst, $mem #@lbu_and_lmask" %}
+format %{ "lhu  $dst, $mem #@lbu_and_lmask" %}
 ins_encode(load_UB_enc(dst, mem));
 ins_pipe( ialu_loadI );
 %}
-instruct lbu_and_rmask(mRegI dst, umemory mem,  immI_255 mask) %{
+instruct lbu_and_rmask(mRegI dst, memory mem,  immI_255 mask) %{
 match(Set dst (AndI (LoadB mem) mask));
 ins_cost(60);
-format %{ "lbu  $dst, $mem #@lbu_and_rmask" %}
+format %{ "lhu  $dst, $mem #@lbu_and_rmask" %}
 ins_encode(load_UB_enc(dst, mem));
 ins_pipe( ialu_loadI );
 %}
 instruct andI_Reg_Reg(mRegI dst, mRegI src1,  mRegI src2) %{
 ins_alignment(16);
 %}
 // Prefetch instructions.
-instruct prefetchrNTA( umemory mem ) %{
+instruct prefetchrNTA( memory mem ) %{
 match(PrefetchRead mem);
 ins_cost(125);
 format %{ "pref $mem\t# Prefetch into non-temporal cache for read @ prefetchrNTA" %}
 ins_encode %{
 int  base = $mem$$base;
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
-assert(index == 0, "no index");
+if( index != 0 ) {
-__ daddiu(AT, as_Register(base), disp);
+if (scale == 0) {
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+} else {
+__ move(AT, as_Register(base));
+}
+if( Assembler::is_simm16(disp) ) {
+__ daddiu(AT, as_Register(base), disp);
+__ daddiu(AT, AT, disp);
+} else {
+__ move(T9, disp);
+__ daddu(AT, as_Register(base), T9);
+}
 __ pref(0, AT, 0); //hint: 0:load
 %}
 ins_pipe(pipe_slow);
 %}
-instruct prefetchwNTA( umemory mem ) %{
+instruct prefetchwNTA( memory mem ) %{
 match(PrefetchWrite mem);
 ins_cost(125);
 format %{ "pref $mem\t# Prefetch to non-temporal cache for write @ prefetchwNTA" %}
 ins_encode %{
 int  base = $mem$$base;
 int  index = $mem$$index;
 int  scale = $mem$$scale;
 int  disp = $mem$$disp;
-assert(index == 0, "no index");
+if( index != 0 ) {
-__ daddiu(AT, as_Register(base), disp);
+if (scale == 0) {
-__ pref(1, AT, 0); //hint: 1:store
+__ daddu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ daddu(AT, as_Register(base), AT);
+}
+} else {
+__ move(AT, as_Register(base));
+}
+if( Assembler::is_simm16(disp) ) {
+__ daddiu(AT, as_Register(base), disp);
+__ daddiu(AT, AT, disp);
+} else {
+__ move(T9, disp);
+__ daddu(AT, as_Register(base), T9);
+}
+__ pref(1, AT, 0); //hint: 1:store
 %}
 ins_pipe(pipe_slow);
 %}
 // Prefetch instructions for allocation.
 int  disp = $mem$$disp;
 Register dst = R0;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+if( Assembler::is_simm16(disp) ) {
-__ gslbx(dst, as_Register(base), as_Register(index), disp);
+if( UseLoongsonISA ) {
+if (scale == 0) {
+__ gslbx(dst, as_Register(base), as_Register(index), disp);
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ gslbx(dst, as_Register(base), AT, disp);
+}
+} else {
+if (scale == 0) {
+__ addu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ addu(AT, as_Register(base), AT);
+}
+__ lb(dst, AT, disp);
+}
+} else {
+if (scale == 0) {
+__ addu(AT, as_Register(base), as_Register(index));
+} else {
+__ dsll(AT, as_Register(index), scale);
+__ addu(AT, as_Register(base), AT);
+}
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gslbx(dst, AT, T9, 0);
+} else {
+__ addu(AT, AT, T9);
+__ lb(dst, AT, 0);
+}
+}
 } else {
-__ lb(dst, as_Register(base), disp);
+if( Assembler::is_simm16(disp) ) {
+__ lb(dst, as_Register(base), disp);
+} else {
+__ move(T9, disp);
+if( UseLoongsonISA ) {
+__ gslbx(dst, as_Register(base), T9, 0);
+} else {
+__ addu(AT, as_Register(base), T9);
+__ lb(dst, AT, 0);
+}
+}
 }
 %}
 ins_pipe(pipe_slow);
 %}
 ins_pc_relative(1);
 ins_alignment(16);
 %}
 // Load Char (16bit unsigned)
-instruct loadUS(mRegI dst, umemory mem) %{
+instruct loadUS(mRegI dst, memory mem) %{
 match(Set dst (LoadUS mem));
 ins_cost(125);
 format %{ "loadUS  $dst,$mem @ loadC" %}
 ins_encode(load_C_enc(dst, mem));
 ins_pipe( ialu_loadI );
 %}
-instruct loadUS_convI2L(mRegL dst, umemory mem) %{
+instruct loadUS_convI2L(mRegL dst, memory mem) %{
 match(Set dst (ConvI2L (LoadUS mem)));
 ins_cost(125);
 format %{ "loadUS  $dst,$mem @ loadUS_convI2L" %}
 ins_encode(load_C_enc(dst, mem));
 format %{ "mov  $dst, zero @ loadConD0"%}
 ins_encode %{
 FloatRegister dst = as_FloatRegister($dst$$reg);
 __ dmtc1(R0, dst);
 %}
 ins_pipe( fpu_loadF );
 %}
 instruct loadConD(regD dst, immD src) %{
 int     index = $mem$$index;
 int     scale = $mem$$scale;
 int      disp = $mem$$disp;
 if( index != 0 ) {
-assert(UseLoongsonISA, "Only supported for Loongson CPUs");
+		if ( UseLoongsonISA ) {
-__ gsswx(R0, as_Register(base), as_Register(index), disp);
+			if ( Assembler::is_simm(disp, 8) ) {
-} else {
+				if ( scale == 0 ) {
-__ sw(R0, as_Register(base), disp);
+					__ gsswx(R0, as_Register(base), as_Register(index), disp);
+				} else {
+					__ dsll(T9, as_Register(index), scale);
+					__ gsswx(R0, as_Register(base), T9, disp);
+				}
+			} else if ( Assembler::is_simm16(disp) ) {
+				if ( scale == 0 ) {
+					__ daddu(AT, as_Register(base), as_Register(index));
+				} else {
+					__ dsll(T9, as_Register(index), scale);
+					__ daddu(AT, as_Register(base), T9);
+				}
+				__ sw(R0, AT, disp);
+			} else {
+				if ( scale == 0 ) {
+					__ move(T9, disp);
+					__ daddu(AT, as_Register(index), T9);
+					__ gsswx(R0, as_Register(base), AT, 0);
+				} else {
+					__ dsll(T9, as_Register(index), scale);
+					__ move(AT, disp);
+					__ daddu(AT, AT, T9);
+					__ gsswx(R0, as_Register(base), AT, 0);
+				}
+			}
+		} else { //not use loongson isa
+		    if(scale != 0) {
+		       __ dsll(T9, as_Register(index), scale);
+		       __ daddu(AT, as_Register(base), T9);
+		    } else {
+		       __ daddu(AT, as_Register(base), as_Register(index));
+		    }
+		   if( Assembler::is_simm16(disp) ) {
+		      __ sw(R0, AT, disp);
+		   } else {
+		      __ move(T9, disp);
+		      __ daddu(AT, AT, T9);
+			  __ sw(R0, AT, 0);
+	       }
+	   }
+} else { //index is 0
+		if ( UseLoongsonISA ) {
+			if ( Assembler::is_simm16(disp) ) {
+				__ sw(R0, as_Register(base), disp);
+			} else {
+				__ move(T9, disp);
+				__ gsswx(R0, as_Register(base), T9, 0);
+			}
+		} else {
+		   if( Assembler::is_simm16(disp) ) {
+		      __ sw(R0, as_Register(base), disp);
+		   } else {
+		      __ move(T9, disp);
+		      __ daddu(AT, as_Register(base), T9);
+			  __ sw(R0, AT, 0);
+		   }
+		}
 }
 %}
 ins_pipe( ialu_storeI );
 %}
 format %{ "store   $mem, $src\t# store float @ storeD_reg" %}
 ins_encode(store_D_reg_enc(mem, src));
 ins_pipe( fpu_storeF );
 %}
+instruct storeD_imm0( memory mem, immD0 zero) %{
+match(Set mem (StoreD mem zero));
+ins_cost(40);
+format %{ "store   $mem, zero\t# store float @ storeD_imm0" %}
+ins_encode %{
+int      base = $mem$$base;
+int     index = $mem$$index;
+int     scale = $mem$$scale;
+int      disp = $mem$$disp;
+__ mtc1(R0, F30);
+__ cvt_d_w(F30, F30);
+if( index != 0 ) {
+		if ( UseLoongsonISA ) {
+			if ( Assembler::is_simm(disp, 8) ) {
+				if (scale == 0) {
+					__ gssdxc1(F30, as_Register(base), as_Register(index), disp);
+				} else {
+					__ dsll(T9, as_Register(index), scale);
+					__ gssdxc1(F30, as_Register(base), T9, disp);
+				}
+			} else if ( Assembler::is_simm16(disp) ) {
+				if (scale == 0) {
+					__ daddu(AT, as_Register(base), as_Register(index));
+					__ sdc1(F30, AT, disp);
+				} else {
+					__ dsll(T9, as_Register(index), scale);
+					__ daddu(AT, as_Register(base), T9);
+					__ sdc1(F30, AT, disp);
+				}
+			} else {
+				if (scale == 0) {
+					__ move(T9, disp);
+					__ daddu(AT, as_Register(index), T9);
+					__ gssdxc1(F30, as_Register(base), AT, 0);
+				} else {
+					__ move(T9, disp);
+					__ dsll(AT, as_Register(index), scale);
+					__ daddu(AT, AT, T9);
+					__ gssdxc1(F30, as_Register(base), AT, 0);
+				}
+			}
+		} else { // not use loongson isa
+		    if(scale != 0) {
+		       __ dsll(T9, as_Register(index), scale);
+		       __ daddu(AT, as_Register(base), T9);
+		    } else {
+		       __ daddu(AT, as_Register(base), as_Register(index));
+		    }
+		   if( Assembler::is_simm16(disp) ) {
+		      __ sdc1(F30, AT, disp);
+		   } else {
+		      __ move(T9, disp);
+		      __ daddu(AT, AT, T9);
+		      __ sdc1(F30, AT, 0);
+		   }
+		}
+} else {// index is 0
+		if ( UseLoongsonISA ) {
+			if ( Assembler::is_simm16(disp) ) {
+				__ sdc1(F30, as_Register(base), disp);
+			} else {
+				__ move(T9, disp);
+				__ gssdxc1(F30, as_Register(base), T9, 0);
+			}
+		} else {
+		   if( Assembler::is_simm16(disp) ) {
+		      __ sdc1(F30, as_Register(base), disp);
+		   } else {
+		      __ move(T9, disp);
+		      __ daddu(AT, as_Register(base), T9);
+		      __ sdc1(F30, AT, 0);
+		   }
+		}
+}
+%}
+ins_pipe( ialu_storeI );
+%}
 instruct loadSSI(mRegI dst, stackSlotI src)
 %{
 match(Set dst src);
 ins_cost(125);
 ins_pipe( pipe_slow );
 ins_pc_relative(1);
 %}
 // Store CMS card-mark Immediate
-instruct storeImmCM(memory mem, mRegI src) %{
+instruct storeImmCM(memory mem, immI8 src) %{
 match(Set mem (StoreCM mem src));
-ins_cost(500);
+ins_cost(150);
-format %{ "sb   $src, $mem  (CMS card-mark) @ storeImmCM" %}
+format %{ "MOV8   $mem,$src\t! CMS card-mark imm0" %}
-ins_encode(store_B_reg_sync_enc(mem, src));
+//  opcode(0xC6);
-ins_pipe( ialu_storeI );
+ins_encode(store_B_immI_enc_sync(mem, src));
-%}
-instruct storeI0CM(memory mem, immI0 zero) %{
-match(Set mem (StoreCM mem zero));
-ins_cost(450);
-format %{ "sb   $zero, $mem  (CMS card-mark) @ storeI0CM" %}
-ins_encode(store_B0_sync_enc(mem));
 ins_pipe( ialu_storeI );
 %}
 // Die now
 instruct ShouldNotReachHere( )
 __ stop("in ShoudNotReachHere");
 %}
 ins_pipe( pipe_jump );
+%}
+instruct leaP8Narrow(mRegP dst, indOffset8Narrow mem)
+%{
+predicate(Universe::narrow_oop_shift() == 0);
+match(Set dst mem);
+ins_cost(110);
+format %{ "leaq    $dst, $mem\t# ptr off8narrow @ leaP8Narrow" %}
+ins_encode %{
+Register  dst  = $dst$$Register;
+Register  base = as_Register($mem$$base);
+int       disp = $mem$$disp;
+__ daddiu(dst, base, disp);
+%}
+ins_pipe( ialu_regI_imm16 );
+%}
+instruct leaPPosIdxScaleOff8(mRegP dst, basePosIndexScaleOffset8 mem)
+%{
+match(Set dst mem);
+ins_cost(110);
+format %{ "leaq    $dst, $mem\t# @ PosIdxScaleOff8" %}
+ins_encode %{
+Register  dst   = $dst$$Register;
+Register  base  = as_Register($mem$$base);
+Register  index = as_Register($mem$$index);
+int       scale = $mem$$scale;
+int       disp  = $mem$$disp;
+if (scale == 0) {
+__ daddu(AT, base, index);
+__ daddiu(dst, AT, disp);
+} else {
+__ dsll(AT, index, scale);
+__ daddu(AT, base, AT);
+__ daddiu(dst, AT, disp);
+}
+%}
+ins_pipe( ialu_regI_imm16 );
+%}
+instruct leaPIdxScale(mRegP dst, indIndexScale mem)
+%{
+match(Set dst mem);
+ins_cost(110);
+format %{ "leaq    $dst, $mem\t# @ leaPIdxScale" %}
+ins_encode %{
+Register  dst   = $dst$$Register;
+Register  base  = as_Register($mem$$base);
+Register  index = as_Register($mem$$index);
+int       scale = $mem$$scale;
+if (scale == 0) {
+__ daddu(dst, base, index);
+} else {
+__ dsll(AT, index, scale);
+__ daddu(dst, base, AT);
+}
+%}
+ins_pipe( ialu_regI_imm16 );
 %}
 // Jump Direct Conditional - Label defines a relative address from Jcc+1
 instruct  jmpLoopEnd(cmpOp cop, mRegI src1, mRegI src2, label labl) %{
 match(CountedLoopEnd cop (CmpI src1 src2));
 ins_pipe(ialu_regI_regI);
 %}
 // Match loading integer and casting it to unsigned int in long register.
 // LoadI + ConvI2L + AndL 0xffffffff.
-instruct loadUI2L_rmask(mRegL dst, umemory mem, immL_32bits mask) %{
+instruct loadUI2L_rmask(mRegL dst, memory mem, immL_32bits mask) %{
 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
 format %{ "lwu     $dst, $mem \t// zero-extend to long @ loadUI2L_rmask" %}
 ins_encode (load_N_enc(dst, mem));
 ins_pipe(ialu_loadI);
 %}
-instruct loadUI2L_lmask(mRegL dst, umemory mem, immL_32bits mask) %{
+instruct loadUI2L_lmask(mRegL dst, memory mem, immL_32bits mask) %{
 match(Set dst (AndL mask (ConvI2L (LoadI mem))));
 format %{ "lwu     $dst, $mem \t// zero-extend to long @ loadUI2L_lmask" %}
 ins_encode (load_N_enc(dst, mem));
 ins_pipe(ialu_loadI);

comparison: src/cpu/mips/vm/mips_64.ad

src/cpu/mips/vm/mips_64.ad

Mercurial > jdk8-mips64-public > hotspot / file comparison

comparison: src/cpu/mips/vm/mips_64.ad

src/cpu/mips/vm/mips_64.ad