src/cpu/mips/vm/assembler_mips.cpp

changeset 389
76857a2c3534
parent 387
2f19d36583f4
child 391
910b77f150c4
     1.1 --- a/src/cpu/mips/vm/assembler_mips.cpp	Tue Mar 28 14:52:30 2017 -0400
     1.2 +++ b/src/cpu/mips/vm/assembler_mips.cpp	Tue Mar 28 16:09:10 2017 -0400
     1.3 @@ -773,7 +773,7 @@
     1.4  
     1.5    li(tmp_reg1, counter_addr);
     1.6    bind(again);
     1.7 -  if(UseSyncLevel <= 1000) sync();
     1.8 +  if(!Use3A2000) sync();
     1.9    ll(tmp_reg2, tmp_reg1, 0);
    1.10    addi(tmp_reg2, tmp_reg2, inc);
    1.11    sc(tmp_reg2, tmp_reg1, 0);
    1.12 @@ -2991,7 +2991,7 @@
    1.13  
    1.14    bind(again);
    1.15  
    1.16 -  if(UseSyncLevel <= 1000) sync();
    1.17 +  if(!Use3A2000) sync();
    1.18    ll(AT, dest);
    1.19    bne(AT, c_reg, nequal);
    1.20    delayed()->nop(); 
    1.21 @@ -3019,10 +3019,10 @@
    1.22  
    1.23    bind(again);
    1.24  #ifdef _LP64
    1.25 -  if(UseSyncLevel <= 1000) sync();
    1.26 +  if(!Use3A2000) sync();
    1.27    lld(AT, dest);
    1.28  #else
    1.29 -  if(UseSyncLevel <= 1000) sync();
    1.30 +  if(!Use3A2000) sync();
    1.31    ll(AT, dest);
    1.32  #endif
    1.33    bne(AT, c_reg, nequal);
    1.34 @@ -3065,7 +3065,7 @@
    1.35  
    1.36  	bind(again);
    1.37  
    1.38 -        if(UseSyncLevel <= 1000) sync();
    1.39 +        if(!Use3A2000) sync();
    1.40  	lld(AT, dest);
    1.41  	bne(AT, c_reg, nequal);
    1.42  	delayed()->nop(); 

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