src/cpu/mips/vm/assembler_mips.cpp

changeset 389
76857a2c3534
parent 387
2f19d36583f4
child 391
910b77f150c4
equal deleted inserted replaced
388:854749bf3dde 389:76857a2c3534
771 void MacroAssembler::atomic_inc32(address counter_addr, int inc, Register tmp_reg1, Register tmp_reg2) { 771 void MacroAssembler::atomic_inc32(address counter_addr, int inc, Register tmp_reg1, Register tmp_reg2) {
772 Label again; 772 Label again;
773 773
774 li(tmp_reg1, counter_addr); 774 li(tmp_reg1, counter_addr);
775 bind(again); 775 bind(again);
776 if(UseSyncLevel <= 1000) sync(); 776 if(!Use3A2000) sync();
777 ll(tmp_reg2, tmp_reg1, 0); 777 ll(tmp_reg2, tmp_reg1, 0);
778 addi(tmp_reg2, tmp_reg2, inc); 778 addi(tmp_reg2, tmp_reg2, inc);
779 sc(tmp_reg2, tmp_reg1, 0); 779 sc(tmp_reg2, tmp_reg1, 0);
780 beq(tmp_reg2, R0, again); 780 beq(tmp_reg2, R0, again);
781 delayed()->nop(); 781 delayed()->nop();
2989 /* 2012/11/11 Jin: MIPS64 can use ll/sc for 32-bit atomic memory access */ 2989 /* 2012/11/11 Jin: MIPS64 can use ll/sc for 32-bit atomic memory access */
2990 Label done, again, nequal; 2990 Label done, again, nequal;
2991 2991
2992 bind(again); 2992 bind(again);
2993 2993
2994 if(UseSyncLevel <= 1000) sync(); 2994 if(!Use3A2000) sync();
2995 ll(AT, dest); 2995 ll(AT, dest);
2996 bne(AT, c_reg, nequal); 2996 bne(AT, c_reg, nequal);
2997 delayed()->nop(); 2997 delayed()->nop();
2998 2998
2999 move(AT, x_reg); 2999 move(AT, x_reg);
3017 void MacroAssembler::cmpxchg(Register x_reg, Address dest, Register c_reg) { 3017 void MacroAssembler::cmpxchg(Register x_reg, Address dest, Register c_reg) {
3018 Label done, again, nequal; 3018 Label done, again, nequal;
3019 3019
3020 bind(again); 3020 bind(again);
3021 #ifdef _LP64 3021 #ifdef _LP64
3022 if(UseSyncLevel <= 1000) sync(); 3022 if(!Use3A2000) sync();
3023 lld(AT, dest); 3023 lld(AT, dest);
3024 #else 3024 #else
3025 if(UseSyncLevel <= 1000) sync(); 3025 if(!Use3A2000) sync();
3026 ll(AT, dest); 3026 ll(AT, dest);
3027 #endif 3027 #endif
3028 bne(AT, c_reg, nequal); 3028 bne(AT, c_reg, nequal);
3029 delayed()->nop(); 3029 delayed()->nop();
3030 3030
3063 dsrl32(c_regLo, c_regLo, 0); 3063 dsrl32(c_regLo, c_regLo, 0);
3064 orr(c_reg, c_regLo, c_regHi); 3064 orr(c_reg, c_regLo, c_regHi);
3065 3065
3066 bind(again); 3066 bind(again);
3067 3067
3068 if(UseSyncLevel <= 1000) sync(); 3068 if(!Use3A2000) sync();
3069 lld(AT, dest); 3069 lld(AT, dest);
3070 bne(AT, c_reg, nequal); 3070 bne(AT, c_reg, nequal);
3071 delayed()->nop(); 3071 delayed()->nop();
3072 3072
3073 //move(AT, x_reg); 3073 //move(AT, x_reg);

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