1.1 --- a/src/cpu/x86/vm/x86.ad Mon Jun 18 15:17:30 2012 -0700 1.2 +++ b/src/cpu/x86/vm/x86.ad Tue Jun 19 15:12:56 2012 -0700 1.3 @@ -2061,7 +2061,7 @@ 1.4 // Integer could be loaded into xmm register directly from memory. 1.5 instruct Repl2I_mem(vecD dst, memory mem) %{ 1.6 predicate(n->as_Vector()->length() == 2); 1.7 - match(Set dst (ReplicateI mem)); 1.8 + match(Set dst (ReplicateI (LoadVector mem))); 1.9 format %{ "movd $dst,$mem\n\t" 1.10 "pshufd $dst,$dst,0x00\t! replicate2I" %} 1.11 ins_encode %{ 1.12 @@ -2073,7 +2073,7 @@ 1.13 1.14 instruct Repl4I_mem(vecX dst, memory mem) %{ 1.15 predicate(n->as_Vector()->length() == 4); 1.16 - match(Set dst (ReplicateI mem)); 1.17 + match(Set dst (ReplicateI (LoadVector mem))); 1.18 format %{ "movd $dst,$mem\n\t" 1.19 "pshufd $dst,$dst,0x00\t! replicate4I" %} 1.20 ins_encode %{ 1.21 @@ -2085,7 +2085,7 @@ 1.22 1.23 instruct Repl8I_mem(vecY dst, memory mem) %{ 1.24 predicate(n->as_Vector()->length() == 8); 1.25 - match(Set dst (ReplicateI mem)); 1.26 + match(Set dst (ReplicateI (LoadVector mem))); 1.27 format %{ "movd $dst,$mem\n\t" 1.28 "pshufd $dst,$dst,0x00\n\t" 1.29 "vinsertf128h $dst,$dst,$dst\t! replicate8I" %} 1.30 @@ -2225,7 +2225,7 @@ 1.31 // Long could be loaded into xmm register directly from memory. 1.32 instruct Repl2L_mem(vecX dst, memory mem) %{ 1.33 predicate(n->as_Vector()->length() == 2); 1.34 - match(Set dst (ReplicateL mem)); 1.35 + match(Set dst (ReplicateL (LoadVector mem))); 1.36 format %{ "movq $dst,$mem\n\t" 1.37 "movlhps $dst,$dst\t! replicate2L" %} 1.38 ins_encode %{ 1.39 @@ -2237,7 +2237,7 @@ 1.40 1.41 instruct Repl4L_mem(vecY dst, memory mem) %{ 1.42 predicate(n->as_Vector()->length() == 4); 1.43 - match(Set dst (ReplicateL mem)); 1.44 + match(Set dst (ReplicateL (LoadVector mem))); 1.45 format %{ "movq $dst,$mem\n\t" 1.46 "movlhps $dst,$dst\n\t" 1.47 "vinsertf128h $dst,$dst,$dst\t! replicate4L" %}