1.1 --- a/src/cpu/x86/vm/x86.ad Mon Jul 16 11:14:41 2012 -0700
1.2 +++ b/src/cpu/x86/vm/x86.ad Mon Jul 16 17:10:22 2012 -0700
1.3 @@ -71,244 +71,244 @@
1.4 // XMM0-XMM3 might hold parameters
1.5
1.6 reg_def XMM0 ( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
1.7 -reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
1.8 -reg_def XMM0c( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next());
1.9 -reg_def XMM0d( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next()->next());
1.10 -reg_def XMM0e( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next()->next()->next());
1.11 -reg_def XMM0f( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next()->next()->next()->next());
1.12 -reg_def XMM0g( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next()->next()->next()->next()->next());
1.13 -reg_def XMM0h( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.14 +reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(1));
1.15 +reg_def XMM0c( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(2));
1.16 +reg_def XMM0d( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(3));
1.17 +reg_def XMM0e( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(4));
1.18 +reg_def XMM0f( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(5));
1.19 +reg_def XMM0g( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(6));
1.20 +reg_def XMM0h( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(7));
1.21
1.22 reg_def XMM1 ( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
1.23 -reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
1.24 -reg_def XMM1c( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()->next());
1.25 -reg_def XMM1d( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()->next()->next());
1.26 -reg_def XMM1e( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()->next()->next()->next());
1.27 -reg_def XMM1f( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()->next()->next()->next()->next());
1.28 -reg_def XMM1g( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()->next()->next()->next()->next()->next());
1.29 -reg_def XMM1h( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.30 +reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(1));
1.31 +reg_def XMM1c( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(2));
1.32 +reg_def XMM1d( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(3));
1.33 +reg_def XMM1e( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(4));
1.34 +reg_def XMM1f( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(5));
1.35 +reg_def XMM1g( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(6));
1.36 +reg_def XMM1h( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(7));
1.37
1.38 reg_def XMM2 ( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
1.39 -reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
1.40 -reg_def XMM2c( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()->next());
1.41 -reg_def XMM2d( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()->next()->next());
1.42 -reg_def XMM2e( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()->next()->next()->next());
1.43 -reg_def XMM2f( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()->next()->next()->next()->next());
1.44 -reg_def XMM2g( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()->next()->next()->next()->next()->next());
1.45 -reg_def XMM2h( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.46 +reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(1));
1.47 +reg_def XMM2c( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(2));
1.48 +reg_def XMM2d( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(3));
1.49 +reg_def XMM2e( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(4));
1.50 +reg_def XMM2f( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(5));
1.51 +reg_def XMM2g( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(6));
1.52 +reg_def XMM2h( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(7));
1.53
1.54 reg_def XMM3 ( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
1.55 -reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
1.56 -reg_def XMM3c( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()->next());
1.57 -reg_def XMM3d( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()->next()->next());
1.58 -reg_def XMM3e( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()->next()->next()->next());
1.59 -reg_def XMM3f( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()->next()->next()->next()->next());
1.60 -reg_def XMM3g( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()->next()->next()->next()->next()->next());
1.61 -reg_def XMM3h( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.62 +reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(1));
1.63 +reg_def XMM3c( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(2));
1.64 +reg_def XMM3d( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(3));
1.65 +reg_def XMM3e( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(4));
1.66 +reg_def XMM3f( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(5));
1.67 +reg_def XMM3g( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(6));
1.68 +reg_def XMM3h( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(7));
1.69
1.70 reg_def XMM4 ( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
1.71 -reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
1.72 -reg_def XMM4c( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()->next());
1.73 -reg_def XMM4d( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()->next()->next());
1.74 -reg_def XMM4e( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()->next()->next()->next());
1.75 -reg_def XMM4f( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()->next()->next()->next()->next());
1.76 -reg_def XMM4g( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()->next()->next()->next()->next()->next());
1.77 -reg_def XMM4h( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.78 +reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(1));
1.79 +reg_def XMM4c( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(2));
1.80 +reg_def XMM4d( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(3));
1.81 +reg_def XMM4e( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(4));
1.82 +reg_def XMM4f( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(5));
1.83 +reg_def XMM4g( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(6));
1.84 +reg_def XMM4h( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(7));
1.85
1.86 reg_def XMM5 ( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
1.87 -reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
1.88 -reg_def XMM5c( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()->next());
1.89 -reg_def XMM5d( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()->next()->next());
1.90 -reg_def XMM5e( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()->next()->next()->next());
1.91 -reg_def XMM5f( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()->next()->next()->next()->next());
1.92 -reg_def XMM5g( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()->next()->next()->next()->next()->next());
1.93 -reg_def XMM5h( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.94 +reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(1));
1.95 +reg_def XMM5c( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(2));
1.96 +reg_def XMM5d( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(3));
1.97 +reg_def XMM5e( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(4));
1.98 +reg_def XMM5f( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(5));
1.99 +reg_def XMM5g( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(6));
1.100 +reg_def XMM5h( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(7));
1.101
1.102 #ifdef _WIN64
1.103
1.104 reg_def XMM6 ( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg());
1.105 -reg_def XMM6b( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next());
1.106 -reg_def XMM6c( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()->next());
1.107 -reg_def XMM6d( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next());
1.108 -reg_def XMM6e( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()->next());
1.109 -reg_def XMM6f( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()->next()->next());
1.110 -reg_def XMM6g( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()->next()->next()->next());
1.111 -reg_def XMM6h( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.112 +reg_def XMM6b( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(1));
1.113 +reg_def XMM6c( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(2));
1.114 +reg_def XMM6d( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(3));
1.115 +reg_def XMM6e( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(4));
1.116 +reg_def XMM6f( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(5));
1.117 +reg_def XMM6g( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(6));
1.118 +reg_def XMM6h( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(7));
1.119
1.120 reg_def XMM7 ( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg());
1.121 -reg_def XMM7b( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next());
1.122 -reg_def XMM7c( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()->next());
1.123 -reg_def XMM7d( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next());
1.124 -reg_def XMM7e( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()->next());
1.125 -reg_def XMM7f( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()->next()->next());
1.126 -reg_def XMM7g( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()->next()->next()->next());
1.127 -reg_def XMM7h( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.128 +reg_def XMM7b( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(1));
1.129 +reg_def XMM7c( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(2));
1.130 +reg_def XMM7d( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(3));
1.131 +reg_def XMM7e( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(4));
1.132 +reg_def XMM7f( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(5));
1.133 +reg_def XMM7g( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(6));
1.134 +reg_def XMM7h( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(7));
1.135
1.136 reg_def XMM8 ( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg());
1.137 -reg_def XMM8b( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next());
1.138 -reg_def XMM8c( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()->next());
1.139 -reg_def XMM8d( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next());
1.140 -reg_def XMM8e( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()->next());
1.141 -reg_def XMM8f( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()->next()->next());
1.142 -reg_def XMM8g( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()->next()->next()->next());
1.143 -reg_def XMM8h( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.144 +reg_def XMM8b( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(1));
1.145 +reg_def XMM8c( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(2));
1.146 +reg_def XMM8d( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(3));
1.147 +reg_def XMM8e( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(4));
1.148 +reg_def XMM8f( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(5));
1.149 +reg_def XMM8g( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(6));
1.150 +reg_def XMM8h( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(7));
1.151
1.152 reg_def XMM9 ( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg());
1.153 -reg_def XMM9b( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next());
1.154 -reg_def XMM9c( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()->next());
1.155 -reg_def XMM9d( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next());
1.156 -reg_def XMM9e( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()->next());
1.157 -reg_def XMM9f( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()->next()->next());
1.158 -reg_def XMM9g( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()->next()->next()->next());
1.159 -reg_def XMM9h( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.160 +reg_def XMM9b( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(1));
1.161 +reg_def XMM9c( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(2));
1.162 +reg_def XMM9d( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(3));
1.163 +reg_def XMM9e( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(4));
1.164 +reg_def XMM9f( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(5));
1.165 +reg_def XMM9g( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(6));
1.166 +reg_def XMM9h( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(7));
1.167
1.168 reg_def XMM10 ( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg());
1.169 -reg_def XMM10b( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next());
1.170 -reg_def XMM10c( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()->next());
1.171 -reg_def XMM10d( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next());
1.172 -reg_def XMM10e( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()->next());
1.173 -reg_def XMM10f( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()->next()->next());
1.174 -reg_def XMM10g( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()->next()->next()->next());
1.175 -reg_def XMM10h( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.176 +reg_def XMM10b( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(1));
1.177 +reg_def XMM10c( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(2));
1.178 +reg_def XMM10d( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(3));
1.179 +reg_def XMM10e( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(4));
1.180 +reg_def XMM10f( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(5));
1.181 +reg_def XMM10g( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(6));
1.182 +reg_def XMM10h( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(7));
1.183
1.184 reg_def XMM11 ( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg());
1.185 -reg_def XMM11b( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next());
1.186 -reg_def XMM11c( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()->next());
1.187 -reg_def XMM11d( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next());
1.188 -reg_def XMM11e( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()->next());
1.189 -reg_def XMM11f( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()->next()->next());
1.190 -reg_def XMM11g( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()->next()->next()->next());
1.191 -reg_def XMM11h( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.192 +reg_def XMM11b( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(1));
1.193 +reg_def XMM11c( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(2));
1.194 +reg_def XMM11d( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(3));
1.195 +reg_def XMM11e( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(4));
1.196 +reg_def XMM11f( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(5));
1.197 +reg_def XMM11g( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(6));
1.198 +reg_def XMM11h( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(7));
1.199
1.200 reg_def XMM12 ( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg());
1.201 -reg_def XMM12b( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next());
1.202 -reg_def XMM12c( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()->next());
1.203 -reg_def XMM12d( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next());
1.204 -reg_def XMM12e( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()->next());
1.205 -reg_def XMM12f( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()->next()->next());
1.206 -reg_def XMM12g( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()->next()->next()->next());
1.207 -reg_def XMM12h( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.208 +reg_def XMM12b( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(1));
1.209 +reg_def XMM12c( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(2));
1.210 +reg_def XMM12d( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(3));
1.211 +reg_def XMM12e( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(4));
1.212 +reg_def XMM12f( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(5));
1.213 +reg_def XMM12g( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(6));
1.214 +reg_def XMM12h( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(7));
1.215
1.216 reg_def XMM13 ( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg());
1.217 -reg_def XMM13b( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next());
1.218 -reg_def XMM13c( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()->next());
1.219 -reg_def XMM13d( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next());
1.220 -reg_def XMM13e( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()->next());
1.221 -reg_def XMM13f( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()->next()->next());
1.222 -reg_def XMM13g( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()->next()->next()->next());
1.223 -reg_def XMM13h( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.224 +reg_def XMM13b( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(1));
1.225 +reg_def XMM13c( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(2));
1.226 +reg_def XMM13d( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(3));
1.227 +reg_def XMM13e( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(4));
1.228 +reg_def XMM13f( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(5));
1.229 +reg_def XMM13g( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(6));
1.230 +reg_def XMM13h( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(7));
1.231
1.232 reg_def XMM14 ( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg());
1.233 -reg_def XMM14b( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next());
1.234 -reg_def XMM14c( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()->next());
1.235 -reg_def XMM14d( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next());
1.236 -reg_def XMM14e( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()->next());
1.237 -reg_def XMM14f( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()->next()->next());
1.238 -reg_def XMM14g( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()->next()->next()->next());
1.239 -reg_def XMM14h( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.240 +reg_def XMM14b( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(1));
1.241 +reg_def XMM14c( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(2));
1.242 +reg_def XMM14d( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(3));
1.243 +reg_def XMM14e( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(4));
1.244 +reg_def XMM14f( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(5));
1.245 +reg_def XMM14g( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(6));
1.246 +reg_def XMM14h( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(7));
1.247
1.248 reg_def XMM15 ( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg());
1.249 -reg_def XMM15b( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next());
1.250 -reg_def XMM15c( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()->next());
1.251 -reg_def XMM15d( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next());
1.252 -reg_def XMM15e( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()->next());
1.253 -reg_def XMM15f( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()->next()->next());
1.254 -reg_def XMM15g( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()->next()->next()->next());
1.255 -reg_def XMM15h( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.256 +reg_def XMM15b( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(1));
1.257 +reg_def XMM15c( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(2));
1.258 +reg_def XMM15d( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(3));
1.259 +reg_def XMM15e( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(4));
1.260 +reg_def XMM15f( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(5));
1.261 +reg_def XMM15g( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(6));
1.262 +reg_def XMM15h( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(7));
1.263
1.264 #else // _WIN64
1.265
1.266 reg_def XMM6 ( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
1.267 -reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
1.268 -reg_def XMM6c( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()->next());
1.269 -reg_def XMM6d( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next());
1.270 -reg_def XMM6e( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()->next());
1.271 -reg_def XMM6f( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()->next()->next());
1.272 -reg_def XMM6g( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()->next()->next()->next());
1.273 -reg_def XMM6h( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.274 +reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(1));
1.275 +reg_def XMM6c( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(2));
1.276 +reg_def XMM6d( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(3));
1.277 +reg_def XMM6e( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(4));
1.278 +reg_def XMM6f( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(5));
1.279 +reg_def XMM6g( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(6));
1.280 +reg_def XMM6h( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(7));
1.281
1.282 reg_def XMM7 ( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
1.283 -reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
1.284 -reg_def XMM7c( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()->next());
1.285 -reg_def XMM7d( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next());
1.286 -reg_def XMM7e( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()->next());
1.287 -reg_def XMM7f( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()->next()->next());
1.288 -reg_def XMM7g( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()->next()->next()->next());
1.289 -reg_def XMM7h( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.290 +reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(1));
1.291 +reg_def XMM7c( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(2));
1.292 +reg_def XMM7d( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(3));
1.293 +reg_def XMM7e( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(4));
1.294 +reg_def XMM7f( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(5));
1.295 +reg_def XMM7g( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(6));
1.296 +reg_def XMM7h( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(7));
1.297
1.298 #ifdef _LP64
1.299
1.300 reg_def XMM8 ( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg());
1.301 -reg_def XMM8b( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next());
1.302 -reg_def XMM8c( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()->next());
1.303 -reg_def XMM8d( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next());
1.304 -reg_def XMM8e( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()->next());
1.305 -reg_def XMM8f( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()->next()->next());
1.306 -reg_def XMM8g( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()->next()->next()->next());
1.307 -reg_def XMM8h( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.308 +reg_def XMM8b( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(1));
1.309 +reg_def XMM8c( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(2));
1.310 +reg_def XMM8d( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(3));
1.311 +reg_def XMM8e( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(4));
1.312 +reg_def XMM8f( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(5));
1.313 +reg_def XMM8g( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(6));
1.314 +reg_def XMM8h( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(7));
1.315
1.316 reg_def XMM9 ( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg());
1.317 -reg_def XMM9b( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next());
1.318 -reg_def XMM9c( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()->next());
1.319 -reg_def XMM9d( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next());
1.320 -reg_def XMM9e( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()->next());
1.321 -reg_def XMM9f( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()->next()->next());
1.322 -reg_def XMM9g( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()->next()->next()->next());
1.323 -reg_def XMM9h( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.324 +reg_def XMM9b( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(1));
1.325 +reg_def XMM9c( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(2));
1.326 +reg_def XMM9d( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(3));
1.327 +reg_def XMM9e( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(4));
1.328 +reg_def XMM9f( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(5));
1.329 +reg_def XMM9g( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(6));
1.330 +reg_def XMM9h( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(7));
1.331
1.332 reg_def XMM10 ( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg());
1.333 -reg_def XMM10b( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next());
1.334 -reg_def XMM10c( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()->next());
1.335 -reg_def XMM10d( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next());
1.336 -reg_def XMM10e( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()->next());
1.337 -reg_def XMM10f( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()->next()->next());
1.338 -reg_def XMM10g( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()->next()->next()->next());
1.339 -reg_def XMM10h( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.340 +reg_def XMM10b( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(1));
1.341 +reg_def XMM10c( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(2));
1.342 +reg_def XMM10d( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(3));
1.343 +reg_def XMM10e( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(4));
1.344 +reg_def XMM10f( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(5));
1.345 +reg_def XMM10g( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(6));
1.346 +reg_def XMM10h( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(7));
1.347
1.348 reg_def XMM11 ( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg());
1.349 -reg_def XMM11b( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next());
1.350 -reg_def XMM11c( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()->next());
1.351 -reg_def XMM11d( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next());
1.352 -reg_def XMM11e( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()->next());
1.353 -reg_def XMM11f( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()->next()->next());
1.354 -reg_def XMM11g( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()->next()->next()->next());
1.355 -reg_def XMM11h( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.356 +reg_def XMM11b( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(1));
1.357 +reg_def XMM11c( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(2));
1.358 +reg_def XMM11d( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(3));
1.359 +reg_def XMM11e( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(4));
1.360 +reg_def XMM11f( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(5));
1.361 +reg_def XMM11g( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(6));
1.362 +reg_def XMM11h( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(7));
1.363
1.364 reg_def XMM12 ( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg());
1.365 -reg_def XMM12b( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next());
1.366 -reg_def XMM12c( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()->next());
1.367 -reg_def XMM12d( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next());
1.368 -reg_def XMM12e( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()->next());
1.369 -reg_def XMM12f( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()->next()->next());
1.370 -reg_def XMM12g( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()->next()->next()->next());
1.371 -reg_def XMM12h( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.372 +reg_def XMM12b( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(1));
1.373 +reg_def XMM12c( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(2));
1.374 +reg_def XMM12d( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(3));
1.375 +reg_def XMM12e( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(4));
1.376 +reg_def XMM12f( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(5));
1.377 +reg_def XMM12g( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(6));
1.378 +reg_def XMM12h( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(7));
1.379
1.380 reg_def XMM13 ( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg());
1.381 -reg_def XMM13b( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next());
1.382 -reg_def XMM13c( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()->next());
1.383 -reg_def XMM13d( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next());
1.384 -reg_def XMM13e( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()->next());
1.385 -reg_def XMM13f( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()->next()->next());
1.386 -reg_def XMM13g( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()->next()->next()->next());
1.387 -reg_def XMM13h( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.388 +reg_def XMM13b( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(1));
1.389 +reg_def XMM13c( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(2));
1.390 +reg_def XMM13d( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(3));
1.391 +reg_def XMM13e( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(4));
1.392 +reg_def XMM13f( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(5));
1.393 +reg_def XMM13g( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(6));
1.394 +reg_def XMM13h( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(7));
1.395
1.396 reg_def XMM14 ( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg());
1.397 -reg_def XMM14b( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next());
1.398 -reg_def XMM14c( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()->next());
1.399 -reg_def XMM14d( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next());
1.400 -reg_def XMM14e( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()->next());
1.401 -reg_def XMM14f( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()->next()->next());
1.402 -reg_def XMM14g( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()->next()->next()->next());
1.403 -reg_def XMM14h( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.404 +reg_def XMM14b( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(1));
1.405 +reg_def XMM14c( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(2));
1.406 +reg_def XMM14d( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(3));
1.407 +reg_def XMM14e( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(4));
1.408 +reg_def XMM14f( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(5));
1.409 +reg_def XMM14g( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(6));
1.410 +reg_def XMM14h( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(7));
1.411
1.412 reg_def XMM15 ( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg());
1.413 -reg_def XMM15b( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next());
1.414 -reg_def XMM15c( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()->next());
1.415 -reg_def XMM15d( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next());
1.416 -reg_def XMM15e( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()->next());
1.417 -reg_def XMM15f( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()->next()->next());
1.418 -reg_def XMM15g( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()->next()->next()->next());
1.419 -reg_def XMM15h( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()->next()->next()->next()->next());
1.420 +reg_def XMM15b( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(1));
1.421 +reg_def XMM15c( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(2));
1.422 +reg_def XMM15d( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(3));
1.423 +reg_def XMM15e( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(4));
1.424 +reg_def XMM15f( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(5));
1.425 +reg_def XMM15g( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(6));
1.426 +reg_def XMM15h( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(7));
1.427
1.428 #endif // _LP64
1.429
1.430 @@ -889,7 +889,7 @@
1.431 ins_pipe(pipe_slow);
1.432 %}
1.433
1.434 -instruct vaddF_reg(regF dst, regF src1, regF src2) %{
1.435 +instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
1.436 predicate(UseAVX > 0);
1.437 match(Set dst (AddF src1 src2));
1.438
1.439 @@ -901,7 +901,7 @@
1.440 ins_pipe(pipe_slow);
1.441 %}
1.442
1.443 -instruct vaddF_mem(regF dst, regF src1, memory src2) %{
1.444 +instruct addF_reg_mem(regF dst, regF src1, memory src2) %{
1.445 predicate(UseAVX > 0);
1.446 match(Set dst (AddF src1 (LoadF src2)));
1.447
1.448 @@ -913,7 +913,7 @@
1.449 ins_pipe(pipe_slow);
1.450 %}
1.451
1.452 -instruct vaddF_imm(regF dst, regF src, immF con) %{
1.453 +instruct addF_reg_imm(regF dst, regF src, immF con) %{
1.454 predicate(UseAVX > 0);
1.455 match(Set dst (AddF src con));
1.456
1.457 @@ -960,7 +960,7 @@
1.458 ins_pipe(pipe_slow);
1.459 %}
1.460
1.461 -instruct vaddD_reg(regD dst, regD src1, regD src2) %{
1.462 +instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
1.463 predicate(UseAVX > 0);
1.464 match(Set dst (AddD src1 src2));
1.465
1.466 @@ -972,7 +972,7 @@
1.467 ins_pipe(pipe_slow);
1.468 %}
1.469
1.470 -instruct vaddD_mem(regD dst, regD src1, memory src2) %{
1.471 +instruct addD_reg_mem(regD dst, regD src1, memory src2) %{
1.472 predicate(UseAVX > 0);
1.473 match(Set dst (AddD src1 (LoadD src2)));
1.474
1.475 @@ -984,7 +984,7 @@
1.476 ins_pipe(pipe_slow);
1.477 %}
1.478
1.479 -instruct vaddD_imm(regD dst, regD src, immD con) %{
1.480 +instruct addD_reg_imm(regD dst, regD src, immD con) %{
1.481 predicate(UseAVX > 0);
1.482 match(Set dst (AddD src con));
1.483
1.484 @@ -1031,7 +1031,7 @@
1.485 ins_pipe(pipe_slow);
1.486 %}
1.487
1.488 -instruct vsubF_reg(regF dst, regF src1, regF src2) %{
1.489 +instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
1.490 predicate(UseAVX > 0);
1.491 match(Set dst (SubF src1 src2));
1.492
1.493 @@ -1043,7 +1043,7 @@
1.494 ins_pipe(pipe_slow);
1.495 %}
1.496
1.497 -instruct vsubF_mem(regF dst, regF src1, memory src2) %{
1.498 +instruct subF_reg_mem(regF dst, regF src1, memory src2) %{
1.499 predicate(UseAVX > 0);
1.500 match(Set dst (SubF src1 (LoadF src2)));
1.501
1.502 @@ -1055,7 +1055,7 @@
1.503 ins_pipe(pipe_slow);
1.504 %}
1.505
1.506 -instruct vsubF_imm(regF dst, regF src, immF con) %{
1.507 +instruct subF_reg_imm(regF dst, regF src, immF con) %{
1.508 predicate(UseAVX > 0);
1.509 match(Set dst (SubF src con));
1.510
1.511 @@ -1102,7 +1102,7 @@
1.512 ins_pipe(pipe_slow);
1.513 %}
1.514
1.515 -instruct vsubD_reg(regD dst, regD src1, regD src2) %{
1.516 +instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
1.517 predicate(UseAVX > 0);
1.518 match(Set dst (SubD src1 src2));
1.519
1.520 @@ -1114,7 +1114,7 @@
1.521 ins_pipe(pipe_slow);
1.522 %}
1.523
1.524 -instruct vsubD_mem(regD dst, regD src1, memory src2) %{
1.525 +instruct subD_reg_mem(regD dst, regD src1, memory src2) %{
1.526 predicate(UseAVX > 0);
1.527 match(Set dst (SubD src1 (LoadD src2)));
1.528
1.529 @@ -1126,7 +1126,7 @@
1.530 ins_pipe(pipe_slow);
1.531 %}
1.532
1.533 -instruct vsubD_imm(regD dst, regD src, immD con) %{
1.534 +instruct subD_reg_imm(regD dst, regD src, immD con) %{
1.535 predicate(UseAVX > 0);
1.536 match(Set dst (SubD src con));
1.537
1.538 @@ -1173,7 +1173,7 @@
1.539 ins_pipe(pipe_slow);
1.540 %}
1.541
1.542 -instruct vmulF_reg(regF dst, regF src1, regF src2) %{
1.543 +instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
1.544 predicate(UseAVX > 0);
1.545 match(Set dst (MulF src1 src2));
1.546
1.547 @@ -1185,7 +1185,7 @@
1.548 ins_pipe(pipe_slow);
1.549 %}
1.550
1.551 -instruct vmulF_mem(regF dst, regF src1, memory src2) %{
1.552 +instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
1.553 predicate(UseAVX > 0);
1.554 match(Set dst (MulF src1 (LoadF src2)));
1.555
1.556 @@ -1197,7 +1197,7 @@
1.557 ins_pipe(pipe_slow);
1.558 %}
1.559
1.560 -instruct vmulF_imm(regF dst, regF src, immF con) %{
1.561 +instruct mulF_reg_imm(regF dst, regF src, immF con) %{
1.562 predicate(UseAVX > 0);
1.563 match(Set dst (MulF src con));
1.564
1.565 @@ -1244,7 +1244,7 @@
1.566 ins_pipe(pipe_slow);
1.567 %}
1.568
1.569 -instruct vmulD_reg(regD dst, regD src1, regD src2) %{
1.570 +instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
1.571 predicate(UseAVX > 0);
1.572 match(Set dst (MulD src1 src2));
1.573
1.574 @@ -1256,7 +1256,7 @@
1.575 ins_pipe(pipe_slow);
1.576 %}
1.577
1.578 -instruct vmulD_mem(regD dst, regD src1, memory src2) %{
1.579 +instruct mulD_reg_mem(regD dst, regD src1, memory src2) %{
1.580 predicate(UseAVX > 0);
1.581 match(Set dst (MulD src1 (LoadD src2)));
1.582
1.583 @@ -1268,7 +1268,7 @@
1.584 ins_pipe(pipe_slow);
1.585 %}
1.586
1.587 -instruct vmulD_imm(regD dst, regD src, immD con) %{
1.588 +instruct mulD_reg_imm(regD dst, regD src, immD con) %{
1.589 predicate(UseAVX > 0);
1.590 match(Set dst (MulD src con));
1.591
1.592 @@ -1315,7 +1315,7 @@
1.593 ins_pipe(pipe_slow);
1.594 %}
1.595
1.596 -instruct vdivF_reg(regF dst, regF src1, regF src2) %{
1.597 +instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
1.598 predicate(UseAVX > 0);
1.599 match(Set dst (DivF src1 src2));
1.600
1.601 @@ -1327,7 +1327,7 @@
1.602 ins_pipe(pipe_slow);
1.603 %}
1.604
1.605 -instruct vdivF_mem(regF dst, regF src1, memory src2) %{
1.606 +instruct divF_reg_mem(regF dst, regF src1, memory src2) %{
1.607 predicate(UseAVX > 0);
1.608 match(Set dst (DivF src1 (LoadF src2)));
1.609
1.610 @@ -1339,7 +1339,7 @@
1.611 ins_pipe(pipe_slow);
1.612 %}
1.613
1.614 -instruct vdivF_imm(regF dst, regF src, immF con) %{
1.615 +instruct divF_reg_imm(regF dst, regF src, immF con) %{
1.616 predicate(UseAVX > 0);
1.617 match(Set dst (DivF src con));
1.618
1.619 @@ -1386,7 +1386,7 @@
1.620 ins_pipe(pipe_slow);
1.621 %}
1.622
1.623 -instruct vdivD_reg(regD dst, regD src1, regD src2) %{
1.624 +instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
1.625 predicate(UseAVX > 0);
1.626 match(Set dst (DivD src1 src2));
1.627
1.628 @@ -1398,7 +1398,7 @@
1.629 ins_pipe(pipe_slow);
1.630 %}
1.631
1.632 -instruct vdivD_mem(regD dst, regD src1, memory src2) %{
1.633 +instruct divD_reg_mem(regD dst, regD src1, memory src2) %{
1.634 predicate(UseAVX > 0);
1.635 match(Set dst (DivD src1 (LoadD src2)));
1.636
1.637 @@ -1410,7 +1410,7 @@
1.638 ins_pipe(pipe_slow);
1.639 %}
1.640
1.641 -instruct vdivD_imm(regD dst, regD src, immD con) %{
1.642 +instruct divD_reg_imm(regD dst, regD src, immD con) %{
1.643 predicate(UseAVX > 0);
1.644 match(Set dst (DivD src con));
1.645
1.646 @@ -1433,7 +1433,7 @@
1.647 ins_pipe(pipe_slow);
1.648 %}
1.649
1.650 -instruct vabsF_reg(regF dst, regF src) %{
1.651 +instruct absF_reg_reg(regF dst, regF src) %{
1.652 predicate(UseAVX > 0);
1.653 match(Set dst (AbsF src));
1.654 ins_cost(150);
1.655 @@ -1457,7 +1457,7 @@
1.656 ins_pipe(pipe_slow);
1.657 %}
1.658
1.659 -instruct vabsD_reg(regD dst, regD src) %{
1.660 +instruct absD_reg_reg(regD dst, regD src) %{
1.661 predicate(UseAVX > 0);
1.662 match(Set dst (AbsD src));
1.663 ins_cost(150);
1.664 @@ -1481,7 +1481,7 @@
1.665 ins_pipe(pipe_slow);
1.666 %}
1.667
1.668 -instruct vnegF_reg(regF dst, regF src) %{
1.669 +instruct negF_reg_reg(regF dst, regF src) %{
1.670 predicate(UseAVX > 0);
1.671 match(Set dst (NegF src));
1.672 ins_cost(150);
1.673 @@ -1505,7 +1505,7 @@
1.674 ins_pipe(pipe_slow);
1.675 %}
1.676
1.677 -instruct vnegD_reg(regD dst, regD src) %{
1.678 +instruct negD_reg_reg(regD dst, regD src) %{
1.679 predicate(UseAVX > 0);
1.680 match(Set dst (NegD src));
1.681 ins_cost(150);
1.682 @@ -1719,12 +1719,12 @@
1.683 format %{ "movd $dst,$src\n\t"
1.684 "punpcklbw $dst,$dst\n\t"
1.685 "pshuflw $dst,$dst,0x00\n\t"
1.686 - "movlhps $dst,$dst\t! replicate16B" %}
1.687 + "punpcklqdq $dst,$dst\t! replicate16B" %}
1.688 ins_encode %{
1.689 __ movdl($dst$$XMMRegister, $src$$Register);
1.690 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
1.691 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
1.692 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.693 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.694 %}
1.695 ins_pipe( pipe_slow );
1.696 %}
1.697 @@ -1735,14 +1735,14 @@
1.698 format %{ "movd $dst,$src\n\t"
1.699 "punpcklbw $dst,$dst\n\t"
1.700 "pshuflw $dst,$dst,0x00\n\t"
1.701 - "movlhps $dst,$dst\n\t"
1.702 - "vinsertf128h $dst,$dst,$dst\t! replicate32B" %}
1.703 + "punpcklqdq $dst,$dst\n\t"
1.704 + "vinserti128h $dst,$dst,$dst\t! replicate32B" %}
1.705 ins_encode %{
1.706 __ movdl($dst$$XMMRegister, $src$$Register);
1.707 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
1.708 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
1.709 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.710 - __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.711 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.712 + __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.713 %}
1.714 ins_pipe( pipe_slow );
1.715 %}
1.716 @@ -1751,9 +1751,9 @@
1.717 instruct Repl4B_imm(vecS dst, immI con) %{
1.718 predicate(n->as_Vector()->length() == 4);
1.719 match(Set dst (ReplicateB con));
1.720 - format %{ "movss $dst,[$constantaddress]\t! replicate4B($con)" %}
1.721 + format %{ "movdl $dst,[$constantaddress]\t! replicate4B($con)" %}
1.722 ins_encode %{
1.723 - __ movflt($dst$$XMMRegister, $constantaddress(replicate4_imm($con$$constant, 1)));
1.724 + __ movdl($dst$$XMMRegister, $constantaddress(replicate4_imm($con$$constant, 1)));
1.725 %}
1.726 ins_pipe( pipe_slow );
1.727 %}
1.728 @@ -1761,9 +1761,9 @@
1.729 instruct Repl8B_imm(vecD dst, immI con) %{
1.730 predicate(n->as_Vector()->length() == 8);
1.731 match(Set dst (ReplicateB con));
1.732 - format %{ "movsd $dst,[$constantaddress]\t! replicate8B($con)" %}
1.733 + format %{ "movq $dst,[$constantaddress]\t! replicate8B($con)" %}
1.734 ins_encode %{
1.735 - __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1)));
1.736 + __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1)));
1.737 %}
1.738 ins_pipe( pipe_slow );
1.739 %}
1.740 @@ -1771,11 +1771,11 @@
1.741 instruct Repl16B_imm(vecX dst, immI con) %{
1.742 predicate(n->as_Vector()->length() == 16);
1.743 match(Set dst (ReplicateB con));
1.744 - format %{ "movsd $dst,[$constantaddress]\t! replicate16B($con)\n\t"
1.745 - "movlhps $dst,$dst" %}
1.746 + format %{ "movq $dst,[$constantaddress]\n\t"
1.747 + "punpcklqdq $dst,$dst\t! replicate16B($con)" %}
1.748 ins_encode %{
1.749 - __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1)));
1.750 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.751 + __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1)));
1.752 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.753 %}
1.754 ins_pipe( pipe_slow );
1.755 %}
1.756 @@ -1783,13 +1783,13 @@
1.757 instruct Repl32B_imm(vecY dst, immI con) %{
1.758 predicate(n->as_Vector()->length() == 32);
1.759 match(Set dst (ReplicateB con));
1.760 - format %{ "movsd $dst,[$constantaddress]\t! lreplicate32B($con)\n\t"
1.761 - "movlhps $dst,$dst\n\t"
1.762 - "vinsertf128h $dst,$dst,$dst" %}
1.763 + format %{ "movq $dst,[$constantaddress]\n\t"
1.764 + "punpcklqdq $dst,$dst\n\t"
1.765 + "vinserti128h $dst,$dst,$dst\t! lreplicate32B($con)" %}
1.766 ins_encode %{
1.767 - __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1)));
1.768 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.769 - __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.770 + __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1)));
1.771 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.772 + __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.773 %}
1.774 ins_pipe( pipe_slow );
1.775 %}
1.776 @@ -1828,11 +1828,11 @@
1.777 instruct Repl32B_zero(vecY dst, immI0 zero) %{
1.778 predicate(n->as_Vector()->length() == 32);
1.779 match(Set dst (ReplicateB zero));
1.780 - format %{ "vxorpd $dst,$dst,$dst\t! replicate32B zero" %}
1.781 + format %{ "vpxor $dst,$dst,$dst\t! replicate32B zero" %}
1.782 ins_encode %{
1.783 // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it).
1.784 bool vector256 = true;
1.785 - __ vxorpd($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256);
1.786 + __ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256);
1.787 %}
1.788 ins_pipe( fpu_reg_reg );
1.789 %}
1.790 @@ -1867,11 +1867,11 @@
1.791 match(Set dst (ReplicateS src));
1.792 format %{ "movd $dst,$src\n\t"
1.793 "pshuflw $dst,$dst,0x00\n\t"
1.794 - "movlhps $dst,$dst\t! replicate8S" %}
1.795 + "punpcklqdq $dst,$dst\t! replicate8S" %}
1.796 ins_encode %{
1.797 __ movdl($dst$$XMMRegister, $src$$Register);
1.798 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
1.799 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.800 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.801 %}
1.802 ins_pipe( pipe_slow );
1.803 %}
1.804 @@ -1881,13 +1881,13 @@
1.805 match(Set dst (ReplicateS src));
1.806 format %{ "movd $dst,$src\n\t"
1.807 "pshuflw $dst,$dst,0x00\n\t"
1.808 - "movlhps $dst,$dst\n\t"
1.809 - "vinsertf128h $dst,$dst,$dst\t! replicate16S" %}
1.810 + "punpcklqdq $dst,$dst\n\t"
1.811 + "vinserti128h $dst,$dst,$dst\t! replicate16S" %}
1.812 ins_encode %{
1.813 __ movdl($dst$$XMMRegister, $src$$Register);
1.814 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
1.815 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.816 - __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.817 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.818 + __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.819 %}
1.820 ins_pipe( pipe_slow );
1.821 %}
1.822 @@ -1896,9 +1896,9 @@
1.823 instruct Repl2S_imm(vecS dst, immI con) %{
1.824 predicate(n->as_Vector()->length() == 2);
1.825 match(Set dst (ReplicateS con));
1.826 - format %{ "movss $dst,[$constantaddress]\t! replicate2S($con)" %}
1.827 + format %{ "movdl $dst,[$constantaddress]\t! replicate2S($con)" %}
1.828 ins_encode %{
1.829 - __ movflt($dst$$XMMRegister, $constantaddress(replicate4_imm($con$$constant, 2)));
1.830 + __ movdl($dst$$XMMRegister, $constantaddress(replicate4_imm($con$$constant, 2)));
1.831 %}
1.832 ins_pipe( fpu_reg_reg );
1.833 %}
1.834 @@ -1906,9 +1906,9 @@
1.835 instruct Repl4S_imm(vecD dst, immI con) %{
1.836 predicate(n->as_Vector()->length() == 4);
1.837 match(Set dst (ReplicateS con));
1.838 - format %{ "movsd $dst,[$constantaddress]\t! replicate4S($con)" %}
1.839 + format %{ "movq $dst,[$constantaddress]\t! replicate4S($con)" %}
1.840 ins_encode %{
1.841 - __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2)));
1.842 + __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2)));
1.843 %}
1.844 ins_pipe( fpu_reg_reg );
1.845 %}
1.846 @@ -1916,11 +1916,11 @@
1.847 instruct Repl8S_imm(vecX dst, immI con) %{
1.848 predicate(n->as_Vector()->length() == 8);
1.849 match(Set dst (ReplicateS con));
1.850 - format %{ "movsd $dst,[$constantaddress]\t! replicate8S($con)\n\t"
1.851 - "movlhps $dst,$dst" %}
1.852 + format %{ "movq $dst,[$constantaddress]\n\t"
1.853 + "punpcklqdq $dst,$dst\t! replicate8S($con)" %}
1.854 ins_encode %{
1.855 - __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2)));
1.856 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.857 + __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2)));
1.858 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.859 %}
1.860 ins_pipe( pipe_slow );
1.861 %}
1.862 @@ -1928,13 +1928,13 @@
1.863 instruct Repl16S_imm(vecY dst, immI con) %{
1.864 predicate(n->as_Vector()->length() == 16);
1.865 match(Set dst (ReplicateS con));
1.866 - format %{ "movsd $dst,[$constantaddress]\t! replicate16S($con)\n\t"
1.867 - "movlhps $dst,$dst\n\t"
1.868 - "vinsertf128h $dst,$dst,$dst" %}
1.869 + format %{ "movq $dst,[$constantaddress]\n\t"
1.870 + "punpcklqdq $dst,$dst\n\t"
1.871 + "vinserti128h $dst,$dst,$dst\t! replicate16S($con)" %}
1.872 ins_encode %{
1.873 - __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2)));
1.874 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.875 - __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.876 + __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2)));
1.877 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.878 + __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.879 %}
1.880 ins_pipe( pipe_slow );
1.881 %}
1.882 @@ -1973,11 +1973,11 @@
1.883 instruct Repl16S_zero(vecY dst, immI0 zero) %{
1.884 predicate(n->as_Vector()->length() == 16);
1.885 match(Set dst (ReplicateS zero));
1.886 - format %{ "vxorpd $dst,$dst,$dst\t! replicate16S zero" %}
1.887 + format %{ "vpxor $dst,$dst,$dst\t! replicate16S zero" %}
1.888 ins_encode %{
1.889 // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it).
1.890 bool vector256 = true;
1.891 - __ vxorpd($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256);
1.892 + __ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256);
1.893 %}
1.894 ins_pipe( fpu_reg_reg );
1.895 %}
1.896 @@ -2012,11 +2012,11 @@
1.897 match(Set dst (ReplicateI src));
1.898 format %{ "movd $dst,$src\n\t"
1.899 "pshufd $dst,$dst,0x00\n\t"
1.900 - "vinsertf128h $dst,$dst,$dst\t! replicate8I" %}
1.901 + "vinserti128h $dst,$dst,$dst\t! replicate8I" %}
1.902 ins_encode %{
1.903 __ movdl($dst$$XMMRegister, $src$$Register);
1.904 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
1.905 - __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.906 + __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.907 %}
1.908 ins_pipe( pipe_slow );
1.909 %}
1.910 @@ -2025,9 +2025,9 @@
1.911 instruct Repl2I_imm(vecD dst, immI con) %{
1.912 predicate(n->as_Vector()->length() == 2);
1.913 match(Set dst (ReplicateI con));
1.914 - format %{ "movsd $dst,[$constantaddress]\t! replicate2I($con)" %}
1.915 + format %{ "movq $dst,[$constantaddress]\t! replicate2I($con)" %}
1.916 ins_encode %{
1.917 - __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4)));
1.918 + __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4)));
1.919 %}
1.920 ins_pipe( fpu_reg_reg );
1.921 %}
1.922 @@ -2035,11 +2035,11 @@
1.923 instruct Repl4I_imm(vecX dst, immI con) %{
1.924 predicate(n->as_Vector()->length() == 4);
1.925 match(Set dst (ReplicateI con));
1.926 - format %{ "movsd $dst,[$constantaddress]\t! replicate4I($con)\n\t"
1.927 - "movlhps $dst,$dst" %}
1.928 + format %{ "movq $dst,[$constantaddress]\t! replicate4I($con)\n\t"
1.929 + "punpcklqdq $dst,$dst" %}
1.930 ins_encode %{
1.931 - __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4)));
1.932 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.933 + __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4)));
1.934 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.935 %}
1.936 ins_pipe( pipe_slow );
1.937 %}
1.938 @@ -2047,13 +2047,13 @@
1.939 instruct Repl8I_imm(vecY dst, immI con) %{
1.940 predicate(n->as_Vector()->length() == 8);
1.941 match(Set dst (ReplicateI con));
1.942 - format %{ "movsd $dst,[$constantaddress]\t! replicate8I($con)\n\t"
1.943 - "movlhps $dst,$dst\n\t"
1.944 - "vinsertf128h $dst,$dst,$dst" %}
1.945 + format %{ "movq $dst,[$constantaddress]\t! replicate8I($con)\n\t"
1.946 + "punpcklqdq $dst,$dst\n\t"
1.947 + "vinserti128h $dst,$dst,$dst" %}
1.948 ins_encode %{
1.949 - __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4)));
1.950 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.951 - __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.952 + __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4)));
1.953 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.954 + __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.955 %}
1.956 ins_pipe( pipe_slow );
1.957 %}
1.958 @@ -2061,7 +2061,7 @@
1.959 // Integer could be loaded into xmm register directly from memory.
1.960 instruct Repl2I_mem(vecD dst, memory mem) %{
1.961 predicate(n->as_Vector()->length() == 2);
1.962 - match(Set dst (ReplicateI (LoadVector mem)));
1.963 + match(Set dst (ReplicateI (LoadI mem)));
1.964 format %{ "movd $dst,$mem\n\t"
1.965 "pshufd $dst,$dst,0x00\t! replicate2I" %}
1.966 ins_encode %{
1.967 @@ -2073,7 +2073,7 @@
1.968
1.969 instruct Repl4I_mem(vecX dst, memory mem) %{
1.970 predicate(n->as_Vector()->length() == 4);
1.971 - match(Set dst (ReplicateI (LoadVector mem)));
1.972 + match(Set dst (ReplicateI (LoadI mem)));
1.973 format %{ "movd $dst,$mem\n\t"
1.974 "pshufd $dst,$dst,0x00\t! replicate4I" %}
1.975 ins_encode %{
1.976 @@ -2085,14 +2085,14 @@
1.977
1.978 instruct Repl8I_mem(vecY dst, memory mem) %{
1.979 predicate(n->as_Vector()->length() == 8);
1.980 - match(Set dst (ReplicateI (LoadVector mem)));
1.981 + match(Set dst (ReplicateI (LoadI mem)));
1.982 format %{ "movd $dst,$mem\n\t"
1.983 "pshufd $dst,$dst,0x00\n\t"
1.984 - "vinsertf128h $dst,$dst,$dst\t! replicate8I" %}
1.985 + "vinserti128h $dst,$dst,$dst\t! replicate8I" %}
1.986 ins_encode %{
1.987 __ movdl($dst$$XMMRegister, $mem$$Address);
1.988 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
1.989 - __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.990 + __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.991 %}
1.992 ins_pipe( pipe_slow );
1.993 %}
1.994 @@ -2121,11 +2121,11 @@
1.995 instruct Repl8I_zero(vecY dst, immI0 zero) %{
1.996 predicate(n->as_Vector()->length() == 8);
1.997 match(Set dst (ReplicateI zero));
1.998 - format %{ "vxorpd $dst,$dst,$dst\t! replicate8I zero" %}
1.999 + format %{ "vpxor $dst,$dst,$dst\t! replicate8I zero" %}
1.1000 ins_encode %{
1.1001 // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it).
1.1002 bool vector256 = true;
1.1003 - __ vxorpd($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256);
1.1004 + __ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256);
1.1005 %}
1.1006 ins_pipe( fpu_reg_reg );
1.1007 %}
1.1008 @@ -2136,10 +2136,10 @@
1.1009 predicate(n->as_Vector()->length() == 2);
1.1010 match(Set dst (ReplicateL src));
1.1011 format %{ "movdq $dst,$src\n\t"
1.1012 - "movlhps $dst,$dst\t! replicate2L" %}
1.1013 + "punpcklqdq $dst,$dst\t! replicate2L" %}
1.1014 ins_encode %{
1.1015 __ movdq($dst$$XMMRegister, $src$$Register);
1.1016 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.1017 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.1018 %}
1.1019 ins_pipe( pipe_slow );
1.1020 %}
1.1021 @@ -2148,12 +2148,12 @@
1.1022 predicate(n->as_Vector()->length() == 4);
1.1023 match(Set dst (ReplicateL src));
1.1024 format %{ "movdq $dst,$src\n\t"
1.1025 - "movlhps $dst,$dst\n\t"
1.1026 - "vinsertf128h $dst,$dst,$dst\t! replicate4L" %}
1.1027 + "punpcklqdq $dst,$dst\n\t"
1.1028 + "vinserti128h $dst,$dst,$dst\t! replicate4L" %}
1.1029 ins_encode %{
1.1030 __ movdq($dst$$XMMRegister, $src$$Register);
1.1031 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.1032 - __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.1033 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.1034 + __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.1035 %}
1.1036 ins_pipe( pipe_slow );
1.1037 %}
1.1038 @@ -2165,12 +2165,12 @@
1.1039 format %{ "movdl $dst,$src.lo\n\t"
1.1040 "movdl $tmp,$src.hi\n\t"
1.1041 "punpckldq $dst,$tmp\n\t"
1.1042 - "movlhps $dst,$dst\t! replicate2L"%}
1.1043 + "punpcklqdq $dst,$dst\t! replicate2L"%}
1.1044 ins_encode %{
1.1045 __ movdl($dst$$XMMRegister, $src$$Register);
1.1046 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
1.1047 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
1.1048 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.1049 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.1050 %}
1.1051 ins_pipe( pipe_slow );
1.1052 %}
1.1053 @@ -2182,14 +2182,14 @@
1.1054 format %{ "movdl $dst,$src.lo\n\t"
1.1055 "movdl $tmp,$src.hi\n\t"
1.1056 "punpckldq $dst,$tmp\n\t"
1.1057 - "movlhps $dst,$dst\n\t"
1.1058 - "vinsertf128h $dst,$dst,$dst\t! replicate4L" %}
1.1059 + "punpcklqdq $dst,$dst\n\t"
1.1060 + "vinserti128h $dst,$dst,$dst\t! replicate4L" %}
1.1061 ins_encode %{
1.1062 __ movdl($dst$$XMMRegister, $src$$Register);
1.1063 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
1.1064 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
1.1065 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.1066 - __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.1067 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.1068 + __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.1069 %}
1.1070 ins_pipe( pipe_slow );
1.1071 %}
1.1072 @@ -2199,11 +2199,11 @@
1.1073 instruct Repl2L_imm(vecX dst, immL con) %{
1.1074 predicate(n->as_Vector()->length() == 2);
1.1075 match(Set dst (ReplicateL con));
1.1076 - format %{ "movsd $dst,[$constantaddress]\t! replicate2L($con)\n\t"
1.1077 - "movlhps $dst,$dst" %}
1.1078 + format %{ "movq $dst,[$constantaddress]\n\t"
1.1079 + "punpcklqdq $dst,$dst\t! replicate2L($con)" %}
1.1080 ins_encode %{
1.1081 - __ movdbl($dst$$XMMRegister, $constantaddress($con));
1.1082 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.1083 + __ movq($dst$$XMMRegister, $constantaddress($con));
1.1084 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.1085 %}
1.1086 ins_pipe( pipe_slow );
1.1087 %}
1.1088 @@ -2211,13 +2211,13 @@
1.1089 instruct Repl4L_imm(vecY dst, immL con) %{
1.1090 predicate(n->as_Vector()->length() == 4);
1.1091 match(Set dst (ReplicateL con));
1.1092 - format %{ "movsd $dst,[$constantaddress]\t! replicate4L($con)\n\t"
1.1093 - "movlhps $dst,$dst\n\t"
1.1094 - "vinsertf128h $dst,$dst,$dst" %}
1.1095 + format %{ "movq $dst,[$constantaddress]\n\t"
1.1096 + "punpcklqdq $dst,$dst\n\t"
1.1097 + "vinserti128h $dst,$dst,$dst\t! replicate4L($con)" %}
1.1098 ins_encode %{
1.1099 - __ movdbl($dst$$XMMRegister, $constantaddress($con));
1.1100 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.1101 - __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.1102 + __ movq($dst$$XMMRegister, $constantaddress($con));
1.1103 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.1104 + __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.1105 %}
1.1106 ins_pipe( pipe_slow );
1.1107 %}
1.1108 @@ -2225,26 +2225,26 @@
1.1109 // Long could be loaded into xmm register directly from memory.
1.1110 instruct Repl2L_mem(vecX dst, memory mem) %{
1.1111 predicate(n->as_Vector()->length() == 2);
1.1112 - match(Set dst (ReplicateL (LoadVector mem)));
1.1113 + match(Set dst (ReplicateL (LoadL mem)));
1.1114 format %{ "movq $dst,$mem\n\t"
1.1115 - "movlhps $dst,$dst\t! replicate2L" %}
1.1116 + "punpcklqdq $dst,$dst\t! replicate2L" %}
1.1117 ins_encode %{
1.1118 __ movq($dst$$XMMRegister, $mem$$Address);
1.1119 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.1120 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.1121 %}
1.1122 ins_pipe( pipe_slow );
1.1123 %}
1.1124
1.1125 instruct Repl4L_mem(vecY dst, memory mem) %{
1.1126 predicate(n->as_Vector()->length() == 4);
1.1127 - match(Set dst (ReplicateL (LoadVector mem)));
1.1128 + match(Set dst (ReplicateL (LoadL mem)));
1.1129 format %{ "movq $dst,$mem\n\t"
1.1130 - "movlhps $dst,$dst\n\t"
1.1131 - "vinsertf128h $dst,$dst,$dst\t! replicate4L" %}
1.1132 + "punpcklqdq $dst,$dst\n\t"
1.1133 + "vinserti128h $dst,$dst,$dst\t! replicate4L" %}
1.1134 ins_encode %{
1.1135 __ movq($dst$$XMMRegister, $mem$$Address);
1.1136 - __ movlhps($dst$$XMMRegister, $dst$$XMMRegister);
1.1137 - __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.1138 + __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
1.1139 + __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
1.1140 %}
1.1141 ins_pipe( pipe_slow );
1.1142 %}
1.1143 @@ -2263,11 +2263,11 @@
1.1144 instruct Repl4L_zero(vecY dst, immL0 zero) %{
1.1145 predicate(n->as_Vector()->length() == 4);
1.1146 match(Set dst (ReplicateL zero));
1.1147 - format %{ "vxorpd $dst,$dst,$dst\t! replicate4L zero" %}
1.1148 + format %{ "vpxor $dst,$dst,$dst\t! replicate4L zero" %}
1.1149 ins_encode %{
1.1150 // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it).
1.1151 bool vector256 = true;
1.1152 - __ vxorpd($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256);
1.1153 + __ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256);
1.1154 %}
1.1155 ins_pipe( fpu_reg_reg );
1.1156 %}
