Tue, 19 Jun 2012 15:12:56 -0700
7177923: SIGBUS on sparc in compiled code for java.util.Calendar.clear()
Summary: disable vectorization of a memory access with more elements per vector than one which is used for alignment on sparc
Reviewed-by: twisti
kvn@3390 | 1 | // |
kvn@3577 | 2 | // Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved. |
kvn@3390 | 3 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
kvn@3390 | 4 | // |
kvn@3390 | 5 | // This code is free software; you can redistribute it and/or modify it |
kvn@3390 | 6 | // under the terms of the GNU General Public License version 2 only, as |
kvn@3390 | 7 | // published by the Free Software Foundation. |
kvn@3390 | 8 | // |
kvn@3390 | 9 | // This code is distributed in the hope that it will be useful, but WITHOUT |
kvn@3390 | 10 | // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
kvn@3390 | 11 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
kvn@3390 | 12 | // version 2 for more details (a copy is included in the LICENSE file that |
kvn@3390 | 13 | // accompanied this code). |
kvn@3390 | 14 | // |
kvn@3390 | 15 | // You should have received a copy of the GNU General Public License version |
kvn@3390 | 16 | // 2 along with this work; if not, write to the Free Software Foundation, |
kvn@3390 | 17 | // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
kvn@3390 | 18 | // |
kvn@3390 | 19 | // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
kvn@3390 | 20 | // or visit www.oracle.com if you need additional information or have any |
kvn@3390 | 21 | // questions. |
kvn@3390 | 22 | // |
kvn@3390 | 23 | // |
kvn@3390 | 24 | |
kvn@3390 | 25 | // X86 Common Architecture Description File |
kvn@3390 | 26 | |
kvn@3882 | 27 | //----------REGISTER DEFINITION BLOCK------------------------------------------ |
kvn@3882 | 28 | // This information is used by the matcher and the register allocator to |
kvn@3882 | 29 | // describe individual registers and classes of registers within the target |
kvn@3882 | 30 | // archtecture. |
kvn@3882 | 31 | |
kvn@3882 | 32 | register %{ |
kvn@3882 | 33 | //----------Architecture Description Register Definitions---------------------- |
kvn@3882 | 34 | // General Registers |
kvn@3882 | 35 | // "reg_def" name ( register save type, C convention save type, |
kvn@3882 | 36 | // ideal register type, encoding ); |
kvn@3882 | 37 | // Register Save Types: |
kvn@3882 | 38 | // |
kvn@3882 | 39 | // NS = No-Save: The register allocator assumes that these registers |
kvn@3882 | 40 | // can be used without saving upon entry to the method, & |
kvn@3882 | 41 | // that they do not need to be saved at call sites. |
kvn@3882 | 42 | // |
kvn@3882 | 43 | // SOC = Save-On-Call: The register allocator assumes that these registers |
kvn@3882 | 44 | // can be used without saving upon entry to the method, |
kvn@3882 | 45 | // but that they must be saved at call sites. |
kvn@3882 | 46 | // |
kvn@3882 | 47 | // SOE = Save-On-Entry: The register allocator assumes that these registers |
kvn@3882 | 48 | // must be saved before using them upon entry to the |
kvn@3882 | 49 | // method, but they do not need to be saved at call |
kvn@3882 | 50 | // sites. |
kvn@3882 | 51 | // |
kvn@3882 | 52 | // AS = Always-Save: The register allocator assumes that these registers |
kvn@3882 | 53 | // must be saved before using them upon entry to the |
kvn@3882 | 54 | // method, & that they must be saved at call sites. |
kvn@3882 | 55 | // |
kvn@3882 | 56 | // Ideal Register Type is used to determine how to save & restore a |
kvn@3882 | 57 | // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get |
kvn@3882 | 58 | // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. |
kvn@3882 | 59 | // |
kvn@3882 | 60 | // The encoding number is the actual bit-pattern placed into the opcodes. |
kvn@3882 | 61 | |
kvn@3882 | 62 | // XMM registers. 256-bit registers or 8 words each, labeled (a)-h. |
kvn@3882 | 63 | // Word a in each register holds a Float, words ab hold a Double. |
kvn@3882 | 64 | // The whole registers are used in SSE4.2 version intrinsics, |
kvn@3882 | 65 | // array copy stubs and superword operations (see UseSSE42Intrinsics, |
kvn@3882 | 66 | // UseXMMForArrayCopy and UseSuperword flags). |
kvn@3882 | 67 | // XMM8-XMM15 must be encoded with REX (VEX for UseAVX). |
kvn@3882 | 68 | // Linux ABI: No register preserved across function calls |
kvn@3882 | 69 | // XMM0-XMM7 might hold parameters |
kvn@3882 | 70 | // Windows ABI: XMM6-XMM15 preserved across function calls |
kvn@3882 | 71 | // XMM0-XMM3 might hold parameters |
kvn@3882 | 72 | |
kvn@3882 | 73 | reg_def XMM0 ( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); |
kvn@3882 | 74 | reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); |
kvn@3882 | 75 | reg_def XMM0c( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next()); |
kvn@3882 | 76 | reg_def XMM0d( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next()->next()); |
kvn@3882 | 77 | reg_def XMM0e( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 78 | reg_def XMM0f( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 79 | reg_def XMM0g( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 80 | reg_def XMM0h( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 81 | |
kvn@3882 | 82 | reg_def XMM1 ( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); |
kvn@3882 | 83 | reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); |
kvn@3882 | 84 | reg_def XMM1c( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()->next()); |
kvn@3882 | 85 | reg_def XMM1d( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()->next()->next()); |
kvn@3882 | 86 | reg_def XMM1e( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 87 | reg_def XMM1f( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 88 | reg_def XMM1g( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 89 | reg_def XMM1h( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 90 | |
kvn@3882 | 91 | reg_def XMM2 ( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); |
kvn@3882 | 92 | reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); |
kvn@3882 | 93 | reg_def XMM2c( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()->next()); |
kvn@3882 | 94 | reg_def XMM2d( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()->next()->next()); |
kvn@3882 | 95 | reg_def XMM2e( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 96 | reg_def XMM2f( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 97 | reg_def XMM2g( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 98 | reg_def XMM2h( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 99 | |
kvn@3882 | 100 | reg_def XMM3 ( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); |
kvn@3882 | 101 | reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); |
kvn@3882 | 102 | reg_def XMM3c( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()->next()); |
kvn@3882 | 103 | reg_def XMM3d( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()->next()->next()); |
kvn@3882 | 104 | reg_def XMM3e( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 105 | reg_def XMM3f( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 106 | reg_def XMM3g( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 107 | reg_def XMM3h( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 108 | |
kvn@3882 | 109 | reg_def XMM4 ( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); |
kvn@3882 | 110 | reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); |
kvn@3882 | 111 | reg_def XMM4c( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()->next()); |
kvn@3882 | 112 | reg_def XMM4d( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()->next()->next()); |
kvn@3882 | 113 | reg_def XMM4e( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 114 | reg_def XMM4f( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 115 | reg_def XMM4g( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 116 | reg_def XMM4h( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 117 | |
kvn@3882 | 118 | reg_def XMM5 ( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); |
kvn@3882 | 119 | reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); |
kvn@3882 | 120 | reg_def XMM5c( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()->next()); |
kvn@3882 | 121 | reg_def XMM5d( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()->next()->next()); |
kvn@3882 | 122 | reg_def XMM5e( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 123 | reg_def XMM5f( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 124 | reg_def XMM5g( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 125 | reg_def XMM5h( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 126 | |
kvn@3882 | 127 | #ifdef _WIN64 |
kvn@3882 | 128 | |
kvn@3882 | 129 | reg_def XMM6 ( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()); |
kvn@3882 | 130 | reg_def XMM6b( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()); |
kvn@3882 | 131 | reg_def XMM6c( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()->next()); |
kvn@3882 | 132 | reg_def XMM6d( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()); |
kvn@3882 | 133 | reg_def XMM6e( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 134 | reg_def XMM6f( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 135 | reg_def XMM6g( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 136 | reg_def XMM6h( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 137 | |
kvn@3882 | 138 | reg_def XMM7 ( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()); |
kvn@3882 | 139 | reg_def XMM7b( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()); |
kvn@3882 | 140 | reg_def XMM7c( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()->next()); |
kvn@3882 | 141 | reg_def XMM7d( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()); |
kvn@3882 | 142 | reg_def XMM7e( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 143 | reg_def XMM7f( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 144 | reg_def XMM7g( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 145 | reg_def XMM7h( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 146 | |
kvn@3882 | 147 | reg_def XMM8 ( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()); |
kvn@3882 | 148 | reg_def XMM8b( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()); |
kvn@3882 | 149 | reg_def XMM8c( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()->next()); |
kvn@3882 | 150 | reg_def XMM8d( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()); |
kvn@3882 | 151 | reg_def XMM8e( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 152 | reg_def XMM8f( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 153 | reg_def XMM8g( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 154 | reg_def XMM8h( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 155 | |
kvn@3882 | 156 | reg_def XMM9 ( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()); |
kvn@3882 | 157 | reg_def XMM9b( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()); |
kvn@3882 | 158 | reg_def XMM9c( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()->next()); |
kvn@3882 | 159 | reg_def XMM9d( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()); |
kvn@3882 | 160 | reg_def XMM9e( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 161 | reg_def XMM9f( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 162 | reg_def XMM9g( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 163 | reg_def XMM9h( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 164 | |
kvn@3882 | 165 | reg_def XMM10 ( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()); |
kvn@3882 | 166 | reg_def XMM10b( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()); |
kvn@3882 | 167 | reg_def XMM10c( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()->next()); |
kvn@3882 | 168 | reg_def XMM10d( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()); |
kvn@3882 | 169 | reg_def XMM10e( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 170 | reg_def XMM10f( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 171 | reg_def XMM10g( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 172 | reg_def XMM10h( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 173 | |
kvn@3882 | 174 | reg_def XMM11 ( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()); |
kvn@3882 | 175 | reg_def XMM11b( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()); |
kvn@3882 | 176 | reg_def XMM11c( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()->next()); |
kvn@3882 | 177 | reg_def XMM11d( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()); |
kvn@3882 | 178 | reg_def XMM11e( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 179 | reg_def XMM11f( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 180 | reg_def XMM11g( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 181 | reg_def XMM11h( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 182 | |
kvn@3882 | 183 | reg_def XMM12 ( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()); |
kvn@3882 | 184 | reg_def XMM12b( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()); |
kvn@3882 | 185 | reg_def XMM12c( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()->next()); |
kvn@3882 | 186 | reg_def XMM12d( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()); |
kvn@3882 | 187 | reg_def XMM12e( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 188 | reg_def XMM12f( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 189 | reg_def XMM12g( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 190 | reg_def XMM12h( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 191 | |
kvn@3882 | 192 | reg_def XMM13 ( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()); |
kvn@3882 | 193 | reg_def XMM13b( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()); |
kvn@3882 | 194 | reg_def XMM13c( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()->next()); |
kvn@3882 | 195 | reg_def XMM13d( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()); |
kvn@3882 | 196 | reg_def XMM13e( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 197 | reg_def XMM13f( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 198 | reg_def XMM13g( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 199 | reg_def XMM13h( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 200 | |
kvn@3882 | 201 | reg_def XMM14 ( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()); |
kvn@3882 | 202 | reg_def XMM14b( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()); |
kvn@3882 | 203 | reg_def XMM14c( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()->next()); |
kvn@3882 | 204 | reg_def XMM14d( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()); |
kvn@3882 | 205 | reg_def XMM14e( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 206 | reg_def XMM14f( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 207 | reg_def XMM14g( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 208 | reg_def XMM14h( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 209 | |
kvn@3882 | 210 | reg_def XMM15 ( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()); |
kvn@3882 | 211 | reg_def XMM15b( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()); |
kvn@3882 | 212 | reg_def XMM15c( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()->next()); |
kvn@3882 | 213 | reg_def XMM15d( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()); |
kvn@3882 | 214 | reg_def XMM15e( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 215 | reg_def XMM15f( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 216 | reg_def XMM15g( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 217 | reg_def XMM15h( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 218 | |
kvn@3882 | 219 | #else // _WIN64 |
kvn@3882 | 220 | |
kvn@3882 | 221 | reg_def XMM6 ( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); |
kvn@3882 | 222 | reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); |
kvn@3882 | 223 | reg_def XMM6c( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()->next()); |
kvn@3882 | 224 | reg_def XMM6d( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()); |
kvn@3882 | 225 | reg_def XMM6e( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 226 | reg_def XMM6f( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 227 | reg_def XMM6g( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 228 | reg_def XMM6h( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 229 | |
kvn@3882 | 230 | reg_def XMM7 ( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); |
kvn@3882 | 231 | reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); |
kvn@3882 | 232 | reg_def XMM7c( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()->next()); |
kvn@3882 | 233 | reg_def XMM7d( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()); |
kvn@3882 | 234 | reg_def XMM7e( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 235 | reg_def XMM7f( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 236 | reg_def XMM7g( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 237 | reg_def XMM7h( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 238 | |
kvn@3882 | 239 | #ifdef _LP64 |
kvn@3882 | 240 | |
kvn@3882 | 241 | reg_def XMM8 ( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()); |
kvn@3882 | 242 | reg_def XMM8b( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()); |
kvn@3882 | 243 | reg_def XMM8c( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()->next()); |
kvn@3882 | 244 | reg_def XMM8d( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()); |
kvn@3882 | 245 | reg_def XMM8e( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 246 | reg_def XMM8f( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 247 | reg_def XMM8g( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 248 | reg_def XMM8h( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 249 | |
kvn@3882 | 250 | reg_def XMM9 ( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()); |
kvn@3882 | 251 | reg_def XMM9b( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()); |
kvn@3882 | 252 | reg_def XMM9c( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()->next()); |
kvn@3882 | 253 | reg_def XMM9d( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()); |
kvn@3882 | 254 | reg_def XMM9e( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 255 | reg_def XMM9f( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 256 | reg_def XMM9g( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 257 | reg_def XMM9h( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 258 | |
kvn@3882 | 259 | reg_def XMM10 ( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()); |
kvn@3882 | 260 | reg_def XMM10b( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()); |
kvn@3882 | 261 | reg_def XMM10c( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()->next()); |
kvn@3882 | 262 | reg_def XMM10d( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()); |
kvn@3882 | 263 | reg_def XMM10e( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 264 | reg_def XMM10f( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 265 | reg_def XMM10g( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 266 | reg_def XMM10h( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 267 | |
kvn@3882 | 268 | reg_def XMM11 ( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()); |
kvn@3882 | 269 | reg_def XMM11b( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()); |
kvn@3882 | 270 | reg_def XMM11c( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()->next()); |
kvn@3882 | 271 | reg_def XMM11d( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()); |
kvn@3882 | 272 | reg_def XMM11e( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 273 | reg_def XMM11f( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 274 | reg_def XMM11g( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 275 | reg_def XMM11h( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 276 | |
kvn@3882 | 277 | reg_def XMM12 ( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()); |
kvn@3882 | 278 | reg_def XMM12b( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()); |
kvn@3882 | 279 | reg_def XMM12c( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()->next()); |
kvn@3882 | 280 | reg_def XMM12d( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()); |
kvn@3882 | 281 | reg_def XMM12e( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 282 | reg_def XMM12f( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 283 | reg_def XMM12g( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 284 | reg_def XMM12h( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 285 | |
kvn@3882 | 286 | reg_def XMM13 ( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()); |
kvn@3882 | 287 | reg_def XMM13b( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()); |
kvn@3882 | 288 | reg_def XMM13c( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()->next()); |
kvn@3882 | 289 | reg_def XMM13d( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()); |
kvn@3882 | 290 | reg_def XMM13e( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 291 | reg_def XMM13f( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 292 | reg_def XMM13g( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 293 | reg_def XMM13h( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 294 | |
kvn@3882 | 295 | reg_def XMM14 ( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()); |
kvn@3882 | 296 | reg_def XMM14b( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()); |
kvn@3882 | 297 | reg_def XMM14c( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()->next()); |
kvn@3882 | 298 | reg_def XMM14d( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()); |
kvn@3882 | 299 | reg_def XMM14e( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 300 | reg_def XMM14f( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 301 | reg_def XMM14g( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 302 | reg_def XMM14h( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 303 | |
kvn@3882 | 304 | reg_def XMM15 ( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()); |
kvn@3882 | 305 | reg_def XMM15b( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()); |
kvn@3882 | 306 | reg_def XMM15c( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()->next()); |
kvn@3882 | 307 | reg_def XMM15d( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()); |
kvn@3882 | 308 | reg_def XMM15e( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()->next()); |
kvn@3882 | 309 | reg_def XMM15f( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()->next()->next()); |
kvn@3882 | 310 | reg_def XMM15g( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 311 | reg_def XMM15h( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()->next()->next()->next()->next()->next()->next()); |
kvn@3882 | 312 | |
kvn@3882 | 313 | #endif // _LP64 |
kvn@3882 | 314 | |
kvn@3882 | 315 | #endif // _WIN64 |
kvn@3882 | 316 | |
kvn@3882 | 317 | #ifdef _LP64 |
kvn@3882 | 318 | reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad()); |
kvn@3882 | 319 | #else |
kvn@3882 | 320 | reg_def RFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad()); |
kvn@3882 | 321 | #endif // _LP64 |
kvn@3882 | 322 | |
kvn@3882 | 323 | alloc_class chunk1(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0g, XMM0h, |
kvn@3882 | 324 | XMM1, XMM1b, XMM1c, XMM1d, XMM1e, XMM1f, XMM1g, XMM1h, |
kvn@3882 | 325 | XMM2, XMM2b, XMM2c, XMM2d, XMM2e, XMM2f, XMM2g, XMM2h, |
kvn@3882 | 326 | XMM3, XMM3b, XMM3c, XMM3d, XMM3e, XMM3f, XMM3g, XMM3h, |
kvn@3882 | 327 | XMM4, XMM4b, XMM4c, XMM4d, XMM4e, XMM4f, XMM4g, XMM4h, |
kvn@3882 | 328 | XMM5, XMM5b, XMM5c, XMM5d, XMM5e, XMM5f, XMM5g, XMM5h, |
kvn@3882 | 329 | XMM6, XMM6b, XMM6c, XMM6d, XMM6e, XMM6f, XMM6g, XMM6h, |
kvn@3882 | 330 | XMM7, XMM7b, XMM7c, XMM7d, XMM7e, XMM7f, XMM7g, XMM7h |
kvn@3882 | 331 | #ifdef _LP64 |
kvn@3882 | 332 | ,XMM8, XMM8b, XMM8c, XMM8d, XMM8e, XMM8f, XMM8g, XMM8h, |
kvn@3882 | 333 | XMM9, XMM9b, XMM9c, XMM9d, XMM9e, XMM9f, XMM9g, XMM9h, |
kvn@3882 | 334 | XMM10, XMM10b, XMM10c, XMM10d, XMM10e, XMM10f, XMM10g, XMM10h, |
kvn@3882 | 335 | XMM11, XMM11b, XMM11c, XMM11d, XMM11e, XMM11f, XMM11g, XMM11h, |
kvn@3882 | 336 | XMM12, XMM12b, XMM12c, XMM12d, XMM12e, XMM12f, XMM12g, XMM12h, |
kvn@3882 | 337 | XMM13, XMM13b, XMM13c, XMM13d, XMM13e, XMM13f, XMM13g, XMM13h, |
kvn@3882 | 338 | XMM14, XMM14b, XMM14c, XMM14d, XMM14e, XMM14f, XMM14g, XMM14h, |
kvn@3882 | 339 | XMM15, XMM15b, XMM15c, XMM15d, XMM15e, XMM15f, XMM15g, XMM15h |
kvn@3882 | 340 | #endif |
kvn@3882 | 341 | ); |
kvn@3882 | 342 | |
kvn@3882 | 343 | // flags allocation class should be last. |
kvn@3882 | 344 | alloc_class chunk2(RFLAGS); |
kvn@3882 | 345 | |
kvn@3882 | 346 | // Singleton class for condition codes |
kvn@3882 | 347 | reg_class int_flags(RFLAGS); |
kvn@3882 | 348 | |
kvn@3882 | 349 | // Class for all float registers |
kvn@3882 | 350 | reg_class float_reg(XMM0, |
kvn@3882 | 351 | XMM1, |
kvn@3882 | 352 | XMM2, |
kvn@3882 | 353 | XMM3, |
kvn@3882 | 354 | XMM4, |
kvn@3882 | 355 | XMM5, |
kvn@3882 | 356 | XMM6, |
kvn@3882 | 357 | XMM7 |
kvn@3882 | 358 | #ifdef _LP64 |
kvn@3882 | 359 | ,XMM8, |
kvn@3882 | 360 | XMM9, |
kvn@3882 | 361 | XMM10, |
kvn@3882 | 362 | XMM11, |
kvn@3882 | 363 | XMM12, |
kvn@3882 | 364 | XMM13, |
kvn@3882 | 365 | XMM14, |
kvn@3882 | 366 | XMM15 |
kvn@3882 | 367 | #endif |
kvn@3882 | 368 | ); |
kvn@3882 | 369 | |
kvn@3882 | 370 | // Class for all double registers |
kvn@3882 | 371 | reg_class double_reg(XMM0, XMM0b, |
kvn@3882 | 372 | XMM1, XMM1b, |
kvn@3882 | 373 | XMM2, XMM2b, |
kvn@3882 | 374 | XMM3, XMM3b, |
kvn@3882 | 375 | XMM4, XMM4b, |
kvn@3882 | 376 | XMM5, XMM5b, |
kvn@3882 | 377 | XMM6, XMM6b, |
kvn@3882 | 378 | XMM7, XMM7b |
kvn@3882 | 379 | #ifdef _LP64 |
kvn@3882 | 380 | ,XMM8, XMM8b, |
kvn@3882 | 381 | XMM9, XMM9b, |
kvn@3882 | 382 | XMM10, XMM10b, |
kvn@3882 | 383 | XMM11, XMM11b, |
kvn@3882 | 384 | XMM12, XMM12b, |
kvn@3882 | 385 | XMM13, XMM13b, |
kvn@3882 | 386 | XMM14, XMM14b, |
kvn@3882 | 387 | XMM15, XMM15b |
kvn@3882 | 388 | #endif |
kvn@3882 | 389 | ); |
kvn@3882 | 390 | |
kvn@3882 | 391 | // Class for all 32bit vector registers |
kvn@3882 | 392 | reg_class vectors_reg(XMM0, |
kvn@3882 | 393 | XMM1, |
kvn@3882 | 394 | XMM2, |
kvn@3882 | 395 | XMM3, |
kvn@3882 | 396 | XMM4, |
kvn@3882 | 397 | XMM5, |
kvn@3882 | 398 | XMM6, |
kvn@3882 | 399 | XMM7 |
kvn@3882 | 400 | #ifdef _LP64 |
kvn@3882 | 401 | ,XMM8, |
kvn@3882 | 402 | XMM9, |
kvn@3882 | 403 | XMM10, |
kvn@3882 | 404 | XMM11, |
kvn@3882 | 405 | XMM12, |
kvn@3882 | 406 | XMM13, |
kvn@3882 | 407 | XMM14, |
kvn@3882 | 408 | XMM15 |
kvn@3882 | 409 | #endif |
kvn@3882 | 410 | ); |
kvn@3882 | 411 | |
kvn@3882 | 412 | // Class for all 64bit vector registers |
kvn@3882 | 413 | reg_class vectord_reg(XMM0, XMM0b, |
kvn@3882 | 414 | XMM1, XMM1b, |
kvn@3882 | 415 | XMM2, XMM2b, |
kvn@3882 | 416 | XMM3, XMM3b, |
kvn@3882 | 417 | XMM4, XMM4b, |
kvn@3882 | 418 | XMM5, XMM5b, |
kvn@3882 | 419 | XMM6, XMM6b, |
kvn@3882 | 420 | XMM7, XMM7b |
kvn@3882 | 421 | #ifdef _LP64 |
kvn@3882 | 422 | ,XMM8, XMM8b, |
kvn@3882 | 423 | XMM9, XMM9b, |
kvn@3882 | 424 | XMM10, XMM10b, |
kvn@3882 | 425 | XMM11, XMM11b, |
kvn@3882 | 426 | XMM12, XMM12b, |
kvn@3882 | 427 | XMM13, XMM13b, |
kvn@3882 | 428 | XMM14, XMM14b, |
kvn@3882 | 429 | XMM15, XMM15b |
kvn@3882 | 430 | #endif |
kvn@3882 | 431 | ); |
kvn@3882 | 432 | |
kvn@3882 | 433 | // Class for all 128bit vector registers |
kvn@3882 | 434 | reg_class vectorx_reg(XMM0, XMM0b, XMM0c, XMM0d, |
kvn@3882 | 435 | XMM1, XMM1b, XMM1c, XMM1d, |
kvn@3882 | 436 | XMM2, XMM2b, XMM2c, XMM2d, |
kvn@3882 | 437 | XMM3, XMM3b, XMM3c, XMM3d, |
kvn@3882 | 438 | XMM4, XMM4b, XMM4c, XMM4d, |
kvn@3882 | 439 | XMM5, XMM5b, XMM5c, XMM5d, |
kvn@3882 | 440 | XMM6, XMM6b, XMM6c, XMM6d, |
kvn@3882 | 441 | XMM7, XMM7b, XMM7c, XMM7d |
kvn@3882 | 442 | #ifdef _LP64 |
kvn@3882 | 443 | ,XMM8, XMM8b, XMM8c, XMM8d, |
kvn@3882 | 444 | XMM9, XMM9b, XMM9c, XMM9d, |
kvn@3882 | 445 | XMM10, XMM10b, XMM10c, XMM10d, |
kvn@3882 | 446 | XMM11, XMM11b, XMM11c, XMM11d, |
kvn@3882 | 447 | XMM12, XMM12b, XMM12c, XMM12d, |
kvn@3882 | 448 | XMM13, XMM13b, XMM13c, XMM13d, |
kvn@3882 | 449 | XMM14, XMM14b, XMM14c, XMM14d, |
kvn@3882 | 450 | XMM15, XMM15b, XMM15c, XMM15d |
kvn@3882 | 451 | #endif |
kvn@3882 | 452 | ); |
kvn@3882 | 453 | |
kvn@3882 | 454 | // Class for all 256bit vector registers |
kvn@3882 | 455 | reg_class vectory_reg(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0g, XMM0h, |
kvn@3882 | 456 | XMM1, XMM1b, XMM1c, XMM1d, XMM1e, XMM1f, XMM1g, XMM1h, |
kvn@3882 | 457 | XMM2, XMM2b, XMM2c, XMM2d, XMM2e, XMM2f, XMM2g, XMM2h, |
kvn@3882 | 458 | XMM3, XMM3b, XMM3c, XMM3d, XMM3e, XMM3f, XMM3g, XMM3h, |
kvn@3882 | 459 | XMM4, XMM4b, XMM4c, XMM4d, XMM4e, XMM4f, XMM4g, XMM4h, |
kvn@3882 | 460 | XMM5, XMM5b, XMM5c, XMM5d, XMM5e, XMM5f, XMM5g, XMM5h, |
kvn@3882 | 461 | XMM6, XMM6b, XMM6c, XMM6d, XMM6e, XMM6f, XMM6g, XMM6h, |
kvn@3882 | 462 | XMM7, XMM7b, XMM7c, XMM7d, XMM7e, XMM7f, XMM7g, XMM7h |
kvn@3882 | 463 | #ifdef _LP64 |
kvn@3882 | 464 | ,XMM8, XMM8b, XMM8c, XMM8d, XMM8e, XMM8f, XMM8g, XMM8h, |
kvn@3882 | 465 | XMM9, XMM9b, XMM9c, XMM9d, XMM9e, XMM9f, XMM9g, XMM9h, |
kvn@3882 | 466 | XMM10, XMM10b, XMM10c, XMM10d, XMM10e, XMM10f, XMM10g, XMM10h, |
kvn@3882 | 467 | XMM11, XMM11b, XMM11c, XMM11d, XMM11e, XMM11f, XMM11g, XMM11h, |
kvn@3882 | 468 | XMM12, XMM12b, XMM12c, XMM12d, XMM12e, XMM12f, XMM12g, XMM12h, |
kvn@3882 | 469 | XMM13, XMM13b, XMM13c, XMM13d, XMM13e, XMM13f, XMM13g, XMM13h, |
kvn@3882 | 470 | XMM14, XMM14b, XMM14c, XMM14d, XMM14e, XMM14f, XMM14g, XMM14h, |
kvn@3882 | 471 | XMM15, XMM15b, XMM15c, XMM15d, XMM15e, XMM15f, XMM15g, XMM15h |
kvn@3882 | 472 | #endif |
kvn@3882 | 473 | ); |
kvn@3882 | 474 | |
kvn@3882 | 475 | %} |
kvn@3882 | 476 | |
kvn@3390 | 477 | source %{ |
kvn@3390 | 478 | // Float masks come from different places depending on platform. |
kvn@3390 | 479 | #ifdef _LP64 |
kvn@3390 | 480 | static address float_signmask() { return StubRoutines::x86::float_sign_mask(); } |
kvn@3390 | 481 | static address float_signflip() { return StubRoutines::x86::float_sign_flip(); } |
kvn@3390 | 482 | static address double_signmask() { return StubRoutines::x86::double_sign_mask(); } |
kvn@3390 | 483 | static address double_signflip() { return StubRoutines::x86::double_sign_flip(); } |
kvn@3390 | 484 | #else |
kvn@3390 | 485 | static address float_signmask() { return (address)float_signmask_pool; } |
kvn@3390 | 486 | static address float_signflip() { return (address)float_signflip_pool; } |
kvn@3390 | 487 | static address double_signmask() { return (address)double_signmask_pool; } |
kvn@3390 | 488 | static address double_signflip() { return (address)double_signflip_pool; } |
kvn@3390 | 489 | #endif |
kvn@3577 | 490 | |
kvn@3882 | 491 | // Map Types to machine register types |
kvn@3882 | 492 | const int Matcher::base2reg[Type::lastype] = { |
kvn@3882 | 493 | Node::NotAMachineReg,0,0, Op_RegI, Op_RegL, 0, Op_RegN, |
kvn@3882 | 494 | Node::NotAMachineReg, Node::NotAMachineReg, /* tuple, array */ |
kvn@3882 | 495 | Op_VecS, Op_VecD, Op_VecX, Op_VecY, /* Vectors */ |
kvn@3882 | 496 | Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, /* the pointers */ |
kvn@3882 | 497 | 0, 0/*abio*/, |
kvn@3882 | 498 | Op_RegP /* Return address */, 0, /* the memories */ |
kvn@3882 | 499 | Op_RegF, Op_RegF, Op_RegF, Op_RegD, Op_RegD, Op_RegD, |
kvn@3882 | 500 | 0 /*bottom*/ |
kvn@3882 | 501 | }; |
kvn@3882 | 502 | |
kvn@3882 | 503 | // Max vector size in bytes. 0 if not supported. |
kvn@3882 | 504 | const int Matcher::vector_width_in_bytes(BasicType bt) { |
kvn@3882 | 505 | assert(is_java_primitive(bt), "only primitive type vectors"); |
kvn@3882 | 506 | if (UseSSE < 2) return 0; |
kvn@3882 | 507 | // SSE2 supports 128bit vectors for all types. |
kvn@3882 | 508 | // AVX2 supports 256bit vectors for all types. |
kvn@3882 | 509 | int size = (UseAVX > 1) ? 32 : 16; |
kvn@3882 | 510 | // AVX1 supports 256bit vectors only for FLOAT and DOUBLE. |
kvn@3882 | 511 | if (UseAVX > 0 && (bt == T_FLOAT || bt == T_DOUBLE)) |
kvn@3882 | 512 | size = 32; |
kvn@3882 | 513 | // Use flag to limit vector size. |
kvn@3882 | 514 | size = MIN2(size,(int)MaxVectorSize); |
kvn@3882 | 515 | // Minimum 2 values in vector (or 4 for bytes). |
kvn@3882 | 516 | switch (bt) { |
kvn@3882 | 517 | case T_DOUBLE: |
kvn@3882 | 518 | case T_LONG: |
kvn@3882 | 519 | if (size < 16) return 0; |
kvn@3882 | 520 | case T_FLOAT: |
kvn@3882 | 521 | case T_INT: |
kvn@3882 | 522 | if (size < 8) return 0; |
kvn@3882 | 523 | case T_BOOLEAN: |
kvn@3882 | 524 | case T_BYTE: |
kvn@3882 | 525 | case T_CHAR: |
kvn@3882 | 526 | case T_SHORT: |
kvn@3882 | 527 | if (size < 4) return 0; |
kvn@3882 | 528 | break; |
kvn@3882 | 529 | default: |
kvn@3882 | 530 | ShouldNotReachHere(); |
kvn@3882 | 531 | } |
kvn@3882 | 532 | return size; |
kvn@3882 | 533 | } |
kvn@3882 | 534 | |
kvn@3882 | 535 | // Limits on vector size (number of elements) loaded into vector. |
kvn@3882 | 536 | const int Matcher::max_vector_size(const BasicType bt) { |
kvn@3882 | 537 | return vector_width_in_bytes(bt)/type2aelembytes(bt); |
kvn@3882 | 538 | } |
kvn@3882 | 539 | const int Matcher::min_vector_size(const BasicType bt) { |
kvn@3882 | 540 | int max_size = max_vector_size(bt); |
kvn@3882 | 541 | // Min size which can be loaded into vector is 4 bytes. |
kvn@3882 | 542 | int size = (type2aelembytes(bt) == 1) ? 4 : 2; |
kvn@3882 | 543 | return MIN2(size,max_size); |
kvn@3882 | 544 | } |
kvn@3882 | 545 | |
kvn@3882 | 546 | // Vector ideal reg corresponding to specidied size in bytes |
kvn@3882 | 547 | const int Matcher::vector_ideal_reg(int size) { |
kvn@3882 | 548 | assert(MaxVectorSize >= size, ""); |
kvn@3882 | 549 | switch(size) { |
kvn@3882 | 550 | case 4: return Op_VecS; |
kvn@3882 | 551 | case 8: return Op_VecD; |
kvn@3882 | 552 | case 16: return Op_VecX; |
kvn@3882 | 553 | case 32: return Op_VecY; |
kvn@3882 | 554 | } |
kvn@3882 | 555 | ShouldNotReachHere(); |
kvn@3882 | 556 | return 0; |
kvn@3882 | 557 | } |
kvn@3882 | 558 | |
kvn@3882 | 559 | // x86 supports misaligned vectors store/load. |
kvn@3882 | 560 | const bool Matcher::misaligned_vectors_ok() { |
kvn@3882 | 561 | return !AlignVector; // can be changed by flag |
kvn@3882 | 562 | } |
kvn@3882 | 563 | |
kvn@3882 | 564 | // Helper methods for MachSpillCopyNode::implementation(). |
kvn@3882 | 565 | static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
kvn@3882 | 566 | int src_hi, int dst_hi, uint ireg, outputStream* st) { |
kvn@3882 | 567 | // In 64-bit VM size calculation is very complex. Emitting instructions |
kvn@3882 | 568 | // into scratch buffer is used to get size in 64-bit VM. |
kvn@3882 | 569 | LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); ) |
kvn@3882 | 570 | assert(ireg == Op_VecS || // 32bit vector |
kvn@3882 | 571 | (src_lo & 1) == 0 && (src_lo + 1) == src_hi && |
kvn@3882 | 572 | (dst_lo & 1) == 0 && (dst_lo + 1) == dst_hi, |
kvn@3882 | 573 | "no non-adjacent vector moves" ); |
kvn@3882 | 574 | if (cbuf) { |
kvn@3882 | 575 | MacroAssembler _masm(cbuf); |
kvn@3882 | 576 | int offset = __ offset(); |
kvn@3882 | 577 | switch (ireg) { |
kvn@3882 | 578 | case Op_VecS: // copy whole register |
kvn@3882 | 579 | case Op_VecD: |
kvn@3882 | 580 | case Op_VecX: |
kvn@3882 | 581 | __ movdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo])); |
kvn@3882 | 582 | break; |
kvn@3882 | 583 | case Op_VecY: |
kvn@3882 | 584 | __ vmovdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo])); |
kvn@3882 | 585 | break; |
kvn@3882 | 586 | default: |
kvn@3882 | 587 | ShouldNotReachHere(); |
kvn@3882 | 588 | } |
kvn@3882 | 589 | int size = __ offset() - offset; |
kvn@3882 | 590 | #ifdef ASSERT |
kvn@3882 | 591 | // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
kvn@3882 | 592 | assert(!do_size || size == 4, "incorrect size calculattion"); |
kvn@3882 | 593 | #endif |
kvn@3882 | 594 | return size; |
kvn@3882 | 595 | #ifndef PRODUCT |
kvn@3882 | 596 | } else if (!do_size) { |
kvn@3882 | 597 | switch (ireg) { |
kvn@3882 | 598 | case Op_VecS: |
kvn@3882 | 599 | case Op_VecD: |
kvn@3882 | 600 | case Op_VecX: |
kvn@3882 | 601 | st->print("movdqu %s,%s\t# spill",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
kvn@3882 | 602 | break; |
kvn@3882 | 603 | case Op_VecY: |
kvn@3882 | 604 | st->print("vmovdqu %s,%s\t# spill",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
kvn@3882 | 605 | break; |
kvn@3882 | 606 | default: |
kvn@3882 | 607 | ShouldNotReachHere(); |
kvn@3882 | 608 | } |
kvn@3882 | 609 | #endif |
kvn@3882 | 610 | } |
kvn@3882 | 611 | // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix. |
kvn@3882 | 612 | return 4; |
kvn@3882 | 613 | } |
kvn@3882 | 614 | |
kvn@3882 | 615 | static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
kvn@3882 | 616 | int stack_offset, int reg, uint ireg, outputStream* st) { |
kvn@3882 | 617 | // In 64-bit VM size calculation is very complex. Emitting instructions |
kvn@3882 | 618 | // into scratch buffer is used to get size in 64-bit VM. |
kvn@3882 | 619 | LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); ) |
kvn@3882 | 620 | if (cbuf) { |
kvn@3882 | 621 | MacroAssembler _masm(cbuf); |
kvn@3882 | 622 | int offset = __ offset(); |
kvn@3882 | 623 | if (is_load) { |
kvn@3882 | 624 | switch (ireg) { |
kvn@3882 | 625 | case Op_VecS: |
kvn@3882 | 626 | __ movdl(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); |
kvn@3882 | 627 | break; |
kvn@3882 | 628 | case Op_VecD: |
kvn@3882 | 629 | __ movq(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); |
kvn@3882 | 630 | break; |
kvn@3882 | 631 | case Op_VecX: |
kvn@3882 | 632 | __ movdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); |
kvn@3882 | 633 | break; |
kvn@3882 | 634 | case Op_VecY: |
kvn@3882 | 635 | __ vmovdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); |
kvn@3882 | 636 | break; |
kvn@3882 | 637 | default: |
kvn@3882 | 638 | ShouldNotReachHere(); |
kvn@3882 | 639 | } |
kvn@3882 | 640 | } else { // store |
kvn@3882 | 641 | switch (ireg) { |
kvn@3882 | 642 | case Op_VecS: |
kvn@3882 | 643 | __ movdl(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); |
kvn@3882 | 644 | break; |
kvn@3882 | 645 | case Op_VecD: |
kvn@3882 | 646 | __ movq(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); |
kvn@3882 | 647 | break; |
kvn@3882 | 648 | case Op_VecX: |
kvn@3882 | 649 | __ movdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); |
kvn@3882 | 650 | break; |
kvn@3882 | 651 | case Op_VecY: |
kvn@3882 | 652 | __ vmovdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); |
kvn@3882 | 653 | break; |
kvn@3882 | 654 | default: |
kvn@3882 | 655 | ShouldNotReachHere(); |
kvn@3882 | 656 | } |
kvn@3882 | 657 | } |
kvn@3882 | 658 | int size = __ offset() - offset; |
kvn@3882 | 659 | #ifdef ASSERT |
kvn@3882 | 660 | int offset_size = (stack_offset == 0) ? 0 : ((stack_offset < 0x80) ? 1 : 4); |
kvn@3882 | 661 | // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
kvn@3882 | 662 | assert(!do_size || size == (5+offset_size), "incorrect size calculattion"); |
kvn@3882 | 663 | #endif |
kvn@3882 | 664 | return size; |
kvn@3882 | 665 | #ifndef PRODUCT |
kvn@3882 | 666 | } else if (!do_size) { |
kvn@3882 | 667 | if (is_load) { |
kvn@3882 | 668 | switch (ireg) { |
kvn@3882 | 669 | case Op_VecS: |
kvn@3882 | 670 | st->print("movd %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset); |
kvn@3882 | 671 | break; |
kvn@3882 | 672 | case Op_VecD: |
kvn@3882 | 673 | st->print("movq %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset); |
kvn@3882 | 674 | break; |
kvn@3882 | 675 | case Op_VecX: |
kvn@3882 | 676 | st->print("movdqu %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset); |
kvn@3882 | 677 | break; |
kvn@3882 | 678 | case Op_VecY: |
kvn@3882 | 679 | st->print("vmovdqu %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset); |
kvn@3882 | 680 | break; |
kvn@3882 | 681 | default: |
kvn@3882 | 682 | ShouldNotReachHere(); |
kvn@3882 | 683 | } |
kvn@3882 | 684 | } else { // store |
kvn@3882 | 685 | switch (ireg) { |
kvn@3882 | 686 | case Op_VecS: |
kvn@3882 | 687 | st->print("movd [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]); |
kvn@3882 | 688 | break; |
kvn@3882 | 689 | case Op_VecD: |
kvn@3882 | 690 | st->print("movq [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]); |
kvn@3882 | 691 | break; |
kvn@3882 | 692 | case Op_VecX: |
kvn@3882 | 693 | st->print("movdqu [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]); |
kvn@3882 | 694 | break; |
kvn@3882 | 695 | case Op_VecY: |
kvn@3882 | 696 | st->print("vmovdqu [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]); |
kvn@3882 | 697 | break; |
kvn@3882 | 698 | default: |
kvn@3882 | 699 | ShouldNotReachHere(); |
kvn@3882 | 700 | } |
kvn@3882 | 701 | } |
kvn@3882 | 702 | #endif |
kvn@3882 | 703 | } |
kvn@3882 | 704 | int offset_size = (stack_offset == 0) ? 0 : ((stack_offset < 0x80) ? 1 : 4); |
kvn@3882 | 705 | // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
kvn@3882 | 706 | return 5+offset_size; |
kvn@3882 | 707 | } |
kvn@3882 | 708 | |
kvn@3882 | 709 | static inline jfloat replicate4_imm(int con, int width) { |
kvn@3882 | 710 | // Load a constant of "width" (in bytes) and replicate it to fill 32bit. |
kvn@3882 | 711 | assert(width == 1 || width == 2, "only byte or short types here"); |
kvn@3882 | 712 | int bit_width = width * 8; |
kvn@3882 | 713 | jint val = con; |
kvn@3882 | 714 | val &= (1 << bit_width) - 1; // mask off sign bits |
kvn@3882 | 715 | while(bit_width < 32) { |
kvn@3882 | 716 | val |= (val << bit_width); |
kvn@3882 | 717 | bit_width <<= 1; |
kvn@3882 | 718 | } |
kvn@3882 | 719 | jfloat fval = *((jfloat*) &val); // coerce to float type |
kvn@3882 | 720 | return fval; |
kvn@3882 | 721 | } |
kvn@3882 | 722 | |
kvn@3882 | 723 | static inline jdouble replicate8_imm(int con, int width) { |
kvn@3882 | 724 | // Load a constant of "width" (in bytes) and replicate it to fill 64bit. |
kvn@3882 | 725 | assert(width == 1 || width == 2 || width == 4, "only byte, short or int types here"); |
kvn@3882 | 726 | int bit_width = width * 8; |
kvn@3882 | 727 | jlong val = con; |
kvn@3882 | 728 | val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits |
kvn@3882 | 729 | while(bit_width < 64) { |
kvn@3882 | 730 | val |= (val << bit_width); |
kvn@3882 | 731 | bit_width <<= 1; |
kvn@3882 | 732 | } |
kvn@3882 | 733 | jdouble dval = *((jdouble*) &val); // coerce to double type |
kvn@3882 | 734 | return dval; |
kvn@3882 | 735 | } |
kvn@3882 | 736 | |
kvn@3577 | 737 | #ifndef PRODUCT |
kvn@3577 | 738 | void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const { |
kvn@3577 | 739 | st->print("nop \t# %d bytes pad for loops and calls", _count); |
kvn@3577 | 740 | } |
kvn@3577 | 741 | #endif |
kvn@3577 | 742 | |
kvn@3577 | 743 | void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const { |
kvn@3577 | 744 | MacroAssembler _masm(&cbuf); |
kvn@3577 | 745 | __ nop(_count); |
kvn@3577 | 746 | } |
kvn@3577 | 747 | |
kvn@3577 | 748 | uint MachNopNode::size(PhaseRegAlloc*) const { |
kvn@3577 | 749 | return _count; |
kvn@3577 | 750 | } |
kvn@3577 | 751 | |
kvn@3577 | 752 | #ifndef PRODUCT |
kvn@3577 | 753 | void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const { |
kvn@3577 | 754 | st->print("# breakpoint"); |
kvn@3577 | 755 | } |
kvn@3577 | 756 | #endif |
kvn@3577 | 757 | |
kvn@3577 | 758 | void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc* ra_) const { |
kvn@3577 | 759 | MacroAssembler _masm(&cbuf); |
kvn@3577 | 760 | __ int3(); |
kvn@3577 | 761 | } |
kvn@3577 | 762 | |
kvn@3577 | 763 | uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const { |
kvn@3577 | 764 | return MachNode::size(ra_); |
kvn@3577 | 765 | } |
kvn@3577 | 766 | |
kvn@3577 | 767 | %} |
kvn@3577 | 768 | |
kvn@3577 | 769 | encode %{ |
kvn@3577 | 770 | |
kvn@3577 | 771 | enc_class preserve_SP %{ |
kvn@3577 | 772 | debug_only(int off0 = cbuf.insts_size()); |
kvn@3577 | 773 | MacroAssembler _masm(&cbuf); |
kvn@3577 | 774 | // RBP is preserved across all calls, even compiled calls. |
kvn@3577 | 775 | // Use it to preserve RSP in places where the callee might change the SP. |
kvn@3577 | 776 | __ movptr(rbp_mh_SP_save, rsp); |
kvn@3577 | 777 | debug_only(int off1 = cbuf.insts_size()); |
kvn@3577 | 778 | assert(off1 - off0 == preserve_SP_size(), "correct size prediction"); |
kvn@3577 | 779 | %} |
kvn@3577 | 780 | |
kvn@3577 | 781 | enc_class restore_SP %{ |
kvn@3577 | 782 | MacroAssembler _masm(&cbuf); |
kvn@3577 | 783 | __ movptr(rsp, rbp_mh_SP_save); |
kvn@3577 | 784 | %} |
kvn@3577 | 785 | |
kvn@3577 | 786 | enc_class call_epilog %{ |
kvn@3577 | 787 | if (VerifyStackAtCalls) { |
kvn@3577 | 788 | // Check that stack depth is unchanged: find majik cookie on stack |
kvn@3577 | 789 | int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word)); |
kvn@3577 | 790 | MacroAssembler _masm(&cbuf); |
kvn@3577 | 791 | Label L; |
kvn@3577 | 792 | __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d); |
kvn@3577 | 793 | __ jccb(Assembler::equal, L); |
kvn@3577 | 794 | // Die if stack mismatch |
kvn@3577 | 795 | __ int3(); |
kvn@3577 | 796 | __ bind(L); |
kvn@3577 | 797 | } |
kvn@3577 | 798 | %} |
kvn@3577 | 799 | |
kvn@3390 | 800 | %} |
kvn@3390 | 801 | |
kvn@3882 | 802 | |
kvn@3882 | 803 | //----------OPERANDS----------------------------------------------------------- |
kvn@3882 | 804 | // Operand definitions must precede instruction definitions for correct parsing |
kvn@3882 | 805 | // in the ADLC because operands constitute user defined types which are used in |
kvn@3882 | 806 | // instruction definitions. |
kvn@3882 | 807 | |
kvn@3882 | 808 | // Vectors |
kvn@3882 | 809 | operand vecS() %{ |
kvn@3882 | 810 | constraint(ALLOC_IN_RC(vectors_reg)); |
kvn@3882 | 811 | match(VecS); |
kvn@3882 | 812 | |
kvn@3882 | 813 | format %{ %} |
kvn@3882 | 814 | interface(REG_INTER); |
kvn@3882 | 815 | %} |
kvn@3882 | 816 | |
kvn@3882 | 817 | operand vecD() %{ |
kvn@3882 | 818 | constraint(ALLOC_IN_RC(vectord_reg)); |
kvn@3882 | 819 | match(VecD); |
kvn@3882 | 820 | |
kvn@3882 | 821 | format %{ %} |
kvn@3882 | 822 | interface(REG_INTER); |
kvn@3882 | 823 | %} |
kvn@3882 | 824 | |
kvn@3882 | 825 | operand vecX() %{ |
kvn@3882 | 826 | constraint(ALLOC_IN_RC(vectorx_reg)); |
kvn@3882 | 827 | match(VecX); |
kvn@3882 | 828 | |
kvn@3882 | 829 | format %{ %} |
kvn@3882 | 830 | interface(REG_INTER); |
kvn@3882 | 831 | %} |
kvn@3882 | 832 | |
kvn@3882 | 833 | operand vecY() %{ |
kvn@3882 | 834 | constraint(ALLOC_IN_RC(vectory_reg)); |
kvn@3882 | 835 | match(VecY); |
kvn@3882 | 836 | |
kvn@3882 | 837 | format %{ %} |
kvn@3882 | 838 | interface(REG_INTER); |
kvn@3882 | 839 | %} |
kvn@3882 | 840 | |
kvn@3882 | 841 | |
kvn@3390 | 842 | // INSTRUCTIONS -- Platform independent definitions (same for 32- and 64-bit) |
kvn@3390 | 843 | |
kvn@3577 | 844 | // ============================================================================ |
kvn@3577 | 845 | |
kvn@3577 | 846 | instruct ShouldNotReachHere() %{ |
kvn@3577 | 847 | match(Halt); |
kvn@3577 | 848 | format %{ "int3\t# ShouldNotReachHere" %} |
kvn@3577 | 849 | ins_encode %{ |
kvn@3577 | 850 | __ int3(); |
kvn@3577 | 851 | %} |
kvn@3577 | 852 | ins_pipe(pipe_slow); |
kvn@3577 | 853 | %} |
kvn@3577 | 854 | |
kvn@3577 | 855 | // ============================================================================ |
kvn@3577 | 856 | |
kvn@3390 | 857 | instruct addF_reg(regF dst, regF src) %{ |
kvn@3390 | 858 | predicate((UseSSE>=1) && (UseAVX == 0)); |
kvn@3390 | 859 | match(Set dst (AddF dst src)); |
kvn@3390 | 860 | |
kvn@3390 | 861 | format %{ "addss $dst, $src" %} |
kvn@3390 | 862 | ins_cost(150); |
kvn@3390 | 863 | ins_encode %{ |
kvn@3390 | 864 | __ addss($dst$$XMMRegister, $src$$XMMRegister); |
kvn@3390 | 865 | %} |
kvn@3390 | 866 | ins_pipe(pipe_slow); |
kvn@3390 | 867 | %} |
kvn@3390 | 868 | |
kvn@3390 | 869 | instruct addF_mem(regF dst, memory src) %{ |
kvn@3390 | 870 | predicate((UseSSE>=1) && (UseAVX == 0)); |
kvn@3390 | 871 | match(Set dst (AddF dst (LoadF src))); |
kvn@3390 | 872 | |
kvn@3390 | 873 | format %{ "addss $dst, $src" %} |
kvn@3390 | 874 | ins_cost(150); |
kvn@3390 | 875 | ins_encode %{ |
kvn@3390 | 876 | __ addss($dst$$XMMRegister, $src$$Address); |
kvn@3390 | 877 | %} |
kvn@3390 | 878 | ins_pipe(pipe_slow); |
kvn@3390 | 879 | %} |
kvn@3390 | 880 | |
kvn@3390 | 881 | instruct addF_imm(regF dst, immF con) %{ |
kvn@3390 | 882 | predicate((UseSSE>=1) && (UseAVX == 0)); |
kvn@3390 | 883 | match(Set dst (AddF dst con)); |
kvn@3390 | 884 | format %{ "addss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
kvn@3390 | 885 | ins_cost(150); |
kvn@3390 | 886 | ins_encode %{ |
kvn@3390 | 887 | __ addss($dst$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 888 | %} |
kvn@3390 | 889 | ins_pipe(pipe_slow); |
kvn@3390 | 890 | %} |
kvn@3390 | 891 | |
kvn@3390 | 892 | instruct vaddF_reg(regF dst, regF src1, regF src2) %{ |
kvn@3390 | 893 | predicate(UseAVX > 0); |
kvn@3390 | 894 | match(Set dst (AddF src1 src2)); |
kvn@3390 | 895 | |
kvn@3390 | 896 | format %{ "vaddss $dst, $src1, $src2" %} |
kvn@3390 | 897 | ins_cost(150); |
kvn@3390 | 898 | ins_encode %{ |
kvn@3390 | 899 | __ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
kvn@3390 | 900 | %} |
kvn@3390 | 901 | ins_pipe(pipe_slow); |
kvn@3390 | 902 | %} |
kvn@3390 | 903 | |
kvn@3390 | 904 | instruct vaddF_mem(regF dst, regF src1, memory src2) %{ |
kvn@3390 | 905 | predicate(UseAVX > 0); |
kvn@3390 | 906 | match(Set dst (AddF src1 (LoadF src2))); |
kvn@3390 | 907 | |
kvn@3390 | 908 | format %{ "vaddss $dst, $src1, $src2" %} |
kvn@3390 | 909 | ins_cost(150); |
kvn@3390 | 910 | ins_encode %{ |
kvn@3390 | 911 | __ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
kvn@3390 | 912 | %} |
kvn@3390 | 913 | ins_pipe(pipe_slow); |
kvn@3390 | 914 | %} |
kvn@3390 | 915 | |
kvn@3390 | 916 | instruct vaddF_imm(regF dst, regF src, immF con) %{ |
kvn@3390 | 917 | predicate(UseAVX > 0); |
kvn@3390 | 918 | match(Set dst (AddF src con)); |
kvn@3390 | 919 | |
kvn@3390 | 920 | format %{ "vaddss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %} |
kvn@3390 | 921 | ins_cost(150); |
kvn@3390 | 922 | ins_encode %{ |
kvn@3390 | 923 | __ vaddss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 924 | %} |
kvn@3390 | 925 | ins_pipe(pipe_slow); |
kvn@3390 | 926 | %} |
kvn@3390 | 927 | |
kvn@3390 | 928 | instruct addD_reg(regD dst, regD src) %{ |
kvn@3390 | 929 | predicate((UseSSE>=2) && (UseAVX == 0)); |
kvn@3390 | 930 | match(Set dst (AddD dst src)); |
kvn@3390 | 931 | |
kvn@3390 | 932 | format %{ "addsd $dst, $src" %} |
kvn@3390 | 933 | ins_cost(150); |
kvn@3390 | 934 | ins_encode %{ |
kvn@3390 | 935 | __ addsd($dst$$XMMRegister, $src$$XMMRegister); |
kvn@3390 | 936 | %} |
kvn@3390 | 937 | ins_pipe(pipe_slow); |
kvn@3390 | 938 | %} |
kvn@3390 | 939 | |
kvn@3390 | 940 | instruct addD_mem(regD dst, memory src) %{ |
kvn@3390 | 941 | predicate((UseSSE>=2) && (UseAVX == 0)); |
kvn@3390 | 942 | match(Set dst (AddD dst (LoadD src))); |
kvn@3390 | 943 | |
kvn@3390 | 944 | format %{ "addsd $dst, $src" %} |
kvn@3390 | 945 | ins_cost(150); |
kvn@3390 | 946 | ins_encode %{ |
kvn@3390 | 947 | __ addsd($dst$$XMMRegister, $src$$Address); |
kvn@3390 | 948 | %} |
kvn@3390 | 949 | ins_pipe(pipe_slow); |
kvn@3390 | 950 | %} |
kvn@3390 | 951 | |
kvn@3390 | 952 | instruct addD_imm(regD dst, immD con) %{ |
kvn@3390 | 953 | predicate((UseSSE>=2) && (UseAVX == 0)); |
kvn@3390 | 954 | match(Set dst (AddD dst con)); |
kvn@3390 | 955 | format %{ "addsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
kvn@3390 | 956 | ins_cost(150); |
kvn@3390 | 957 | ins_encode %{ |
kvn@3390 | 958 | __ addsd($dst$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 959 | %} |
kvn@3390 | 960 | ins_pipe(pipe_slow); |
kvn@3390 | 961 | %} |
kvn@3390 | 962 | |
kvn@3390 | 963 | instruct vaddD_reg(regD dst, regD src1, regD src2) %{ |
kvn@3390 | 964 | predicate(UseAVX > 0); |
kvn@3390 | 965 | match(Set dst (AddD src1 src2)); |
kvn@3390 | 966 | |
kvn@3390 | 967 | format %{ "vaddsd $dst, $src1, $src2" %} |
kvn@3390 | 968 | ins_cost(150); |
kvn@3390 | 969 | ins_encode %{ |
kvn@3390 | 970 | __ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
kvn@3390 | 971 | %} |
kvn@3390 | 972 | ins_pipe(pipe_slow); |
kvn@3390 | 973 | %} |
kvn@3390 | 974 | |
kvn@3390 | 975 | instruct vaddD_mem(regD dst, regD src1, memory src2) %{ |
kvn@3390 | 976 | predicate(UseAVX > 0); |
kvn@3390 | 977 | match(Set dst (AddD src1 (LoadD src2))); |
kvn@3390 | 978 | |
kvn@3390 | 979 | format %{ "vaddsd $dst, $src1, $src2" %} |
kvn@3390 | 980 | ins_cost(150); |
kvn@3390 | 981 | ins_encode %{ |
kvn@3390 | 982 | __ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
kvn@3390 | 983 | %} |
kvn@3390 | 984 | ins_pipe(pipe_slow); |
kvn@3390 | 985 | %} |
kvn@3390 | 986 | |
kvn@3390 | 987 | instruct vaddD_imm(regD dst, regD src, immD con) %{ |
kvn@3390 | 988 | predicate(UseAVX > 0); |
kvn@3390 | 989 | match(Set dst (AddD src con)); |
kvn@3390 | 990 | |
kvn@3390 | 991 | format %{ "vaddsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %} |
kvn@3390 | 992 | ins_cost(150); |
kvn@3390 | 993 | ins_encode %{ |
kvn@3390 | 994 | __ vaddsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 995 | %} |
kvn@3390 | 996 | ins_pipe(pipe_slow); |
kvn@3390 | 997 | %} |
kvn@3390 | 998 | |
kvn@3390 | 999 | instruct subF_reg(regF dst, regF src) %{ |
kvn@3390 | 1000 | predicate((UseSSE>=1) && (UseAVX == 0)); |
kvn@3390 | 1001 | match(Set dst (SubF dst src)); |
kvn@3390 | 1002 | |
kvn@3390 | 1003 | format %{ "subss $dst, $src" %} |
kvn@3390 | 1004 | ins_cost(150); |
kvn@3390 | 1005 | ins_encode %{ |
kvn@3390 | 1006 | __ subss($dst$$XMMRegister, $src$$XMMRegister); |
kvn@3390 | 1007 | %} |
kvn@3390 | 1008 | ins_pipe(pipe_slow); |
kvn@3390 | 1009 | %} |
kvn@3390 | 1010 | |
kvn@3390 | 1011 | instruct subF_mem(regF dst, memory src) %{ |
kvn@3390 | 1012 | predicate((UseSSE>=1) && (UseAVX == 0)); |
kvn@3390 | 1013 | match(Set dst (SubF dst (LoadF src))); |
kvn@3390 | 1014 | |
kvn@3390 | 1015 | format %{ "subss $dst, $src" %} |
kvn@3390 | 1016 | ins_cost(150); |
kvn@3390 | 1017 | ins_encode %{ |
kvn@3390 | 1018 | __ subss($dst$$XMMRegister, $src$$Address); |
kvn@3390 | 1019 | %} |
kvn@3390 | 1020 | ins_pipe(pipe_slow); |
kvn@3390 | 1021 | %} |
kvn@3390 | 1022 | |
kvn@3390 | 1023 | instruct subF_imm(regF dst, immF con) %{ |
kvn@3390 | 1024 | predicate((UseSSE>=1) && (UseAVX == 0)); |
kvn@3390 | 1025 | match(Set dst (SubF dst con)); |
kvn@3390 | 1026 | format %{ "subss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
kvn@3390 | 1027 | ins_cost(150); |
kvn@3390 | 1028 | ins_encode %{ |
kvn@3390 | 1029 | __ subss($dst$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 1030 | %} |
kvn@3390 | 1031 | ins_pipe(pipe_slow); |
kvn@3390 | 1032 | %} |
kvn@3390 | 1033 | |
kvn@3390 | 1034 | instruct vsubF_reg(regF dst, regF src1, regF src2) %{ |
kvn@3390 | 1035 | predicate(UseAVX > 0); |
kvn@3390 | 1036 | match(Set dst (SubF src1 src2)); |
kvn@3390 | 1037 | |
kvn@3390 | 1038 | format %{ "vsubss $dst, $src1, $src2" %} |
kvn@3390 | 1039 | ins_cost(150); |
kvn@3390 | 1040 | ins_encode %{ |
kvn@3390 | 1041 | __ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
kvn@3390 | 1042 | %} |
kvn@3390 | 1043 | ins_pipe(pipe_slow); |
kvn@3390 | 1044 | %} |
kvn@3390 | 1045 | |
kvn@3390 | 1046 | instruct vsubF_mem(regF dst, regF src1, memory src2) %{ |
kvn@3390 | 1047 | predicate(UseAVX > 0); |
kvn@3390 | 1048 | match(Set dst (SubF src1 (LoadF src2))); |
kvn@3390 | 1049 | |
kvn@3390 | 1050 | format %{ "vsubss $dst, $src1, $src2" %} |
kvn@3390 | 1051 | ins_cost(150); |
kvn@3390 | 1052 | ins_encode %{ |
kvn@3390 | 1053 | __ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
kvn@3390 | 1054 | %} |
kvn@3390 | 1055 | ins_pipe(pipe_slow); |
kvn@3390 | 1056 | %} |
kvn@3390 | 1057 | |
kvn@3390 | 1058 | instruct vsubF_imm(regF dst, regF src, immF con) %{ |
kvn@3390 | 1059 | predicate(UseAVX > 0); |
kvn@3390 | 1060 | match(Set dst (SubF src con)); |
kvn@3390 | 1061 | |
kvn@3390 | 1062 | format %{ "vsubss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %} |
kvn@3390 | 1063 | ins_cost(150); |
kvn@3390 | 1064 | ins_encode %{ |
kvn@3390 | 1065 | __ vsubss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 1066 | %} |
kvn@3390 | 1067 | ins_pipe(pipe_slow); |
kvn@3390 | 1068 | %} |
kvn@3390 | 1069 | |
kvn@3390 | 1070 | instruct subD_reg(regD dst, regD src) %{ |
kvn@3390 | 1071 | predicate((UseSSE>=2) && (UseAVX == 0)); |
kvn@3390 | 1072 | match(Set dst (SubD dst src)); |
kvn@3390 | 1073 | |
kvn@3390 | 1074 | format %{ "subsd $dst, $src" %} |
kvn@3390 | 1075 | ins_cost(150); |
kvn@3390 | 1076 | ins_encode %{ |
kvn@3390 | 1077 | __ subsd($dst$$XMMRegister, $src$$XMMRegister); |
kvn@3390 | 1078 | %} |
kvn@3390 | 1079 | ins_pipe(pipe_slow); |
kvn@3390 | 1080 | %} |
kvn@3390 | 1081 | |
kvn@3390 | 1082 | instruct subD_mem(regD dst, memory src) %{ |
kvn@3390 | 1083 | predicate((UseSSE>=2) && (UseAVX == 0)); |
kvn@3390 | 1084 | match(Set dst (SubD dst (LoadD src))); |
kvn@3390 | 1085 | |
kvn@3390 | 1086 | format %{ "subsd $dst, $src" %} |
kvn@3390 | 1087 | ins_cost(150); |
kvn@3390 | 1088 | ins_encode %{ |
kvn@3390 | 1089 | __ subsd($dst$$XMMRegister, $src$$Address); |
kvn@3390 | 1090 | %} |
kvn@3390 | 1091 | ins_pipe(pipe_slow); |
kvn@3390 | 1092 | %} |
kvn@3390 | 1093 | |
kvn@3390 | 1094 | instruct subD_imm(regD dst, immD con) %{ |
kvn@3390 | 1095 | predicate((UseSSE>=2) && (UseAVX == 0)); |
kvn@3390 | 1096 | match(Set dst (SubD dst con)); |
kvn@3390 | 1097 | format %{ "subsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
kvn@3390 | 1098 | ins_cost(150); |
kvn@3390 | 1099 | ins_encode %{ |
kvn@3390 | 1100 | __ subsd($dst$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 1101 | %} |
kvn@3390 | 1102 | ins_pipe(pipe_slow); |
kvn@3390 | 1103 | %} |
kvn@3390 | 1104 | |
kvn@3390 | 1105 | instruct vsubD_reg(regD dst, regD src1, regD src2) %{ |
kvn@3390 | 1106 | predicate(UseAVX > 0); |
kvn@3390 | 1107 | match(Set dst (SubD src1 src2)); |
kvn@3390 | 1108 | |
kvn@3390 | 1109 | format %{ "vsubsd $dst, $src1, $src2" %} |
kvn@3390 | 1110 | ins_cost(150); |
kvn@3390 | 1111 | ins_encode %{ |
kvn@3390 | 1112 | __ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
kvn@3390 | 1113 | %} |
kvn@3390 | 1114 | ins_pipe(pipe_slow); |
kvn@3390 | 1115 | %} |
kvn@3390 | 1116 | |
kvn@3390 | 1117 | instruct vsubD_mem(regD dst, regD src1, memory src2) %{ |
kvn@3390 | 1118 | predicate(UseAVX > 0); |
kvn@3390 | 1119 | match(Set dst (SubD src1 (LoadD src2))); |
kvn@3390 | 1120 | |
kvn@3390 | 1121 | format %{ "vsubsd $dst, $src1, $src2" %} |
kvn@3390 | 1122 | ins_cost(150); |
kvn@3390 | 1123 | ins_encode %{ |
kvn@3390 | 1124 | __ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
kvn@3390 | 1125 | %} |
kvn@3390 | 1126 | ins_pipe(pipe_slow); |
kvn@3390 | 1127 | %} |
kvn@3390 | 1128 | |
kvn@3390 | 1129 | instruct vsubD_imm(regD dst, regD src, immD con) %{ |
kvn@3390 | 1130 | predicate(UseAVX > 0); |
kvn@3390 | 1131 | match(Set dst (SubD src con)); |
kvn@3390 | 1132 | |
kvn@3390 | 1133 | format %{ "vsubsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %} |
kvn@3390 | 1134 | ins_cost(150); |
kvn@3390 | 1135 | ins_encode %{ |
kvn@3390 | 1136 | __ vsubsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 1137 | %} |
kvn@3390 | 1138 | ins_pipe(pipe_slow); |
kvn@3390 | 1139 | %} |
kvn@3390 | 1140 | |
kvn@3390 | 1141 | instruct mulF_reg(regF dst, regF src) %{ |
kvn@3390 | 1142 | predicate((UseSSE>=1) && (UseAVX == 0)); |
kvn@3390 | 1143 | match(Set dst (MulF dst src)); |
kvn@3390 | 1144 | |
kvn@3390 | 1145 | format %{ "mulss $dst, $src" %} |
kvn@3390 | 1146 | ins_cost(150); |
kvn@3390 | 1147 | ins_encode %{ |
kvn@3390 | 1148 | __ mulss($dst$$XMMRegister, $src$$XMMRegister); |
kvn@3390 | 1149 | %} |
kvn@3390 | 1150 | ins_pipe(pipe_slow); |
kvn@3390 | 1151 | %} |
kvn@3390 | 1152 | |
kvn@3390 | 1153 | instruct mulF_mem(regF dst, memory src) %{ |
kvn@3390 | 1154 | predicate((UseSSE>=1) && (UseAVX == 0)); |
kvn@3390 | 1155 | match(Set dst (MulF dst (LoadF src))); |
kvn@3390 | 1156 | |
kvn@3390 | 1157 | format %{ "mulss $dst, $src" %} |
kvn@3390 | 1158 | ins_cost(150); |
kvn@3390 | 1159 | ins_encode %{ |
kvn@3390 | 1160 | __ mulss($dst$$XMMRegister, $src$$Address); |
kvn@3390 | 1161 | %} |
kvn@3390 | 1162 | ins_pipe(pipe_slow); |
kvn@3390 | 1163 | %} |
kvn@3390 | 1164 | |
kvn@3390 | 1165 | instruct mulF_imm(regF dst, immF con) %{ |
kvn@3390 | 1166 | predicate((UseSSE>=1) && (UseAVX == 0)); |
kvn@3390 | 1167 | match(Set dst (MulF dst con)); |
kvn@3390 | 1168 | format %{ "mulss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
kvn@3390 | 1169 | ins_cost(150); |
kvn@3390 | 1170 | ins_encode %{ |
kvn@3390 | 1171 | __ mulss($dst$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 1172 | %} |
kvn@3390 | 1173 | ins_pipe(pipe_slow); |
kvn@3390 | 1174 | %} |
kvn@3390 | 1175 | |
kvn@3390 | 1176 | instruct vmulF_reg(regF dst, regF src1, regF src2) %{ |
kvn@3390 | 1177 | predicate(UseAVX > 0); |
kvn@3390 | 1178 | match(Set dst (MulF src1 src2)); |
kvn@3390 | 1179 | |
kvn@3390 | 1180 | format %{ "vmulss $dst, $src1, $src2" %} |
kvn@3390 | 1181 | ins_cost(150); |
kvn@3390 | 1182 | ins_encode %{ |
kvn@3390 | 1183 | __ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
kvn@3390 | 1184 | %} |
kvn@3390 | 1185 | ins_pipe(pipe_slow); |
kvn@3390 | 1186 | %} |
kvn@3390 | 1187 | |
kvn@3390 | 1188 | instruct vmulF_mem(regF dst, regF src1, memory src2) %{ |
kvn@3390 | 1189 | predicate(UseAVX > 0); |
kvn@3390 | 1190 | match(Set dst (MulF src1 (LoadF src2))); |
kvn@3390 | 1191 | |
kvn@3390 | 1192 | format %{ "vmulss $dst, $src1, $src2" %} |
kvn@3390 | 1193 | ins_cost(150); |
kvn@3390 | 1194 | ins_encode %{ |
kvn@3390 | 1195 | __ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
kvn@3390 | 1196 | %} |
kvn@3390 | 1197 | ins_pipe(pipe_slow); |
kvn@3390 | 1198 | %} |
kvn@3390 | 1199 | |
kvn@3390 | 1200 | instruct vmulF_imm(regF dst, regF src, immF con) %{ |
kvn@3390 | 1201 | predicate(UseAVX > 0); |
kvn@3390 | 1202 | match(Set dst (MulF src con)); |
kvn@3390 | 1203 | |
kvn@3390 | 1204 | format %{ "vmulss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %} |
kvn@3390 | 1205 | ins_cost(150); |
kvn@3390 | 1206 | ins_encode %{ |
kvn@3390 | 1207 | __ vmulss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 1208 | %} |
kvn@3390 | 1209 | ins_pipe(pipe_slow); |
kvn@3390 | 1210 | %} |
kvn@3390 | 1211 | |
kvn@3390 | 1212 | instruct mulD_reg(regD dst, regD src) %{ |
kvn@3390 | 1213 | predicate((UseSSE>=2) && (UseAVX == 0)); |
kvn@3390 | 1214 | match(Set dst (MulD dst src)); |
kvn@3390 | 1215 | |
kvn@3390 | 1216 | format %{ "mulsd $dst, $src" %} |
kvn@3390 | 1217 | ins_cost(150); |
kvn@3390 | 1218 | ins_encode %{ |
kvn@3390 | 1219 | __ mulsd($dst$$XMMRegister, $src$$XMMRegister); |
kvn@3390 | 1220 | %} |
kvn@3390 | 1221 | ins_pipe(pipe_slow); |
kvn@3390 | 1222 | %} |
kvn@3390 | 1223 | |
kvn@3390 | 1224 | instruct mulD_mem(regD dst, memory src) %{ |
kvn@3390 | 1225 | predicate((UseSSE>=2) && (UseAVX == 0)); |
kvn@3390 | 1226 | match(Set dst (MulD dst (LoadD src))); |
kvn@3390 | 1227 | |
kvn@3390 | 1228 | format %{ "mulsd $dst, $src" %} |
kvn@3390 | 1229 | ins_cost(150); |
kvn@3390 | 1230 | ins_encode %{ |
kvn@3390 | 1231 | __ mulsd($dst$$XMMRegister, $src$$Address); |
kvn@3390 | 1232 | %} |
kvn@3390 | 1233 | ins_pipe(pipe_slow); |
kvn@3390 | 1234 | %} |
kvn@3390 | 1235 | |
kvn@3390 | 1236 | instruct mulD_imm(regD dst, immD con) %{ |
kvn@3390 | 1237 | predicate((UseSSE>=2) && (UseAVX == 0)); |
kvn@3390 | 1238 | match(Set dst (MulD dst con)); |
kvn@3390 | 1239 | format %{ "mulsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
kvn@3390 | 1240 | ins_cost(150); |
kvn@3390 | 1241 | ins_encode %{ |
kvn@3390 | 1242 | __ mulsd($dst$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 1243 | %} |
kvn@3390 | 1244 | ins_pipe(pipe_slow); |
kvn@3390 | 1245 | %} |
kvn@3390 | 1246 | |
kvn@3390 | 1247 | instruct vmulD_reg(regD dst, regD src1, regD src2) %{ |
kvn@3390 | 1248 | predicate(UseAVX > 0); |
kvn@3390 | 1249 | match(Set dst (MulD src1 src2)); |
kvn@3390 | 1250 | |
kvn@3390 | 1251 | format %{ "vmulsd $dst, $src1, $src2" %} |
kvn@3390 | 1252 | ins_cost(150); |
kvn@3390 | 1253 | ins_encode %{ |
kvn@3390 | 1254 | __ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
kvn@3390 | 1255 | %} |
kvn@3390 | 1256 | ins_pipe(pipe_slow); |
kvn@3390 | 1257 | %} |
kvn@3390 | 1258 | |
kvn@3390 | 1259 | instruct vmulD_mem(regD dst, regD src1, memory src2) %{ |
kvn@3390 | 1260 | predicate(UseAVX > 0); |
kvn@3390 | 1261 | match(Set dst (MulD src1 (LoadD src2))); |
kvn@3390 | 1262 | |
kvn@3390 | 1263 | format %{ "vmulsd $dst, $src1, $src2" %} |
kvn@3390 | 1264 | ins_cost(150); |
kvn@3390 | 1265 | ins_encode %{ |
kvn@3390 | 1266 | __ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
kvn@3390 | 1267 | %} |
kvn@3390 | 1268 | ins_pipe(pipe_slow); |
kvn@3390 | 1269 | %} |
kvn@3390 | 1270 | |
kvn@3390 | 1271 | instruct vmulD_imm(regD dst, regD src, immD con) %{ |
kvn@3390 | 1272 | predicate(UseAVX > 0); |
kvn@3390 | 1273 | match(Set dst (MulD src con)); |
kvn@3390 | 1274 | |
kvn@3390 | 1275 | format %{ "vmulsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %} |
kvn@3390 | 1276 | ins_cost(150); |
kvn@3390 | 1277 | ins_encode %{ |
kvn@3390 | 1278 | __ vmulsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 1279 | %} |
kvn@3390 | 1280 | ins_pipe(pipe_slow); |
kvn@3390 | 1281 | %} |
kvn@3390 | 1282 | |
kvn@3390 | 1283 | instruct divF_reg(regF dst, regF src) %{ |
kvn@3390 | 1284 | predicate((UseSSE>=1) && (UseAVX == 0)); |
kvn@3390 | 1285 | match(Set dst (DivF dst src)); |
kvn@3390 | 1286 | |
kvn@3390 | 1287 | format %{ "divss $dst, $src" %} |
kvn@3390 | 1288 | ins_cost(150); |
kvn@3390 | 1289 | ins_encode %{ |
kvn@3390 | 1290 | __ divss($dst$$XMMRegister, $src$$XMMRegister); |
kvn@3390 | 1291 | %} |
kvn@3390 | 1292 | ins_pipe(pipe_slow); |
kvn@3390 | 1293 | %} |
kvn@3390 | 1294 | |
kvn@3390 | 1295 | instruct divF_mem(regF dst, memory src) %{ |
kvn@3390 | 1296 | predicate((UseSSE>=1) && (UseAVX == 0)); |
kvn@3390 | 1297 | match(Set dst (DivF dst (LoadF src))); |
kvn@3390 | 1298 | |
kvn@3390 | 1299 | format %{ "divss $dst, $src" %} |
kvn@3390 | 1300 | ins_cost(150); |
kvn@3390 | 1301 | ins_encode %{ |
kvn@3390 | 1302 | __ divss($dst$$XMMRegister, $src$$Address); |
kvn@3390 | 1303 | %} |
kvn@3390 | 1304 | ins_pipe(pipe_slow); |
kvn@3390 | 1305 | %} |
kvn@3390 | 1306 | |
kvn@3390 | 1307 | instruct divF_imm(regF dst, immF con) %{ |
kvn@3390 | 1308 | predicate((UseSSE>=1) && (UseAVX == 0)); |
kvn@3390 | 1309 | match(Set dst (DivF dst con)); |
kvn@3390 | 1310 | format %{ "divss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
kvn@3390 | 1311 | ins_cost(150); |
kvn@3390 | 1312 | ins_encode %{ |
kvn@3390 | 1313 | __ divss($dst$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 1314 | %} |
kvn@3390 | 1315 | ins_pipe(pipe_slow); |
kvn@3390 | 1316 | %} |
kvn@3390 | 1317 | |
kvn@3390 | 1318 | instruct vdivF_reg(regF dst, regF src1, regF src2) %{ |
kvn@3390 | 1319 | predicate(UseAVX > 0); |
kvn@3390 | 1320 | match(Set dst (DivF src1 src2)); |
kvn@3390 | 1321 | |
kvn@3390 | 1322 | format %{ "vdivss $dst, $src1, $src2" %} |
kvn@3390 | 1323 | ins_cost(150); |
kvn@3390 | 1324 | ins_encode %{ |
kvn@3390 | 1325 | __ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
kvn@3390 | 1326 | %} |
kvn@3390 | 1327 | ins_pipe(pipe_slow); |
kvn@3390 | 1328 | %} |
kvn@3390 | 1329 | |
kvn@3390 | 1330 | instruct vdivF_mem(regF dst, regF src1, memory src2) %{ |
kvn@3390 | 1331 | predicate(UseAVX > 0); |
kvn@3390 | 1332 | match(Set dst (DivF src1 (LoadF src2))); |
kvn@3390 | 1333 | |
kvn@3390 | 1334 | format %{ "vdivss $dst, $src1, $src2" %} |
kvn@3390 | 1335 | ins_cost(150); |
kvn@3390 | 1336 | ins_encode %{ |
kvn@3390 | 1337 | __ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
kvn@3390 | 1338 | %} |
kvn@3390 | 1339 | ins_pipe(pipe_slow); |
kvn@3390 | 1340 | %} |
kvn@3390 | 1341 | |
kvn@3390 | 1342 | instruct vdivF_imm(regF dst, regF src, immF con) %{ |
kvn@3390 | 1343 | predicate(UseAVX > 0); |
kvn@3390 | 1344 | match(Set dst (DivF src con)); |
kvn@3390 | 1345 | |
kvn@3390 | 1346 | format %{ "vdivss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %} |
kvn@3390 | 1347 | ins_cost(150); |
kvn@3390 | 1348 | ins_encode %{ |
kvn@3390 | 1349 | __ vdivss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 1350 | %} |
kvn@3390 | 1351 | ins_pipe(pipe_slow); |
kvn@3390 | 1352 | %} |
kvn@3390 | 1353 | |
kvn@3390 | 1354 | instruct divD_reg(regD dst, regD src) %{ |
kvn@3390 | 1355 | predicate((UseSSE>=2) && (UseAVX == 0)); |
kvn@3390 | 1356 | match(Set dst (DivD dst src)); |
kvn@3390 | 1357 | |
kvn@3390 | 1358 | format %{ "divsd $dst, $src" %} |
kvn@3390 | 1359 | ins_cost(150); |
kvn@3390 | 1360 | ins_encode %{ |
kvn@3390 | 1361 | __ divsd($dst$$XMMRegister, $src$$XMMRegister); |
kvn@3390 | 1362 | %} |
kvn@3390 | 1363 | ins_pipe(pipe_slow); |
kvn@3390 | 1364 | %} |
kvn@3390 | 1365 | |
kvn@3390 | 1366 | instruct divD_mem(regD dst, memory src) %{ |
kvn@3390 | 1367 | predicate((UseSSE>=2) && (UseAVX == 0)); |
kvn@3390 | 1368 | match(Set dst (DivD dst (LoadD src))); |
kvn@3390 | 1369 | |
kvn@3390 | 1370 | format %{ "divsd $dst, $src" %} |
kvn@3390 | 1371 | ins_cost(150); |
kvn@3390 | 1372 | ins_encode %{ |
kvn@3390 | 1373 | __ divsd($dst$$XMMRegister, $src$$Address); |
kvn@3390 | 1374 | %} |
kvn@3390 | 1375 | ins_pipe(pipe_slow); |
kvn@3390 | 1376 | %} |
kvn@3390 | 1377 | |
kvn@3390 | 1378 | instruct divD_imm(regD dst, immD con) %{ |
kvn@3390 | 1379 | predicate((UseSSE>=2) && (UseAVX == 0)); |
kvn@3390 | 1380 | match(Set dst (DivD dst con)); |
kvn@3390 | 1381 | format %{ "divsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
kvn@3390 | 1382 | ins_cost(150); |
kvn@3390 | 1383 | ins_encode %{ |
kvn@3390 | 1384 | __ divsd($dst$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 1385 | %} |
kvn@3390 | 1386 | ins_pipe(pipe_slow); |
kvn@3390 | 1387 | %} |
kvn@3390 | 1388 | |
kvn@3390 | 1389 | instruct vdivD_reg(regD dst, regD src1, regD src2) %{ |
kvn@3390 | 1390 | predicate(UseAVX > 0); |
kvn@3390 | 1391 | match(Set dst (DivD src1 src2)); |
kvn@3390 | 1392 | |
kvn@3390 | 1393 | format %{ "vdivsd $dst, $src1, $src2" %} |
kvn@3390 | 1394 | ins_cost(150); |
kvn@3390 | 1395 | ins_encode %{ |
kvn@3390 | 1396 | __ vdivsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
kvn@3390 | 1397 | %} |
kvn@3390 | 1398 | ins_pipe(pipe_slow); |
kvn@3390 | 1399 | %} |
kvn@3390 | 1400 | |
kvn@3390 | 1401 | instruct vdivD_mem(regD dst, regD src1, memory src2) %{ |
kvn@3390 | 1402 | predicate(UseAVX > 0); |
kvn@3390 | 1403 | match(Set dst (DivD src1 (LoadD src2))); |
kvn@3390 | 1404 | |
kvn@3390 | 1405 | format %{ "vdivsd $dst, $src1, $src2" %} |
kvn@3390 | 1406 | ins_cost(150); |
kvn@3390 | 1407 | ins_encode %{ |
kvn@3390 | 1408 | __ vdivsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
kvn@3390 | 1409 | %} |
kvn@3390 | 1410 | ins_pipe(pipe_slow); |
kvn@3390 | 1411 | %} |
kvn@3390 | 1412 | |
kvn@3390 | 1413 | instruct vdivD_imm(regD dst, regD src, immD con) %{ |
kvn@3390 | 1414 | predicate(UseAVX > 0); |
kvn@3390 | 1415 | match(Set dst (DivD src con)); |
kvn@3390 | 1416 | |
kvn@3390 | 1417 | format %{ "vdivsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %} |
kvn@3390 | 1418 | ins_cost(150); |
kvn@3390 | 1419 | ins_encode %{ |
kvn@3390 | 1420 | __ vdivsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 1421 | %} |
kvn@3390 | 1422 | ins_pipe(pipe_slow); |
kvn@3390 | 1423 | %} |
kvn@3390 | 1424 | |
kvn@3390 | 1425 | instruct absF_reg(regF dst) %{ |
kvn@3390 | 1426 | predicate((UseSSE>=1) && (UseAVX == 0)); |
kvn@3390 | 1427 | match(Set dst (AbsF dst)); |
kvn@3390 | 1428 | ins_cost(150); |
kvn@3390 | 1429 | format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %} |
kvn@3390 | 1430 | ins_encode %{ |
kvn@3390 | 1431 | __ andps($dst$$XMMRegister, ExternalAddress(float_signmask())); |
kvn@3390 | 1432 | %} |
kvn@3390 | 1433 | ins_pipe(pipe_slow); |
kvn@3390 | 1434 | %} |
kvn@3390 | 1435 | |
kvn@3390 | 1436 | instruct vabsF_reg(regF dst, regF src) %{ |
kvn@3390 | 1437 | predicate(UseAVX > 0); |
kvn@3390 | 1438 | match(Set dst (AbsF src)); |
kvn@3390 | 1439 | ins_cost(150); |
kvn@3390 | 1440 | format %{ "vandps $dst, $src, [0x7fffffff]\t# abs float by sign masking" %} |
kvn@3390 | 1441 | ins_encode %{ |
kvn@3390 | 1442 | __ vandps($dst$$XMMRegister, $src$$XMMRegister, |
kvn@3390 | 1443 | ExternalAddress(float_signmask())); |
kvn@3390 | 1444 | %} |
kvn@3390 | 1445 | ins_pipe(pipe_slow); |
kvn@3390 | 1446 | %} |
kvn@3390 | 1447 | |
kvn@3390 | 1448 | instruct absD_reg(regD dst) %{ |
kvn@3390 | 1449 | predicate((UseSSE>=2) && (UseAVX == 0)); |
kvn@3390 | 1450 | match(Set dst (AbsD dst)); |
kvn@3390 | 1451 | ins_cost(150); |
kvn@3390 | 1452 | format %{ "andpd $dst, [0x7fffffffffffffff]\t" |
kvn@3390 | 1453 | "# abs double by sign masking" %} |
kvn@3390 | 1454 | ins_encode %{ |
kvn@3390 | 1455 | __ andpd($dst$$XMMRegister, ExternalAddress(double_signmask())); |
kvn@3390 | 1456 | %} |
kvn@3390 | 1457 | ins_pipe(pipe_slow); |
kvn@3390 | 1458 | %} |
kvn@3390 | 1459 | |
kvn@3390 | 1460 | instruct vabsD_reg(regD dst, regD src) %{ |
kvn@3390 | 1461 | predicate(UseAVX > 0); |
kvn@3390 | 1462 | match(Set dst (AbsD src)); |
kvn@3390 | 1463 | ins_cost(150); |
kvn@3390 | 1464 | format %{ "vandpd $dst, $src, [0x7fffffffffffffff]\t" |
kvn@3390 | 1465 | "# abs double by sign masking" %} |
kvn@3390 | 1466 | ins_encode %{ |
kvn@3390 | 1467 | __ vandpd($dst$$XMMRegister, $src$$XMMRegister, |
kvn@3390 | 1468 | ExternalAddress(double_signmask())); |
kvn@3390 | 1469 | %} |
kvn@3390 | 1470 | ins_pipe(pipe_slow); |
kvn@3390 | 1471 | %} |
kvn@3390 | 1472 | |
kvn@3390 | 1473 | instruct negF_reg(regF dst) %{ |
kvn@3390 | 1474 | predicate((UseSSE>=1) && (UseAVX == 0)); |
kvn@3390 | 1475 | match(Set dst (NegF dst)); |
kvn@3390 | 1476 | ins_cost(150); |
kvn@3390 | 1477 | format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %} |
kvn@3390 | 1478 | ins_encode %{ |
kvn@3390 | 1479 | __ xorps($dst$$XMMRegister, ExternalAddress(float_signflip())); |
kvn@3390 | 1480 | %} |
kvn@3390 | 1481 | ins_pipe(pipe_slow); |
kvn@3390 | 1482 | %} |
kvn@3390 | 1483 | |
kvn@3390 | 1484 | instruct vnegF_reg(regF dst, regF src) %{ |
kvn@3390 | 1485 | predicate(UseAVX > 0); |
kvn@3390 | 1486 | match(Set dst (NegF src)); |
kvn@3390 | 1487 | ins_cost(150); |
kvn@3390 | 1488 | format %{ "vxorps $dst, $src, [0x80000000]\t# neg float by sign flipping" %} |
kvn@3390 | 1489 | ins_encode %{ |
kvn@3390 | 1490 | __ vxorps($dst$$XMMRegister, $src$$XMMRegister, |
kvn@3390 | 1491 | ExternalAddress(float_signflip())); |
kvn@3390 | 1492 | %} |
kvn@3390 | 1493 | ins_pipe(pipe_slow); |
kvn@3390 | 1494 | %} |
kvn@3390 | 1495 | |
kvn@3390 | 1496 | instruct negD_reg(regD dst) %{ |
kvn@3390 | 1497 | predicate((UseSSE>=2) && (UseAVX == 0)); |
kvn@3390 | 1498 | match(Set dst (NegD dst)); |
kvn@3390 | 1499 | ins_cost(150); |
kvn@3390 | 1500 | format %{ "xorpd $dst, [0x8000000000000000]\t" |
kvn@3390 | 1501 | "# neg double by sign flipping" %} |
kvn@3390 | 1502 | ins_encode %{ |
kvn@3390 | 1503 | __ xorpd($dst$$XMMRegister, ExternalAddress(double_signflip())); |
kvn@3390 | 1504 | %} |
kvn@3390 | 1505 | ins_pipe(pipe_slow); |
kvn@3390 | 1506 | %} |
kvn@3390 | 1507 | |
kvn@3390 | 1508 | instruct vnegD_reg(regD dst, regD src) %{ |
kvn@3390 | 1509 | predicate(UseAVX > 0); |
kvn@3390 | 1510 | match(Set dst (NegD src)); |
kvn@3390 | 1511 | ins_cost(150); |
kvn@3390 | 1512 | format %{ "vxorpd $dst, $src, [0x8000000000000000]\t" |
kvn@3390 | 1513 | "# neg double by sign flipping" %} |
kvn@3390 | 1514 | ins_encode %{ |
kvn@3390 | 1515 | __ vxorpd($dst$$XMMRegister, $src$$XMMRegister, |
kvn@3390 | 1516 | ExternalAddress(double_signflip())); |
kvn@3390 | 1517 | %} |
kvn@3390 | 1518 | ins_pipe(pipe_slow); |
kvn@3390 | 1519 | %} |
kvn@3390 | 1520 | |
kvn@3390 | 1521 | instruct sqrtF_reg(regF dst, regF src) %{ |
kvn@3390 | 1522 | predicate(UseSSE>=1); |
kvn@3390 | 1523 | match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); |
kvn@3390 | 1524 | |
kvn@3390 | 1525 | format %{ "sqrtss $dst, $src" %} |
kvn@3390 | 1526 | ins_cost(150); |
kvn@3390 | 1527 | ins_encode %{ |
kvn@3390 | 1528 | __ sqrtss($dst$$XMMRegister, $src$$XMMRegister); |
kvn@3390 | 1529 | %} |
kvn@3390 | 1530 | ins_pipe(pipe_slow); |
kvn@3390 | 1531 | %} |
kvn@3390 | 1532 | |
kvn@3390 | 1533 | instruct sqrtF_mem(regF dst, memory src) %{ |
kvn@3390 | 1534 | predicate(UseSSE>=1); |
kvn@3390 | 1535 | match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src))))); |
kvn@3390 | 1536 | |
kvn@3390 | 1537 | format %{ "sqrtss $dst, $src" %} |
kvn@3390 | 1538 | ins_cost(150); |
kvn@3390 | 1539 | ins_encode %{ |
kvn@3390 | 1540 | __ sqrtss($dst$$XMMRegister, $src$$Address); |
kvn@3390 | 1541 | %} |
kvn@3390 | 1542 | ins_pipe(pipe_slow); |
kvn@3390 | 1543 | %} |
kvn@3390 | 1544 | |
kvn@3390 | 1545 | instruct sqrtF_imm(regF dst, immF con) %{ |
kvn@3390 | 1546 | predicate(UseSSE>=1); |
kvn@3390 | 1547 | match(Set dst (ConvD2F (SqrtD (ConvF2D con)))); |
kvn@3390 | 1548 | format %{ "sqrtss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
kvn@3390 | 1549 | ins_cost(150); |
kvn@3390 | 1550 | ins_encode %{ |
kvn@3390 | 1551 | __ sqrtss($dst$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 1552 | %} |
kvn@3390 | 1553 | ins_pipe(pipe_slow); |
kvn@3390 | 1554 | %} |
kvn@3390 | 1555 | |
kvn@3390 | 1556 | instruct sqrtD_reg(regD dst, regD src) %{ |
kvn@3390 | 1557 | predicate(UseSSE>=2); |
kvn@3390 | 1558 | match(Set dst (SqrtD src)); |
kvn@3390 | 1559 | |
kvn@3390 | 1560 | format %{ "sqrtsd $dst, $src" %} |
kvn@3390 | 1561 | ins_cost(150); |
kvn@3390 | 1562 | ins_encode %{ |
kvn@3390 | 1563 | __ sqrtsd($dst$$XMMRegister, $src$$XMMRegister); |
kvn@3390 | 1564 | %} |
kvn@3390 | 1565 | ins_pipe(pipe_slow); |
kvn@3390 | 1566 | %} |
kvn@3390 | 1567 | |
kvn@3390 | 1568 | instruct sqrtD_mem(regD dst, memory src) %{ |
kvn@3390 | 1569 | predicate(UseSSE>=2); |
kvn@3390 | 1570 | match(Set dst (SqrtD (LoadD src))); |
kvn@3390 | 1571 | |
kvn@3390 | 1572 | format %{ "sqrtsd $dst, $src" %} |
kvn@3390 | 1573 | ins_cost(150); |
kvn@3390 | 1574 | ins_encode %{ |
kvn@3390 | 1575 | __ sqrtsd($dst$$XMMRegister, $src$$Address); |
kvn@3390 | 1576 | %} |
kvn@3390 | 1577 | ins_pipe(pipe_slow); |
kvn@3390 | 1578 | %} |
kvn@3390 | 1579 | |
kvn@3390 | 1580 | instruct sqrtD_imm(regD dst, immD con) %{ |
kvn@3390 | 1581 | predicate(UseSSE>=2); |
kvn@3390 | 1582 | match(Set dst (SqrtD con)); |
kvn@3390 | 1583 | format %{ "sqrtsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
kvn@3390 | 1584 | ins_cost(150); |
kvn@3390 | 1585 | ins_encode %{ |
kvn@3390 | 1586 | __ sqrtsd($dst$$XMMRegister, $constantaddress($con)); |
kvn@3390 | 1587 | %} |
kvn@3390 | 1588 | ins_pipe(pipe_slow); |
kvn@3390 | 1589 | %} |
kvn@3390 | 1590 | |
kvn@3882 | 1591 | |
kvn@3882 | 1592 | // ====================VECTOR INSTRUCTIONS===================================== |
kvn@3882 | 1593 | |
kvn@3882 | 1594 | // Load vectors (4 bytes long) |
kvn@3882 | 1595 | instruct loadV4(vecS dst, memory mem) %{ |
kvn@3882 | 1596 | predicate(n->as_LoadVector()->memory_size() == 4); |
kvn@3882 | 1597 | match(Set dst (LoadVector mem)); |
kvn@3882 | 1598 | ins_cost(125); |
kvn@3882 | 1599 | format %{ "movd $dst,$mem\t! load vector (4 bytes)" %} |
kvn@3882 | 1600 | ins_encode %{ |
kvn@3882 | 1601 | __ movdl($dst$$XMMRegister, $mem$$Address); |
kvn@3882 | 1602 | %} |
kvn@3882 | 1603 | ins_pipe( pipe_slow ); |
kvn@3882 | 1604 | %} |
kvn@3882 | 1605 | |
kvn@3882 | 1606 | // Load vectors (8 bytes long) |
kvn@3882 | 1607 | instruct loadV8(vecD dst, memory mem) %{ |
kvn@3882 | 1608 | predicate(n->as_LoadVector()->memory_size() == 8); |
kvn@3882 | 1609 | match(Set dst (LoadVector mem)); |
kvn@3882 | 1610 | ins_cost(125); |
kvn@3882 | 1611 | format %{ "movq $dst,$mem\t! load vector (8 bytes)" %} |
kvn@3882 | 1612 | ins_encode %{ |
kvn@3882 | 1613 | __ movq($dst$$XMMRegister, $mem$$Address); |
kvn@3882 | 1614 | %} |
kvn@3882 | 1615 | ins_pipe( pipe_slow ); |
kvn@3882 | 1616 | %} |
kvn@3882 | 1617 | |
kvn@3882 | 1618 | // Load vectors (16 bytes long) |
kvn@3882 | 1619 | instruct loadV16(vecX dst, memory mem) %{ |
kvn@3882 | 1620 | predicate(n->as_LoadVector()->memory_size() == 16); |
kvn@3882 | 1621 | match(Set dst (LoadVector mem)); |
kvn@3882 | 1622 | ins_cost(125); |
kvn@3882 | 1623 | format %{ "movdqu $dst,$mem\t! load vector (16 bytes)" %} |
kvn@3882 | 1624 | ins_encode %{ |
kvn@3882 | 1625 | __ movdqu($dst$$XMMRegister, $mem$$Address); |
kvn@3882 | 1626 | %} |
kvn@3882 | 1627 | ins_pipe( pipe_slow ); |
kvn@3882 | 1628 | %} |
kvn@3882 | 1629 | |
kvn@3882 | 1630 | // Load vectors (32 bytes long) |
kvn@3882 | 1631 | instruct loadV32(vecY dst, memory mem) %{ |
kvn@3882 | 1632 | predicate(n->as_LoadVector()->memory_size() == 32); |
kvn@3882 | 1633 | match(Set dst (LoadVector mem)); |
kvn@3882 | 1634 | ins_cost(125); |
kvn@3882 | 1635 | format %{ "vmovdqu $dst,$mem\t! load vector (32 bytes)" %} |
kvn@3882 | 1636 | ins_encode %{ |
kvn@3882 | 1637 | __ vmovdqu($dst$$XMMRegister, $mem$$Address); |
kvn@3882 | 1638 | %} |
kvn@3882 | 1639 | ins_pipe( pipe_slow ); |
kvn@3882 | 1640 | %} |
kvn@3882 | 1641 | |
kvn@3882 | 1642 | // Store vectors |
kvn@3882 | 1643 | instruct storeV4(memory mem, vecS src) %{ |
kvn@3882 | 1644 | predicate(n->as_StoreVector()->memory_size() == 4); |
kvn@3882 | 1645 | match(Set mem (StoreVector mem src)); |
kvn@3882 | 1646 | ins_cost(145); |
kvn@3882 | 1647 | format %{ "movd $mem,$src\t! store vector (4 bytes)" %} |
kvn@3882 | 1648 | ins_encode %{ |
kvn@3882 | 1649 | __ movdl($mem$$Address, $src$$XMMRegister); |
kvn@3882 | 1650 | %} |
kvn@3882 | 1651 | ins_pipe( pipe_slow ); |
kvn@3882 | 1652 | %} |
kvn@3882 | 1653 | |
kvn@3882 | 1654 | instruct storeV8(memory mem, vecD src) %{ |
kvn@3882 | 1655 | predicate(n->as_StoreVector()->memory_size() == 8); |
kvn@3882 | 1656 | match(Set mem (StoreVector mem src)); |
kvn@3882 | 1657 | ins_cost(145); |
kvn@3882 | 1658 | format %{ "movq $mem,$src\t! store vector (8 bytes)" %} |
kvn@3882 | 1659 | ins_encode %{ |
kvn@3882 | 1660 | __ movq($mem$$Address, $src$$XMMRegister); |
kvn@3882 | 1661 | %} |
kvn@3882 | 1662 | ins_pipe( pipe_slow ); |
kvn@3882 | 1663 | %} |
kvn@3882 | 1664 | |
kvn@3882 | 1665 | instruct storeV16(memory mem, vecX src) %{ |
kvn@3882 | 1666 | predicate(n->as_StoreVector()->memory_size() == 16); |
kvn@3882 | 1667 | match(Set mem (StoreVector mem src)); |
kvn@3882 | 1668 | ins_cost(145); |
kvn@3882 | 1669 | format %{ "movdqu $mem,$src\t! store vector (16 bytes)" %} |
kvn@3882 | 1670 | ins_encode %{ |
kvn@3882 | 1671 | __ movdqu($mem$$Address, $src$$XMMRegister); |
kvn@3882 | 1672 | %} |
kvn@3882 | 1673 | ins_pipe( pipe_slow ); |
kvn@3882 | 1674 | %} |
kvn@3882 | 1675 | |
kvn@3882 | 1676 | instruct storeV32(memory mem, vecY src) %{ |
kvn@3882 | 1677 | predicate(n->as_StoreVector()->memory_size() == 32); |
kvn@3882 | 1678 | match(Set mem (StoreVector mem src)); |
kvn@3882 | 1679 | ins_cost(145); |
kvn@3882 | 1680 | format %{ "vmovdqu $mem,$src\t! store vector (32 bytes)" %} |
kvn@3882 | 1681 | ins_encode %{ |
kvn@3882 | 1682 | __ vmovdqu($mem$$Address, $src$$XMMRegister); |
kvn@3882 | 1683 | %} |
kvn@3882 | 1684 | ins_pipe( pipe_slow ); |
kvn@3882 | 1685 | %} |
kvn@3882 | 1686 | |
kvn@3882 | 1687 | // Replicate byte scalar to be vector |
kvn@3882 | 1688 | instruct Repl4B(vecS dst, rRegI src) %{ |
kvn@3882 | 1689 | predicate(n->as_Vector()->length() == 4); |
kvn@3882 | 1690 | match(Set dst (ReplicateB src)); |
kvn@3882 | 1691 | format %{ "movd $dst,$src\n\t" |
kvn@3882 | 1692 | "punpcklbw $dst,$dst\n\t" |
kvn@3882 | 1693 | "pshuflw $dst,$dst,0x00\t! replicate4B" %} |
kvn@3882 | 1694 | ins_encode %{ |
kvn@3882 | 1695 | __ movdl($dst$$XMMRegister, $src$$Register); |
kvn@3882 | 1696 | __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1697 | __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
kvn@3882 | 1698 | %} |
kvn@3882 | 1699 | ins_pipe( pipe_slow ); |
kvn@3882 | 1700 | %} |
kvn@3882 | 1701 | |
kvn@3882 | 1702 | instruct Repl8B(vecD dst, rRegI src) %{ |
kvn@3882 | 1703 | predicate(n->as_Vector()->length() == 8); |
kvn@3882 | 1704 | match(Set dst (ReplicateB src)); |
kvn@3882 | 1705 | format %{ "movd $dst,$src\n\t" |
kvn@3882 | 1706 | "punpcklbw $dst,$dst\n\t" |
kvn@3882 | 1707 | "pshuflw $dst,$dst,0x00\t! replicate8B" %} |
kvn@3882 | 1708 | ins_encode %{ |
kvn@3882 | 1709 | __ movdl($dst$$XMMRegister, $src$$Register); |
kvn@3882 | 1710 | __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1711 | __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
kvn@3882 | 1712 | %} |
kvn@3882 | 1713 | ins_pipe( pipe_slow ); |
kvn@3882 | 1714 | %} |
kvn@3882 | 1715 | |
kvn@3882 | 1716 | instruct Repl16B(vecX dst, rRegI src) %{ |
kvn@3882 | 1717 | predicate(n->as_Vector()->length() == 16); |
kvn@3882 | 1718 | match(Set dst (ReplicateB src)); |
kvn@3882 | 1719 | format %{ "movd $dst,$src\n\t" |
kvn@3882 | 1720 | "punpcklbw $dst,$dst\n\t" |
kvn@3882 | 1721 | "pshuflw $dst,$dst,0x00\n\t" |
kvn@3882 | 1722 | "movlhps $dst,$dst\t! replicate16B" %} |
kvn@3882 | 1723 | ins_encode %{ |
kvn@3882 | 1724 | __ movdl($dst$$XMMRegister, $src$$Register); |
kvn@3882 | 1725 | __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1726 | __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
kvn@3882 | 1727 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1728 | %} |
kvn@3882 | 1729 | ins_pipe( pipe_slow ); |
kvn@3882 | 1730 | %} |
kvn@3882 | 1731 | |
kvn@3882 | 1732 | instruct Repl32B(vecY dst, rRegI src) %{ |
kvn@3882 | 1733 | predicate(n->as_Vector()->length() == 32); |
kvn@3882 | 1734 | match(Set dst (ReplicateB src)); |
kvn@3882 | 1735 | format %{ "movd $dst,$src\n\t" |
kvn@3882 | 1736 | "punpcklbw $dst,$dst\n\t" |
kvn@3882 | 1737 | "pshuflw $dst,$dst,0x00\n\t" |
kvn@3882 | 1738 | "movlhps $dst,$dst\n\t" |
kvn@3882 | 1739 | "vinsertf128h $dst,$dst,$dst\t! replicate32B" %} |
kvn@3882 | 1740 | ins_encode %{ |
kvn@3882 | 1741 | __ movdl($dst$$XMMRegister, $src$$Register); |
kvn@3882 | 1742 | __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1743 | __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
kvn@3882 | 1744 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1745 | __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1746 | %} |
kvn@3882 | 1747 | ins_pipe( pipe_slow ); |
kvn@3882 | 1748 | %} |
kvn@3882 | 1749 | |
kvn@3882 | 1750 | // Replicate byte scalar immediate to be vector by loading from const table. |
kvn@3882 | 1751 | instruct Repl4B_imm(vecS dst, immI con) %{ |
kvn@3882 | 1752 | predicate(n->as_Vector()->length() == 4); |
kvn@3882 | 1753 | match(Set dst (ReplicateB con)); |
kvn@3882 | 1754 | format %{ "movss $dst,[$constantaddress]\t! replicate4B($con)" %} |
kvn@3882 | 1755 | ins_encode %{ |
kvn@3882 | 1756 | __ movflt($dst$$XMMRegister, $constantaddress(replicate4_imm($con$$constant, 1))); |
kvn@3882 | 1757 | %} |
kvn@3882 | 1758 | ins_pipe( pipe_slow ); |
kvn@3882 | 1759 | %} |
kvn@3882 | 1760 | |
kvn@3882 | 1761 | instruct Repl8B_imm(vecD dst, immI con) %{ |
kvn@3882 | 1762 | predicate(n->as_Vector()->length() == 8); |
kvn@3882 | 1763 | match(Set dst (ReplicateB con)); |
kvn@3882 | 1764 | format %{ "movsd $dst,[$constantaddress]\t! replicate8B($con)" %} |
kvn@3882 | 1765 | ins_encode %{ |
kvn@3882 | 1766 | __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1))); |
kvn@3882 | 1767 | %} |
kvn@3882 | 1768 | ins_pipe( pipe_slow ); |
kvn@3882 | 1769 | %} |
kvn@3882 | 1770 | |
kvn@3882 | 1771 | instruct Repl16B_imm(vecX dst, immI con) %{ |
kvn@3882 | 1772 | predicate(n->as_Vector()->length() == 16); |
kvn@3882 | 1773 | match(Set dst (ReplicateB con)); |
kvn@3882 | 1774 | format %{ "movsd $dst,[$constantaddress]\t! replicate16B($con)\n\t" |
kvn@3882 | 1775 | "movlhps $dst,$dst" %} |
kvn@3882 | 1776 | ins_encode %{ |
kvn@3882 | 1777 | __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1))); |
kvn@3882 | 1778 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1779 | %} |
kvn@3882 | 1780 | ins_pipe( pipe_slow ); |
kvn@3882 | 1781 | %} |
kvn@3882 | 1782 | |
kvn@3882 | 1783 | instruct Repl32B_imm(vecY dst, immI con) %{ |
kvn@3882 | 1784 | predicate(n->as_Vector()->length() == 32); |
kvn@3882 | 1785 | match(Set dst (ReplicateB con)); |
kvn@3882 | 1786 | format %{ "movsd $dst,[$constantaddress]\t! lreplicate32B($con)\n\t" |
kvn@3882 | 1787 | "movlhps $dst,$dst\n\t" |
kvn@3882 | 1788 | "vinsertf128h $dst,$dst,$dst" %} |
kvn@3882 | 1789 | ins_encode %{ |
kvn@3882 | 1790 | __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1))); |
kvn@3882 | 1791 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1792 | __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1793 | %} |
kvn@3882 | 1794 | ins_pipe( pipe_slow ); |
kvn@3882 | 1795 | %} |
kvn@3882 | 1796 | |
kvn@3882 | 1797 | // Replicate byte scalar zero to be vector |
kvn@3882 | 1798 | instruct Repl4B_zero(vecS dst, immI0 zero) %{ |
kvn@3882 | 1799 | predicate(n->as_Vector()->length() == 4); |
kvn@3882 | 1800 | match(Set dst (ReplicateB zero)); |
kvn@3882 | 1801 | format %{ "pxor $dst,$dst\t! replicate4B zero" %} |
kvn@3882 | 1802 | ins_encode %{ |
kvn@3882 | 1803 | __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1804 | %} |
kvn@3882 | 1805 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 1806 | %} |
kvn@3882 | 1807 | |
kvn@3882 | 1808 | instruct Repl8B_zero(vecD dst, immI0 zero) %{ |
kvn@3882 | 1809 | predicate(n->as_Vector()->length() == 8); |
kvn@3882 | 1810 | match(Set dst (ReplicateB zero)); |
kvn@3882 | 1811 | format %{ "pxor $dst,$dst\t! replicate8B zero" %} |
kvn@3882 | 1812 | ins_encode %{ |
kvn@3882 | 1813 | __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1814 | %} |
kvn@3882 | 1815 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 1816 | %} |
kvn@3882 | 1817 | |
kvn@3882 | 1818 | instruct Repl16B_zero(vecX dst, immI0 zero) %{ |
kvn@3882 | 1819 | predicate(n->as_Vector()->length() == 16); |
kvn@3882 | 1820 | match(Set dst (ReplicateB zero)); |
kvn@3882 | 1821 | format %{ "pxor $dst,$dst\t! replicate16B zero" %} |
kvn@3882 | 1822 | ins_encode %{ |
kvn@3882 | 1823 | __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1824 | %} |
kvn@3882 | 1825 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 1826 | %} |
kvn@3882 | 1827 | |
kvn@3882 | 1828 | instruct Repl32B_zero(vecY dst, immI0 zero) %{ |
kvn@3882 | 1829 | predicate(n->as_Vector()->length() == 32); |
kvn@3882 | 1830 | match(Set dst (ReplicateB zero)); |
kvn@3882 | 1831 | format %{ "vxorpd $dst,$dst,$dst\t! replicate32B zero" %} |
kvn@3882 | 1832 | ins_encode %{ |
kvn@3882 | 1833 | // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it). |
kvn@3882 | 1834 | bool vector256 = true; |
kvn@3882 | 1835 | __ vxorpd($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
kvn@3882 | 1836 | %} |
kvn@3882 | 1837 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 1838 | %} |
kvn@3882 | 1839 | |
kvn@3882 | 1840 | // Replicate char/short (2 byte) scalar to be vector |
kvn@3882 | 1841 | instruct Repl2S(vecS dst, rRegI src) %{ |
kvn@3882 | 1842 | predicate(n->as_Vector()->length() == 2); |
kvn@3882 | 1843 | match(Set dst (ReplicateS src)); |
kvn@3882 | 1844 | format %{ "movd $dst,$src\n\t" |
kvn@3882 | 1845 | "pshuflw $dst,$dst,0x00\t! replicate2S" %} |
kvn@3882 | 1846 | ins_encode %{ |
kvn@3882 | 1847 | __ movdl($dst$$XMMRegister, $src$$Register); |
kvn@3882 | 1848 | __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
kvn@3882 | 1849 | %} |
kvn@3882 | 1850 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 1851 | %} |
kvn@3882 | 1852 | |
kvn@3882 | 1853 | instruct Repl4S(vecD dst, rRegI src) %{ |
kvn@3882 | 1854 | predicate(n->as_Vector()->length() == 4); |
kvn@3882 | 1855 | match(Set dst (ReplicateS src)); |
kvn@3882 | 1856 | format %{ "movd $dst,$src\n\t" |
kvn@3882 | 1857 | "pshuflw $dst,$dst,0x00\t! replicate4S" %} |
kvn@3882 | 1858 | ins_encode %{ |
kvn@3882 | 1859 | __ movdl($dst$$XMMRegister, $src$$Register); |
kvn@3882 | 1860 | __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
kvn@3882 | 1861 | %} |
kvn@3882 | 1862 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 1863 | %} |
kvn@3882 | 1864 | |
kvn@3882 | 1865 | instruct Repl8S(vecX dst, rRegI src) %{ |
kvn@3882 | 1866 | predicate(n->as_Vector()->length() == 8); |
kvn@3882 | 1867 | match(Set dst (ReplicateS src)); |
kvn@3882 | 1868 | format %{ "movd $dst,$src\n\t" |
kvn@3882 | 1869 | "pshuflw $dst,$dst,0x00\n\t" |
kvn@3882 | 1870 | "movlhps $dst,$dst\t! replicate8S" %} |
kvn@3882 | 1871 | ins_encode %{ |
kvn@3882 | 1872 | __ movdl($dst$$XMMRegister, $src$$Register); |
kvn@3882 | 1873 | __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
kvn@3882 | 1874 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1875 | %} |
kvn@3882 | 1876 | ins_pipe( pipe_slow ); |
kvn@3882 | 1877 | %} |
kvn@3882 | 1878 | |
kvn@3882 | 1879 | instruct Repl16S(vecY dst, rRegI src) %{ |
kvn@3882 | 1880 | predicate(n->as_Vector()->length() == 16); |
kvn@3882 | 1881 | match(Set dst (ReplicateS src)); |
kvn@3882 | 1882 | format %{ "movd $dst,$src\n\t" |
kvn@3882 | 1883 | "pshuflw $dst,$dst,0x00\n\t" |
kvn@3882 | 1884 | "movlhps $dst,$dst\n\t" |
kvn@3882 | 1885 | "vinsertf128h $dst,$dst,$dst\t! replicate16S" %} |
kvn@3882 | 1886 | ins_encode %{ |
kvn@3882 | 1887 | __ movdl($dst$$XMMRegister, $src$$Register); |
kvn@3882 | 1888 | __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
kvn@3882 | 1889 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1890 | __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1891 | %} |
kvn@3882 | 1892 | ins_pipe( pipe_slow ); |
kvn@3882 | 1893 | %} |
kvn@3882 | 1894 | |
kvn@3882 | 1895 | // Replicate char/short (2 byte) scalar immediate to be vector by loading from const table. |
kvn@3882 | 1896 | instruct Repl2S_imm(vecS dst, immI con) %{ |
kvn@3882 | 1897 | predicate(n->as_Vector()->length() == 2); |
kvn@3882 | 1898 | match(Set dst (ReplicateS con)); |
kvn@3882 | 1899 | format %{ "movss $dst,[$constantaddress]\t! replicate2S($con)" %} |
kvn@3882 | 1900 | ins_encode %{ |
kvn@3882 | 1901 | __ movflt($dst$$XMMRegister, $constantaddress(replicate4_imm($con$$constant, 2))); |
kvn@3882 | 1902 | %} |
kvn@3882 | 1903 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 1904 | %} |
kvn@3882 | 1905 | |
kvn@3882 | 1906 | instruct Repl4S_imm(vecD dst, immI con) %{ |
kvn@3882 | 1907 | predicate(n->as_Vector()->length() == 4); |
kvn@3882 | 1908 | match(Set dst (ReplicateS con)); |
kvn@3882 | 1909 | format %{ "movsd $dst,[$constantaddress]\t! replicate4S($con)" %} |
kvn@3882 | 1910 | ins_encode %{ |
kvn@3882 | 1911 | __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2))); |
kvn@3882 | 1912 | %} |
kvn@3882 | 1913 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 1914 | %} |
kvn@3882 | 1915 | |
kvn@3882 | 1916 | instruct Repl8S_imm(vecX dst, immI con) %{ |
kvn@3882 | 1917 | predicate(n->as_Vector()->length() == 8); |
kvn@3882 | 1918 | match(Set dst (ReplicateS con)); |
kvn@3882 | 1919 | format %{ "movsd $dst,[$constantaddress]\t! replicate8S($con)\n\t" |
kvn@3882 | 1920 | "movlhps $dst,$dst" %} |
kvn@3882 | 1921 | ins_encode %{ |
kvn@3882 | 1922 | __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2))); |
kvn@3882 | 1923 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1924 | %} |
kvn@3882 | 1925 | ins_pipe( pipe_slow ); |
kvn@3882 | 1926 | %} |
kvn@3882 | 1927 | |
kvn@3882 | 1928 | instruct Repl16S_imm(vecY dst, immI con) %{ |
kvn@3882 | 1929 | predicate(n->as_Vector()->length() == 16); |
kvn@3882 | 1930 | match(Set dst (ReplicateS con)); |
kvn@3882 | 1931 | format %{ "movsd $dst,[$constantaddress]\t! replicate16S($con)\n\t" |
kvn@3882 | 1932 | "movlhps $dst,$dst\n\t" |
kvn@3882 | 1933 | "vinsertf128h $dst,$dst,$dst" %} |
kvn@3882 | 1934 | ins_encode %{ |
kvn@3882 | 1935 | __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2))); |
kvn@3882 | 1936 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1937 | __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1938 | %} |
kvn@3882 | 1939 | ins_pipe( pipe_slow ); |
kvn@3882 | 1940 | %} |
kvn@3882 | 1941 | |
kvn@3882 | 1942 | // Replicate char/short (2 byte) scalar zero to be vector |
kvn@3882 | 1943 | instruct Repl2S_zero(vecS dst, immI0 zero) %{ |
kvn@3882 | 1944 | predicate(n->as_Vector()->length() == 2); |
kvn@3882 | 1945 | match(Set dst (ReplicateS zero)); |
kvn@3882 | 1946 | format %{ "pxor $dst,$dst\t! replicate2S zero" %} |
kvn@3882 | 1947 | ins_encode %{ |
kvn@3882 | 1948 | __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1949 | %} |
kvn@3882 | 1950 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 1951 | %} |
kvn@3882 | 1952 | |
kvn@3882 | 1953 | instruct Repl4S_zero(vecD dst, immI0 zero) %{ |
kvn@3882 | 1954 | predicate(n->as_Vector()->length() == 4); |
kvn@3882 | 1955 | match(Set dst (ReplicateS zero)); |
kvn@3882 | 1956 | format %{ "pxor $dst,$dst\t! replicate4S zero" %} |
kvn@3882 | 1957 | ins_encode %{ |
kvn@3882 | 1958 | __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1959 | %} |
kvn@3882 | 1960 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 1961 | %} |
kvn@3882 | 1962 | |
kvn@3882 | 1963 | instruct Repl8S_zero(vecX dst, immI0 zero) %{ |
kvn@3882 | 1964 | predicate(n->as_Vector()->length() == 8); |
kvn@3882 | 1965 | match(Set dst (ReplicateS zero)); |
kvn@3882 | 1966 | format %{ "pxor $dst,$dst\t! replicate8S zero" %} |
kvn@3882 | 1967 | ins_encode %{ |
kvn@3882 | 1968 | __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 1969 | %} |
kvn@3882 | 1970 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 1971 | %} |
kvn@3882 | 1972 | |
kvn@3882 | 1973 | instruct Repl16S_zero(vecY dst, immI0 zero) %{ |
kvn@3882 | 1974 | predicate(n->as_Vector()->length() == 16); |
kvn@3882 | 1975 | match(Set dst (ReplicateS zero)); |
kvn@3882 | 1976 | format %{ "vxorpd $dst,$dst,$dst\t! replicate16S zero" %} |
kvn@3882 | 1977 | ins_encode %{ |
kvn@3882 | 1978 | // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it). |
kvn@3882 | 1979 | bool vector256 = true; |
kvn@3882 | 1980 | __ vxorpd($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
kvn@3882 | 1981 | %} |
kvn@3882 | 1982 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 1983 | %} |
kvn@3882 | 1984 | |
kvn@3882 | 1985 | // Replicate integer (4 byte) scalar to be vector |
kvn@3882 | 1986 | instruct Repl2I(vecD dst, rRegI src) %{ |
kvn@3882 | 1987 | predicate(n->as_Vector()->length() == 2); |
kvn@3882 | 1988 | match(Set dst (ReplicateI src)); |
kvn@3882 | 1989 | format %{ "movd $dst,$src\n\t" |
kvn@3882 | 1990 | "pshufd $dst,$dst,0x00\t! replicate2I" %} |
kvn@3882 | 1991 | ins_encode %{ |
kvn@3882 | 1992 | __ movdl($dst$$XMMRegister, $src$$Register); |
kvn@3882 | 1993 | __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
kvn@3882 | 1994 | %} |
kvn@3882 | 1995 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 1996 | %} |
kvn@3882 | 1997 | |
kvn@3882 | 1998 | instruct Repl4I(vecX dst, rRegI src) %{ |
kvn@3882 | 1999 | predicate(n->as_Vector()->length() == 4); |
kvn@3882 | 2000 | match(Set dst (ReplicateI src)); |
kvn@3882 | 2001 | format %{ "movd $dst,$src\n\t" |
kvn@3882 | 2002 | "pshufd $dst,$dst,0x00\t! replicate4I" %} |
kvn@3882 | 2003 | ins_encode %{ |
kvn@3882 | 2004 | __ movdl($dst$$XMMRegister, $src$$Register); |
kvn@3882 | 2005 | __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
kvn@3882 | 2006 | %} |
kvn@3882 | 2007 | ins_pipe( pipe_slow ); |
kvn@3882 | 2008 | %} |
kvn@3882 | 2009 | |
kvn@3882 | 2010 | instruct Repl8I(vecY dst, rRegI src) %{ |
kvn@3882 | 2011 | predicate(n->as_Vector()->length() == 8); |
kvn@3882 | 2012 | match(Set dst (ReplicateI src)); |
kvn@3882 | 2013 | format %{ "movd $dst,$src\n\t" |
kvn@3882 | 2014 | "pshufd $dst,$dst,0x00\n\t" |
kvn@3882 | 2015 | "vinsertf128h $dst,$dst,$dst\t! replicate8I" %} |
kvn@3882 | 2016 | ins_encode %{ |
kvn@3882 | 2017 | __ movdl($dst$$XMMRegister, $src$$Register); |
kvn@3882 | 2018 | __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
kvn@3882 | 2019 | __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2020 | %} |
kvn@3882 | 2021 | ins_pipe( pipe_slow ); |
kvn@3882 | 2022 | %} |
kvn@3882 | 2023 | |
kvn@3882 | 2024 | // Replicate integer (4 byte) scalar immediate to be vector by loading from const table. |
kvn@3882 | 2025 | instruct Repl2I_imm(vecD dst, immI con) %{ |
kvn@3882 | 2026 | predicate(n->as_Vector()->length() == 2); |
kvn@3882 | 2027 | match(Set dst (ReplicateI con)); |
kvn@3882 | 2028 | format %{ "movsd $dst,[$constantaddress]\t! replicate2I($con)" %} |
kvn@3882 | 2029 | ins_encode %{ |
kvn@3882 | 2030 | __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4))); |
kvn@3882 | 2031 | %} |
kvn@3882 | 2032 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 2033 | %} |
kvn@3882 | 2034 | |
kvn@3882 | 2035 | instruct Repl4I_imm(vecX dst, immI con) %{ |
kvn@3882 | 2036 | predicate(n->as_Vector()->length() == 4); |
kvn@3882 | 2037 | match(Set dst (ReplicateI con)); |
kvn@3882 | 2038 | format %{ "movsd $dst,[$constantaddress]\t! replicate4I($con)\n\t" |
kvn@3882 | 2039 | "movlhps $dst,$dst" %} |
kvn@3882 | 2040 | ins_encode %{ |
kvn@3882 | 2041 | __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4))); |
kvn@3882 | 2042 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2043 | %} |
kvn@3882 | 2044 | ins_pipe( pipe_slow ); |
kvn@3882 | 2045 | %} |
kvn@3882 | 2046 | |
kvn@3882 | 2047 | instruct Repl8I_imm(vecY dst, immI con) %{ |
kvn@3882 | 2048 | predicate(n->as_Vector()->length() == 8); |
kvn@3882 | 2049 | match(Set dst (ReplicateI con)); |
kvn@3882 | 2050 | format %{ "movsd $dst,[$constantaddress]\t! replicate8I($con)\n\t" |
kvn@3882 | 2051 | "movlhps $dst,$dst\n\t" |
kvn@3882 | 2052 | "vinsertf128h $dst,$dst,$dst" %} |
kvn@3882 | 2053 | ins_encode %{ |
kvn@3882 | 2054 | __ movdbl($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4))); |
kvn@3882 | 2055 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2056 | __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2057 | %} |
kvn@3882 | 2058 | ins_pipe( pipe_slow ); |
kvn@3882 | 2059 | %} |
kvn@3882 | 2060 | |
kvn@3882 | 2061 | // Integer could be loaded into xmm register directly from memory. |
kvn@3882 | 2062 | instruct Repl2I_mem(vecD dst, memory mem) %{ |
kvn@3882 | 2063 | predicate(n->as_Vector()->length() == 2); |
kvn@3886 | 2064 | match(Set dst (ReplicateI (LoadVector mem))); |
kvn@3882 | 2065 | format %{ "movd $dst,$mem\n\t" |
kvn@3882 | 2066 | "pshufd $dst,$dst,0x00\t! replicate2I" %} |
kvn@3882 | 2067 | ins_encode %{ |
kvn@3882 | 2068 | __ movdl($dst$$XMMRegister, $mem$$Address); |
kvn@3882 | 2069 | __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
kvn@3882 | 2070 | %} |
kvn@3882 | 2071 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 2072 | %} |
kvn@3882 | 2073 | |
kvn@3882 | 2074 | instruct Repl4I_mem(vecX dst, memory mem) %{ |
kvn@3882 | 2075 | predicate(n->as_Vector()->length() == 4); |
kvn@3886 | 2076 | match(Set dst (ReplicateI (LoadVector mem))); |
kvn@3882 | 2077 | format %{ "movd $dst,$mem\n\t" |
kvn@3882 | 2078 | "pshufd $dst,$dst,0x00\t! replicate4I" %} |
kvn@3882 | 2079 | ins_encode %{ |
kvn@3882 | 2080 | __ movdl($dst$$XMMRegister, $mem$$Address); |
kvn@3882 | 2081 | __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
kvn@3882 | 2082 | %} |
kvn@3882 | 2083 | ins_pipe( pipe_slow ); |
kvn@3882 | 2084 | %} |
kvn@3882 | 2085 | |
kvn@3882 | 2086 | instruct Repl8I_mem(vecY dst, memory mem) %{ |
kvn@3882 | 2087 | predicate(n->as_Vector()->length() == 8); |
kvn@3886 | 2088 | match(Set dst (ReplicateI (LoadVector mem))); |
kvn@3882 | 2089 | format %{ "movd $dst,$mem\n\t" |
kvn@3882 | 2090 | "pshufd $dst,$dst,0x00\n\t" |
kvn@3882 | 2091 | "vinsertf128h $dst,$dst,$dst\t! replicate8I" %} |
kvn@3882 | 2092 | ins_encode %{ |
kvn@3882 | 2093 | __ movdl($dst$$XMMRegister, $mem$$Address); |
kvn@3882 | 2094 | __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
kvn@3882 | 2095 | __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2096 | %} |
kvn@3882 | 2097 | ins_pipe( pipe_slow ); |
kvn@3882 | 2098 | %} |
kvn@3882 | 2099 | |
kvn@3882 | 2100 | // Replicate integer (4 byte) scalar zero to be vector |
kvn@3882 | 2101 | instruct Repl2I_zero(vecD dst, immI0 zero) %{ |
kvn@3882 | 2102 | predicate(n->as_Vector()->length() == 2); |
kvn@3882 | 2103 | match(Set dst (ReplicateI zero)); |
kvn@3882 | 2104 | format %{ "pxor $dst,$dst\t! replicate2I" %} |
kvn@3882 | 2105 | ins_encode %{ |
kvn@3882 | 2106 | __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2107 | %} |
kvn@3882 | 2108 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 2109 | %} |
kvn@3882 | 2110 | |
kvn@3882 | 2111 | instruct Repl4I_zero(vecX dst, immI0 zero) %{ |
kvn@3882 | 2112 | predicate(n->as_Vector()->length() == 4); |
kvn@3882 | 2113 | match(Set dst (ReplicateI zero)); |
kvn@3882 | 2114 | format %{ "pxor $dst,$dst\t! replicate4I zero)" %} |
kvn@3882 | 2115 | ins_encode %{ |
kvn@3882 | 2116 | __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2117 | %} |
kvn@3882 | 2118 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 2119 | %} |
kvn@3882 | 2120 | |
kvn@3882 | 2121 | instruct Repl8I_zero(vecY dst, immI0 zero) %{ |
kvn@3882 | 2122 | predicate(n->as_Vector()->length() == 8); |
kvn@3882 | 2123 | match(Set dst (ReplicateI zero)); |
kvn@3882 | 2124 | format %{ "vxorpd $dst,$dst,$dst\t! replicate8I zero" %} |
kvn@3882 | 2125 | ins_encode %{ |
kvn@3882 | 2126 | // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it). |
kvn@3882 | 2127 | bool vector256 = true; |
kvn@3882 | 2128 | __ vxorpd($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
kvn@3882 | 2129 | %} |
kvn@3882 | 2130 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 2131 | %} |
kvn@3882 | 2132 | |
kvn@3882 | 2133 | // Replicate long (8 byte) scalar to be vector |
kvn@3882 | 2134 | #ifdef _LP64 |
kvn@3882 | 2135 | instruct Repl2L(vecX dst, rRegL src) %{ |
kvn@3882 | 2136 | predicate(n->as_Vector()->length() == 2); |
kvn@3882 | 2137 | match(Set dst (ReplicateL src)); |
kvn@3882 | 2138 | format %{ "movdq $dst,$src\n\t" |
kvn@3882 | 2139 | "movlhps $dst,$dst\t! replicate2L" %} |
kvn@3882 | 2140 | ins_encode %{ |
kvn@3882 | 2141 | __ movdq($dst$$XMMRegister, $src$$Register); |
kvn@3882 | 2142 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2143 | %} |
kvn@3882 | 2144 | ins_pipe( pipe_slow ); |
kvn@3882 | 2145 | %} |
kvn@3882 | 2146 | |
kvn@3882 | 2147 | instruct Repl4L(vecY dst, rRegL src) %{ |
kvn@3882 | 2148 | predicate(n->as_Vector()->length() == 4); |
kvn@3882 | 2149 | match(Set dst (ReplicateL src)); |
kvn@3882 | 2150 | format %{ "movdq $dst,$src\n\t" |
kvn@3882 | 2151 | "movlhps $dst,$dst\n\t" |
kvn@3882 | 2152 | "vinsertf128h $dst,$dst,$dst\t! replicate4L" %} |
kvn@3882 | 2153 | ins_encode %{ |
kvn@3882 | 2154 | __ movdq($dst$$XMMRegister, $src$$Register); |
kvn@3882 | 2155 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2156 | __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2157 | %} |
kvn@3882 | 2158 | ins_pipe( pipe_slow ); |
kvn@3882 | 2159 | %} |
kvn@3882 | 2160 | #else // _LP64 |
kvn@3882 | 2161 | instruct Repl2L(vecX dst, eRegL src, regD tmp) %{ |
kvn@3882 | 2162 | predicate(n->as_Vector()->length() == 2); |
kvn@3882 | 2163 | match(Set dst (ReplicateL src)); |
kvn@3882 | 2164 | effect(TEMP dst, USE src, TEMP tmp); |
kvn@3882 | 2165 | format %{ "movdl $dst,$src.lo\n\t" |
kvn@3882 | 2166 | "movdl $tmp,$src.hi\n\t" |
kvn@3882 | 2167 | "punpckldq $dst,$tmp\n\t" |
kvn@3882 | 2168 | "movlhps $dst,$dst\t! replicate2L"%} |
kvn@3882 | 2169 | ins_encode %{ |
kvn@3882 | 2170 | __ movdl($dst$$XMMRegister, $src$$Register); |
kvn@3882 | 2171 | __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); |
kvn@3882 | 2172 | __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); |
kvn@3882 | 2173 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2174 | %} |
kvn@3882 | 2175 | ins_pipe( pipe_slow ); |
kvn@3882 | 2176 | %} |
kvn@3882 | 2177 | |
kvn@3882 | 2178 | instruct Repl4L(vecY dst, eRegL src, regD tmp) %{ |
kvn@3882 | 2179 | predicate(n->as_Vector()->length() == 4); |
kvn@3882 | 2180 | match(Set dst (ReplicateL src)); |
kvn@3882 | 2181 | effect(TEMP dst, USE src, TEMP tmp); |
kvn@3882 | 2182 | format %{ "movdl $dst,$src.lo\n\t" |
kvn@3882 | 2183 | "movdl $tmp,$src.hi\n\t" |
kvn@3882 | 2184 | "punpckldq $dst,$tmp\n\t" |
kvn@3882 | 2185 | "movlhps $dst,$dst\n\t" |
kvn@3882 | 2186 | "vinsertf128h $dst,$dst,$dst\t! replicate4L" %} |
kvn@3882 | 2187 | ins_encode %{ |
kvn@3882 | 2188 | __ movdl($dst$$XMMRegister, $src$$Register); |
kvn@3882 | 2189 | __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); |
kvn@3882 | 2190 | __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); |
kvn@3882 | 2191 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2192 | __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2193 | %} |
kvn@3882 | 2194 | ins_pipe( pipe_slow ); |
kvn@3882 | 2195 | %} |
kvn@3882 | 2196 | #endif // _LP64 |
kvn@3882 | 2197 | |
kvn@3882 | 2198 | // Replicate long (8 byte) scalar immediate to be vector by loading from const table. |
kvn@3882 | 2199 | instruct Repl2L_imm(vecX dst, immL con) %{ |
kvn@3882 | 2200 | predicate(n->as_Vector()->length() == 2); |
kvn@3882 | 2201 | match(Set dst (ReplicateL con)); |
kvn@3882 | 2202 | format %{ "movsd $dst,[$constantaddress]\t! replicate2L($con)\n\t" |
kvn@3882 | 2203 | "movlhps $dst,$dst" %} |
kvn@3882 | 2204 | ins_encode %{ |
kvn@3882 | 2205 | __ movdbl($dst$$XMMRegister, $constantaddress($con)); |
kvn@3882 | 2206 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2207 | %} |
kvn@3882 | 2208 | ins_pipe( pipe_slow ); |
kvn@3882 | 2209 | %} |
kvn@3882 | 2210 | |
kvn@3882 | 2211 | instruct Repl4L_imm(vecY dst, immL con) %{ |
kvn@3882 | 2212 | predicate(n->as_Vector()->length() == 4); |
kvn@3882 | 2213 | match(Set dst (ReplicateL con)); |
kvn@3882 | 2214 | format %{ "movsd $dst,[$constantaddress]\t! replicate4L($con)\n\t" |
kvn@3882 | 2215 | "movlhps $dst,$dst\n\t" |
kvn@3882 | 2216 | "vinsertf128h $dst,$dst,$dst" %} |
kvn@3882 | 2217 | ins_encode %{ |
kvn@3882 | 2218 | __ movdbl($dst$$XMMRegister, $constantaddress($con)); |
kvn@3882 | 2219 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2220 | __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2221 | %} |
kvn@3882 | 2222 | ins_pipe( pipe_slow ); |
kvn@3882 | 2223 | %} |
kvn@3882 | 2224 | |
kvn@3882 | 2225 | // Long could be loaded into xmm register directly from memory. |
kvn@3882 | 2226 | instruct Repl2L_mem(vecX dst, memory mem) %{ |
kvn@3882 | 2227 | predicate(n->as_Vector()->length() == 2); |
kvn@3886 | 2228 | match(Set dst (ReplicateL (LoadVector mem))); |
kvn@3882 | 2229 | format %{ "movq $dst,$mem\n\t" |
kvn@3882 | 2230 | "movlhps $dst,$dst\t! replicate2L" %} |
kvn@3882 | 2231 | ins_encode %{ |
kvn@3882 | 2232 | __ movq($dst$$XMMRegister, $mem$$Address); |
kvn@3882 | 2233 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2234 | %} |
kvn@3882 | 2235 | ins_pipe( pipe_slow ); |
kvn@3882 | 2236 | %} |
kvn@3882 | 2237 | |
kvn@3882 | 2238 | instruct Repl4L_mem(vecY dst, memory mem) %{ |
kvn@3882 | 2239 | predicate(n->as_Vector()->length() == 4); |
kvn@3886 | 2240 | match(Set dst (ReplicateL (LoadVector mem))); |
kvn@3882 | 2241 | format %{ "movq $dst,$mem\n\t" |
kvn@3882 | 2242 | "movlhps $dst,$dst\n\t" |
kvn@3882 | 2243 | "vinsertf128h $dst,$dst,$dst\t! replicate4L" %} |
kvn@3882 | 2244 | ins_encode %{ |
kvn@3882 | 2245 | __ movq($dst$$XMMRegister, $mem$$Address); |
kvn@3882 | 2246 | __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2247 | __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2248 | %} |
kvn@3882 | 2249 | ins_pipe( pipe_slow ); |
kvn@3882 | 2250 | %} |
kvn@3882 | 2251 | |
kvn@3882 | 2252 | // Replicate long (8 byte) scalar zero to be vector |
kvn@3882 | 2253 | instruct Repl2L_zero(vecX dst, immL0 zero) %{ |
kvn@3882 | 2254 | predicate(n->as_Vector()->length() == 2); |
kvn@3882 | 2255 | match(Set dst (ReplicateL zero)); |
kvn@3882 | 2256 | format %{ "pxor $dst,$dst\t! replicate2L zero" %} |
kvn@3882 | 2257 | ins_encode %{ |
kvn@3882 | 2258 | __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2259 | %} |
kvn@3882 | 2260 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 2261 | %} |
kvn@3882 | 2262 | |
kvn@3882 | 2263 | instruct Repl4L_zero(vecY dst, immL0 zero) %{ |
kvn@3882 | 2264 | predicate(n->as_Vector()->length() == 4); |
kvn@3882 | 2265 | match(Set dst (ReplicateL zero)); |
kvn@3882 | 2266 | format %{ "vxorpd $dst,$dst,$dst\t! replicate4L zero" %} |
kvn@3882 | 2267 | ins_encode %{ |
kvn@3882 | 2268 | // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it). |
kvn@3882 | 2269 | bool vector256 = true; |
kvn@3882 | 2270 | __ vxorpd($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
kvn@3882 | 2271 | %} |
kvn@3882 | 2272 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 2273 | %} |
kvn@3882 | 2274 | |
kvn@3882 | 2275 | // Replicate float (4 byte) scalar to be vector |
kvn@3882 | 2276 | instruct Repl2F(vecD dst, regF src) %{ |
kvn@3882 | 2277 | predicate(n->as_Vector()->length() == 2); |
kvn@3882 | 2278 | match(Set dst (ReplicateF src)); |
kvn@3882 | 2279 | format %{ "pshufd $dst,$dst,0x00\t! replicate2F" %} |
kvn@3882 | 2280 | ins_encode %{ |
kvn@3882 | 2281 | __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); |
kvn@3882 | 2282 | %} |
kvn@3882 | 2283 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 2284 | %} |
kvn@3882 | 2285 | |
kvn@3882 | 2286 | instruct Repl4F(vecX dst, regF src) %{ |
kvn@3882 | 2287 | predicate(n->as_Vector()->length() == 4); |
kvn@3882 | 2288 | match(Set dst (ReplicateF src)); |
kvn@3882 | 2289 | format %{ "pshufd $dst,$dst,0x00\t! replicate4F" %} |
kvn@3882 | 2290 | ins_encode %{ |
kvn@3882 | 2291 | __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); |
kvn@3882 | 2292 | %} |
kvn@3882 | 2293 | ins_pipe( pipe_slow ); |
kvn@3882 | 2294 | %} |
kvn@3882 | 2295 | |
kvn@3882 | 2296 | instruct Repl8F(vecY dst, regF src) %{ |
kvn@3882 | 2297 | predicate(n->as_Vector()->length() == 8); |
kvn@3882 | 2298 | match(Set dst (ReplicateF src)); |
kvn@3882 | 2299 | format %{ "pshufd $dst,$src,0x00\n\t" |
kvn@3882 | 2300 | "vinsertf128h $dst,$dst,$dst\t! replicate8F" %} |
kvn@3882 | 2301 | ins_encode %{ |
kvn@3882 | 2302 | __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); |
kvn@3882 | 2303 | __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2304 | %} |
kvn@3882 | 2305 | ins_pipe( pipe_slow ); |
kvn@3882 | 2306 | %} |
kvn@3882 | 2307 | |
kvn@3882 | 2308 | // Replicate float (4 byte) scalar zero to be vector |
kvn@3882 | 2309 | instruct Repl2F_zero(vecD dst, immF0 zero) %{ |
kvn@3882 | 2310 | predicate(n->as_Vector()->length() == 2); |
kvn@3882 | 2311 | match(Set dst (ReplicateF zero)); |
kvn@3882 | 2312 | format %{ "xorps $dst,$dst\t! replicate2F zero" %} |
kvn@3882 | 2313 | ins_encode %{ |
kvn@3882 | 2314 | __ xorps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2315 | %} |
kvn@3882 | 2316 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 2317 | %} |
kvn@3882 | 2318 | |
kvn@3882 | 2319 | instruct Repl4F_zero(vecX dst, immF0 zero) %{ |
kvn@3882 | 2320 | predicate(n->as_Vector()->length() == 4); |
kvn@3882 | 2321 | match(Set dst (ReplicateF zero)); |
kvn@3882 | 2322 | format %{ "xorps $dst,$dst\t! replicate4F zero" %} |
kvn@3882 | 2323 | ins_encode %{ |
kvn@3882 | 2324 | __ xorps($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2325 | %} |
kvn@3882 | 2326 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 2327 | %} |
kvn@3882 | 2328 | |
kvn@3882 | 2329 | instruct Repl8F_zero(vecY dst, immF0 zero) %{ |
kvn@3882 | 2330 | predicate(n->as_Vector()->length() == 8); |
kvn@3882 | 2331 | match(Set dst (ReplicateF zero)); |
kvn@3882 | 2332 | format %{ "vxorps $dst,$dst,$dst\t! replicate8F zero" %} |
kvn@3882 | 2333 | ins_encode %{ |
kvn@3882 | 2334 | bool vector256 = true; |
kvn@3882 | 2335 | __ vxorps($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
kvn@3882 | 2336 | %} |
kvn@3882 | 2337 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 2338 | %} |
kvn@3882 | 2339 | |
kvn@3882 | 2340 | // Replicate double (8 bytes) scalar to be vector |
kvn@3882 | 2341 | instruct Repl2D(vecX dst, regD src) %{ |
kvn@3882 | 2342 | predicate(n->as_Vector()->length() == 2); |
kvn@3882 | 2343 | match(Set dst (ReplicateD src)); |
kvn@3882 | 2344 | format %{ "pshufd $dst,$src,0x44\t! replicate2D" %} |
kvn@3882 | 2345 | ins_encode %{ |
kvn@3882 | 2346 | __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x44); |
kvn@3882 | 2347 | %} |
kvn@3882 | 2348 | ins_pipe( pipe_slow ); |
kvn@3882 | 2349 | %} |
kvn@3882 | 2350 | |
kvn@3882 | 2351 | instruct Repl4D(vecY dst, regD src) %{ |
kvn@3882 | 2352 | predicate(n->as_Vector()->length() == 4); |
kvn@3882 | 2353 | match(Set dst (ReplicateD src)); |
kvn@3882 | 2354 | format %{ "pshufd $dst,$src,0x44\n\t" |
kvn@3882 | 2355 | "vinsertf128h $dst,$dst,$dst\t! replicate4D" %} |
kvn@3882 | 2356 | ins_encode %{ |
kvn@3882 | 2357 | __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x44); |
kvn@3882 | 2358 | __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2359 | %} |
kvn@3882 | 2360 | ins_pipe( pipe_slow ); |
kvn@3882 | 2361 | %} |
kvn@3882 | 2362 | |
kvn@3882 | 2363 | // Replicate double (8 byte) scalar zero to be vector |
kvn@3882 | 2364 | instruct Repl2D_zero(vecX dst, immD0 zero) %{ |
kvn@3882 | 2365 | predicate(n->as_Vector()->length() == 2); |
kvn@3882 | 2366 | match(Set dst (ReplicateD zero)); |
kvn@3882 | 2367 | format %{ "xorpd $dst,$dst\t! replicate2D zero" %} |
kvn@3882 | 2368 | ins_encode %{ |
kvn@3882 | 2369 | __ xorpd($dst$$XMMRegister, $dst$$XMMRegister); |
kvn@3882 | 2370 | %} |
kvn@3882 | 2371 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 2372 | %} |
kvn@3882 | 2373 | |
kvn@3882 | 2374 | instruct Repl4D_zero(vecY dst, immD0 zero) %{ |
kvn@3882 | 2375 | predicate(n->as_Vector()->length() == 4); |
kvn@3882 | 2376 | match(Set dst (ReplicateD zero)); |
kvn@3882 | 2377 | format %{ "vxorpd $dst,$dst,$dst,vect256\t! replicate4D zero" %} |
kvn@3882 | 2378 | ins_encode %{ |
kvn@3882 | 2379 | bool vector256 = true; |
kvn@3882 | 2380 | __ vxorpd($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
kvn@3882 | 2381 | %} |
kvn@3882 | 2382 | ins_pipe( fpu_reg_reg ); |
kvn@3882 | 2383 | %} |
kvn@3882 | 2384 |