1.1 --- a/src/share/vm/c1/c1_LIR.cpp Mon Jun 11 16:44:16 2018 +0800
1.2 +++ b/src/share/vm/c1/c1_LIR.cpp Mon Jun 11 17:42:16 2018 +0800
1.3 @@ -262,7 +262,44 @@
1.4 }
1.5 }
1.6
1.7 +#ifdef MIPS
1.8 +bool LIR_OprDesc::has_common_register(LIR_Opr opr) const {
1.9 +#ifdef _LP64
1.10 + return is_same_register(opr);
1.11 +#else
1.12 + if (!(is_register() && opr->is_register())) return false;
1.13 + if (!(kind_field() == opr->kind_field())) return false;
1.14
1.15 + if (is_single_cpu()) {
1.16 + if (opr->is_single_cpu()) {
1.17 + return as_register() == opr->as_register();
1.18 + } else {
1.19 + Register dst = as_register();
1.20 + Register lo = opr->as_register_lo();
1.21 + Register hi = opr->as_register_hi();
1.22 + if (dst == lo || dst == hi) return true;
1.23 + }
1.24 +
1.25 + } else {
1.26 + Register dst_lo = as_register_lo();
1.27 + Register dst_hi = as_register_hi();
1.28 +
1.29 + if (opr->is_single_cpu()) {
1.30 + Register src = opr->as_register();
1.31 + if (dst_lo == src || dst_hi == src) return true;
1.32 + } else {
1.33 + Register src_lo = opr->as_register_lo();
1.34 + Register src_hi = opr->as_register_hi();
1.35 + if (dst_lo == src_lo ||
1.36 + dst_lo == src_hi ||
1.37 + dst_hi == src_lo ||
1.38 + dst_hi == src_hi) return true;
1.39 + }
1.40 + }
1.41 + return false;
1.42 +#endif
1.43 +}
1.44 +#endif
1.45
1.46 void LIR_Op2::verify() const {
1.47 #ifdef ASSERT
