diff -r 87ee44a01d68 -r 239e32ede77d src/share/vm/c1/c1_LIR.cpp
--- a/src/share/vm/c1/c1_LIR.cpp	Mon Jun 11 16:44:16 2018 +0800
+++ b/src/share/vm/c1/c1_LIR.cpp	Mon Jun 11 17:42:16 2018 +0800
@@ -262,7 +262,44 @@
   }
 }
 
+#ifdef MIPS
+bool LIR_OprDesc::has_common_register(LIR_Opr opr) const {
+#ifdef _LP64
+  return is_same_register(opr);
+#else
+  if (!(is_register() && opr->is_register())) return false;
+  if (!(kind_field() == opr->kind_field()))   return false;
 
+  if (is_single_cpu()) {
+    if (opr->is_single_cpu()) {
+      return as_register() == opr->as_register();
+    } else {
+      Register dst = as_register();
+      Register  lo = opr->as_register_lo();
+      Register  hi = opr->as_register_hi();
+      if (dst == lo || dst == hi) return true;
+    }
+
+  } else {
+    Register dst_lo = as_register_lo();
+    Register dst_hi = as_register_hi();
+
+    if (opr->is_single_cpu()) {
+      Register src = opr->as_register();
+      if (dst_lo == src || dst_hi == src) return true;
+    } else {
+      Register src_lo = opr->as_register_lo();
+      Register src_hi = opr->as_register_hi();
+      if (dst_lo == src_lo ||
+          dst_lo == src_hi ||
+          dst_hi == src_lo ||
+          dst_hi == src_hi) return true;
+    }
+  }
+  return false;
+#endif
+}
+#endif
 
 void LIR_Op2::verify() const {
 #ifdef ASSERT