Mercurial > jdk8-mips64-public > hotspot / file revision
src/share/vm/c1/c1_LIR.cpp@239e32ede77d
src/share/vm/c1/c1_LIR.cpp
Mon, 11 Jun 2018 17:42:16 +0800
- author
- fujie
- date
- Mon, 11 Jun 2018 17:42:16 +0800
- changeset 9143
- 239e32ede77d
- parent 9142
- 87ee44a01d68
- child 9157
- 2966b0be4027
- permissions
- -rw-r--r--
#7166 [C1] EdgeMoveOptimizer must consider branch operands for MIPS
1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 /*
26 * This file has been modified by Loongson Technology in 2015. These
27 * modifications are Copyright (c) 2015 Loongson Technology, and are made
28 * available on the same license terms set forth above.
29 */
31 #include "precompiled.hpp"
32 #include "c1/c1_InstructionPrinter.hpp"
33 #include "c1/c1_LIR.hpp"
34 #include "c1/c1_LIRAssembler.hpp"
35 #include "c1/c1_ValueStack.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "runtime/sharedRuntime.hpp"
39 Register LIR_OprDesc::as_register() const {
40 return FrameMap::cpu_rnr2reg(cpu_regnr());
41 }
43 Register LIR_OprDesc::as_register_lo() const {
44 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
45 }
47 Register LIR_OprDesc::as_register_hi() const {
48 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
49 }
51 #if defined(X86)
53 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
54 return FrameMap::nr2xmmreg(xmm_regnr());
55 }
57 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
58 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
59 return FrameMap::nr2xmmreg(xmm_regnrLo());
60 }
62 #endif // X86
64 #if defined(SPARC) || defined(PPC) || defined(MIPS)
66 FloatRegister LIR_OprDesc::as_float_reg() const {
67 return FrameMap::nr2floatreg(fpu_regnr());
68 }
70 FloatRegister LIR_OprDesc::as_double_reg() const {
71 return FrameMap::nr2floatreg(fpu_regnrHi());
72 }
74 #endif
76 #ifdef ARM
78 FloatRegister LIR_OprDesc::as_float_reg() const {
79 return as_FloatRegister(fpu_regnr());
80 }
82 FloatRegister LIR_OprDesc::as_double_reg() const {
83 return as_FloatRegister(fpu_regnrLo());
84 }
86 #endif
89 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
91 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
92 ValueTag tag = type->tag();
93 switch (tag) {
94 case metaDataTag : {
95 ClassConstant* c = type->as_ClassConstant();
96 if (c != NULL && !c->value()->is_loaded()) {
97 return LIR_OprFact::metadataConst(NULL);
98 } else if (c != NULL) {
99 return LIR_OprFact::metadataConst(c->value()->constant_encoding());
100 } else {
101 MethodConstant* m = type->as_MethodConstant();
102 assert (m != NULL, "not a class or a method?");
103 return LIR_OprFact::metadataConst(m->value()->constant_encoding());
104 }
105 }
106 case objectTag : {
107 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
108 }
109 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
110 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
111 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
112 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
113 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
114 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
115 }
116 }
119 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
120 switch (type->tag()) {
121 case objectTag: return LIR_OprFact::oopConst(NULL);
122 case addressTag:return LIR_OprFact::addressConst(0);
123 case intTag: return LIR_OprFact::intConst(0);
124 case floatTag: return LIR_OprFact::floatConst(0.0);
125 case longTag: return LIR_OprFact::longConst(0);
126 case doubleTag: return LIR_OprFact::doubleConst(0.0);
127 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
128 }
129 return illegalOpr;
130 }
134 //---------------------------------------------------
137 LIR_Address::Scale LIR_Address::scale(BasicType type) {
138 int elem_size = type2aelembytes(type);
139 switch (elem_size) {
140 case 1: return LIR_Address::times_1;
141 case 2: return LIR_Address::times_2;
142 case 4: return LIR_Address::times_4;
143 case 8: return LIR_Address::times_8;
144 }
145 ShouldNotReachHere();
146 return LIR_Address::times_1;
147 }
150 #ifndef PRODUCT
151 void LIR_Address::verify0() const {
152 #if defined(SPARC) || defined(PPC) || defined(MIPS)
153 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
154 assert(disp() == 0 || index()->is_illegal(), "can't have both");
155 #endif
156 #ifdef _LP64
157 assert(base()->is_cpu_register(), "wrong base operand");
158 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
159 #ifndef MIPS
160 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
161 "wrong type for addresses");
162 #endif
163 #else
164 assert(base()->is_single_cpu(), "wrong base operand");
165 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
166 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
167 "wrong type for addresses");
168 #endif
169 }
170 #endif
173 //---------------------------------------------------
175 char LIR_OprDesc::type_char(BasicType t) {
176 switch (t) {
177 case T_ARRAY:
178 t = T_OBJECT;
179 case T_BOOLEAN:
180 case T_CHAR:
181 case T_FLOAT:
182 case T_DOUBLE:
183 case T_BYTE:
184 case T_SHORT:
185 case T_INT:
186 case T_LONG:
187 case T_OBJECT:
188 case T_ADDRESS:
189 case T_VOID:
190 return ::type2char(t);
191 case T_METADATA:
192 return 'M';
193 case T_ILLEGAL:
194 return '?';
196 default:
197 ShouldNotReachHere();
198 return '?';
199 }
200 }
202 #ifndef PRODUCT
203 void LIR_OprDesc::validate_type() const {
205 #ifdef ASSERT
206 if (!is_pointer() && !is_illegal()) {
207 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
208 switch (as_BasicType(type_field())) {
209 case T_LONG:
210 assert((kindfield == cpu_register || kindfield == stack_value) &&
211 size_field() == double_size, "must match");
212 break;
213 case T_FLOAT:
214 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
215 assert((kindfield == fpu_register || kindfield == stack_value
216 ARM_ONLY(|| kindfield == cpu_register)
217 PPC_ONLY(|| kindfield == cpu_register) ) &&
218 size_field() == single_size, "must match");
219 break;
220 case T_DOUBLE:
221 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
222 assert((kindfield == fpu_register || kindfield == stack_value
223 ARM_ONLY(|| kindfield == cpu_register)
224 PPC_ONLY(|| kindfield == cpu_register) ) &&
225 size_field() == double_size, "must match");
226 break;
227 case T_BOOLEAN:
228 case T_CHAR:
229 case T_BYTE:
230 case T_SHORT:
231 case T_INT:
232 case T_ADDRESS:
233 case T_OBJECT:
234 case T_METADATA:
235 case T_ARRAY:
236 assert((kindfield == cpu_register || kindfield == stack_value) &&
237 size_field() == single_size, "must match");
238 break;
240 case T_ILLEGAL:
241 // XXX TKR also means unknown right now
242 // assert(is_illegal(), "must match");
243 break;
245 default:
246 ShouldNotReachHere();
247 }
248 }
249 #endif
251 }
252 #endif // PRODUCT
255 bool LIR_OprDesc::is_oop() const {
256 if (is_pointer()) {
257 return pointer()->is_oop_pointer();
258 } else {
259 OprType t= type_field();
260 assert(t != unknown_type, "not set");
261 return t == object_type;
262 }
263 }
265 #ifdef MIPS
266 bool LIR_OprDesc::has_common_register(LIR_Opr opr) const {
267 #ifdef _LP64
268 return is_same_register(opr);
269 #else
270 if (!(is_register() && opr->is_register())) return false;
271 if (!(kind_field() == opr->kind_field())) return false;
273 if (is_single_cpu()) {
274 if (opr->is_single_cpu()) {
275 return as_register() == opr->as_register();
276 } else {
277 Register dst = as_register();
278 Register lo = opr->as_register_lo();
279 Register hi = opr->as_register_hi();
280 if (dst == lo || dst == hi) return true;
281 }
283 } else {
284 Register dst_lo = as_register_lo();
285 Register dst_hi = as_register_hi();
287 if (opr->is_single_cpu()) {
288 Register src = opr->as_register();
289 if (dst_lo == src || dst_hi == src) return true;
290 } else {
291 Register src_lo = opr->as_register_lo();
292 Register src_hi = opr->as_register_hi();
293 if (dst_lo == src_lo ||
294 dst_lo == src_hi ||
295 dst_hi == src_lo ||
296 dst_hi == src_hi) return true;
297 }
298 }
299 return false;
300 #endif
301 }
302 #endif
304 void LIR_Op2::verify() const {
305 #ifdef ASSERT
306 switch (code()) {
307 case lir_cmove:
308 case lir_xchg:
309 break;
311 default:
312 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
313 "can't produce oops from arith");
314 }
316 if (TwoOperandLIRForm) {
317 switch (code()) {
318 case lir_add:
319 case lir_sub:
320 case lir_mul:
321 case lir_mul_strictfp:
322 case lir_div:
323 case lir_div_strictfp:
324 case lir_rem:
325 case lir_logic_and:
326 case lir_logic_or:
327 case lir_logic_xor:
328 case lir_shl:
329 case lir_shr:
330 assert(in_opr1() == result_opr(), "opr1 and result must match");
331 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
332 break;
334 // special handling for lir_ushr because of write barriers
335 case lir_ushr:
336 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
337 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
338 break;
340 }
341 }
342 #endif
343 }
346 #ifndef MIPS
347 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
348 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
349 , _cond(cond)
350 , _type(type)
351 , _label(block->label())
352 , _block(block)
353 , _ublock(NULL)
354 , _stub(NULL) {
355 }
357 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
358 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
359 , _cond(cond)
360 , _type(type)
361 , _label(stub->entry())
362 , _block(NULL)
363 , _ublock(NULL)
364 , _stub(stub) {
365 }
367 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
368 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
369 , _cond(cond)
370 , _type(type)
371 , _label(block->label())
372 , _block(block)
373 , _ublock(ublock)
374 , _stub(NULL)
375 {
376 }
378 #else
379 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
380 BlockBegin* block):
381 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
382 _cond(cond),
383 _type(type),
384 _label(block->label()),
385 _block(block),
386 _ublock(NULL),
387 _stub(NULL) {
388 }
390 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
391 CodeStub* stub):
392 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
393 _cond(cond),
394 _type(type),
395 _label(stub->entry()),
396 _block(NULL),
397 _ublock(NULL),
398 _stub(stub) {
399 }
402 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
403 BlockBegin *block, BlockBegin *ublock):
404 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
405 _cond(cond),
406 _type(type),
407 _label(block->label()),
408 _block(block),
409 _ublock(ublock),
410 _stub(NULL) {
411 }
413 #endif
414 void LIR_OpBranch::change_block(BlockBegin* b) {
415 assert(_block != NULL, "must have old block");
416 assert(_block->label() == label(), "must be equal");
418 _block = b;
419 _label = b->label();
420 }
422 void LIR_OpBranch::change_ublock(BlockBegin* b) {
423 assert(_ublock != NULL, "must have old block");
424 _ublock = b;
425 }
427 void LIR_OpBranch::negate_cond() {
428 switch (_cond) {
429 case lir_cond_equal: _cond = lir_cond_notEqual; break;
430 case lir_cond_notEqual: _cond = lir_cond_equal; break;
431 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
432 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
433 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
434 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
435 default: ShouldNotReachHere();
436 }
437 }
440 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
441 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
442 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
443 CodeStub* stub)
445 : LIR_Op(code, result, NULL)
446 , _object(object)
447 , _array(LIR_OprFact::illegalOpr)
448 , _klass(klass)
449 , _tmp1(tmp1)
450 , _tmp2(tmp2)
451 , _tmp3(tmp3)
452 , _fast_check(fast_check)
453 , _stub(stub)
454 , _info_for_patch(info_for_patch)
455 , _info_for_exception(info_for_exception)
456 , _profiled_method(NULL)
457 , _profiled_bci(-1)
458 , _should_profile(false)
459 {
460 if (code == lir_checkcast) {
461 assert(info_for_exception != NULL, "checkcast throws exceptions");
462 } else if (code == lir_instanceof) {
463 assert(info_for_exception == NULL, "instanceof throws no exceptions");
464 } else {
465 ShouldNotReachHere();
466 }
467 }
471 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
472 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
473 , _object(object)
474 , _array(array)
475 , _klass(NULL)
476 , _tmp1(tmp1)
477 , _tmp2(tmp2)
478 , _tmp3(tmp3)
479 , _fast_check(false)
480 , _stub(NULL)
481 , _info_for_patch(NULL)
482 , _info_for_exception(info_for_exception)
483 , _profiled_method(NULL)
484 , _profiled_bci(-1)
485 , _should_profile(false)
486 {
487 if (code == lir_store_check) {
488 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
489 assert(info_for_exception != NULL, "store_check throws exceptions");
490 } else {
491 ShouldNotReachHere();
492 }
493 }
496 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
497 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
498 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
499 , _tmp(tmp)
500 , _src(src)
501 , _src_pos(src_pos)
502 , _dst(dst)
503 , _dst_pos(dst_pos)
504 , _flags(flags)
505 , _expected_type(expected_type)
506 , _length(length) {
507 _stub = new ArrayCopyStub(this);
508 }
510 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res)
511 : LIR_Op(lir_updatecrc32, res, NULL)
512 , _crc(crc)
513 , _val(val) {
514 }
516 //-------------------verify--------------------------
518 void LIR_Op1::verify() const {
519 switch(code()) {
520 case lir_move:
521 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
522 break;
523 case lir_null_check:
524 assert(in_opr()->is_register(), "must be");
525 break;
526 case lir_return:
527 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
528 break;
529 }
530 }
532 void LIR_OpRTCall::verify() const {
533 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
534 }
536 //-------------------visits--------------------------
538 // complete rework of LIR instruction visitor.
539 // The virtual call for each instruction type is replaced by a big
540 // switch that adds the operands for each instruction
542 void LIR_OpVisitState::visit(LIR_Op* op) {
543 // copy information from the LIR_Op
544 reset();
545 set_op(op);
547 switch (op->code()) {
549 // LIR_Op0
550 case lir_word_align: // result and info always invalid
551 case lir_backwardbranch_target: // result and info always invalid
552 case lir_build_frame: // result and info always invalid
553 case lir_fpop_raw: // result and info always invalid
554 case lir_24bit_FPU: // result and info always invalid
555 case lir_reset_FPU: // result and info always invalid
556 case lir_breakpoint: // result and info always invalid
557 case lir_membar: // result and info always invalid
558 case lir_membar_acquire: // result and info always invalid
559 case lir_membar_release: // result and info always invalid
560 case lir_membar_loadload: // result and info always invalid
561 case lir_membar_storestore: // result and info always invalid
562 case lir_membar_loadstore: // result and info always invalid
563 case lir_membar_storeload: // result and info always invalid
564 {
565 assert(op->as_Op0() != NULL, "must be");
566 assert(op->_info == NULL, "info not used by this instruction");
567 assert(op->_result->is_illegal(), "not used");
568 break;
569 }
571 case lir_nop: // may have info, result always invalid
572 case lir_std_entry: // may have result, info always invalid
573 case lir_osr_entry: // may have result, info always invalid
574 case lir_get_thread: // may have result, info always invalid
575 {
576 assert(op->as_Op0() != NULL, "must be");
577 if (op->_info != NULL) do_info(op->_info);
578 if (op->_result->is_valid()) do_output(op->_result);
579 break;
580 }
583 // LIR_OpLabel
584 case lir_label: // result and info always invalid
585 {
586 assert(op->as_OpLabel() != NULL, "must be");
587 assert(op->_info == NULL, "info not used by this instruction");
588 assert(op->_result->is_illegal(), "not used");
589 break;
590 }
593 // LIR_Op1
594 case lir_fxch: // input always valid, result and info always invalid
595 case lir_fld: // input always valid, result and info always invalid
596 case lir_ffree: // input always valid, result and info always invalid
597 case lir_push: // input always valid, result and info always invalid
598 case lir_pop: // input always valid, result and info always invalid
599 case lir_return: // input always valid, result and info always invalid
600 case lir_leal: // input and result always valid, info always invalid
601 case lir_neg: // input and result always valid, info always invalid
602 case lir_monaddr: // input and result always valid, info always invalid
603 case lir_null_check: // input and info always valid, result always invalid
604 case lir_move: // input and result always valid, may have info
605 case lir_pack64: // input and result always valid
606 case lir_unpack64: // input and result always valid
607 case lir_prefetchr: // input always valid, result and info always invalid
608 case lir_prefetchw: // input always valid, result and info always invalid
609 {
610 assert(op->as_Op1() != NULL, "must be");
611 LIR_Op1* op1 = (LIR_Op1*)op;
613 if (op1->_info) do_info(op1->_info);
614 if (op1->_opr->is_valid()) do_input(op1->_opr);
615 if (op1->_result->is_valid()) do_output(op1->_result);
617 break;
618 }
620 case lir_safepoint:
621 {
622 assert(op->as_Op1() != NULL, "must be");
623 LIR_Op1* op1 = (LIR_Op1*)op;
625 assert(op1->_info != NULL, ""); do_info(op1->_info);
626 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
627 assert(op1->_result->is_illegal(), "safepoint does not produce value");
629 break;
630 }
632 // LIR_OpConvert;
633 case lir_convert: // input and result always valid, info always invalid
634 {
635 assert(op->as_OpConvert() != NULL, "must be");
636 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
638 assert(opConvert->_info == NULL, "must be");
639 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
640 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
641 #ifdef PPC
642 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
643 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
644 #endif
645 do_stub(opConvert->_stub);
647 break;
648 }
650 // LIR_OpBranch;
651 case lir_branch: // may have info, input and result register always invalid
652 case lir_cond_float_branch: // may have info, input and result register always invalid
653 {
654 assert(op->as_OpBranch() != NULL, "must be");
655 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
657 #ifdef MIPS
658 if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
659 if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
660 if (opBranch->_tmp1->is_valid()) do_temp(opBranch->_tmp1);
661 if (opBranch->_tmp2->is_valid()) do_temp(opBranch->_tmp2);
662 if (opBranch->_tmp3->is_valid()) do_temp(opBranch->_tmp3);
663 if (opBranch->_tmp4->is_valid()) do_temp(opBranch->_tmp4);
664 if (opBranch->_tmp5->is_valid()) do_temp(opBranch->_tmp5);
665 #endif
666 if (opBranch->_info != NULL) do_info(opBranch->_info);
667 assert(opBranch->_result->is_illegal(), "not used");
668 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
670 break;
671 }
674 // LIR_OpAllocObj
675 case lir_alloc_object:
676 {
677 assert(op->as_OpAllocObj() != NULL, "must be");
678 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
680 if (opAllocObj->_info) do_info(opAllocObj->_info);
681 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
682 do_temp(opAllocObj->_opr);
683 }
684 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
685 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
686 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
687 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
688 #ifdef MIPS
689 if (opAllocObj->_tmp5->is_valid()) do_temp(opAllocObj->_tmp5);
690 if (opAllocObj->_tmp6->is_valid()) do_temp(opAllocObj->_tmp6);
691 #endif
692 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
693 do_stub(opAllocObj->_stub);
694 break;
695 }
698 // LIR_OpRoundFP;
699 case lir_roundfp: {
700 assert(op->as_OpRoundFP() != NULL, "must be");
701 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
703 assert(op->_info == NULL, "info not used by this instruction");
704 assert(opRoundFP->_tmp->is_illegal(), "not used");
705 do_input(opRoundFP->_opr);
706 do_output(opRoundFP->_result);
708 break;
709 }
712 // LIR_Op2
713 #ifdef MIPS
714 case lir_null_check_for_branch:
715 #else
716 case lir_cmp:
717 #endif
718 case lir_cmp_l2i:
719 case lir_ucmp_fd2i:
720 case lir_cmp_fd2i:
721 case lir_add:
722 case lir_sub:
723 case lir_mul:
724 case lir_div:
725 case lir_rem:
726 case lir_sqrt:
727 case lir_abs:
728 case lir_logic_and:
729 case lir_logic_or:
730 case lir_logic_xor:
731 case lir_shl:
732 case lir_shr:
733 case lir_ushr:
734 case lir_xadd:
735 case lir_xchg:
736 case lir_assert:
737 {
738 assert(op->as_Op2() != NULL, "must be");
739 LIR_Op2* op2 = (LIR_Op2*)op;
740 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
741 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
743 if (op2->_info) do_info(op2->_info);
744 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
745 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
746 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
747 if (op2->_result->is_valid()) do_output(op2->_result);
748 if (op->code() == lir_xchg || op->code() == lir_xadd) {
749 // on ARM and PPC, return value is loaded first so could
750 // destroy inputs. On other platforms that implement those
751 // (x86, sparc), the extra constrainsts are harmless.
752 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
753 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
754 }
756 break;
757 }
759 // special handling for cmove: right input operand must not be equal
760 // to the result operand, otherwise the backend fails
761 case lir_cmove:
762 {
763 assert(op->as_Op2() != NULL, "must be");
764 LIR_Op2* op2 = (LIR_Op2*)op;
766 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
767 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
768 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
770 do_input(op2->_opr1);
771 do_input(op2->_opr2);
772 do_temp(op2->_opr2);
773 do_output(op2->_result);
775 break;
776 }
778 // vspecial handling for strict operations: register input operands
779 // as temp to guarantee that they do not overlap with other
780 // registers
781 case lir_mul_strictfp:
782 case lir_div_strictfp:
783 {
784 assert(op->as_Op2() != NULL, "must be");
785 LIR_Op2* op2 = (LIR_Op2*)op;
787 assert(op2->_info == NULL, "not used");
788 assert(op2->_opr1->is_valid(), "used");
789 assert(op2->_opr2->is_valid(), "used");
790 assert(op2->_result->is_valid(), "used");
791 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
792 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
794 do_input(op2->_opr1); do_temp(op2->_opr1);
795 do_input(op2->_opr2); do_temp(op2->_opr2);
796 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
797 do_output(op2->_result);
799 break;
800 }
802 case lir_throw: {
803 assert(op->as_Op2() != NULL, "must be");
804 LIR_Op2* op2 = (LIR_Op2*)op;
806 if (op2->_info) do_info(op2->_info);
807 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
808 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
809 assert(op2->_result->is_illegal(), "no result");
810 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
811 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
813 break;
814 }
816 case lir_unwind: {
817 assert(op->as_Op1() != NULL, "must be");
818 LIR_Op1* op1 = (LIR_Op1*)op;
820 assert(op1->_info == NULL, "no info");
821 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
822 assert(op1->_result->is_illegal(), "no result");
824 break;
825 }
828 case lir_tan:
829 case lir_sin:
830 case lir_cos:
831 case lir_log:
832 case lir_log10:
833 case lir_exp: {
834 assert(op->as_Op2() != NULL, "must be");
835 LIR_Op2* op2 = (LIR_Op2*)op;
837 // On x86 tan/sin/cos need two temporary fpu stack slots and
838 // log/log10 need one so handle opr2 and tmp as temp inputs.
839 // Register input operand as temp to guarantee that it doesn't
840 // overlap with the input.
841 assert(op2->_info == NULL, "not used");
842 assert(op2->_tmp5->is_illegal(), "not used");
843 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used");
844 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used");
845 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used");
846 assert(op2->_opr1->is_valid(), "used");
847 do_input(op2->_opr1); do_temp(op2->_opr1);
849 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
850 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
851 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2);
852 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3);
853 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4);
854 if (op2->_result->is_valid()) do_output(op2->_result);
856 break;
857 }
859 case lir_pow: {
860 assert(op->as_Op2() != NULL, "must be");
861 LIR_Op2* op2 = (LIR_Op2*)op;
863 // On x86 pow needs two temporary fpu stack slots: tmp1 and
864 // tmp2. Register input operands as temps to guarantee that it
865 // doesn't overlap with the temporary slots.
866 assert(op2->_info == NULL, "not used");
867 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used");
868 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid()
869 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used");
870 assert(op2->_result->is_valid(), "used");
872 do_input(op2->_opr1); do_temp(op2->_opr1);
873 do_input(op2->_opr2); do_temp(op2->_opr2);
874 do_temp(op2->_tmp1);
875 do_temp(op2->_tmp2);
876 do_temp(op2->_tmp3);
877 do_temp(op2->_tmp4);
878 do_temp(op2->_tmp5);
879 do_output(op2->_result);
881 break;
882 }
884 // LIR_Op3
885 #ifdef MIPS
886 case lir_frem:
887 #endif
888 case lir_idiv:
889 case lir_irem: {
890 assert(op->as_Op3() != NULL, "must be");
891 LIR_Op3* op3= (LIR_Op3*)op;
893 if (op3->_info) do_info(op3->_info);
894 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
896 // second operand is input and temp, so ensure that second operand
897 // and third operand get not the same register
898 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
899 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
900 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
902 if (op3->_result->is_valid()) do_output(op3->_result);
904 break;
905 }
908 // LIR_OpJavaCall
909 case lir_static_call:
910 case lir_optvirtual_call:
911 case lir_icvirtual_call:
912 case lir_virtual_call:
913 case lir_dynamic_call: {
914 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
915 assert(opJavaCall != NULL, "must be");
917 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
919 // only visit register parameters
920 int n = opJavaCall->_arguments->length();
921 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
922 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
923 do_input(*opJavaCall->_arguments->adr_at(i));
924 }
925 }
927 if (opJavaCall->_info) do_info(opJavaCall->_info);
928 if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr &&
929 opJavaCall->is_method_handle_invoke()) {
930 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
931 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
932 }
933 do_call();
934 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
936 break;
937 }
940 // LIR_OpRTCall
941 case lir_rtcall: {
942 assert(op->as_OpRTCall() != NULL, "must be");
943 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
945 // only visit register parameters
946 int n = opRTCall->_arguments->length();
947 for (int i = 0; i < n; i++) {
948 if (!opRTCall->_arguments->at(i)->is_pointer()) {
949 do_input(*opRTCall->_arguments->adr_at(i));
950 }
951 }
952 if (opRTCall->_info) do_info(opRTCall->_info);
953 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
954 do_call();
955 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
957 break;
958 }
961 // LIR_OpArrayCopy
962 case lir_arraycopy: {
963 assert(op->as_OpArrayCopy() != NULL, "must be");
964 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
966 assert(opArrayCopy->_result->is_illegal(), "unused");
967 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
968 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
969 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
970 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
971 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
972 #ifndef MIPS
973 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
974 #endif
975 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
977 // the implementation of arraycopy always has a call into the runtime
978 do_call();
980 break;
981 }
984 // LIR_OpUpdateCRC32
985 case lir_updatecrc32: {
986 assert(op->as_OpUpdateCRC32() != NULL, "must be");
987 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op;
989 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc);
990 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val);
991 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result);
992 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
994 break;
995 }
998 // LIR_OpLock
999 case lir_lock:
1000 case lir_unlock: {
1001 assert(op->as_OpLock() != NULL, "must be");
1002 LIR_OpLock* opLock = (LIR_OpLock*)op;
1004 if (opLock->_info) do_info(opLock->_info);
1006 // TODO: check if these operands really have to be temp
1007 // (or if input is sufficient). This may have influence on the oop map!
1008 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
1009 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
1010 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
1012 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
1013 assert(opLock->_result->is_illegal(), "unused");
1015 do_stub(opLock->_stub);
1017 break;
1018 }
1021 // LIR_OpDelay
1022 case lir_delay_slot: {
1023 assert(op->as_OpDelay() != NULL, "must be");
1024 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
1026 visit(opDelay->delay_op());
1027 break;
1028 }
1030 // LIR_OpTypeCheck
1031 case lir_instanceof:
1032 case lir_checkcast:
1033 case lir_store_check: {
1034 assert(op->as_OpTypeCheck() != NULL, "must be");
1035 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
1037 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
1038 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
1039 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
1040 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
1041 do_temp(opTypeCheck->_object);
1042 }
1043 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
1044 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
1045 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
1046 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
1047 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
1048 do_stub(opTypeCheck->_stub);
1049 break;
1050 }
1052 // LIR_OpCompareAndSwap
1053 case lir_cas_long:
1054 case lir_cas_obj:
1055 case lir_cas_int: {
1056 assert(op->as_OpCompareAndSwap() != NULL, "must be");
1057 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
1059 assert(opCompareAndSwap->_addr->is_valid(), "used");
1060 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
1061 assert(opCompareAndSwap->_new_value->is_valid(), "used");
1062 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
1063 do_input(opCompareAndSwap->_addr);
1064 do_temp(opCompareAndSwap->_addr);
1065 do_input(opCompareAndSwap->_cmp_value);
1066 do_temp(opCompareAndSwap->_cmp_value);
1067 do_input(opCompareAndSwap->_new_value);
1068 do_temp(opCompareAndSwap->_new_value);
1069 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
1070 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
1071 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
1073 break;
1074 }
1077 // LIR_OpAllocArray;
1078 case lir_alloc_array: {
1079 assert(op->as_OpAllocArray() != NULL, "must be");
1080 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
1082 if (opAllocArray->_info) do_info(opAllocArray->_info);
1083 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
1084 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
1085 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
1086 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
1087 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
1088 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
1089 #ifdef MIPS
1090 if (opAllocArray->_tmp5->is_valid()) do_temp(opAllocArray->_tmp5);
1091 #endif
1092 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
1093 do_stub(opAllocArray->_stub);
1094 break;
1095 }
1097 // LIR_OpProfileCall:
1098 case lir_profile_call: {
1099 assert(op->as_OpProfileCall() != NULL, "must be");
1100 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
1102 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
1103 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
1104 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
1105 break;
1106 }
1108 // LIR_OpProfileType:
1109 case lir_profile_type: {
1110 assert(op->as_OpProfileType() != NULL, "must be");
1111 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op;
1113 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp);
1114 do_input(opProfileType->_obj);
1115 do_temp(opProfileType->_tmp);
1116 break;
1117 }
1118 default:
1119 ShouldNotReachHere();
1120 }
1121 }
1124 void LIR_OpVisitState::do_stub(CodeStub* stub) {
1125 if (stub != NULL) {
1126 stub->visit(this);
1127 }
1128 }
1130 XHandlers* LIR_OpVisitState::all_xhandler() {
1131 XHandlers* result = NULL;
1133 int i;
1134 for (i = 0; i < info_count(); i++) {
1135 if (info_at(i)->exception_handlers() != NULL) {
1136 result = info_at(i)->exception_handlers();
1137 break;
1138 }
1139 }
1141 #ifdef ASSERT
1142 for (i = 0; i < info_count(); i++) {
1143 assert(info_at(i)->exception_handlers() == NULL ||
1144 info_at(i)->exception_handlers() == result,
1145 "only one xhandler list allowed per LIR-operation");
1146 }
1147 #endif
1149 if (result != NULL) {
1150 return result;
1151 } else {
1152 return new XHandlers();
1153 }
1155 return result;
1156 }
1159 #ifdef ASSERT
1160 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1161 visit(op);
1163 return opr_count(inputMode) == 0 &&
1164 opr_count(outputMode) == 0 &&
1165 opr_count(tempMode) == 0 &&
1166 info_count() == 0 &&
1167 !has_call() &&
1168 !has_slow_case();
1169 }
1170 #endif
1172 //---------------------------------------------------
1175 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1176 masm->emit_call(this);
1177 }
1179 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1180 masm->emit_rtcall(this);
1181 }
1183 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1184 masm->emit_opLabel(this);
1185 }
1187 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1188 masm->emit_arraycopy(this);
1189 masm->append_code_stub(stub());
1190 }
1192 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) {
1193 masm->emit_updatecrc32(this);
1194 }
1196 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1197 masm->emit_op0(this);
1198 }
1200 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1201 masm->emit_op1(this);
1202 }
1204 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1205 masm->emit_alloc_obj(this);
1206 masm->append_code_stub(stub());
1207 }
1209 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1210 masm->emit_opBranch(this);
1211 if (stub()) {
1212 masm->append_code_stub(stub());
1213 }
1214 }
1216 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1217 masm->emit_opConvert(this);
1218 if (stub() != NULL) {
1219 masm->append_code_stub(stub());
1220 }
1221 }
1223 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1224 masm->emit_op2(this);
1225 }
1227 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1228 masm->emit_alloc_array(this);
1229 masm->append_code_stub(stub());
1230 }
1232 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1233 masm->emit_opTypeCheck(this);
1234 if (stub()) {
1235 masm->append_code_stub(stub());
1236 }
1237 }
1239 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1240 masm->emit_compare_and_swap(this);
1241 }
1243 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1244 masm->emit_op3(this);
1245 }
1247 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1248 masm->emit_lock(this);
1249 if (stub()) {
1250 masm->append_code_stub(stub());
1251 }
1252 }
1254 #ifdef ASSERT
1255 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1256 masm->emit_assert(this);
1257 }
1258 #endif
1260 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1261 masm->emit_delay(this);
1262 }
1264 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1265 masm->emit_profile_call(this);
1266 }
1268 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1269 masm->emit_profile_type(this);
1270 }
1272 // LIR_List
1273 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1274 : _operations(8)
1275 , _compilation(compilation)
1276 #ifndef PRODUCT
1277 , _block(block)
1278 #endif
1279 #ifdef ASSERT
1280 , _file(NULL)
1281 , _line(0)
1282 #endif
1283 { }
1286 #ifdef ASSERT
1287 void LIR_List::set_file_and_line(const char * file, int line) {
1288 const char * f = strrchr(file, '/');
1289 if (f == NULL) f = strrchr(file, '\\');
1290 if (f == NULL) {
1291 f = file;
1292 } else {
1293 f++;
1294 }
1295 _file = f;
1296 _line = line;
1297 }
1298 #endif
1301 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1302 assert(this == buffer->lir_list(), "wrong lir list");
1303 const int n = _operations.length();
1305 if (buffer->number_of_ops() > 0) {
1306 // increase size of instructions list
1307 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1308 // insert ops from buffer into instructions list
1309 int op_index = buffer->number_of_ops() - 1;
1310 int ip_index = buffer->number_of_insertion_points() - 1;
1311 int from_index = n - 1;
1312 int to_index = _operations.length() - 1;
1313 for (; ip_index >= 0; ip_index --) {
1314 int index = buffer->index_at(ip_index);
1315 // make room after insertion point
1316 while (index < from_index) {
1317 _operations.at_put(to_index --, _operations.at(from_index --));
1318 }
1319 // insert ops from buffer
1320 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1321 _operations.at_put(to_index --, buffer->op_at(op_index --));
1322 }
1323 }
1324 }
1326 buffer->finish();
1327 }
1330 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1331 assert(reg->type() == T_OBJECT, "bad reg");
1332 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1333 }
1335 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1336 assert(reg->type() == T_METADATA, "bad reg");
1337 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1338 }
1340 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1341 append(new LIR_Op1(
1342 lir_move,
1343 LIR_OprFact::address(addr),
1344 src,
1345 addr->type(),
1346 patch_code,
1347 info));
1348 }
1351 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1352 append(new LIR_Op1(
1353 lir_move,
1354 LIR_OprFact::address(address),
1355 dst,
1356 address->type(),
1357 patch_code,
1358 info, lir_move_volatile));
1359 }
1361 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1362 #ifdef MIPS
1363 add(base, offset, base);
1364 offset = 0;
1365 #endif
1366 append(new LIR_Op1(
1367 lir_move,
1368 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1369 dst,
1370 type,
1371 patch_code,
1372 info, lir_move_volatile));
1373 }
1376 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1377 append(new LIR_Op1(
1378 is_store ? lir_prefetchw : lir_prefetchr,
1379 LIR_OprFact::address(addr)));
1380 }
1383 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1384 append(new LIR_Op1(
1385 lir_move,
1386 LIR_OprFact::intConst(v),
1387 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1388 type,
1389 patch_code,
1390 info));
1391 }
1394 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1395 append(new LIR_Op1(
1396 lir_move,
1397 LIR_OprFact::oopConst(o),
1398 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1399 type,
1400 patch_code,
1401 info));
1402 }
1405 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1406 append(new LIR_Op1(
1407 lir_move,
1408 src,
1409 LIR_OprFact::address(addr),
1410 addr->type(),
1411 patch_code,
1412 info));
1413 }
1416 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1417 append(new LIR_Op1(
1418 lir_move,
1419 src,
1420 LIR_OprFact::address(addr),
1421 addr->type(),
1422 patch_code,
1423 info,
1424 lir_move_volatile));
1425 }
1427 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1428 #ifdef MIPS
1429 add(base, offset, base);
1430 offset = 0;
1431 #endif
1432 append(new LIR_Op1(
1433 lir_move,
1434 src,
1435 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1436 type,
1437 patch_code,
1438 info, lir_move_volatile));
1439 }
1441 #ifdef MIPS
1442 void LIR_List::frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1443 append(new LIR_Op3(
1444 lir_frem,
1445 left,
1446 right,
1447 tmp,
1448 res,
1449 info));
1450 }
1451 #endif
1453 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1454 append(new LIR_Op3(
1455 lir_idiv,
1456 left,
1457 right,
1458 tmp,
1459 res,
1460 info));
1461 }
1464 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1465 append(new LIR_Op3(
1466 lir_idiv,
1467 left,
1468 LIR_OprFact::intConst(right),
1469 tmp,
1470 res,
1471 info));
1472 }
1475 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1476 append(new LIR_Op3(
1477 lir_irem,
1478 left,
1479 right,
1480 tmp,
1481 res,
1482 info));
1483 }
1486 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1487 append(new LIR_Op3(
1488 lir_irem,
1489 left,
1490 LIR_OprFact::intConst(right),
1491 tmp,
1492 res,
1493 info));
1494 }
1497 #ifndef MIPS
1498 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1499 append(new LIR_Op2(
1500 lir_cmp,
1501 condition,
1502 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1503 LIR_OprFact::intConst(c),
1504 info));
1505 }
1507 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1508 append(new LIR_Op2(
1509 lir_cmp,
1510 condition,
1511 reg,
1512 LIR_OprFact::address(addr),
1513 info));
1514 }
1515 #endif
1517 void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) {
1518 if (deoptimize_on_null) {
1519 // Emit an explicit null check and deoptimize if opr is null
1520 CodeStub* deopt = new DeoptimizeStub(info);
1521 #ifndef MIPS
1522 cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1523 branch(lir_cond_equal, T_OBJECT, deopt);
1524 #else
1525 null_check_for_branch(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1526 branch(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL), T_OBJECT, deopt);
1527 #endif
1528 } else {
1529 // Emit an implicit null check
1530 append(new LIR_Op1(lir_null_check, opr, info));
1531 }
1532 }
1534 #ifndef MIPS
1535 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1536 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1537 append(new LIR_OpAllocObj(
1538 klass,
1539 dst,
1540 t1,
1541 t2,
1542 t3,
1543 t4,
1544 header_size,
1545 object_size,
1546 init_check,
1547 stub));
1548 }
1550 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1551 append(new LIR_OpAllocArray(
1552 klass,
1553 len,
1554 dst,
1555 t1,
1556 t2,
1557 t3,
1558 t4,
1559 type,
1560 stub));
1561 }
1562 #else
1563 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, LIR_Opr t5, LIR_Opr t6,
1564 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1565 append(new LIR_OpAllocObj(
1566 klass,
1567 dst,
1568 t1,
1569 t2,
1570 t3,
1571 t4,
1572 t5,
1573 t6,
1574 header_size,
1575 object_size,
1576 init_check,
1577 stub));
1578 }
1579 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, LIR_Opr t5,
1580 BasicType type, LIR_Opr klass, CodeStub* stub) {
1581 append(new LIR_OpAllocArray(
1582 klass,
1583 len,
1584 dst,
1585 t1,
1586 t2,
1587 t3,
1588 t4,
1589 t5,
1590 type,
1591 stub));
1592 }
1594 #endif
1596 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1597 append(new LIR_Op2(
1598 lir_shl,
1599 value,
1600 count,
1601 dst,
1602 tmp));
1603 }
1605 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1606 append(new LIR_Op2(
1607 lir_shr,
1608 value,
1609 count,
1610 dst,
1611 tmp));
1612 }
1615 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1616 append(new LIR_Op2(
1617 lir_ushr,
1618 value,
1619 count,
1620 dst,
1621 tmp));
1622 }
1624 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1625 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1626 left,
1627 right,
1628 dst));
1629 }
1631 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1632 append(new LIR_OpLock(
1633 lir_lock,
1634 hdr,
1635 obj,
1636 lock,
1637 scratch,
1638 stub,
1639 info));
1640 }
1642 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1643 append(new LIR_OpLock(
1644 lir_unlock,
1645 hdr,
1646 obj,
1647 lock,
1648 scratch,
1649 stub,
1650 NULL));
1651 }
1654 void check_LIR() {
1655 // cannot do the proper checking as PRODUCT and other modes return different results
1656 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1657 }
1661 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1662 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1663 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1664 ciMethod* profiled_method, int profiled_bci) {
1665 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1666 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1667 if (profiled_method != NULL) {
1668 c->set_profiled_method(profiled_method);
1669 c->set_profiled_bci(profiled_bci);
1670 c->set_should_profile(true);
1671 }
1672 append(c);
1673 }
1675 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1676 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1677 if (profiled_method != NULL) {
1678 c->set_profiled_method(profiled_method);
1679 c->set_profiled_bci(profiled_bci);
1680 c->set_should_profile(true);
1681 }
1682 append(c);
1683 }
1686 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1687 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1688 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1689 if (profiled_method != NULL) {
1690 c->set_profiled_method(profiled_method);
1691 c->set_profiled_bci(profiled_bci);
1692 c->set_should_profile(true);
1693 }
1694 append(c);
1695 }
1697 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1698 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1699 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1700 }
1702 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1703 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1704 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1705 }
1707 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1708 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1709 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1710 }
1713 #ifdef PRODUCT
1715 void print_LIR(BlockList* blocks) {
1716 }
1718 #else
1719 // LIR_OprDesc
1720 void LIR_OprDesc::print() const {
1721 print(tty);
1722 }
1724 void LIR_OprDesc::print(outputStream* out) const {
1725 if (is_illegal()) {
1726 return;
1727 }
1729 out->print("[");
1730 if (is_pointer()) {
1731 pointer()->print_value_on(out);
1732 } else if (is_single_stack()) {
1733 out->print("stack:%d", single_stack_ix());
1734 } else if (is_double_stack()) {
1735 out->print("dbl_stack:%d",double_stack_ix());
1736 } else if (is_virtual()) {
1737 out->print("R%d", vreg_number());
1738 } else if (is_single_cpu()) {
1739 out->print("%s", as_register()->name());
1740 } else if (is_double_cpu()) {
1741 out->print("%s", as_register_hi()->name());
1742 out->print("%s", as_register_lo()->name());
1743 #if defined(X86)
1744 } else if (is_single_xmm()) {
1745 out->print("%s", as_xmm_float_reg()->name());
1746 } else if (is_double_xmm()) {
1747 out->print("%s", as_xmm_double_reg()->name());
1748 } else if (is_single_fpu()) {
1749 out->print("fpu%d", fpu_regnr());
1750 } else if (is_double_fpu()) {
1751 out->print("fpu%d", fpu_regnrLo());
1752 #elif defined(ARM)
1753 } else if (is_single_fpu()) {
1754 out->print("s%d", fpu_regnr());
1755 } else if (is_double_fpu()) {
1756 out->print("d%d", fpu_regnrLo() >> 1);
1757 #else
1758 } else if (is_single_fpu()) {
1759 out->print("%s", as_float_reg()->name());
1760 } else if (is_double_fpu()) {
1761 out->print("%s", as_double_reg()->name());
1762 #endif
1764 } else if (is_illegal()) {
1765 out->print("-");
1766 } else {
1767 out->print("Unknown Operand");
1768 }
1769 if (!is_illegal()) {
1770 out->print("|%c", type_char());
1771 }
1772 if (is_register() && is_last_use()) {
1773 out->print("(last_use)");
1774 }
1775 out->print("]");
1776 }
1779 // LIR_Address
1780 void LIR_Const::print_value_on(outputStream* out) const {
1781 switch (type()) {
1782 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1783 case T_INT: out->print("int:%d", as_jint()); break;
1784 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1785 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1786 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1787 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break;
1788 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break;
1789 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break;
1790 }
1791 }
1793 // LIR_Address
1794 void LIR_Address::print_value_on(outputStream* out) const {
1795 out->print("Base:"); _base->print(out);
1796 #ifndef MIPS
1797 if (!_index->is_illegal()) {
1798 out->print(" Index:"); _index->print(out);
1799 switch (scale()) {
1800 case times_1: break;
1801 case times_2: out->print(" * 2"); break;
1802 case times_4: out->print(" * 4"); break;
1803 case times_8: out->print(" * 8"); break;
1804 }
1805 }
1806 #endif
1807 out->print(" Disp: " INTX_FORMAT, _disp);
1808 }
1810 // debug output of block header without InstructionPrinter
1811 // (because phi functions are not necessary for LIR)
1812 static void print_block(BlockBegin* x) {
1813 // print block id
1814 BlockEnd* end = x->end();
1815 tty->print("B%d ", x->block_id());
1817 // print flags
1818 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1819 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1820 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1821 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1822 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1823 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1824 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1826 // print block bci range
1827 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1829 // print predecessors and successors
1830 if (x->number_of_preds() > 0) {
1831 tty->print("preds: ");
1832 for (int i = 0; i < x->number_of_preds(); i ++) {
1833 tty->print("B%d ", x->pred_at(i)->block_id());
1834 }
1835 }
1837 if (x->number_of_sux() > 0) {
1838 tty->print("sux: ");
1839 for (int i = 0; i < x->number_of_sux(); i ++) {
1840 tty->print("B%d ", x->sux_at(i)->block_id());
1841 }
1842 }
1844 // print exception handlers
1845 if (x->number_of_exception_handlers() > 0) {
1846 tty->print("xhandler: ");
1847 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1848 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1849 }
1850 }
1852 tty->cr();
1853 }
1855 void print_LIR(BlockList* blocks) {
1856 tty->print_cr("LIR:");
1857 int i;
1858 for (i = 0; i < blocks->length(); i++) {
1859 BlockBegin* bb = blocks->at(i);
1860 print_block(bb);
1861 tty->print("__id_Instruction___________________________________________"); tty->cr();
1862 bb->lir()->print_instructions();
1863 }
1864 }
1866 void LIR_List::print_instructions() {
1867 for (int i = 0; i < _operations.length(); i++) {
1868 _operations.at(i)->print(); tty->cr();
1869 }
1870 tty->cr();
1871 }
1873 // LIR_Ops printing routines
1874 // LIR_Op
1875 void LIR_Op::print_on(outputStream* out) const {
1876 if (id() != -1 || PrintCFGToFile) {
1877 out->print("%4d ", id());
1878 } else {
1879 out->print(" ");
1880 }
1881 out->print("%s ", name());
1882 print_instr(out);
1883 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1884 #ifdef ASSERT
1885 if (Verbose && _file != NULL) {
1886 out->print(" (%s:%d)", _file, _line);
1887 }
1888 #endif
1889 }
1891 const char * LIR_Op::name() const {
1892 const char* s = NULL;
1893 switch(code()) {
1894 // LIR_Op0
1895 case lir_membar: s = "membar"; break;
1896 case lir_membar_acquire: s = "membar_acquire"; break;
1897 case lir_membar_release: s = "membar_release"; break;
1898 case lir_membar_loadload: s = "membar_loadload"; break;
1899 case lir_membar_storestore: s = "membar_storestore"; break;
1900 case lir_membar_loadstore: s = "membar_loadstore"; break;
1901 case lir_membar_storeload: s = "membar_storeload"; break;
1902 case lir_word_align: s = "word_align"; break;
1903 case lir_label: s = "label"; break;
1904 case lir_nop: s = "nop"; break;
1905 case lir_backwardbranch_target: s = "backbranch"; break;
1906 case lir_std_entry: s = "std_entry"; break;
1907 case lir_osr_entry: s = "osr_entry"; break;
1908 case lir_build_frame: s = "build_frm"; break;
1909 case lir_fpop_raw: s = "fpop_raw"; break;
1910 case lir_24bit_FPU: s = "24bit_FPU"; break;
1911 case lir_reset_FPU: s = "reset_FPU"; break;
1912 case lir_breakpoint: s = "breakpoint"; break;
1913 case lir_get_thread: s = "get_thread"; break;
1914 // LIR_Op1
1915 case lir_fxch: s = "fxch"; break;
1916 case lir_fld: s = "fld"; break;
1917 case lir_ffree: s = "ffree"; break;
1918 case lir_push: s = "push"; break;
1919 case lir_pop: s = "pop"; break;
1920 case lir_null_check: s = "null_check"; break;
1921 case lir_return: s = "return"; break;
1922 case lir_safepoint: s = "safepoint"; break;
1923 case lir_neg: s = "neg"; break;
1924 case lir_leal: s = "leal"; break;
1925 case lir_branch: s = "branch"; break;
1926 case lir_cond_float_branch: s = "flt_cond_br"; break;
1927 case lir_move: s = "move"; break;
1928 case lir_roundfp: s = "roundfp"; break;
1929 case lir_rtcall: s = "rtcall"; break;
1930 case lir_throw: s = "throw"; break;
1931 case lir_unwind: s = "unwind"; break;
1932 case lir_convert: s = "convert"; break;
1933 case lir_alloc_object: s = "alloc_obj"; break;
1934 case lir_monaddr: s = "mon_addr"; break;
1935 case lir_pack64: s = "pack64"; break;
1936 case lir_unpack64: s = "unpack64"; break;
1937 // LIR_Op2
1938 #ifdef MIPS
1939 case lir_null_check_for_branch: s = "null_check_for_branch"; break;
1940 #else
1941 case lir_cmp: s = "cmp"; break;
1942 #endif
1943 case lir_cmp_l2i: s = "cmp_l2i"; break;
1944 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1945 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1946 case lir_cmove: s = "cmove"; break;
1947 case lir_add: s = "add"; break;
1948 case lir_sub: s = "sub"; break;
1949 case lir_mul: s = "mul"; break;
1950 case lir_mul_strictfp: s = "mul_strictfp"; break;
1951 case lir_div: s = "div"; break;
1952 case lir_div_strictfp: s = "div_strictfp"; break;
1953 case lir_rem: s = "rem"; break;
1954 case lir_abs: s = "abs"; break;
1955 case lir_sqrt: s = "sqrt"; break;
1956 case lir_sin: s = "sin"; break;
1957 case lir_cos: s = "cos"; break;
1958 case lir_tan: s = "tan"; break;
1959 case lir_log: s = "log"; break;
1960 case lir_log10: s = "log10"; break;
1961 case lir_exp: s = "exp"; break;
1962 case lir_pow: s = "pow"; break;
1963 case lir_logic_and: s = "logic_and"; break;
1964 case lir_logic_or: s = "logic_or"; break;
1965 case lir_logic_xor: s = "logic_xor"; break;
1966 case lir_shl: s = "shift_left"; break;
1967 case lir_shr: s = "shift_right"; break;
1968 case lir_ushr: s = "ushift_right"; break;
1969 case lir_alloc_array: s = "alloc_array"; break;
1970 case lir_xadd: s = "xadd"; break;
1971 case lir_xchg: s = "xchg"; break;
1972 // LIR_Op3
1973 #ifdef MIPS
1974 case lir_frem: s = "frem"; break;
1975 #endif
1976 case lir_idiv: s = "idiv"; break;
1977 case lir_irem: s = "irem"; break;
1978 // LIR_OpJavaCall
1979 case lir_static_call: s = "static"; break;
1980 case lir_optvirtual_call: s = "optvirtual"; break;
1981 case lir_icvirtual_call: s = "icvirtual"; break;
1982 case lir_virtual_call: s = "virtual"; break;
1983 case lir_dynamic_call: s = "dynamic"; break;
1984 // LIR_OpArrayCopy
1985 case lir_arraycopy: s = "arraycopy"; break;
1986 // LIR_OpUpdateCRC32
1987 case lir_updatecrc32: s = "updatecrc32"; break;
1988 // LIR_OpLock
1989 case lir_lock: s = "lock"; break;
1990 case lir_unlock: s = "unlock"; break;
1991 // LIR_OpDelay
1992 case lir_delay_slot: s = "delay"; break;
1993 // LIR_OpTypeCheck
1994 case lir_instanceof: s = "instanceof"; break;
1995 case lir_checkcast: s = "checkcast"; break;
1996 case lir_store_check: s = "store_check"; break;
1997 // LIR_OpCompareAndSwap
1998 case lir_cas_long: s = "cas_long"; break;
1999 case lir_cas_obj: s = "cas_obj"; break;
2000 case lir_cas_int: s = "cas_int"; break;
2001 // LIR_OpProfileCall
2002 case lir_profile_call: s = "profile_call"; break;
2003 // LIR_OpProfileType
2004 case lir_profile_type: s = "profile_type"; break;
2005 // LIR_OpAssert
2006 #ifdef ASSERT
2007 case lir_assert: s = "assert"; break;
2008 #endif
2009 case lir_none: ShouldNotReachHere();break;
2010 default: s = "illegal_op"; break;
2011 }
2012 return s;
2013 }
2015 // LIR_OpJavaCall
2016 void LIR_OpJavaCall::print_instr(outputStream* out) const {
2017 out->print("call: ");
2018 out->print("[addr: " INTPTR_FORMAT "]", p2i(address()));
2019 if (receiver()->is_valid()) {
2020 out->print(" [recv: "); receiver()->print(out); out->print("]");
2021 }
2022 if (result_opr()->is_valid()) {
2023 out->print(" [result: "); result_opr()->print(out); out->print("]");
2024 }
2025 }
2027 // LIR_OpLabel
2028 void LIR_OpLabel::print_instr(outputStream* out) const {
2029 out->print("[label:" INTPTR_FORMAT "]", p2i(_label));
2030 }
2032 // LIR_OpArrayCopy
2033 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
2034 src()->print(out); out->print(" ");
2035 src_pos()->print(out); out->print(" ");
2036 dst()->print(out); out->print(" ");
2037 dst_pos()->print(out); out->print(" ");
2038 length()->print(out); out->print(" ");
2039 tmp()->print(out); out->print(" ");
2040 }
2042 // LIR_OpUpdateCRC32
2043 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const {
2044 crc()->print(out); out->print(" ");
2045 val()->print(out); out->print(" ");
2046 result_opr()->print(out); out->print(" ");
2047 }
2049 // LIR_OpCompareAndSwap
2050 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
2051 addr()->print(out); out->print(" ");
2052 cmp_value()->print(out); out->print(" ");
2053 new_value()->print(out); out->print(" ");
2054 tmp1()->print(out); out->print(" ");
2055 tmp2()->print(out); out->print(" ");
2057 }
2059 // LIR_Op0
2060 void LIR_Op0::print_instr(outputStream* out) const {
2061 result_opr()->print(out);
2062 }
2064 // LIR_Op1
2065 const char * LIR_Op1::name() const {
2066 if (code() == lir_move) {
2067 switch (move_kind()) {
2068 case lir_move_normal:
2069 return "move";
2070 case lir_move_unaligned:
2071 return "unaligned move";
2072 case lir_move_volatile:
2073 return "volatile_move";
2074 case lir_move_wide:
2075 return "wide_move";
2076 default:
2077 ShouldNotReachHere();
2078 return "illegal_op";
2079 }
2080 } else {
2081 return LIR_Op::name();
2082 }
2083 }
2086 void LIR_Op1::print_instr(outputStream* out) const {
2087 _opr->print(out); out->print(" ");
2088 result_opr()->print(out); out->print(" ");
2089 print_patch_code(out, patch_code());
2090 }
2093 // LIR_Op1
2094 void LIR_OpRTCall::print_instr(outputStream* out) const {
2095 intx a = (intx)addr();
2096 out->print("%s", Runtime1::name_for_address(addr()));
2097 out->print(" ");
2098 tmp()->print(out);
2099 }
2101 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
2102 switch(code) {
2103 case lir_patch_none: break;
2104 case lir_patch_low: out->print("[patch_low]"); break;
2105 case lir_patch_high: out->print("[patch_high]"); break;
2106 case lir_patch_normal: out->print("[patch_normal]"); break;
2107 default: ShouldNotReachHere();
2108 }
2109 }
2111 // LIR_OpBranch
2112 void LIR_OpBranch::print_instr(outputStream* out) const {
2113 print_condition(out, cond()); out->print(" ");
2114 #ifdef MIPS
2115 in_opr1()->print(out); out->print(" ");
2116 in_opr2()->print(out); out->print(" ");
2117 #endif
2118 if (block() != NULL) {
2119 out->print("[B%d] ", block()->block_id());
2120 } else if (stub() != NULL) {
2121 out->print("[");
2122 stub()->print_name(out);
2123 out->print(": " INTPTR_FORMAT "]", p2i(stub()));
2124 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
2125 } else {
2126 out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
2127 }
2128 if (ublock() != NULL) {
2129 out->print("unordered: [B%d] ", ublock()->block_id());
2130 }
2131 }
2133 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
2134 switch(cond) {
2135 case lir_cond_equal: out->print("[EQ]"); break;
2136 case lir_cond_notEqual: out->print("[NE]"); break;
2137 case lir_cond_less: out->print("[LT]"); break;
2138 case lir_cond_lessEqual: out->print("[LE]"); break;
2139 case lir_cond_greaterEqual: out->print("[GE]"); break;
2140 case lir_cond_greater: out->print("[GT]"); break;
2141 case lir_cond_belowEqual: out->print("[BE]"); break;
2142 case lir_cond_aboveEqual: out->print("[AE]"); break;
2143 case lir_cond_always: out->print("[AL]"); break;
2144 default: out->print("[%d]",cond); break;
2145 }
2146 }
2148 // LIR_OpConvert
2149 void LIR_OpConvert::print_instr(outputStream* out) const {
2150 print_bytecode(out, bytecode());
2151 in_opr()->print(out); out->print(" ");
2152 result_opr()->print(out); out->print(" ");
2153 #ifdef PPC
2154 if(tmp1()->is_valid()) {
2155 tmp1()->print(out); out->print(" ");
2156 tmp2()->print(out); out->print(" ");
2157 }
2158 #endif
2159 }
2161 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
2162 switch(code) {
2163 case Bytecodes::_d2f: out->print("[d2f] "); break;
2164 case Bytecodes::_d2i: out->print("[d2i] "); break;
2165 case Bytecodes::_d2l: out->print("[d2l] "); break;
2166 case Bytecodes::_f2d: out->print("[f2d] "); break;
2167 case Bytecodes::_f2i: out->print("[f2i] "); break;
2168 case Bytecodes::_f2l: out->print("[f2l] "); break;
2169 case Bytecodes::_i2b: out->print("[i2b] "); break;
2170 case Bytecodes::_i2c: out->print("[i2c] "); break;
2171 case Bytecodes::_i2d: out->print("[i2d] "); break;
2172 case Bytecodes::_i2f: out->print("[i2f] "); break;
2173 case Bytecodes::_i2l: out->print("[i2l] "); break;
2174 case Bytecodes::_i2s: out->print("[i2s] "); break;
2175 case Bytecodes::_l2i: out->print("[l2i] "); break;
2176 case Bytecodes::_l2f: out->print("[l2f] "); break;
2177 case Bytecodes::_l2d: out->print("[l2d] "); break;
2178 default:
2179 out->print("[?%d]",code);
2180 break;
2181 }
2182 }
2184 void LIR_OpAllocObj::print_instr(outputStream* out) const {
2185 klass()->print(out); out->print(" ");
2186 obj()->print(out); out->print(" ");
2187 tmp1()->print(out); out->print(" ");
2188 tmp2()->print(out); out->print(" ");
2189 tmp3()->print(out); out->print(" ");
2190 tmp4()->print(out); out->print(" ");
2191 #ifdef MIPS
2192 tmp5()->print(out); out->print(" ");
2193 tmp6()->print(out); out->print(" ");
2194 #endif
2195 out->print("[hdr:%d]", header_size()); out->print(" ");
2196 out->print("[obj:%d]", object_size()); out->print(" ");
2197 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2198 }
2200 void LIR_OpRoundFP::print_instr(outputStream* out) const {
2201 _opr->print(out); out->print(" ");
2202 tmp()->print(out); out->print(" ");
2203 result_opr()->print(out); out->print(" ");
2204 }
2206 // LIR_Op2
2207 void LIR_Op2::print_instr(outputStream* out) const {
2208 #ifndef MIPS
2209 if (code() == lir_cmove) {
2210 print_condition(out, condition()); out->print(" ");
2211 }
2212 #endif
2213 in_opr1()->print(out); out->print(" ");
2214 in_opr2()->print(out); out->print(" ");
2215 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
2216 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
2217 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
2218 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
2219 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
2220 result_opr()->print(out);
2221 }
2223 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2224 klass()->print(out); out->print(" ");
2225 len()->print(out); out->print(" ");
2226 obj()->print(out); out->print(" ");
2227 tmp1()->print(out); out->print(" ");
2228 tmp2()->print(out); out->print(" ");
2229 tmp3()->print(out); out->print(" ");
2230 tmp4()->print(out); out->print(" ");
2231 #ifdef MIPS
2232 tmp5()->print(out); out->print(" ");
2233 #endif
2234 out->print("[type:0x%x]", type()); out->print(" ");
2235 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2236 }
2239 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
2240 object()->print(out); out->print(" ");
2241 if (code() == lir_store_check) {
2242 array()->print(out); out->print(" ");
2243 }
2244 if (code() != lir_store_check) {
2245 klass()->print_name_on(out); out->print(" ");
2246 if (fast_check()) out->print("fast_check ");
2247 }
2248 tmp1()->print(out); out->print(" ");
2249 tmp2()->print(out); out->print(" ");
2250 tmp3()->print(out); out->print(" ");
2251 result_opr()->print(out); out->print(" ");
2252 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2253 }
2256 // LIR_Op3
2257 void LIR_Op3::print_instr(outputStream* out) const {
2258 in_opr1()->print(out); out->print(" ");
2259 in_opr2()->print(out); out->print(" ");
2260 in_opr3()->print(out); out->print(" ");
2261 result_opr()->print(out);
2262 }
2265 void LIR_OpLock::print_instr(outputStream* out) const {
2266 hdr_opr()->print(out); out->print(" ");
2267 obj_opr()->print(out); out->print(" ");
2268 lock_opr()->print(out); out->print(" ");
2269 if (_scratch->is_valid()) {
2270 _scratch->print(out); out->print(" ");
2271 }
2272 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2273 }
2275 #ifdef ASSERT
2276 void LIR_OpAssert::print_instr(outputStream* out) const {
2277 tty->print_cr("function LIR_OpAssert::print_instr unimplemented yet! ");
2278 Unimplemented();
2279 /*
2280 print_condition(out, condition()); out->print(" ");
2281 in_opr1()->print(out); out->print(" ");
2282 in_opr2()->print(out); out->print(", \"");
2283 out->print("%s", msg()); out->print("\"");
2284 */
2285 }
2286 #endif
2289 void LIR_OpDelay::print_instr(outputStream* out) const {
2290 _op->print_on(out);
2291 }
2294 // LIR_OpProfileCall
2295 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2296 profiled_method()->name()->print_symbol_on(out);
2297 out->print(".");
2298 profiled_method()->holder()->name()->print_symbol_on(out);
2299 out->print(" @ %d ", profiled_bci());
2300 mdo()->print(out); out->print(" ");
2301 recv()->print(out); out->print(" ");
2302 tmp1()->print(out); out->print(" ");
2303 }
2305 // LIR_OpProfileType
2306 void LIR_OpProfileType::print_instr(outputStream* out) const {
2307 out->print("exact = "); exact_klass()->print_name_on(out);
2308 out->print("current = "); ciTypeEntries::print_ciklass(out, current_klass());
2309 mdp()->print(out); out->print(" ");
2310 obj()->print(out); out->print(" ");
2311 tmp()->print(out); out->print(" ");
2312 }
2314 #endif // PRODUCT
2316 // Implementation of LIR_InsertionBuffer
2318 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2319 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2321 int i = number_of_insertion_points() - 1;
2322 if (i < 0 || index_at(i) < index) {
2323 append_new(index, 1);
2324 } else {
2325 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2326 assert(count_at(i) > 0, "check");
2327 set_count_at(i, count_at(i) + 1);
2328 }
2329 _ops.push(op);
2331 DEBUG_ONLY(verify());
2332 }
2334 #ifdef ASSERT
2335 void LIR_InsertionBuffer::verify() {
2336 int sum = 0;
2337 int prev_idx = -1;
2339 for (int i = 0; i < number_of_insertion_points(); i++) {
2340 assert(prev_idx < index_at(i), "index must be ordered ascending");
2341 sum += count_at(i);
2342 }
2343 assert(sum == number_of_ops(), "wrong total sum");
2344 }
2345 #endif
