1.1 --- a/src/cpu/x86/vm/vm_version_x86.hpp Fri Jan 06 16:18:29 2012 -0800
1.2 +++ b/src/cpu/x86/vm/vm_version_x86.hpp Fri Jan 06 20:09:20 2012 -0800
1.3 @@ -78,7 +78,10 @@
1.4 sse4_2 : 1,
1.5 : 2,
1.6 popcnt : 1,
1.7 - : 8;
1.8 + : 3,
1.9 + osxsave : 1,
1.10 + avx : 1,
1.11 + : 3;
1.12 } bits;
1.13 };
1.14
1.15 @@ -168,6 +171,15 @@
1.16 } bits;
1.17 };
1.18
1.19 + union ExtCpuid7Edx {
1.20 + uint32_t value;
1.21 + struct {
1.22 + uint32_t : 8,
1.23 + tsc_invariance : 1,
1.24 + : 23;
1.25 + } bits;
1.26 + };
1.27 +
1.28 union ExtCpuid8Ecx {
1.29 uint32_t value;
1.30 struct {
1.31 @@ -176,12 +188,31 @@
1.32 } bits;
1.33 };
1.34
1.35 - union ExtCpuid7Edx {
1.36 + union SefCpuid7Eax {
1.37 + uint32_t value;
1.38 + };
1.39 +
1.40 + union SefCpuid7Ebx {
1.41 uint32_t value;
1.42 struct {
1.43 - uint32_t : 8,
1.44 - tsc_invariance : 1,
1.45 - : 23;
1.46 + uint32_t fsgsbase : 1,
1.47 + : 2,
1.48 + bmi1 : 1,
1.49 + : 1,
1.50 + avx2 : 1,
1.51 + : 2,
1.52 + bmi2 : 1,
1.53 + : 23;
1.54 + } bits;
1.55 + };
1.56 +
1.57 + union XemXcr0Eax {
1.58 + uint32_t value;
1.59 + struct {
1.60 + uint32_t x87 : 1,
1.61 + sse : 1,
1.62 + ymm : 1,
1.63 + : 29;
1.64 } bits;
1.65 };
1.66
1.67 @@ -211,7 +242,9 @@
1.68 CPU_POPCNT = (1 << 13),
1.69 CPU_LZCNT = (1 << 14),
1.70 CPU_TSC = (1 << 15),
1.71 - CPU_TSCINV = (1 << 16)
1.72 + CPU_TSCINV = (1 << 16),
1.73 + CPU_AVX = (1 << 17),
1.74 + CPU_AVX2 = (1 << 18)
1.75 } cpuFeatureFlags;
1.76
1.77 enum {
1.78 @@ -250,6 +283,12 @@
1.79 uint32_t dcp_cpuid4_ecx; // unused currently
1.80 uint32_t dcp_cpuid4_edx; // unused currently
1.81
1.82 + // cpuid function 7 (structured extended features)
1.83 + SefCpuid7Eax sef_cpuid7_eax;
1.84 + SefCpuid7Ebx sef_cpuid7_ebx;
1.85 + uint32_t sef_cpuid7_ecx; // unused currently
1.86 + uint32_t sef_cpuid7_edx; // unused currently
1.87 +
1.88 // cpuid function 0xB (processor topology)
1.89 // ecx = 0
1.90 uint32_t tpl_cpuidB0_eax;
1.91 @@ -303,6 +342,10 @@
1.92 uint32_t ext_cpuid8_ebx; // reserved
1.93 ExtCpuid8Ecx ext_cpuid8_ecx;
1.94 uint32_t ext_cpuid8_edx; // reserved
1.95 +
1.96 + // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
1.97 + XemXcr0Eax xem_xcr0_eax;
1.98 + uint32_t xem_xcr0_edx; // reserved
1.99 };
1.100
1.101 // The actual cpuid info block
1.102 @@ -360,6 +403,14 @@
1.103 result |= CPU_SSE4_2;
1.104 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
1.105 result |= CPU_POPCNT;
1.106 + if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
1.107 + _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
1.108 + _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
1.109 + _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
1.110 + result |= CPU_AVX;
1.111 + if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
1.112 + result |= CPU_AVX2;
1.113 + }
1.114 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
1.115 result |= CPU_TSC;
1.116 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
1.117 @@ -386,6 +437,7 @@
1.118 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
1.119 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
1.120 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
1.121 + static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
1.122 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
1.123 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
1.124 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
1.125 @@ -393,6 +445,7 @@
1.126 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
1.127 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
1.128 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
1.129 + static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
1.130
1.131 // Initialization
1.132 static void initialize();
1.133 @@ -483,6 +536,8 @@
1.134 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; }
1.135 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; }
1.136 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; }
1.137 + static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; }
1.138 + static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; }
1.139 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; }
1.140
1.141 // Intel features
