1.1 --- a/src/cpu/x86/vm/vm_version_x86.hpp Wed Feb 15 12:17:30 2012 -0800
1.2 +++ b/src/cpu/x86/vm/vm_version_x86.hpp Thu Feb 16 13:50:54 2012 -0500
1.3 @@ -249,13 +249,18 @@
1.4
1.5 enum {
1.6 // AMD
1.7 - CPU_FAMILY_AMD_11H = 17,
1.8 + CPU_FAMILY_AMD_11H = 0x11,
1.9 // Intel
1.10 CPU_FAMILY_INTEL_CORE = 6,
1.11 - CPU_MODEL_NEHALEM_EP = 26,
1.12 - CPU_MODEL_WESTMERE_EP = 44,
1.13 -// CPU_MODEL_IVYBRIDGE_EP = ??, TODO - get real value
1.14 - CPU_MODEL_SANDYBRIDGE_EP = 45
1.15 + CPU_MODEL_NEHALEM = 0x1e,
1.16 + CPU_MODEL_NEHALEM_EP = 0x1a,
1.17 + CPU_MODEL_NEHALEM_EX = 0x2e,
1.18 + CPU_MODEL_WESTMERE = 0x25,
1.19 + CPU_MODEL_WESTMERE_EP = 0x2c,
1.20 + CPU_MODEL_WESTMERE_EX = 0x2f,
1.21 + CPU_MODEL_SANDYBRIDGE = 0x2a,
1.22 + CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
1.23 + CPU_MODEL_IVYBRIDGE_EP = 0x3a
1.24 } cpuExtendedFamily;
1.25
1.26 // cpuid information block. All info derived from executing cpuid with
1.27 @@ -325,7 +330,7 @@
1.28 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
1.29 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
1.30
1.31 - // cpuid function 0x80000005 //AMD L1, Intel reserved
1.32 + // cpuid function 0x80000005 // AMD L1, Intel reserved
1.33 uint32_t ext_cpuid5_eax; // unused currently
1.34 uint32_t ext_cpuid5_ebx; // reserved
1.35 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
1.36 @@ -547,15 +552,15 @@
1.37 static bool is_intel_tsc_synched_at_init() {
1.38 if (is_intel_family_core()) {
1.39 uint32_t ext_model = extended_cpu_model();
1.40 - if (ext_model == CPU_MODEL_NEHALEM_EP ||
1.41 - ext_model == CPU_MODEL_WESTMERE_EP ||
1.42 -// TODO ext_model == CPU_MODEL_IVYBRIDGE_EP ||
1.43 - ext_model == CPU_MODEL_SANDYBRIDGE_EP) {
1.44 - // 2-socket invtsc support. EX versions with 4 sockets are not
1.45 - // guaranteed to synchronize tscs at initialization via a double
1.46 - // handshake. The tscs can be explicitly set in software. Code
1.47 - // that uses tsc values must be prepared for them to arbitrarily
1.48 - // jump backward or forward.
1.49 + if (ext_model == CPU_MODEL_NEHALEM_EP ||
1.50 + ext_model == CPU_MODEL_WESTMERE_EP ||
1.51 + ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
1.52 + ext_model == CPU_MODEL_IVYBRIDGE_EP) {
1.53 + // <= 2-socket invariant tsc support. EX versions are usually used
1.54 + // in > 2-socket systems and likely don't synchronize tscs at
1.55 + // initialization.
1.56 + // Code that uses tsc values must be prepared for them to arbitrarily
1.57 + // jump forward or backward.
1.58 return true;
1.59 }
1.60 }
