src/cpu/x86/vm/vm_version_x86.hpp

changeset 3388
127b3692c168
parent 3063
9f12ede5571a
child 3400
22cee0ee8927
     1.1 --- a/src/cpu/x86/vm/vm_version_x86.hpp	Tue Dec 13 17:10:52 2011 -0800
     1.2 +++ b/src/cpu/x86/vm/vm_version_x86.hpp	Wed Dec 14 14:54:38 2011 -0800
     1.3 @@ -78,7 +78,10 @@
     1.4                 sse4_2   : 1,
     1.5                          : 2,
     1.6                 popcnt   : 1,
     1.7 -                        : 8;
     1.8 +                        : 3,
     1.9 +               osxsave  : 1,
    1.10 +               avx      : 1,
    1.11 +                        : 3;
    1.12      } bits;
    1.13    };
    1.14  
    1.15 @@ -176,6 +179,34 @@
    1.16      } bits;
    1.17    };
    1.18  
    1.19 +  union SefCpuid7Eax {
    1.20 +    uint32_t value;
    1.21 +  };
    1.22 +
    1.23 +  union SefCpuid7Ebx {
    1.24 +    uint32_t value;
    1.25 +    struct {
    1.26 +      uint32_t fsgsbase : 1,
    1.27 +                        : 2,
    1.28 +                   bmi1 : 1,
    1.29 +                        : 1,
    1.30 +                   avx2 : 1,
    1.31 +                        : 2,
    1.32 +                   bmi2 : 1,
    1.33 +                        : 23;
    1.34 +    } bits;
    1.35 +  };
    1.36 +
    1.37 +  union XemXcr0Eax {
    1.38 +    uint32_t value;
    1.39 +    struct {
    1.40 +      uint32_t x87 : 1,
    1.41 +               sse : 1,
    1.42 +               ymm : 1,
    1.43 +                   : 29;
    1.44 +    } bits;
    1.45 +  };
    1.46 +
    1.47  protected:
    1.48     static int _cpu;
    1.49     static int _model;
    1.50 @@ -200,7 +231,9 @@
    1.51       CPU_SSE4_1 = (1 << 11),
    1.52       CPU_SSE4_2 = (1 << 12),
    1.53       CPU_POPCNT = (1 << 13),
    1.54 -     CPU_LZCNT  = (1 << 14)
    1.55 +     CPU_LZCNT  = (1 << 14),
    1.56 +     CPU_AVX    = (1 << 15),
    1.57 +     CPU_AVX2   = (1 << 16)
    1.58     } cpuFeatureFlags;
    1.59  
    1.60    // cpuid information block.  All info derived from executing cpuid with
    1.61 @@ -228,6 +261,12 @@
    1.62      uint32_t     dcp_cpuid4_ecx; // unused currently
    1.63      uint32_t     dcp_cpuid4_edx; // unused currently
    1.64  
    1.65 +    // cpuid function 7 (structured extended features)
    1.66 +    SefCpuid7Eax sef_cpuid7_eax;
    1.67 +    SefCpuid7Ebx sef_cpuid7_ebx;
    1.68 +    uint32_t     sef_cpuid7_ecx; // unused currently
    1.69 +    uint32_t     sef_cpuid7_edx; // unused currently
    1.70 +
    1.71      // cpuid function 0xB (processor topology)
    1.72      // ecx = 0
    1.73      uint32_t     tpl_cpuidB0_eax;
    1.74 @@ -275,6 +314,10 @@
    1.75      uint32_t     ext_cpuid8_ebx; // reserved
    1.76      ExtCpuid8Ecx ext_cpuid8_ecx;
    1.77      uint32_t     ext_cpuid8_edx; // reserved
    1.78 +
    1.79 +    // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
    1.80 +    XemXcr0Eax   xem_xcr0_eax;
    1.81 +    uint32_t     xem_xcr0_edx; // reserved
    1.82    };
    1.83  
    1.84    // The actual cpuid info block
    1.85 @@ -328,6 +371,14 @@
    1.86        result |= CPU_SSE4_2;
    1.87      if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
    1.88        result |= CPU_POPCNT;
    1.89 +    if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
    1.90 +        _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
    1.91 +        _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
    1.92 +        _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
    1.93 +      result |= CPU_AVX;
    1.94 +      if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
    1.95 +        result |= CPU_AVX2;
    1.96 +    }
    1.97  
    1.98      // AMD features.
    1.99      if (is_amd()) {
   1.100 @@ -350,12 +401,14 @@
   1.101    static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
   1.102    static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
   1.103    static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
   1.104 +  static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
   1.105    static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
   1.106    static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
   1.107    static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
   1.108    static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
   1.109    static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
   1.110    static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
   1.111 +  static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
   1.112  
   1.113    // Initialization
   1.114    static void initialize();
   1.115 @@ -447,6 +500,8 @@
   1.116    static bool supports_sse4_1()   { return (_cpuFeatures & CPU_SSE4_1) != 0; }
   1.117    static bool supports_sse4_2()   { return (_cpuFeatures & CPU_SSE4_2) != 0; }
   1.118    static bool supports_popcnt()   { return (_cpuFeatures & CPU_POPCNT) != 0; }
   1.119 +  static bool supports_avx()      { return (_cpuFeatures & CPU_AVX) != 0; }
   1.120 +  static bool supports_avx2()     { return (_cpuFeatures & CPU_AVX2) != 0; }
   1.121    //
   1.122    // AMD features
   1.123    //

mercurial