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src/share/vm/c1/c1_LIR.cpp@04ff2f6cd0eb
src/share/vm/c1/c1_LIR.cpp
Tue, 17 Oct 2017 12:58:25 +0800
- author
- aoqi
- date
- Tue, 17 Oct 2017 12:58:25 +0800
- changeset 7994
- 04ff2f6cd0eb
- parent 7854
- e8260b6328fb
- parent 6876
- 710a3c8b516e
- child 8856
- ac27a9c85bea
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merge
1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 /*
26 * This file has been modified by Loongson Technology in 2015. These
27 * modifications are Copyright (c) 2015 Loongson Technology, and are made
28 * available on the same license terms set forth above.
29 */
31 #include "precompiled.hpp"
32 #include "c1/c1_InstructionPrinter.hpp"
33 #include "c1/c1_LIR.hpp"
34 #include "c1/c1_LIRAssembler.hpp"
35 #include "c1/c1_ValueStack.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "runtime/sharedRuntime.hpp"
39 Register LIR_OprDesc::as_register() const {
40 return FrameMap::cpu_rnr2reg(cpu_regnr());
41 }
43 Register LIR_OprDesc::as_register_lo() const {
44 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
45 }
47 Register LIR_OprDesc::as_register_hi() const {
48 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
49 }
51 #if defined(X86)
53 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
54 return FrameMap::nr2xmmreg(xmm_regnr());
55 }
57 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
58 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
59 return FrameMap::nr2xmmreg(xmm_regnrLo());
60 }
62 #endif // X86
64 #if defined(SPARC) || defined(PPC)
66 FloatRegister LIR_OprDesc::as_float_reg() const {
67 return FrameMap::nr2floatreg(fpu_regnr());
68 }
70 FloatRegister LIR_OprDesc::as_double_reg() const {
71 return FrameMap::nr2floatreg(fpu_regnrHi());
72 }
74 #endif
75 #ifdef MIPS64
77 FloatRegister LIR_OprDesc::as_float_reg() const {
78 return FrameMap::nr2floatreg(fpu_regnr());
79 }
81 FloatRegister LIR_OprDesc::as_double_reg() const {
82 return FrameMap::nr2floatreg(fpu_regnrHi());
83 }
85 FloatRegister LIR_OprDesc::as_fpu_lo() const {
86 return FrameMap::nr2floatreg(fpu_regnrLo());
87 }
89 FloatRegister LIR_OprDesc::as_fpu_hi() const {
90 return FrameMap::nr2floatreg(fpu_regnrHi());
91 }
93 #endif
95 #ifdef ARM
97 FloatRegister LIR_OprDesc::as_float_reg() const {
98 return as_FloatRegister(fpu_regnr());
99 }
101 FloatRegister LIR_OprDesc::as_double_reg() const {
102 return as_FloatRegister(fpu_regnrLo());
103 }
105 #endif
108 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
110 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
111 ValueTag tag = type->tag();
112 switch (tag) {
113 case metaDataTag : {
114 ClassConstant* c = type->as_ClassConstant();
115 if (c != NULL && !c->value()->is_loaded()) {
116 return LIR_OprFact::metadataConst(NULL);
117 } else if (c != NULL) {
118 return LIR_OprFact::metadataConst(c->value()->constant_encoding());
119 } else {
120 MethodConstant* m = type->as_MethodConstant();
121 assert (m != NULL, "not a class or a method?");
122 return LIR_OprFact::metadataConst(m->value()->constant_encoding());
123 }
124 }
125 case objectTag : {
126 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
127 }
128 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
129 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
130 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
131 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
132 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
133 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
134 }
135 }
138 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
139 switch (type->tag()) {
140 case objectTag: return LIR_OprFact::oopConst(NULL);
141 case addressTag:return LIR_OprFact::addressConst(0);
142 case intTag: return LIR_OprFact::intConst(0);
143 case floatTag: return LIR_OprFact::floatConst(0.0);
144 case longTag: return LIR_OprFact::longConst(0);
145 case doubleTag: return LIR_OprFact::doubleConst(0.0);
146 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
147 }
148 return illegalOpr;
149 }
153 //---------------------------------------------------
156 LIR_Address::Scale LIR_Address::scale(BasicType type) {
157 int elem_size = type2aelembytes(type);
158 switch (elem_size) {
159 case 1: return LIR_Address::times_1;
160 case 2: return LIR_Address::times_2;
161 case 4: return LIR_Address::times_4;
162 case 8: return LIR_Address::times_8;
163 }
164 ShouldNotReachHere();
165 return LIR_Address::times_1;
166 }
169 #ifndef PRODUCT
170 void LIR_Address::verify0() const {
171 #if defined(SPARC) || defined(PPC)
172 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
173 assert(disp() == 0 || index()->is_illegal(), "can't have both");
174 #endif
175 #ifdef _LP64
176 assert(base()->is_cpu_register(), "wrong base operand");
177 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
178 #ifndef MIPS64
179 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
180 "wrong type for addresses");
181 #endif
182 #else
183 assert(base()->is_single_cpu(), "wrong base operand");
184 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
185 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
186 "wrong type for addresses");
187 #endif
188 }
189 #endif
192 //---------------------------------------------------
194 char LIR_OprDesc::type_char(BasicType t) {
195 switch (t) {
196 case T_ARRAY:
197 t = T_OBJECT;
198 case T_BOOLEAN:
199 case T_CHAR:
200 case T_FLOAT:
201 case T_DOUBLE:
202 case T_BYTE:
203 case T_SHORT:
204 case T_INT:
205 case T_LONG:
206 case T_OBJECT:
207 case T_ADDRESS:
208 case T_VOID:
209 return ::type2char(t);
210 case T_METADATA:
211 return 'M';
212 case T_ILLEGAL:
213 return '?';
215 default:
216 ShouldNotReachHere();
217 return '?';
218 }
219 }
221 #ifndef PRODUCT
222 void LIR_OprDesc::validate_type() const {
224 #ifdef ASSERT
225 if (!is_pointer() && !is_illegal()) {
226 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
227 switch (as_BasicType(type_field())) {
228 case T_LONG:
229 assert((kindfield == cpu_register || kindfield == stack_value) &&
230 size_field() == double_size, "must match");
231 break;
232 case T_FLOAT:
233 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
234 assert((kindfield == fpu_register || kindfield == stack_value
235 ARM_ONLY(|| kindfield == cpu_register)
236 PPC_ONLY(|| kindfield == cpu_register) ) &&
237 size_field() == single_size, "must match");
238 break;
239 case T_DOUBLE:
240 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
241 assert((kindfield == fpu_register || kindfield == stack_value
242 ARM_ONLY(|| kindfield == cpu_register)
243 PPC_ONLY(|| kindfield == cpu_register) ) &&
244 size_field() == double_size, "must match");
245 break;
246 case T_BOOLEAN:
247 case T_CHAR:
248 case T_BYTE:
249 case T_SHORT:
250 case T_INT:
251 case T_ADDRESS:
252 case T_OBJECT:
253 case T_METADATA:
254 case T_ARRAY:
255 assert((kindfield == cpu_register || kindfield == stack_value) &&
256 size_field() == single_size, "must match");
257 break;
259 case T_ILLEGAL:
260 // XXX TKR also means unknown right now
261 // assert(is_illegal(), "must match");
262 break;
264 default:
265 ShouldNotReachHere();
266 }
267 }
268 #endif
270 }
271 #endif // PRODUCT
274 bool LIR_OprDesc::is_oop() const {
275 if (is_pointer()) {
276 return pointer()->is_oop_pointer();
277 } else {
278 OprType t= type_field();
279 assert(t != unknown_type, "not set");
280 return t == object_type;
281 }
282 }
286 void LIR_Op2::verify() const {
287 #ifdef ASSERT
288 switch (code()) {
289 case lir_cmove:
290 case lir_xchg:
291 break;
293 default:
294 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
295 "can't produce oops from arith");
296 }
298 if (TwoOperandLIRForm) {
299 switch (code()) {
300 case lir_add:
301 case lir_sub:
302 case lir_mul:
303 case lir_mul_strictfp:
304 case lir_div:
305 case lir_div_strictfp:
306 case lir_rem:
307 case lir_logic_and:
308 case lir_logic_or:
309 case lir_logic_xor:
310 case lir_shl:
311 case lir_shr:
312 assert(in_opr1() == result_opr(), "opr1 and result must match");
313 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
314 break;
316 // special handling for lir_ushr because of write barriers
317 case lir_ushr:
318 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
319 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
320 break;
322 }
323 }
324 #endif
325 }
328 #ifndef MIPS64
329 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
330 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
331 , _cond(cond)
332 , _type(type)
333 , _label(block->label())
334 , _block(block)
335 , _ublock(NULL)
336 , _stub(NULL) {
337 }
339 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
340 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
341 , _cond(cond)
342 , _type(type)
343 , _label(stub->entry())
344 , _block(NULL)
345 , _ublock(NULL)
346 , _stub(stub) {
347 }
349 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
350 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
351 , _cond(cond)
352 , _type(type)
353 , _label(block->label())
354 , _block(block)
355 , _ublock(ublock)
356 , _stub(NULL)
357 {
358 }
360 #else
361 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
362 BlockBegin* block):
363 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
364 _cond(cond),
365 _type(type),
366 _label(block->label()),
367 _block(block),
368 _ublock(NULL),
369 _stub(NULL) {
370 }
372 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
373 CodeStub* stub):
374 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
375 _cond(cond),
376 _type(type),
377 _label(stub->entry()),
378 _block(NULL),
379 _ublock(NULL),
380 _stub(stub) {
381 }
384 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
385 BlockBegin *block, BlockBegin *ublock):
386 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
387 _cond(cond),
388 _type(type),
389 _label(block->label()),
390 _block(block),
391 _ublock(ublock),
392 _stub(NULL) {
393 }
395 #endif
397 void LIR_OpBranch::change_block(BlockBegin* b) {
398 assert(_block != NULL, "must have old block");
399 assert(_block->label() == label(), "must be equal");
401 _block = b;
402 _label = b->label();
403 }
405 void LIR_OpBranch::change_ublock(BlockBegin* b) {
406 assert(_ublock != NULL, "must have old block");
407 _ublock = b;
408 }
410 void LIR_OpBranch::negate_cond() {
411 switch (_cond) {
412 case lir_cond_equal: _cond = lir_cond_notEqual; break;
413 case lir_cond_notEqual: _cond = lir_cond_equal; break;
414 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
415 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
416 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
417 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
418 default: ShouldNotReachHere();
419 }
420 }
423 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
424 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
425 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
426 CodeStub* stub)
428 : LIR_Op(code, result, NULL)
429 , _object(object)
430 , _array(LIR_OprFact::illegalOpr)
431 , _klass(klass)
432 , _tmp1(tmp1)
433 , _tmp2(tmp2)
434 , _tmp3(tmp3)
435 , _fast_check(fast_check)
436 , _stub(stub)
437 , _info_for_patch(info_for_patch)
438 , _info_for_exception(info_for_exception)
439 , _profiled_method(NULL)
440 , _profiled_bci(-1)
441 , _should_profile(false)
442 {
443 if (code == lir_checkcast) {
444 assert(info_for_exception != NULL, "checkcast throws exceptions");
445 } else if (code == lir_instanceof) {
446 assert(info_for_exception == NULL, "instanceof throws no exceptions");
447 } else {
448 ShouldNotReachHere();
449 }
450 }
454 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
455 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
456 , _object(object)
457 , _array(array)
458 , _klass(NULL)
459 , _tmp1(tmp1)
460 , _tmp2(tmp2)
461 , _tmp3(tmp3)
462 , _fast_check(false)
463 , _stub(NULL)
464 , _info_for_patch(NULL)
465 , _info_for_exception(info_for_exception)
466 , _profiled_method(NULL)
467 , _profiled_bci(-1)
468 , _should_profile(false)
469 {
470 if (code == lir_store_check) {
471 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
472 assert(info_for_exception != NULL, "store_check throws exceptions");
473 } else {
474 ShouldNotReachHere();
475 }
476 }
479 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
480 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
481 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
482 , _tmp(tmp)
483 , _src(src)
484 , _src_pos(src_pos)
485 , _dst(dst)
486 , _dst_pos(dst_pos)
487 , _flags(flags)
488 , _expected_type(expected_type)
489 , _length(length) {
490 _stub = new ArrayCopyStub(this);
491 }
493 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res)
494 : LIR_Op(lir_updatecrc32, res, NULL)
495 , _crc(crc)
496 , _val(val) {
497 }
499 //-------------------verify--------------------------
501 void LIR_Op1::verify() const {
502 switch(code()) {
503 case lir_move:
504 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
505 break;
506 case lir_null_check:
507 assert(in_opr()->is_register(), "must be");
508 break;
509 case lir_return:
510 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
511 break;
512 }
513 }
515 void LIR_OpRTCall::verify() const {
516 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
517 }
519 //-------------------visits--------------------------
521 // complete rework of LIR instruction visitor.
522 // The virtual call for each instruction type is replaced by a big
523 // switch that adds the operands for each instruction
525 void LIR_OpVisitState::visit(LIR_Op* op) {
526 // copy information from the LIR_Op
527 reset();
528 set_op(op);
530 switch (op->code()) {
532 // LIR_Op0
533 case lir_word_align: // result and info always invalid
534 case lir_backwardbranch_target: // result and info always invalid
535 case lir_build_frame: // result and info always invalid
536 case lir_fpop_raw: // result and info always invalid
537 case lir_24bit_FPU: // result and info always invalid
538 case lir_reset_FPU: // result and info always invalid
539 case lir_breakpoint: // result and info always invalid
540 case lir_membar: // result and info always invalid
541 case lir_membar_acquire: // result and info always invalid
542 case lir_membar_release: // result and info always invalid
543 case lir_membar_loadload: // result and info always invalid
544 case lir_membar_storestore: // result and info always invalid
545 case lir_membar_loadstore: // result and info always invalid
546 case lir_membar_storeload: // result and info always invalid
547 {
548 assert(op->as_Op0() != NULL, "must be");
549 assert(op->_info == NULL, "info not used by this instruction");
550 assert(op->_result->is_illegal(), "not used");
551 break;
552 }
554 case lir_nop: // may have info, result always invalid
555 case lir_std_entry: // may have result, info always invalid
556 case lir_osr_entry: // may have result, info always invalid
557 case lir_get_thread: // may have result, info always invalid
558 {
559 assert(op->as_Op0() != NULL, "must be");
560 if (op->_info != NULL) do_info(op->_info);
561 if (op->_result->is_valid()) do_output(op->_result);
562 break;
563 }
566 // LIR_OpLabel
567 case lir_label: // result and info always invalid
568 {
569 assert(op->as_OpLabel() != NULL, "must be");
570 assert(op->_info == NULL, "info not used by this instruction");
571 assert(op->_result->is_illegal(), "not used");
572 break;
573 }
576 // LIR_Op1
577 case lir_fxch: // input always valid, result and info always invalid
578 case lir_fld: // input always valid, result and info always invalid
579 case lir_ffree: // input always valid, result and info always invalid
580 case lir_push: // input always valid, result and info always invalid
581 case lir_pop: // input always valid, result and info always invalid
582 case lir_return: // input always valid, result and info always invalid
583 case lir_leal: // input and result always valid, info always invalid
584 case lir_neg: // input and result always valid, info always invalid
585 case lir_monaddr: // input and result always valid, info always invalid
586 case lir_null_check: // input and info always valid, result always invalid
587 case lir_move: // input and result always valid, may have info
588 case lir_pack64: // input and result always valid
589 case lir_unpack64: // input and result always valid
590 case lir_prefetchr: // input always valid, result and info always invalid
591 case lir_prefetchw: // input always valid, result and info always invalid
592 {
593 assert(op->as_Op1() != NULL, "must be");
594 LIR_Op1* op1 = (LIR_Op1*)op;
596 if (op1->_info) do_info(op1->_info);
597 if (op1->_opr->is_valid()) do_input(op1->_opr);
598 if (op1->_result->is_valid()) do_output(op1->_result);
600 break;
601 }
603 case lir_safepoint:
604 {
605 assert(op->as_Op1() != NULL, "must be");
606 LIR_Op1* op1 = (LIR_Op1*)op;
608 assert(op1->_info != NULL, ""); do_info(op1->_info);
609 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
610 assert(op1->_result->is_illegal(), "safepoint does not produce value");
612 break;
613 }
615 // LIR_OpConvert;
616 case lir_convert: // input and result always valid, info always invalid
617 {
618 assert(op->as_OpConvert() != NULL, "must be");
619 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
621 assert(opConvert->_info == NULL, "must be");
622 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
623 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
624 #ifdef PPC
625 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
626 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
627 #endif
628 do_stub(opConvert->_stub);
630 break;
631 }
633 // LIR_OpBranch;
634 case lir_branch: // may have info, input and result register always invalid
635 case lir_cond_float_branch: // may have info, input and result register always invalid
636 {
637 assert(op->as_OpBranch() != NULL, "must be");
638 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
640 #ifdef MIPS64
641 if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
642 if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
643 if (opBranch->_tmp1->is_valid()) do_temp(opBranch->_tmp1);
644 if (opBranch->_tmp2->is_valid()) do_temp(opBranch->_tmp2);
645 if (opBranch->_tmp3->is_valid()) do_temp(opBranch->_tmp3);
646 if (opBranch->_tmp4->is_valid()) do_temp(opBranch->_tmp4);
647 if (opBranch->_tmp5->is_valid()) do_temp(opBranch->_tmp5);
648 #endif
649 if (opBranch->_info != NULL) do_info(opBranch->_info);
650 assert(opBranch->_result->is_illegal(), "not used");
651 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
653 break;
654 }
657 // LIR_OpAllocObj
658 case lir_alloc_object:
659 {
660 assert(op->as_OpAllocObj() != NULL, "must be");
661 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
663 if (opAllocObj->_info) do_info(opAllocObj->_info);
664 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
665 do_temp(opAllocObj->_opr);
666 }
667 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
668 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
669 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
670 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
671 #ifdef MIPS64
672 if (opAllocObj->_tmp5->is_valid()) do_temp(opAllocObj->_tmp5);
673 if (opAllocObj->_tmp6->is_valid()) do_temp(opAllocObj->_tmp6);
674 #endif
675 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
676 do_stub(opAllocObj->_stub);
677 break;
678 }
681 // LIR_OpRoundFP;
682 case lir_roundfp: {
683 assert(op->as_OpRoundFP() != NULL, "must be");
684 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
686 assert(op->_info == NULL, "info not used by this instruction");
687 assert(opRoundFP->_tmp->is_illegal(), "not used");
688 do_input(opRoundFP->_opr);
689 do_output(opRoundFP->_result);
691 break;
692 }
695 // LIR_Op2
696 #ifdef MIPS64
697 case lir_null_check_for_branch:
698 #else
699 case lir_cmp:
700 #endif
701 case lir_cmp_l2i:
702 case lir_ucmp_fd2i:
703 case lir_cmp_fd2i:
704 case lir_add:
705 case lir_sub:
706 case lir_mul:
707 case lir_div:
708 case lir_rem:
709 case lir_sqrt:
710 case lir_abs:
711 case lir_logic_and:
712 case lir_logic_or:
713 case lir_logic_xor:
714 case lir_shl:
715 case lir_shr:
716 case lir_ushr:
717 case lir_xadd:
718 case lir_xchg:
719 case lir_assert:
720 {
721 assert(op->as_Op2() != NULL, "must be");
722 LIR_Op2* op2 = (LIR_Op2*)op;
723 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
724 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
726 if (op2->_info) do_info(op2->_info);
727 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
728 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
729 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
730 if (op2->_result->is_valid()) do_output(op2->_result);
731 if (op->code() == lir_xchg || op->code() == lir_xadd) {
732 // on ARM and PPC, return value is loaded first so could
733 // destroy inputs. On other platforms that implement those
734 // (x86, sparc), the extra constrainsts are harmless.
735 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
736 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
737 }
739 break;
740 }
742 // special handling for cmove: right input operand must not be equal
743 // to the result operand, otherwise the backend fails
744 case lir_cmove:
745 {
746 assert(op->as_Op2() != NULL, "must be");
747 LIR_Op2* op2 = (LIR_Op2*)op;
749 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
750 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
751 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
753 do_input(op2->_opr1);
754 do_input(op2->_opr2);
755 do_temp(op2->_opr2);
756 do_output(op2->_result);
758 break;
759 }
761 // vspecial handling for strict operations: register input operands
762 // as temp to guarantee that they do not overlap with other
763 // registers
764 case lir_mul_strictfp:
765 case lir_div_strictfp:
766 {
767 assert(op->as_Op2() != NULL, "must be");
768 LIR_Op2* op2 = (LIR_Op2*)op;
770 assert(op2->_info == NULL, "not used");
771 assert(op2->_opr1->is_valid(), "used");
772 assert(op2->_opr2->is_valid(), "used");
773 assert(op2->_result->is_valid(), "used");
774 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
775 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
777 do_input(op2->_opr1); do_temp(op2->_opr1);
778 do_input(op2->_opr2); do_temp(op2->_opr2);
779 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
780 do_output(op2->_result);
782 break;
783 }
785 case lir_throw: {
786 assert(op->as_Op2() != NULL, "must be");
787 LIR_Op2* op2 = (LIR_Op2*)op;
789 if (op2->_info) do_info(op2->_info);
790 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
791 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
792 assert(op2->_result->is_illegal(), "no result");
793 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
794 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
796 break;
797 }
799 case lir_unwind: {
800 assert(op->as_Op1() != NULL, "must be");
801 LIR_Op1* op1 = (LIR_Op1*)op;
803 assert(op1->_info == NULL, "no info");
804 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
805 assert(op1->_result->is_illegal(), "no result");
807 break;
808 }
811 case lir_tan:
812 case lir_sin:
813 case lir_cos:
814 case lir_log:
815 case lir_log10:
816 case lir_exp: {
817 assert(op->as_Op2() != NULL, "must be");
818 LIR_Op2* op2 = (LIR_Op2*)op;
820 // On x86 tan/sin/cos need two temporary fpu stack slots and
821 // log/log10 need one so handle opr2 and tmp as temp inputs.
822 // Register input operand as temp to guarantee that it doesn't
823 // overlap with the input.
824 assert(op2->_info == NULL, "not used");
825 assert(op2->_tmp5->is_illegal(), "not used");
826 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used");
827 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used");
828 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used");
829 assert(op2->_opr1->is_valid(), "used");
830 do_input(op2->_opr1); do_temp(op2->_opr1);
832 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
833 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
834 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2);
835 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3);
836 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4);
837 if (op2->_result->is_valid()) do_output(op2->_result);
839 break;
840 }
842 case lir_pow: {
843 assert(op->as_Op2() != NULL, "must be");
844 LIR_Op2* op2 = (LIR_Op2*)op;
846 // On x86 pow needs two temporary fpu stack slots: tmp1 and
847 // tmp2. Register input operands as temps to guarantee that it
848 // doesn't overlap with the temporary slots.
849 assert(op2->_info == NULL, "not used");
850 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used");
851 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid()
852 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used");
853 assert(op2->_result->is_valid(), "used");
855 do_input(op2->_opr1); do_temp(op2->_opr1);
856 do_input(op2->_opr2); do_temp(op2->_opr2);
857 do_temp(op2->_tmp1);
858 do_temp(op2->_tmp2);
859 do_temp(op2->_tmp3);
860 do_temp(op2->_tmp4);
861 do_temp(op2->_tmp5);
862 do_output(op2->_result);
864 break;
865 }
867 // LIR_Op3
868 #ifdef MIPS64
869 case lir_frem:
870 #endif
871 case lir_idiv:
872 case lir_irem: {
873 assert(op->as_Op3() != NULL, "must be");
874 LIR_Op3* op3= (LIR_Op3*)op;
876 if (op3->_info) do_info(op3->_info);
877 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
879 // second operand is input and temp, so ensure that second operand
880 // and third operand get not the same register
881 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
882 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
883 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
885 if (op3->_result->is_valid()) do_output(op3->_result);
887 break;
888 }
891 // LIR_OpJavaCall
892 case lir_static_call:
893 case lir_optvirtual_call:
894 case lir_icvirtual_call:
895 case lir_virtual_call:
896 case lir_dynamic_call: {
897 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
898 assert(opJavaCall != NULL, "must be");
900 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
902 // only visit register parameters
903 int n = opJavaCall->_arguments->length();
904 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
905 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
906 do_input(*opJavaCall->_arguments->adr_at(i));
907 }
908 }
910 if (opJavaCall->_info) do_info(opJavaCall->_info);
911 if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr &&
912 opJavaCall->is_method_handle_invoke()) {
913 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
914 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
915 }
916 do_call();
917 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
919 break;
920 }
923 // LIR_OpRTCall
924 case lir_rtcall: {
925 assert(op->as_OpRTCall() != NULL, "must be");
926 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
928 // only visit register parameters
929 int n = opRTCall->_arguments->length();
930 for (int i = 0; i < n; i++) {
931 if (!opRTCall->_arguments->at(i)->is_pointer()) {
932 do_input(*opRTCall->_arguments->adr_at(i));
933 }
934 }
935 if (opRTCall->_info) do_info(opRTCall->_info);
936 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
937 do_call();
938 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
940 break;
941 }
944 // LIR_OpArrayCopy
945 case lir_arraycopy: {
946 assert(op->as_OpArrayCopy() != NULL, "must be");
947 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
949 assert(opArrayCopy->_result->is_illegal(), "unused");
950 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
951 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
952 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
953 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
954 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
955 #ifndef MIPS64
956 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
957 #endif
958 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
960 // the implementation of arraycopy always has a call into the runtime
961 do_call();
963 break;
964 }
967 // LIR_OpUpdateCRC32
968 case lir_updatecrc32: {
969 assert(op->as_OpUpdateCRC32() != NULL, "must be");
970 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op;
972 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc);
973 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val);
974 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result);
975 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
977 break;
978 }
981 // LIR_OpLock
982 case lir_lock:
983 case lir_unlock: {
984 assert(op->as_OpLock() != NULL, "must be");
985 LIR_OpLock* opLock = (LIR_OpLock*)op;
987 if (opLock->_info) do_info(opLock->_info);
989 // TODO: check if these operands really have to be temp
990 // (or if input is sufficient). This may have influence on the oop map!
991 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
992 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
993 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
995 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
996 assert(opLock->_result->is_illegal(), "unused");
998 do_stub(opLock->_stub);
1000 break;
1001 }
1004 // LIR_OpDelay
1005 case lir_delay_slot: {
1006 assert(op->as_OpDelay() != NULL, "must be");
1007 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
1009 visit(opDelay->delay_op());
1010 break;
1011 }
1013 // LIR_OpTypeCheck
1014 case lir_instanceof:
1015 case lir_checkcast:
1016 case lir_store_check: {
1017 assert(op->as_OpTypeCheck() != NULL, "must be");
1018 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
1020 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
1021 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
1022 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
1023 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
1024 do_temp(opTypeCheck->_object);
1025 }
1026 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
1027 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
1028 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
1029 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
1030 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
1031 do_stub(opTypeCheck->_stub);
1032 break;
1033 }
1035 // LIR_OpCompareAndSwap
1036 case lir_cas_long:
1037 case lir_cas_obj:
1038 case lir_cas_int: {
1039 assert(op->as_OpCompareAndSwap() != NULL, "must be");
1040 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
1042 assert(opCompareAndSwap->_addr->is_valid(), "used");
1043 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
1044 assert(opCompareAndSwap->_new_value->is_valid(), "used");
1045 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
1046 do_input(opCompareAndSwap->_addr);
1047 do_temp(opCompareAndSwap->_addr);
1048 do_input(opCompareAndSwap->_cmp_value);
1049 do_temp(opCompareAndSwap->_cmp_value);
1050 do_input(opCompareAndSwap->_new_value);
1051 do_temp(opCompareAndSwap->_new_value);
1052 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
1053 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
1054 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
1056 break;
1057 }
1060 // LIR_OpAllocArray;
1061 case lir_alloc_array: {
1062 assert(op->as_OpAllocArray() != NULL, "must be");
1063 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
1065 if (opAllocArray->_info) do_info(opAllocArray->_info);
1066 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
1067 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
1068 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
1069 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
1070 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
1071 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
1072 #ifdef MIPS64
1073 if (opAllocArray->_tmp5->is_valid()) do_temp(opAllocArray->_tmp5);
1074 #endif
1075 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
1076 do_stub(opAllocArray->_stub);
1077 break;
1078 }
1080 // LIR_OpProfileCall:
1081 case lir_profile_call: {
1082 assert(op->as_OpProfileCall() != NULL, "must be");
1083 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
1085 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
1086 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
1087 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
1088 break;
1089 }
1091 // LIR_OpProfileType:
1092 case lir_profile_type: {
1093 assert(op->as_OpProfileType() != NULL, "must be");
1094 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op;
1096 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp);
1097 do_input(opProfileType->_obj);
1098 do_temp(opProfileType->_tmp);
1099 break;
1100 }
1101 default:
1102 ShouldNotReachHere();
1103 }
1104 }
1107 void LIR_OpVisitState::do_stub(CodeStub* stub) {
1108 if (stub != NULL) {
1109 stub->visit(this);
1110 }
1111 }
1113 XHandlers* LIR_OpVisitState::all_xhandler() {
1114 XHandlers* result = NULL;
1116 int i;
1117 for (i = 0; i < info_count(); i++) {
1118 if (info_at(i)->exception_handlers() != NULL) {
1119 result = info_at(i)->exception_handlers();
1120 break;
1121 }
1122 }
1124 #ifdef ASSERT
1125 for (i = 0; i < info_count(); i++) {
1126 assert(info_at(i)->exception_handlers() == NULL ||
1127 info_at(i)->exception_handlers() == result,
1128 "only one xhandler list allowed per LIR-operation");
1129 }
1130 #endif
1132 if (result != NULL) {
1133 return result;
1134 } else {
1135 return new XHandlers();
1136 }
1138 return result;
1139 }
1142 #ifdef ASSERT
1143 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1144 visit(op);
1146 return opr_count(inputMode) == 0 &&
1147 opr_count(outputMode) == 0 &&
1148 opr_count(tempMode) == 0 &&
1149 info_count() == 0 &&
1150 !has_call() &&
1151 !has_slow_case();
1152 }
1153 #endif
1155 //---------------------------------------------------
1158 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1159 masm->emit_call(this);
1160 }
1162 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1163 masm->emit_rtcall(this);
1164 }
1166 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1167 masm->emit_opLabel(this);
1168 }
1170 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1171 masm->emit_arraycopy(this);
1172 masm->append_code_stub(stub());
1173 }
1175 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) {
1176 masm->emit_updatecrc32(this);
1177 }
1179 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1180 masm->emit_op0(this);
1181 }
1183 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1184 masm->emit_op1(this);
1185 }
1187 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1188 masm->emit_alloc_obj(this);
1189 masm->append_code_stub(stub());
1190 }
1192 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1193 masm->emit_opBranch(this);
1194 if (stub()) {
1195 masm->append_code_stub(stub());
1196 }
1197 }
1199 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1200 masm->emit_opConvert(this);
1201 if (stub() != NULL) {
1202 masm->append_code_stub(stub());
1203 }
1204 }
1206 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1207 masm->emit_op2(this);
1208 }
1210 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1211 masm->emit_alloc_array(this);
1212 masm->append_code_stub(stub());
1213 }
1215 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1216 masm->emit_opTypeCheck(this);
1217 if (stub()) {
1218 masm->append_code_stub(stub());
1219 }
1220 }
1222 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1223 masm->emit_compare_and_swap(this);
1224 }
1226 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1227 masm->emit_op3(this);
1228 }
1230 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1231 masm->emit_lock(this);
1232 if (stub()) {
1233 masm->append_code_stub(stub());
1234 }
1235 }
1237 #ifdef ASSERT
1238 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1239 masm->emit_assert(this);
1240 }
1241 #endif
1243 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1244 masm->emit_delay(this);
1245 }
1247 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1248 masm->emit_profile_call(this);
1249 }
1251 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1252 masm->emit_profile_type(this);
1253 }
1255 // LIR_List
1256 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1257 : _operations(8)
1258 , _compilation(compilation)
1259 #ifndef PRODUCT
1260 , _block(block)
1261 #endif
1262 #ifdef ASSERT
1263 , _file(NULL)
1264 , _line(0)
1265 #endif
1266 { }
1269 #ifdef ASSERT
1270 void LIR_List::set_file_and_line(const char * file, int line) {
1271 const char * f = strrchr(file, '/');
1272 if (f == NULL) f = strrchr(file, '\\');
1273 if (f == NULL) {
1274 f = file;
1275 } else {
1276 f++;
1277 }
1278 _file = f;
1279 _line = line;
1280 }
1281 #endif
1284 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1285 assert(this == buffer->lir_list(), "wrong lir list");
1286 const int n = _operations.length();
1288 if (buffer->number_of_ops() > 0) {
1289 // increase size of instructions list
1290 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1291 // insert ops from buffer into instructions list
1292 int op_index = buffer->number_of_ops() - 1;
1293 int ip_index = buffer->number_of_insertion_points() - 1;
1294 int from_index = n - 1;
1295 int to_index = _operations.length() - 1;
1296 for (; ip_index >= 0; ip_index --) {
1297 int index = buffer->index_at(ip_index);
1298 // make room after insertion point
1299 while (index < from_index) {
1300 _operations.at_put(to_index --, _operations.at(from_index --));
1301 }
1302 // insert ops from buffer
1303 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1304 _operations.at_put(to_index --, buffer->op_at(op_index --));
1305 }
1306 }
1307 }
1309 buffer->finish();
1310 }
1313 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1314 assert(reg->type() == T_OBJECT, "bad reg");
1315 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1316 }
1318 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1319 assert(reg->type() == T_METADATA, "bad reg");
1320 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1321 }
1323 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1324 append(new LIR_Op1(
1325 lir_move,
1326 LIR_OprFact::address(addr),
1327 src,
1328 addr->type(),
1329 patch_code,
1330 info));
1331 }
1334 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1335 append(new LIR_Op1(
1336 lir_move,
1337 LIR_OprFact::address(address),
1338 dst,
1339 address->type(),
1340 patch_code,
1341 info, lir_move_volatile));
1342 }
1344 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1345 #ifndef MIPS64
1346 append(new LIR_Op1(
1347 lir_move,
1348 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1349 dst,
1350 type,
1351 patch_code,
1352 info, lir_move_volatile));
1353 #else
1354 add(base, offset, base);
1355 append(new LIR_Op1(
1356 lir_move,
1357 LIR_OprFact::address(new LIR_Address(base, 0, type)),
1358 dst,
1359 type,
1360 patch_code,
1361 info, lir_move_volatile));
1362 #endif
1363 }
1366 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1367 append(new LIR_Op1(
1368 is_store ? lir_prefetchw : lir_prefetchr,
1369 LIR_OprFact::address(addr)));
1370 }
1373 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1374 append(new LIR_Op1(
1375 lir_move,
1376 LIR_OprFact::intConst(v),
1377 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1378 type,
1379 patch_code,
1380 info));
1381 }
1384 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1385 append(new LIR_Op1(
1386 lir_move,
1387 LIR_OprFact::oopConst(o),
1388 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1389 type,
1390 patch_code,
1391 info));
1392 }
1395 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1396 append(new LIR_Op1(
1397 lir_move,
1398 src,
1399 LIR_OprFact::address(addr),
1400 addr->type(),
1401 patch_code,
1402 info));
1403 }
1406 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1407 append(new LIR_Op1(
1408 lir_move,
1409 src,
1410 LIR_OprFact::address(addr),
1411 addr->type(),
1412 patch_code,
1413 info,
1414 lir_move_volatile));
1415 }
1417 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1418 #ifndef MIPS64
1419 append(new LIR_Op1(
1420 lir_move,
1421 src,
1422 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1423 type,
1424 patch_code,
1425 info, lir_move_volatile));
1426 #else
1427 add(base, offset, base);
1428 append(new LIR_Op1(
1429 lir_move,
1430 src,
1431 LIR_OprFact::address(new LIR_Address(base, 0, type)),
1432 type,
1433 patch_code,
1434 info, lir_move_volatile));
1436 #endif
1438 }
1440 #ifdef MIPS64
1441 void LIR_List::frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1442 append(new LIR_Op3(
1443 lir_frem,
1444 left,
1445 right,
1446 tmp,
1447 res,
1448 info));
1449 }
1450 #endif
1452 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1453 append(new LIR_Op3(
1454 lir_idiv,
1455 left,
1456 right,
1457 tmp,
1458 res,
1459 info));
1460 }
1463 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1464 append(new LIR_Op3(
1465 lir_idiv,
1466 left,
1467 LIR_OprFact::intConst(right),
1468 tmp,
1469 res,
1470 info));
1471 }
1474 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1475 append(new LIR_Op3(
1476 lir_irem,
1477 left,
1478 right,
1479 tmp,
1480 res,
1481 info));
1482 }
1485 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1486 append(new LIR_Op3(
1487 lir_irem,
1488 left,
1489 LIR_OprFact::intConst(right),
1490 tmp,
1491 res,
1492 info));
1493 }
1496 #ifndef MIPS64
1497 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1498 append(new LIR_Op2(
1499 lir_cmp,
1500 condition,
1501 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1502 LIR_OprFact::intConst(c),
1503 info));
1504 }
1507 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1508 append(new LIR_Op2(
1509 lir_cmp,
1510 condition,
1511 reg,
1512 LIR_OprFact::address(addr),
1513 info));
1514 }
1516 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1517 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1518 append(new LIR_OpAllocObj(
1519 klass,
1520 dst,
1521 t1,
1522 t2,
1523 t3,
1524 t4,
1525 header_size,
1526 object_size,
1527 init_check,
1528 stub));
1529 }
1531 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1532 append(new LIR_OpAllocArray(
1533 klass,
1534 len,
1535 dst,
1536 t1,
1537 t2,
1538 t3,
1539 t4,
1540 type,
1541 stub));
1542 }
1543 #else
1544 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, LIR_Opr t5, LIR_Opr t6,
1545 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1546 append(new LIR_OpAllocObj(
1547 klass,
1548 dst,
1549 t1,
1550 t2,
1551 t3,
1552 t4,
1553 t5,
1554 t6,
1555 header_size,
1556 object_size,
1557 init_check,
1558 stub));
1559 }
1560 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, LIR_Opr t5,
1561 BasicType type, LIR_Opr klass, CodeStub* stub) {
1562 append(new LIR_OpAllocArray(
1563 klass,
1564 len,
1565 dst,
1566 t1,
1567 t2,
1568 t3,
1569 t4,
1570 t5,
1571 type,
1572 stub));
1573 }
1575 #endif
1577 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1578 append(new LIR_Op2(
1579 lir_shl,
1580 value,
1581 count,
1582 dst,
1583 tmp));
1584 }
1586 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1587 append(new LIR_Op2(
1588 lir_shr,
1589 value,
1590 count,
1591 dst,
1592 tmp));
1593 }
1596 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1597 append(new LIR_Op2(
1598 lir_ushr,
1599 value,
1600 count,
1601 dst,
1602 tmp));
1603 }
1605 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1606 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1607 left,
1608 right,
1609 dst));
1610 }
1612 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1613 append(new LIR_OpLock(
1614 lir_lock,
1615 hdr,
1616 obj,
1617 lock,
1618 scratch,
1619 stub,
1620 info));
1621 }
1623 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1624 append(new LIR_OpLock(
1625 lir_unlock,
1626 hdr,
1627 obj,
1628 lock,
1629 scratch,
1630 stub,
1631 NULL));
1632 }
1635 void check_LIR() {
1636 // cannot do the proper checking as PRODUCT and other modes return different results
1637 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1638 }
1642 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1643 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1644 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1645 ciMethod* profiled_method, int profiled_bci) {
1646 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1647 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1648 if (profiled_method != NULL) {
1649 c->set_profiled_method(profiled_method);
1650 c->set_profiled_bci(profiled_bci);
1651 c->set_should_profile(true);
1652 }
1653 append(c);
1654 }
1656 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1657 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1658 if (profiled_method != NULL) {
1659 c->set_profiled_method(profiled_method);
1660 c->set_profiled_bci(profiled_bci);
1661 c->set_should_profile(true);
1662 }
1663 append(c);
1664 }
1666 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1667 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1668 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1669 if (profiled_method != NULL) {
1670 c->set_profiled_method(profiled_method);
1671 c->set_profiled_bci(profiled_bci);
1672 c->set_should_profile(true);
1673 }
1674 append(c);
1675 }
1677 #ifndef MIPS64
1678 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1679 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1680 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1681 }
1683 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1684 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1685 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1686 }
1688 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1689 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1690 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1691 }
1692 #else
1693 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1694 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1695 // // implying successful swap of new_value into addr
1696 append(new LIR_OpCompareAndSwap(lir_cas_long,
1697 addr,
1698 cmp_value,
1699 new_value,
1700 t1,
1701 t2,
1702 result));
1703 }
1705 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1706 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1707 // // implying successful swap of new_value into addr
1708 append(new LIR_OpCompareAndSwap(lir_cas_obj,
1709 addr,
1710 cmp_value,
1711 new_value,
1712 t1,
1713 t2,
1714 result));
1715 }
1717 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1718 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1719 // // implying successful swap of new_value into addr
1720 append(new LIR_OpCompareAndSwap(lir_cas_int,
1721 addr,
1722 cmp_value,
1723 new_value,
1724 t1,
1725 t2,
1726 result));
1727 }
1728 #endif
1731 #ifdef PRODUCT
1733 void print_LIR(BlockList* blocks) {
1734 }
1736 #else
1737 // LIR_OprDesc
1738 void LIR_OprDesc::print() const {
1739 print(tty);
1740 }
1742 void LIR_OprDesc::print(outputStream* out) const {
1743 if (is_illegal()) {
1744 return;
1745 }
1747 out->print("[");
1748 if (is_pointer()) {
1749 pointer()->print_value_on(out);
1750 } else if (is_single_stack()) {
1751 out->print("stack:%d", single_stack_ix());
1752 } else if (is_double_stack()) {
1753 out->print("dbl_stack:%d",double_stack_ix());
1754 } else if (is_virtual()) {
1755 out->print("R%d", vreg_number());
1756 } else if (is_single_cpu()) {
1757 out->print("%s", as_register()->name());
1758 } else if (is_double_cpu()) {
1759 out->print("%s", as_register_hi()->name());
1760 out->print("%s", as_register_lo()->name());
1761 #if defined(X86)
1762 } else if (is_single_xmm()) {
1763 out->print("%s", as_xmm_float_reg()->name());
1764 } else if (is_double_xmm()) {
1765 out->print("%s", as_xmm_double_reg()->name());
1766 } else if (is_single_fpu()) {
1767 out->print("fpu%d", fpu_regnr());
1768 } else if (is_double_fpu()) {
1769 out->print("fpu%d", fpu_regnrLo());
1770 #elif defined(ARM)
1771 } else if (is_single_fpu()) {
1772 out->print("s%d", fpu_regnr());
1773 } else if (is_double_fpu()) {
1774 out->print("d%d", fpu_regnrLo() >> 1);
1775 #else
1776 } else if (is_single_fpu()) {
1777 out->print("%s", as_float_reg()->name());
1778 } else if (is_double_fpu()) {
1779 out->print("%s", as_double_reg()->name());
1780 #endif
1782 } else if (is_illegal()) {
1783 out->print("-");
1784 } else {
1785 out->print("Unknown Operand");
1786 }
1787 if (!is_illegal()) {
1788 out->print("|%c", type_char());
1789 }
1790 if (is_register() && is_last_use()) {
1791 out->print("(last_use)");
1792 }
1793 out->print("]");
1794 }
1797 // LIR_Address
1798 void LIR_Const::print_value_on(outputStream* out) const {
1799 switch (type()) {
1800 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1801 case T_INT: out->print("int:%d", as_jint()); break;
1802 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1803 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1804 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1805 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break;
1806 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break;
1807 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break;
1808 }
1809 }
1811 // LIR_Address
1812 void LIR_Address::print_value_on(outputStream* out) const {
1813 out->print("Base:"); _base->print(out);
1814 #ifndef MIPS64
1815 if (!_index->is_illegal()) {
1816 out->print(" Index:"); _index->print(out);
1817 switch (scale()) {
1818 case times_1: break;
1819 case times_2: out->print(" * 2"); break;
1820 case times_4: out->print(" * 4"); break;
1821 case times_8: out->print(" * 8"); break;
1822 }
1823 }
1824 #endif
1825 out->print(" Disp: " INTX_FORMAT, _disp);
1826 }
1828 // debug output of block header without InstructionPrinter
1829 // (because phi functions are not necessary for LIR)
1830 static void print_block(BlockBegin* x) {
1831 // print block id
1832 BlockEnd* end = x->end();
1833 tty->print("B%d ", x->block_id());
1835 // print flags
1836 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1837 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1838 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1839 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1840 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1841 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1842 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1844 // print block bci range
1845 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1847 // print predecessors and successors
1848 if (x->number_of_preds() > 0) {
1849 tty->print("preds: ");
1850 for (int i = 0; i < x->number_of_preds(); i ++) {
1851 tty->print("B%d ", x->pred_at(i)->block_id());
1852 }
1853 }
1855 if (x->number_of_sux() > 0) {
1856 tty->print("sux: ");
1857 for (int i = 0; i < x->number_of_sux(); i ++) {
1858 tty->print("B%d ", x->sux_at(i)->block_id());
1859 }
1860 }
1862 // print exception handlers
1863 if (x->number_of_exception_handlers() > 0) {
1864 tty->print("xhandler: ");
1865 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1866 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1867 }
1868 }
1870 tty->cr();
1871 }
1873 void print_LIR(BlockList* blocks) {
1874 tty->print_cr("LIR:");
1875 int i;
1876 for (i = 0; i < blocks->length(); i++) {
1877 BlockBegin* bb = blocks->at(i);
1878 print_block(bb);
1879 tty->print("__id_Instruction___________________________________________"); tty->cr();
1880 bb->lir()->print_instructions();
1881 }
1882 }
1884 void LIR_List::print_instructions() {
1885 for (int i = 0; i < _operations.length(); i++) {
1886 _operations.at(i)->print(); tty->cr();
1887 }
1888 tty->cr();
1889 }
1891 // LIR_Ops printing routines
1892 // LIR_Op
1893 void LIR_Op::print_on(outputStream* out) const {
1894 if (id() != -1 || PrintCFGToFile) {
1895 out->print("%4d ", id());
1896 } else {
1897 out->print(" ");
1898 }
1899 out->print("%s ", name());
1900 print_instr(out);
1901 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1902 #ifdef ASSERT
1903 if (Verbose && _file != NULL) {
1904 out->print(" (%s:%d)", _file, _line);
1905 }
1906 #endif
1907 }
1909 const char * LIR_Op::name() const {
1910 const char* s = NULL;
1911 switch(code()) {
1912 // LIR_Op0
1913 case lir_membar: s = "membar"; break;
1914 case lir_membar_acquire: s = "membar_acquire"; break;
1915 case lir_membar_release: s = "membar_release"; break;
1916 case lir_membar_loadload: s = "membar_loadload"; break;
1917 case lir_membar_storestore: s = "membar_storestore"; break;
1918 case lir_membar_loadstore: s = "membar_loadstore"; break;
1919 case lir_membar_storeload: s = "membar_storeload"; break;
1920 case lir_word_align: s = "word_align"; break;
1921 case lir_label: s = "label"; break;
1922 case lir_nop: s = "nop"; break;
1923 case lir_backwardbranch_target: s = "backbranch"; break;
1924 case lir_std_entry: s = "std_entry"; break;
1925 case lir_osr_entry: s = "osr_entry"; break;
1926 case lir_build_frame: s = "build_frm"; break;
1927 case lir_fpop_raw: s = "fpop_raw"; break;
1928 case lir_24bit_FPU: s = "24bit_FPU"; break;
1929 case lir_reset_FPU: s = "reset_FPU"; break;
1930 case lir_breakpoint: s = "breakpoint"; break;
1931 case lir_get_thread: s = "get_thread"; break;
1932 // LIR_Op1
1933 case lir_fxch: s = "fxch"; break;
1934 case lir_fld: s = "fld"; break;
1935 case lir_ffree: s = "ffree"; break;
1936 case lir_push: s = "push"; break;
1937 case lir_pop: s = "pop"; break;
1938 case lir_null_check: s = "null_check"; break;
1939 case lir_return: s = "return"; break;
1940 case lir_safepoint: s = "safepoint"; break;
1941 case lir_neg: s = "neg"; break;
1942 case lir_leal: s = "leal"; break;
1943 case lir_branch: s = "branch"; break;
1944 case lir_cond_float_branch: s = "flt_cond_br"; break;
1945 case lir_move: s = "move"; break;
1946 case lir_roundfp: s = "roundfp"; break;
1947 case lir_rtcall: s = "rtcall"; break;
1948 case lir_throw: s = "throw"; break;
1949 case lir_unwind: s = "unwind"; break;
1950 case lir_convert: s = "convert"; break;
1951 case lir_alloc_object: s = "alloc_obj"; break;
1952 case lir_monaddr: s = "mon_addr"; break;
1953 case lir_pack64: s = "pack64"; break;
1954 case lir_unpack64: s = "unpack64"; break;
1955 // LIR_Op2
1956 #ifdef MIPS64
1957 case lir_null_check_for_branch: s = "null_check_for_branch"; break;
1958 #else
1959 case lir_cmp: s = "cmp"; break;
1960 #endif
1961 case lir_cmp_l2i: s = "cmp_l2i"; break;
1962 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1963 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1964 case lir_cmove: s = "cmove"; break;
1965 case lir_add: s = "add"; break;
1966 case lir_sub: s = "sub"; break;
1967 case lir_mul: s = "mul"; break;
1968 case lir_mul_strictfp: s = "mul_strictfp"; break;
1969 case lir_div: s = "div"; break;
1970 case lir_div_strictfp: s = "div_strictfp"; break;
1971 case lir_rem: s = "rem"; break;
1972 case lir_abs: s = "abs"; break;
1973 case lir_sqrt: s = "sqrt"; break;
1974 case lir_sin: s = "sin"; break;
1975 case lir_cos: s = "cos"; break;
1976 case lir_tan: s = "tan"; break;
1977 case lir_log: s = "log"; break;
1978 case lir_log10: s = "log10"; break;
1979 case lir_exp: s = "exp"; break;
1980 case lir_pow: s = "pow"; break;
1981 case lir_logic_and: s = "logic_and"; break;
1982 case lir_logic_or: s = "logic_or"; break;
1983 case lir_logic_xor: s = "logic_xor"; break;
1984 case lir_shl: s = "shift_left"; break;
1985 case lir_shr: s = "shift_right"; break;
1986 case lir_ushr: s = "ushift_right"; break;
1987 case lir_alloc_array: s = "alloc_array"; break;
1988 case lir_xadd: s = "xadd"; break;
1989 case lir_xchg: s = "xchg"; break;
1990 // LIR_Op3
1991 #ifdef MIPS64
1992 case lir_frem: s = "frem"; break;
1993 #endif
1994 case lir_idiv: s = "idiv"; break;
1995 case lir_irem: s = "irem"; break;
1996 // LIR_OpJavaCall
1997 case lir_static_call: s = "static"; break;
1998 case lir_optvirtual_call: s = "optvirtual"; break;
1999 case lir_icvirtual_call: s = "icvirtual"; break;
2000 case lir_virtual_call: s = "virtual"; break;
2001 case lir_dynamic_call: s = "dynamic"; break;
2002 // LIR_OpArrayCopy
2003 case lir_arraycopy: s = "arraycopy"; break;
2004 // LIR_OpUpdateCRC32
2005 case lir_updatecrc32: s = "updatecrc32"; break;
2006 // LIR_OpLock
2007 case lir_lock: s = "lock"; break;
2008 case lir_unlock: s = "unlock"; break;
2009 // LIR_OpDelay
2010 case lir_delay_slot: s = "delay"; break;
2011 // LIR_OpTypeCheck
2012 case lir_instanceof: s = "instanceof"; break;
2013 case lir_checkcast: s = "checkcast"; break;
2014 case lir_store_check: s = "store_check"; break;
2015 // LIR_OpCompareAndSwap
2016 case lir_cas_long: s = "cas_long"; break;
2017 case lir_cas_obj: s = "cas_obj"; break;
2018 case lir_cas_int: s = "cas_int"; break;
2019 // LIR_OpProfileCall
2020 case lir_profile_call: s = "profile_call"; break;
2021 // LIR_OpProfileType
2022 case lir_profile_type: s = "profile_type"; break;
2023 // LIR_OpAssert
2024 #ifdef ASSERT
2025 case lir_assert: s = "assert"; break;
2026 #endif
2027 case lir_none: ShouldNotReachHere();break;
2028 default: s = "illegal_op"; break;
2029 }
2030 return s;
2031 }
2033 // LIR_OpJavaCall
2034 void LIR_OpJavaCall::print_instr(outputStream* out) const {
2035 out->print("call: ");
2036 out->print("[addr: " INTPTR_FORMAT "]", p2i(address()));
2037 if (receiver()->is_valid()) {
2038 out->print(" [recv: "); receiver()->print(out); out->print("]");
2039 }
2040 if (result_opr()->is_valid()) {
2041 out->print(" [result: "); result_opr()->print(out); out->print("]");
2042 }
2043 }
2045 // LIR_OpLabel
2046 void LIR_OpLabel::print_instr(outputStream* out) const {
2047 out->print("[label:" INTPTR_FORMAT "]", p2i(_label));
2048 }
2050 // LIR_OpArrayCopy
2051 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
2052 src()->print(out); out->print(" ");
2053 src_pos()->print(out); out->print(" ");
2054 dst()->print(out); out->print(" ");
2055 dst_pos()->print(out); out->print(" ");
2056 length()->print(out); out->print(" ");
2057 tmp()->print(out); out->print(" ");
2058 }
2060 // LIR_OpUpdateCRC32
2061 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const {
2062 crc()->print(out); out->print(" ");
2063 val()->print(out); out->print(" ");
2064 result_opr()->print(out); out->print(" ");
2065 }
2067 // LIR_OpCompareAndSwap
2068 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
2069 addr()->print(out); out->print(" ");
2070 cmp_value()->print(out); out->print(" ");
2071 new_value()->print(out); out->print(" ");
2072 tmp1()->print(out); out->print(" ");
2073 tmp2()->print(out); out->print(" ");
2075 }
2077 // LIR_Op0
2078 void LIR_Op0::print_instr(outputStream* out) const {
2079 result_opr()->print(out);
2080 }
2082 // LIR_Op1
2083 const char * LIR_Op1::name() const {
2084 if (code() == lir_move) {
2085 switch (move_kind()) {
2086 case lir_move_normal:
2087 return "move";
2088 case lir_move_unaligned:
2089 return "unaligned move";
2090 case lir_move_volatile:
2091 return "volatile_move";
2092 case lir_move_wide:
2093 return "wide_move";
2094 default:
2095 ShouldNotReachHere();
2096 return "illegal_op";
2097 }
2098 } else {
2099 return LIR_Op::name();
2100 }
2101 }
2104 void LIR_Op1::print_instr(outputStream* out) const {
2105 _opr->print(out); out->print(" ");
2106 result_opr()->print(out); out->print(" ");
2107 print_patch_code(out, patch_code());
2108 }
2111 // LIR_Op1
2112 void LIR_OpRTCall::print_instr(outputStream* out) const {
2113 intx a = (intx)addr();
2114 out->print("%s", Runtime1::name_for_address(addr()));
2115 out->print(" ");
2116 tmp()->print(out);
2117 }
2119 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
2120 switch(code) {
2121 case lir_patch_none: break;
2122 case lir_patch_low: out->print("[patch_low]"); break;
2123 case lir_patch_high: out->print("[patch_high]"); break;
2124 case lir_patch_normal: out->print("[patch_normal]"); break;
2125 default: ShouldNotReachHere();
2126 }
2127 }
2129 // LIR_OpBranch
2130 void LIR_OpBranch::print_instr(outputStream* out) const {
2131 print_condition(out, cond()); out->print(" ");
2132 #ifdef MIPS64
2133 in_opr1()->print(out); out->print(" ");
2134 in_opr2()->print(out); out->print(" ");
2135 #endif
2136 if (block() != NULL) {
2137 out->print("[B%d] ", block()->block_id());
2138 } else if (stub() != NULL) {
2139 out->print("[");
2140 stub()->print_name(out);
2141 out->print(": " INTPTR_FORMAT "]", p2i(stub()));
2142 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
2143 } else {
2144 out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
2145 }
2146 if (ublock() != NULL) {
2147 out->print("unordered: [B%d] ", ublock()->block_id());
2148 }
2149 }
2151 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
2152 switch(cond) {
2153 case lir_cond_equal: out->print("[EQ]"); break;
2154 case lir_cond_notEqual: out->print("[NE]"); break;
2155 case lir_cond_less: out->print("[LT]"); break;
2156 case lir_cond_lessEqual: out->print("[LE]"); break;
2157 case lir_cond_greaterEqual: out->print("[GE]"); break;
2158 case lir_cond_greater: out->print("[GT]"); break;
2159 case lir_cond_belowEqual: out->print("[BE]"); break;
2160 case lir_cond_aboveEqual: out->print("[AE]"); break;
2161 case lir_cond_always: out->print("[AL]"); break;
2162 default: out->print("[%d]",cond); break;
2163 }
2164 }
2166 // LIR_OpConvert
2167 void LIR_OpConvert::print_instr(outputStream* out) const {
2168 print_bytecode(out, bytecode());
2169 in_opr()->print(out); out->print(" ");
2170 result_opr()->print(out); out->print(" ");
2171 #ifdef PPC
2172 if(tmp1()->is_valid()) {
2173 tmp1()->print(out); out->print(" ");
2174 tmp2()->print(out); out->print(" ");
2175 }
2176 #endif
2177 }
2179 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
2180 switch(code) {
2181 case Bytecodes::_d2f: out->print("[d2f] "); break;
2182 case Bytecodes::_d2i: out->print("[d2i] "); break;
2183 case Bytecodes::_d2l: out->print("[d2l] "); break;
2184 case Bytecodes::_f2d: out->print("[f2d] "); break;
2185 case Bytecodes::_f2i: out->print("[f2i] "); break;
2186 case Bytecodes::_f2l: out->print("[f2l] "); break;
2187 case Bytecodes::_i2b: out->print("[i2b] "); break;
2188 case Bytecodes::_i2c: out->print("[i2c] "); break;
2189 case Bytecodes::_i2d: out->print("[i2d] "); break;
2190 case Bytecodes::_i2f: out->print("[i2f] "); break;
2191 case Bytecodes::_i2l: out->print("[i2l] "); break;
2192 case Bytecodes::_i2s: out->print("[i2s] "); break;
2193 case Bytecodes::_l2i: out->print("[l2i] "); break;
2194 case Bytecodes::_l2f: out->print("[l2f] "); break;
2195 case Bytecodes::_l2d: out->print("[l2d] "); break;
2196 default:
2197 out->print("[?%d]",code);
2198 break;
2199 }
2200 }
2202 void LIR_OpAllocObj::print_instr(outputStream* out) const {
2203 klass()->print(out); out->print(" ");
2204 obj()->print(out); out->print(" ");
2205 tmp1()->print(out); out->print(" ");
2206 tmp2()->print(out); out->print(" ");
2207 tmp3()->print(out); out->print(" ");
2208 tmp4()->print(out); out->print(" ");
2209 #ifdef MIPS64
2210 tmp5()->print(out); out->print(" ");
2211 tmp6()->print(out); out->print(" ");
2212 #endif
2213 out->print("[hdr:%d]", header_size()); out->print(" ");
2214 out->print("[obj:%d]", object_size()); out->print(" ");
2215 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2216 }
2218 void LIR_OpRoundFP::print_instr(outputStream* out) const {
2219 _opr->print(out); out->print(" ");
2220 tmp()->print(out); out->print(" ");
2221 result_opr()->print(out); out->print(" ");
2222 }
2224 // LIR_Op2
2225 void LIR_Op2::print_instr(outputStream* out) const {
2226 #ifndef MIPS64
2227 if (code() == lir_cmove) {
2228 print_condition(out, condition()); out->print(" ");
2229 }
2230 #endif
2231 in_opr1()->print(out); out->print(" ");
2232 in_opr2()->print(out); out->print(" ");
2233 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
2234 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
2235 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
2236 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
2237 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
2238 result_opr()->print(out);
2239 }
2241 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2242 klass()->print(out); out->print(" ");
2243 len()->print(out); out->print(" ");
2244 obj()->print(out); out->print(" ");
2245 tmp1()->print(out); out->print(" ");
2246 tmp2()->print(out); out->print(" ");
2247 tmp3()->print(out); out->print(" ");
2248 tmp4()->print(out); out->print(" ");
2249 #ifdef MIPS64
2250 tmp5()->print(out); out->print(" ");
2251 #endif
2252 out->print("[type:0x%x]", type()); out->print(" ");
2253 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2254 }
2257 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
2258 object()->print(out); out->print(" ");
2259 if (code() == lir_store_check) {
2260 array()->print(out); out->print(" ");
2261 }
2262 if (code() != lir_store_check) {
2263 klass()->print_name_on(out); out->print(" ");
2264 if (fast_check()) out->print("fast_check ");
2265 }
2266 tmp1()->print(out); out->print(" ");
2267 tmp2()->print(out); out->print(" ");
2268 tmp3()->print(out); out->print(" ");
2269 result_opr()->print(out); out->print(" ");
2270 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2271 }
2274 // LIR_Op3
2275 void LIR_Op3::print_instr(outputStream* out) const {
2276 in_opr1()->print(out); out->print(" ");
2277 in_opr2()->print(out); out->print(" ");
2278 in_opr3()->print(out); out->print(" ");
2279 result_opr()->print(out);
2280 }
2283 void LIR_OpLock::print_instr(outputStream* out) const {
2284 hdr_opr()->print(out); out->print(" ");
2285 obj_opr()->print(out); out->print(" ");
2286 lock_opr()->print(out); out->print(" ");
2287 if (_scratch->is_valid()) {
2288 _scratch->print(out); out->print(" ");
2289 }
2290 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2291 }
2293 #ifdef ASSERT
2294 void LIR_OpAssert::print_instr(outputStream* out) const {
2295 tty->print_cr("function LIR_OpAssert::print_instr unimplemented yet! ");
2296 Unimplemented();
2297 /*
2298 print_condition(out, condition()); out->print(" ");
2299 in_opr1()->print(out); out->print(" ");
2300 in_opr2()->print(out); out->print(", \"");
2301 out->print("%s", msg()); out->print("\"");
2302 */
2303 }
2304 #endif
2307 void LIR_OpDelay::print_instr(outputStream* out) const {
2308 _op->print_on(out);
2309 }
2312 // LIR_OpProfileCall
2313 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2314 profiled_method()->name()->print_symbol_on(out);
2315 out->print(".");
2316 profiled_method()->holder()->name()->print_symbol_on(out);
2317 out->print(" @ %d ", profiled_bci());
2318 mdo()->print(out); out->print(" ");
2319 recv()->print(out); out->print(" ");
2320 tmp1()->print(out); out->print(" ");
2321 }
2323 // LIR_OpProfileType
2324 void LIR_OpProfileType::print_instr(outputStream* out) const {
2325 out->print("exact = "); exact_klass()->print_name_on(out);
2326 out->print("current = "); ciTypeEntries::print_ciklass(out, current_klass());
2327 mdp()->print(out); out->print(" ");
2328 obj()->print(out); out->print(" ");
2329 tmp()->print(out); out->print(" ");
2330 }
2332 #endif // PRODUCT
2334 // Implementation of LIR_InsertionBuffer
2336 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2337 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2339 int i = number_of_insertion_points() - 1;
2340 if (i < 0 || index_at(i) < index) {
2341 append_new(index, 1);
2342 } else {
2343 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2344 assert(count_at(i) > 0, "check");
2345 set_count_at(i, count_at(i) + 1);
2346 }
2347 _ops.push(op);
2349 DEBUG_ONLY(verify());
2350 }
2352 #ifdef ASSERT
2353 void LIR_InsertionBuffer::verify() {
2354 int sum = 0;
2355 int prev_idx = -1;
2357 for (int i = 0; i < number_of_insertion_points(); i++) {
2358 assert(prev_idx < index_at(i), "index must be ordered ascending");
2359 sum += count_at(i);
2360 }
2361 assert(sum == number_of_ops(), "wrong total sum");
2362 }
2363 #endif
