Mercurial > jdk8-mips64-public > hotspot / file comparison
comparison: src/cpu/ppc/vm/assembler_ppc.hpp
src/cpu/ppc/vm/assembler_ppc.hpp
- changeset 9713
- c4567d28f31f
- parent 9687
- 846245a33793
- child 9730
- 42118db355f5
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| 9712:d7e1e002b496 | 9713:c4567d28f31f |
|---|---|
| 1998 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b); | 1998 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b); |
| 1999 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b); | 1999 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b); |
| 2000 inline void vsbox( VectorRegister d, VectorRegister a); | 2000 inline void vsbox( VectorRegister d, VectorRegister a); |
| 2001 | 2001 |
| 2002 // SHA (introduced with Power 8) | 2002 // SHA (introduced with Power 8) |
| 2003 // Not yet implemented. | 2003 inline void vshasigmad(VectorRegister d, VectorRegister a, bool st, int six); |
| 2004 inline void vshasigmaw(VectorRegister d, VectorRegister a, bool st, int six); | |
| 2004 | 2005 |
| 2005 // Vector Binary Polynomial Multiplication (introduced with Power 8) | 2006 // Vector Binary Polynomial Multiplication (introduced with Power 8) |
| 2006 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b); | 2007 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b); |
| 2007 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b); | 2008 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b); |
| 2008 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b); | 2009 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b); |
| 2094 inline void stvx( VectorRegister d, Register s2); | 2095 inline void stvx( VectorRegister d, Register s2); |
| 2095 inline void stvxl( VectorRegister d, Register s2); | 2096 inline void stvxl( VectorRegister d, Register s2); |
| 2096 inline void lvsl( VectorRegister d, Register s2); | 2097 inline void lvsl( VectorRegister d, Register s2); |
| 2097 inline void lvsr( VectorRegister d, Register s2); | 2098 inline void lvsr( VectorRegister d, Register s2); |
| 2098 | 2099 |
| 2100 // Endianess specific concatenation of 2 loaded vectors. | |
| 2101 inline void load_perm(VectorRegister perm, Register addr); | |
| 2102 inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm); | |
| 2103 | |
| 2099 // RegisterOrConstant versions. | 2104 // RegisterOrConstant versions. |
| 2100 // These emitters choose between the versions using two registers and | 2105 // These emitters choose between the versions using two registers and |
| 2101 // those with register and immediate, depending on the content of roc. | 2106 // those with register and immediate, depending on the content of roc. |
| 2102 // If the constant is not encodable as immediate, instructions to | 2107 // If the constant is not encodable as immediate, instructions to |
| 2103 // load the constant are emitted beforehand. Store instructions need a | 2108 // load the constant are emitted beforehand. Store instructions need a |
