2098 inline void lvsr( VectorRegister d, Register s2); |
2098 inline void lvsr( VectorRegister d, Register s2); |
2099 |
2099 |
2100 // Endianess specific concatenation of 2 loaded vectors. |
2100 // Endianess specific concatenation of 2 loaded vectors. |
2101 inline void load_perm(VectorRegister perm, Register addr); |
2101 inline void load_perm(VectorRegister perm, Register addr); |
2102 inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm); |
2102 inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm); |
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2103 inline void vec_perm(VectorRegister dest, VectorRegister first, VectorRegister second, VectorRegister perm); |
2103 |
2104 |
2104 // RegisterOrConstant versions. |
2105 // RegisterOrConstant versions. |
2105 // These emitters choose between the versions using two registers and |
2106 // These emitters choose between the versions using two registers and |
2106 // those with register and immediate, depending on the content of roc. |
2107 // those with register and immediate, depending on the content of roc. |
2107 // If the constant is not encodable as immediate, instructions to |
2108 // If the constant is not encodable as immediate, instructions to |