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src/os_cpu/bsd_x86/vm/bsd_x86_64.ad@f08d439fab8c (annotated)

src/os_cpu/bsd_x86/vm/bsd_x86_64.ad

Sun, 25 Sep 2011 16:03:29 -0700

author

never

date

Sun, 25 Sep 2011 16:03:29 -0700

changeset 3156

f08d439fab8c

child 3577

9b8ce46870df

permissions

-rw-r--r--

7089790: integrate bsd-port changes
Reviewed-by: kvn, twisti, jrose
Contributed-by: Kurt Miller <kurt@intricatesoftware.com>, Greg Lewis <glewis@eyesbeyond.com>, Jung-uk Kim <jkim@freebsd.org>, Christos Zoulas <christos@zoulas.com>, Landon Fuller <landonf@plausible.coop>, The FreeBSD Foundation <board@freebsdfoundation.org>, Michael Franz <mvfranz@gmail.com>, Roger Hoover <rhoover@apple.com>, Alexander Strange <astrange@apple.com>

never@3156	1	//
never@3156	2	// Copyright (c) 2003, 2006, Oracle and/or its affiliates. All rights reserved.
never@3156	3	// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
never@3156	4	//
never@3156	5	// This code is free software; you can redistribute it and/or modify it
never@3156	6	// under the terms of the GNU General Public License version 2 only, as
never@3156	7	// published by the Free Software Foundation.
never@3156	8	//
never@3156	9	// This code is distributed in the hope that it will be useful, but WITHOUT
never@3156	10	// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
never@3156	11	// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
never@3156	12	// version 2 for more details (a copy is included in the LICENSE file that
never@3156	13	// accompanied this code).
never@3156	14	//
never@3156	15	// You should have received a copy of the GNU General Public License version
never@3156	16	// 2 along with this work; if not, write to the Free Software Foundation,
never@3156	17	// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
never@3156	18	//
never@3156	19	// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
never@3156	20	// or visit www.oracle.com if you need additional information or have any
never@3156	21	// questions.
never@3156	22	//
never@3156	23	//
never@3156	24
never@3156	25	// AMD64 Bsd Architecture Description File
never@3156	26
never@3156	27	//----------OS-DEPENDENT ENCODING BLOCK----------------------------------------
never@3156	28	// This block specifies the encoding classes used by the compiler to
never@3156	29	// output byte streams. Encoding classes generate functions which are
never@3156	30	// called by Machine Instruction Nodes in order to generate the bit
never@3156	31	// encoding of the instruction. Operands specify their base encoding
never@3156	32	// interface with the interface keyword. There are currently
never@3156	33	// supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
never@3156	34	// COND_INTER. REG_INTER causes an operand to generate a function
never@3156	35	// which returns its register number when queried. CONST_INTER causes
never@3156	36	// an operand to generate a function which returns the value of the
never@3156	37	// constant when queried. MEMORY_INTER causes an operand to generate
never@3156	38	// four functions which return the Base Register, the Index Register,
never@3156	39	// the Scale Value, and the Offset Value of the operand when queried.
never@3156	40	// COND_INTER causes an operand to generate six functions which return
never@3156	41	// the encoding code (ie - encoding bits for the instruction)
never@3156	42	// associated with each basic boolean condition for a conditional
never@3156	43	// instruction. Instructions specify two basic values for encoding.
never@3156	44	// They use the ins_encode keyword to specify their encoding class
never@3156	45	// (which must be one of the class names specified in the encoding
never@3156	46	// block), and they use the opcode keyword to specify, in order, their
never@3156	47	// primary, secondary, and tertiary opcode. Only the opcode sections
never@3156	48	// which a particular instruction needs for encoding need to be
never@3156	49	// specified.
never@3156	50	encode %{
never@3156	51	// Build emit functions for each basic byte or larger field in the intel
never@3156	52	// encoding scheme (opcode, rm, sib, immediate), and call them from C++
never@3156	53	// code in the enc_class source block. Emit functions will live in the
never@3156	54	// main source block for now. In future, we can generalize this by
never@3156	55	// adding a syntax that specifies the sizes of fields in an order,
never@3156	56	// so that the adlc can build the emit functions automagically
never@3156	57
never@3156	58	enc_class Java_To_Runtime(method meth)
never@3156	59	%{
never@3156	60	// No relocation needed
never@3156	61
never@3156	62	// movq r10, <meth>
never@3156	63	emit_opcode(cbuf, Assembler::REX_WB);
never@3156	64	emit_opcode(cbuf, 0xB8 | (R10_enc - 8));
never@3156	65	emit_d64(cbuf, (int64_t) $meth$$method);
never@3156	66
never@3156	67	// call (r10)
never@3156	68	emit_opcode(cbuf, Assembler::REX_B);
never@3156	69	emit_opcode(cbuf, 0xFF);
never@3156	70	emit_opcode(cbuf, 0xD0 | (R10_enc - 8));
never@3156	71	%}
never@3156	72
never@3156	73	enc_class bsd_breakpoint
never@3156	74	%{
never@3156	75	MacroAssembler* masm = new MacroAssembler(&cbuf);
never@3156	76	masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
never@3156	77	%}
never@3156	78
never@3156	79	enc_class call_epilog
never@3156	80	%{
never@3156	81	if (VerifyStackAtCalls) {
never@3156	82	// Check that stack depth is unchanged: find majik cookie on stack
never@3156	83	int framesize =
never@3156	84	ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
never@3156	85	if (framesize) {
never@3156	86	if (framesize < 0x80) {
never@3156	87	emit_opcode(cbuf, Assembler::REX_W);
never@3156	88	emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood
never@3156	89	emit_d8(cbuf, 0x7C);
never@3156	90	emit_d8(cbuf, 0x24);
never@3156	91	emit_d8(cbuf, framesize); // Find majik cookie from ESP
never@3156	92	emit_d32(cbuf, 0xbadb100d);
never@3156	93	} else {
never@3156	94	emit_opcode(cbuf, Assembler::REX_W);
never@3156	95	emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood
never@3156	96	emit_d8(cbuf, 0xBC);
never@3156	97	emit_d8(cbuf, 0x24);
never@3156	98	emit_d32(cbuf, framesize); // Find majik cookie from ESP
never@3156	99	emit_d32(cbuf, 0xbadb100d);
never@3156	100	}
never@3156	101	}
never@3156	102	// jmp EQ around INT3
never@3156	103	// QQQ TODO
never@3156	104	const int jump_around = 5; // size of call to breakpoint, 1 for CC
never@3156	105	emit_opcode(cbuf, 0x74);
never@3156	106	emit_d8(cbuf, jump_around);
never@3156	107	// QQQ temporary
never@3156	108	emit_break(cbuf);
never@3156	109	// Die if stack mismatch
never@3156	110	// emit_opcode(cbuf,0xCC);
never@3156	111	}
never@3156	112	%}
never@3156	113
never@3156	114	%}
never@3156	115
never@3156	116	// INSTRUCTIONS -- Platform dependent
never@3156	117
never@3156	118	//----------OS and Locking Instructions----------------------------------------
never@3156	119
never@3156	120	// This name is KNOWN by the ADLC and cannot be changed.
never@3156	121	// The ADLC forces a 'TypeRawPtr::BOTTOM' output type
never@3156	122	// for this guy.
never@3156	123	instruct tlsLoadP(r15_RegP dst)
never@3156	124	%{
never@3156	125	match(Set dst (ThreadLocal));
never@3156	126	effect(DEF dst);
never@3156	127
never@3156	128	size(0);
never@3156	129	format %{ "# TLS is in R15" %}
never@3156	130	ins_encode( /*empty encoding*/ );
never@3156	131	ins_pipe(ialu_reg_reg);
never@3156	132	%}
never@3156	133
never@3156	134	// Die now
never@3156	135	instruct ShouldNotReachHere()
never@3156	136	%{
never@3156	137	match(Halt);
never@3156	138
never@3156	139	// Use the following format syntax
never@3156	140	format %{ "int3\t# ShouldNotReachHere" %}
never@3156	141	// QQQ TODO for now call breakpoint
never@3156	142	// opcode(0xCC);
never@3156	143	// ins_encode(Opc);
never@3156	144	ins_encode(bsd_breakpoint);
never@3156	145	ins_pipe(pipe_slow);
never@3156	146	%}
never@3156	147
never@3156	148
never@3156	149	// Platform dependent source
never@3156	150
never@3156	151	source
never@3156	152	%{
never@3156	153
never@3156	154	int MachCallRuntimeNode::ret_addr_offset() {
never@3156	155	return 13; // movq r10,#addr; callq (r10)
never@3156	156	}
never@3156	157
never@3156	158	// emit an interrupt that is caught by the debugger
never@3156	159	void emit_break(CodeBuffer& cbuf) {
never@3156	160	// Debugger doesn't really catch this but best we can do so far QQQ
never@3156	161	MacroAssembler* masm = new MacroAssembler(&cbuf);
never@3156	162	masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
never@3156	163	}
never@3156	164
never@3156	165	void MachBreakpointNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
never@3156	166	emit_break(cbuf);
never@3156	167	}
never@3156	168
never@3156	169	uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
never@3156	170	return 5;
never@3156	171	}
never@3156	172
never@3156	173	%}