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1 // |
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2 // Copyright (c) 2003, 2006, Oracle and/or its affiliates. All rights reserved. |
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3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 // |
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5 // This code is free software; you can redistribute it and/or modify it |
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6 // under the terms of the GNU General Public License version 2 only, as |
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7 // published by the Free Software Foundation. |
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8 // |
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9 // This code is distributed in the hope that it will be useful, but WITHOUT |
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10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 // version 2 for more details (a copy is included in the LICENSE file that |
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13 // accompanied this code). |
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14 // |
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15 // You should have received a copy of the GNU General Public License version |
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16 // 2 along with this work; if not, write to the Free Software Foundation, |
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17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 // |
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
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22 // |
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23 // |
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24 |
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25 // AMD64 Bsd Architecture Description File |
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26 |
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27 //----------OS-DEPENDENT ENCODING BLOCK---------------------------------------- |
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28 // This block specifies the encoding classes used by the compiler to |
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29 // output byte streams. Encoding classes generate functions which are |
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30 // called by Machine Instruction Nodes in order to generate the bit |
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31 // encoding of the instruction. Operands specify their base encoding |
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32 // interface with the interface keyword. There are currently |
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33 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, & |
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34 // COND_INTER. REG_INTER causes an operand to generate a function |
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35 // which returns its register number when queried. CONST_INTER causes |
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36 // an operand to generate a function which returns the value of the |
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37 // constant when queried. MEMORY_INTER causes an operand to generate |
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38 // four functions which return the Base Register, the Index Register, |
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39 // the Scale Value, and the Offset Value of the operand when queried. |
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40 // COND_INTER causes an operand to generate six functions which return |
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41 // the encoding code (ie - encoding bits for the instruction) |
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42 // associated with each basic boolean condition for a conditional |
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43 // instruction. Instructions specify two basic values for encoding. |
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44 // They use the ins_encode keyword to specify their encoding class |
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45 // (which must be one of the class names specified in the encoding |
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46 // block), and they use the opcode keyword to specify, in order, their |
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47 // primary, secondary, and tertiary opcode. Only the opcode sections |
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48 // which a particular instruction needs for encoding need to be |
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49 // specified. |
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50 encode %{ |
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51 // Build emit functions for each basic byte or larger field in the intel |
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52 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ |
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53 // code in the enc_class source block. Emit functions will live in the |
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54 // main source block for now. In future, we can generalize this by |
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55 // adding a syntax that specifies the sizes of fields in an order, |
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56 // so that the adlc can build the emit functions automagically |
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57 |
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58 enc_class Java_To_Runtime(method meth) |
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59 %{ |
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60 // No relocation needed |
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61 |
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62 // movq r10, <meth> |
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63 emit_opcode(cbuf, Assembler::REX_WB); |
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64 emit_opcode(cbuf, 0xB8 | (R10_enc - 8)); |
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65 emit_d64(cbuf, (int64_t) $meth$$method); |
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66 |
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67 // call (r10) |
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68 emit_opcode(cbuf, Assembler::REX_B); |
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69 emit_opcode(cbuf, 0xFF); |
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70 emit_opcode(cbuf, 0xD0 | (R10_enc - 8)); |
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71 %} |
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72 |
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73 enc_class bsd_breakpoint |
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74 %{ |
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75 MacroAssembler* masm = new MacroAssembler(&cbuf); |
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76 masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); |
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77 %} |
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78 |
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79 enc_class call_epilog |
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80 %{ |
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81 if (VerifyStackAtCalls) { |
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82 // Check that stack depth is unchanged: find majik cookie on stack |
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83 int framesize = |
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84 ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word)); |
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85 if (framesize) { |
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86 if (framesize < 0x80) { |
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87 emit_opcode(cbuf, Assembler::REX_W); |
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88 emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood |
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89 emit_d8(cbuf, 0x7C); |
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90 emit_d8(cbuf, 0x24); |
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91 emit_d8(cbuf, framesize); // Find majik cookie from ESP |
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92 emit_d32(cbuf, 0xbadb100d); |
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93 } else { |
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94 emit_opcode(cbuf, Assembler::REX_W); |
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95 emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood |
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96 emit_d8(cbuf, 0xBC); |
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97 emit_d8(cbuf, 0x24); |
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98 emit_d32(cbuf, framesize); // Find majik cookie from ESP |
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99 emit_d32(cbuf, 0xbadb100d); |
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100 } |
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101 } |
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102 // jmp EQ around INT3 |
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103 // QQQ TODO |
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104 const int jump_around = 5; // size of call to breakpoint, 1 for CC |
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105 emit_opcode(cbuf, 0x74); |
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106 emit_d8(cbuf, jump_around); |
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107 // QQQ temporary |
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108 emit_break(cbuf); |
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109 // Die if stack mismatch |
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110 // emit_opcode(cbuf,0xCC); |
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111 } |
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112 %} |
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113 |
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114 %} |
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115 |
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116 // INSTRUCTIONS -- Platform dependent |
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117 |
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118 //----------OS and Locking Instructions---------------------------------------- |
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119 |
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120 // This name is KNOWN by the ADLC and cannot be changed. |
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121 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type |
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122 // for this guy. |
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123 instruct tlsLoadP(r15_RegP dst) |
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124 %{ |
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125 match(Set dst (ThreadLocal)); |
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126 effect(DEF dst); |
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127 |
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128 size(0); |
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129 format %{ "# TLS is in R15" %} |
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130 ins_encode( /*empty encoding*/ ); |
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131 ins_pipe(ialu_reg_reg); |
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132 %} |
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133 |
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134 // Die now |
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135 instruct ShouldNotReachHere() |
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136 %{ |
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137 match(Halt); |
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138 |
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139 // Use the following format syntax |
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140 format %{ "int3\t# ShouldNotReachHere" %} |
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141 // QQQ TODO for now call breakpoint |
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142 // opcode(0xCC); |
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143 // ins_encode(Opc); |
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144 ins_encode(bsd_breakpoint); |
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145 ins_pipe(pipe_slow); |
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146 %} |
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147 |
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148 |
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149 // Platform dependent source |
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150 |
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151 source |
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152 %{ |
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153 |
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154 int MachCallRuntimeNode::ret_addr_offset() { |
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155 return 13; // movq r10,#addr; callq (r10) |
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156 } |
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157 |
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158 // emit an interrupt that is caught by the debugger |
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159 void emit_break(CodeBuffer& cbuf) { |
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160 // Debugger doesn't really catch this but best we can do so far QQQ |
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161 MacroAssembler* masm = new MacroAssembler(&cbuf); |
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162 masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); |
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163 } |
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164 |
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165 void MachBreakpointNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
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166 emit_break(cbuf); |
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167 } |
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168 |
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169 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const { |
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170 return 5; |
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171 } |
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172 |
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173 %} |