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src/cpu/mips/vm/templateTable_mips_64.hpp@d885f8d65c58 (annotated)
src/cpu/mips/vm/templateTable_mips_64.hpp
Tue, 26 Jul 2016 17:06:17 +0800
- author
- fujie
- date
- Tue, 26 Jul 2016 17:06:17 +0800
- changeset 41
- d885f8d65c58
- parent 1
- 2d8a650513c2
- child 6880
- 52ea28d233d2
- permissions
- -rw-r--r--
Add multiply word to GPR instruction (mul) in MIPS assembler.
| aoqi@1 | 1 | /* |
| aoqi@1 | 2 | * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. |
| aoqi@1 | 3 | * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. |
| aoqi@1 | 4 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| aoqi@1 | 5 | * |
| aoqi@1 | 6 | * This code is free software; you can redistribute it and/or modify it |
| aoqi@1 | 7 | * under the terms of the GNU General Public License version 2 only, as |
| aoqi@1 | 8 | * published by the Free Software Foundation. |
| aoqi@1 | 9 | * |
| aoqi@1 | 10 | * This code is distributed in the hope that it will be useful, but WITHOUT |
| aoqi@1 | 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| aoqi@1 | 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| aoqi@1 | 13 | * version 2 for more details (a copy is included in the LICENSE file that |
| aoqi@1 | 14 | * accompanied this code). |
| aoqi@1 | 15 | * |
| aoqi@1 | 16 | * You should have received a copy of the GNU General Public License version |
| aoqi@1 | 17 | * 2 along with this work; if not, write to the Free Software Foundation, |
| aoqi@1 | 18 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
| aoqi@1 | 19 | * |
| aoqi@1 | 20 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| aoqi@1 | 21 | * or visit www.oracle.com if you need additional information or have any |
| aoqi@1 | 22 | * questions. |
| aoqi@1 | 23 | * |
| aoqi@1 | 24 | */ |
| aoqi@1 | 25 | |
| aoqi@1 | 26 | #ifndef CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP |
| aoqi@1 | 27 | #define CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP |
| aoqi@1 | 28 | static void prepare_invoke(int byte_no, Register method, Register index = noreg, Register recv = noreg, |
| aoqi@1 | 29 | Register flags = noreg); |
| aoqi@1 | 30 | static void invokevirtual_helper(Register index, Register recv, |
| aoqi@1 | 31 | Register flags); |
| aoqi@1 | 32 | //static void volatile_barrier(Assembler::Membar_mask_bits order_constraint); |
| aoqi@1 | 33 | static void volatile_barrier(); |
| aoqi@1 | 34 | |
| aoqi@1 | 35 | // Helpers |
| aoqi@1 | 36 | static void index_check(Register array, Register index); |
| aoqi@1 | 37 | static void index_check_without_pop(Register array, Register index); |
| aoqi@1 | 38 | |
| aoqi@1 | 39 | #endif // CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP |
| aoqi@1 | 40 |
