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src/share/vm/c1/c1_LIRAssembler.hpp@b92c45f2bc75 (annotated)

src/share/vm/c1/c1_LIRAssembler.hpp

Wed, 02 Feb 2011 11:35:26 -0500

author
bobv
date
Wed, 02 Feb 2011 11:35:26 -0500
changeset 2508
b92c45f2bc75
parent 2412
037c727f35fb
child 2708
1d1603768966
permissions
-rw-r--r--

7016023: Enable building ARM and PPC from src/closed repository
Reviewed-by: dholmes, bdelsart

duke@435 1 /*
trims@1907 2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
duke@435 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435 4 *
duke@435 5 * This code is free software; you can redistribute it and/or modify it
duke@435 6 * under the terms of the GNU General Public License version 2 only, as
duke@435 7 * published by the Free Software Foundation.
duke@435 8 *
duke@435 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@435 13 * accompanied this code).
duke@435 14 *
duke@435 15 * You should have received a copy of the GNU General Public License version
duke@435 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@435 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435 18 *
trims@1907 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907 20 * or visit www.oracle.com if you need additional information or have any
trims@1907 21 * questions.
duke@435 22 *
duke@435 23 */
duke@435 24
stefank@2314 25 #ifndef SHARE_VM_C1_C1_LIRASSEMBLER_HPP
stefank@2314 26 #define SHARE_VM_C1_C1_LIRASSEMBLER_HPP
stefank@2314 27
stefank@2314 28 #include "c1/c1_CodeStubs.hpp"
stefank@2314 29 #include "ci/ciMethodData.hpp"
stefank@2314 30 #include "oops/methodDataOop.hpp"
stefank@2314 31 #include "utilities/top.hpp"
stefank@2314 32
duke@435 33 class Compilation;
duke@435 34 class ScopeValue;
ysr@777 35 class BarrierSet;
duke@435 36
duke@435 37 class LIR_Assembler: public CompilationResourceObj {
duke@435 38 private:
duke@435 39 C1_MacroAssembler* _masm;
duke@435 40 CodeStubList* _slow_case_stubs;
ysr@777 41 BarrierSet* _bs;
duke@435 42
duke@435 43 Compilation* _compilation;
duke@435 44 FrameMap* _frame_map;
duke@435 45 BlockBegin* _current_block;
duke@435 46
duke@435 47 Instruction* _pending_non_safepoint;
duke@435 48 int _pending_non_safepoint_offset;
duke@435 49
never@1813 50 Label _unwind_handler_entry;
never@1813 51
duke@435 52 #ifdef ASSERT
duke@435 53 BlockList _branch_target_blocks;
duke@435 54 void check_no_unbound_labels();
duke@435 55 #endif
duke@435 56
duke@435 57 FrameMap* frame_map() const { return _frame_map; }
duke@435 58
duke@435 59 void set_current_block(BlockBegin* b) { _current_block = b; }
duke@435 60 BlockBegin* current_block() const { return _current_block; }
duke@435 61
duke@435 62 // non-safepoint debug info management
duke@435 63 void flush_debug_info(int before_pc_offset) {
duke@435 64 if (_pending_non_safepoint != NULL) {
duke@435 65 if (_pending_non_safepoint_offset < before_pc_offset)
duke@435 66 record_non_safepoint_debug_info();
duke@435 67 _pending_non_safepoint = NULL;
duke@435 68 }
duke@435 69 }
duke@435 70 void process_debug_info(LIR_Op* op);
duke@435 71 void record_non_safepoint_debug_info();
duke@435 72
duke@435 73 // unified bailout support
duke@435 74 void bailout(const char* msg) const { compilation()->bailout(msg); }
duke@435 75 bool bailed_out() const { return compilation()->bailed_out(); }
duke@435 76
duke@435 77 // code emission patterns and accessors
duke@435 78 void check_codespace();
duke@435 79 bool needs_icache(ciMethod* method) const;
duke@435 80
duke@435 81 // returns offset of icache check
duke@435 82 int check_icache();
duke@435 83
duke@435 84 void jobject2reg(jobject o, Register reg);
duke@435 85 void jobject2reg_with_patching(Register reg, CodeEmitInfo* info);
duke@435 86
duke@435 87 void emit_stubs(CodeStubList* stub_list);
duke@435 88
duke@435 89 // addresses
never@739 90 Address as_Address(LIR_Address* addr);
never@739 91 Address as_Address_lo(LIR_Address* addr);
never@739 92 Address as_Address_hi(LIR_Address* addr);
duke@435 93
duke@435 94 // debug information
twisti@1919 95 void add_call_info(int pc_offset, CodeEmitInfo* cinfo);
duke@435 96 void add_debug_info_for_branch(CodeEmitInfo* info);
duke@435 97 void add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo);
duke@435 98 void add_debug_info_for_div0_here(CodeEmitInfo* info);
duke@435 99 void add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo);
duke@435 100 void add_debug_info_for_null_check_here(CodeEmitInfo* info);
duke@435 101
duke@435 102 void set_24bit_FPU();
duke@435 103 void reset_FPU();
duke@435 104 void fpop();
duke@435 105 void fxch(int i);
duke@435 106 void fld(int i);
duke@435 107 void ffree(int i);
duke@435 108
duke@435 109 void breakpoint();
duke@435 110 void push(LIR_Opr opr);
duke@435 111 void pop(LIR_Opr opr);
duke@435 112
duke@435 113 // patching
duke@435 114 void append_patching_stub(PatchingStub* stub);
duke@435 115 void patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info);
duke@435 116
duke@435 117 void comp_op(LIR_Condition condition, LIR_Opr src, LIR_Opr result, LIR_Op2* op);
duke@435 118
duke@435 119 public:
duke@435 120 LIR_Assembler(Compilation* c);
duke@435 121 ~LIR_Assembler();
duke@435 122 C1_MacroAssembler* masm() const { return _masm; }
duke@435 123 Compilation* compilation() const { return _compilation; }
duke@435 124 ciMethod* method() const { return compilation()->method(); }
duke@435 125
duke@435 126 CodeOffsets* offsets() const { return _compilation->offsets(); }
duke@435 127 int code_offset() const;
duke@435 128 address pc() const;
duke@435 129
duke@435 130 int initial_frame_size_in_bytes();
duke@435 131
duke@435 132 // test for constants which can be encoded directly in instructions
duke@435 133 static bool is_small_constant(LIR_Opr opr);
duke@435 134
duke@435 135 static LIR_Opr receiverOpr();
duke@435 136 static LIR_Opr incomingReceiverOpr();
duke@435 137 static LIR_Opr osrBufferPointer();
duke@435 138
duke@435 139 // stubs
duke@435 140 void emit_slow_case_stubs();
duke@435 141 void emit_static_call_stub();
duke@435 142 void emit_code_stub(CodeStub* op);
duke@435 143 void add_call_info_here(CodeEmitInfo* info) { add_call_info(code_offset(), info); }
duke@435 144
duke@435 145 // code patterns
twisti@1639 146 int emit_exception_handler();
never@1813 147 int emit_unwind_handler();
duke@435 148 void emit_exception_entries(ExceptionInfoList* info_list);
twisti@1639 149 int emit_deopt_handler();
duke@435 150
duke@435 151 void emit_code(BlockList* hir);
duke@435 152 void emit_block(BlockBegin* block);
duke@435 153 void emit_lir_list(LIR_List* list);
duke@435 154
duke@435 155 // any last minute peephole optimizations are performed here. In
duke@435 156 // particular sparc uses this for delay slot filling.
duke@435 157 void peephole(LIR_List* list);
duke@435 158
duke@435 159 void emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info);
duke@435 160
duke@435 161 void return_op(LIR_Opr result);
duke@435 162
duke@435 163 // returns offset of poll instruction
duke@435 164 int safepoint_poll(LIR_Opr result, CodeEmitInfo* info);
duke@435 165
duke@435 166 void const2reg (LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info);
duke@435 167 void const2stack(LIR_Opr src, LIR_Opr dest);
iveresov@2344 168 void const2mem (LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide);
duke@435 169 void reg2stack (LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack);
duke@435 170 void reg2reg (LIR_Opr src, LIR_Opr dest);
iveresov@2344 171 void reg2mem (LIR_Opr src, LIR_Opr dest, BasicType type,
iveresov@2344 172 LIR_PatchCode patch_code, CodeEmitInfo* info,
iveresov@2344 173 bool pop_fpu_stack, bool wide, bool unaligned);
duke@435 174 void stack2reg (LIR_Opr src, LIR_Opr dest, BasicType type);
duke@435 175 void stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type);
duke@435 176 void mem2reg (LIR_Opr src, LIR_Opr dest, BasicType type,
iveresov@2344 177 LIR_PatchCode patch_code,
iveresov@2344 178 CodeEmitInfo* info, bool wide, bool unaligned);
duke@435 179
duke@435 180 void prefetchr (LIR_Opr src);
duke@435 181 void prefetchw (LIR_Opr src);
duke@435 182
duke@435 183 void shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp);
duke@435 184 void shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest);
duke@435 185
duke@435 186 void move_regs(Register from_reg, Register to_reg);
duke@435 187 void swap_reg(Register a, Register b);
duke@435 188
duke@435 189 void emit_op0(LIR_Op0* op);
duke@435 190 void emit_op1(LIR_Op1* op);
duke@435 191 void emit_op2(LIR_Op2* op);
duke@435 192 void emit_op3(LIR_Op3* op);
duke@435 193 void emit_opBranch(LIR_OpBranch* op);
duke@435 194 void emit_opLabel(LIR_OpLabel* op);
duke@435 195 void emit_arraycopy(LIR_OpArrayCopy* op);
duke@435 196 void emit_opConvert(LIR_OpConvert* op);
duke@435 197 void emit_alloc_obj(LIR_OpAllocObj* op);
duke@435 198 void emit_alloc_array(LIR_OpAllocArray* op);
duke@435 199 void emit_opTypeCheck(LIR_OpTypeCheck* op);
iveresov@2146 200 void emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null);
duke@435 201 void emit_compare_and_swap(LIR_OpCompareAndSwap* op);
duke@435 202 void emit_lock(LIR_OpLock* op);
duke@435 203 void emit_call(LIR_OpJavaCall* op);
duke@435 204 void emit_rtcall(LIR_OpRTCall* op);
duke@435 205 void emit_profile_call(LIR_OpProfileCall* op);
duke@435 206 void emit_delay(LIR_OpDelay* op);
duke@435 207
duke@435 208 void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack);
duke@435 209 void arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info);
duke@435 210 void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op);
duke@435 211
duke@435 212 void logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest);
duke@435 213
duke@435 214 void roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack);
duke@435 215 void move_op(LIR_Opr src, LIR_Opr result, BasicType type,
iveresov@2344 216 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide);
duke@435 217 void volatile_move_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info);
duke@435 218 void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions
duke@435 219 void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op);
iveresov@2412 220 void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result, BasicType type);
duke@435 221
twisti@1730 222 void call( LIR_OpJavaCall* op, relocInfo::relocType rtype);
twisti@1730 223 void ic_call( LIR_OpJavaCall* op);
twisti@1730 224 void vtable_call( LIR_OpJavaCall* op);
twisti@1730 225
duke@435 226 void osr_entry();
duke@435 227
duke@435 228 void build_frame();
duke@435 229
never@1813 230 void throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info);
never@1813 231 void unwind_op(LIR_Opr exceptionOop);
duke@435 232 void monitor_address(int monitor_ix, LIR_Opr dst);
duke@435 233
duke@435 234 void align_backward_branch_target();
duke@435 235 void align_call(LIR_Code code);
duke@435 236
duke@435 237 void negate(LIR_Opr left, LIR_Opr dest);
duke@435 238 void leal(LIR_Opr left, LIR_Opr dest);
duke@435 239
duke@435 240 void rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info);
duke@435 241
duke@435 242 void membar();
duke@435 243 void membar_acquire();
duke@435 244 void membar_release();
duke@435 245 void get_thread(LIR_Opr result);
duke@435 246
duke@435 247 void verify_oop_map(CodeEmitInfo* info);
duke@435 248
stefank@2314 249 #ifdef TARGET_ARCH_x86
stefank@2314 250 # include "c1_LIRAssembler_x86.hpp"
stefank@2314 251 #endif
stefank@2314 252 #ifdef TARGET_ARCH_sparc
stefank@2314 253 # include "c1_LIRAssembler_sparc.hpp"
stefank@2314 254 #endif
bobv@2508 255 #ifdef TARGET_ARCH_arm
bobv@2508 256 # include "c1_LIRAssembler_arm.hpp"
bobv@2508 257 #endif
bobv@2508 258 #ifdef TARGET_ARCH_ppc
bobv@2508 259 # include "c1_LIRAssembler_ppc.hpp"
bobv@2508 260 #endif
stefank@2314 261
duke@435 262 };
stefank@2314 263
stefank@2314 264 #endif // SHARE_VM_C1_C1_LIRASSEMBLER_HPP

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