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src/cpu/mips/vm/disassembler_mips.hpp@b4f2008f15f8 (annotated)
src/cpu/mips/vm/disassembler_mips.hpp
Fri, 04 Nov 2016 16:16:16 +0800
- author
- aoqi
- date
- Fri, 04 Nov 2016 16:16:16 +0800
- changeset 130
- b4f2008f15f8
- parent 1
- 2d8a650513c2
- child 433
- bd82ffa08941
- permissions
- -rw-r--r--
Disassembler::decode can be used in product version, therefore Instructions part in JVM crash logs can be shown in disassembly form which is readable.
The Instructions part in a JVM crash log would be like:
Instructions: (pc=0x000000ffece332f8)
0x000000ffece332b8: 08 00 e0 03 00 00 00 00 f0 ff bd 67 08 00 be ff
0x000000ffece332c8: 2d f0 a0 03 08 00 02 24 2d e8 c0 03 08 00 be df
0x000000ffece332d8: 10 00 bd 67 08 00 e0 03 00 00 00 00 e0 ff bd 67
0x000000ffece332e8: 18 00 be ff 2d f0 a0 03 00 00 c4 ff 00 00 c2 df
0x000000ffece332f8: 0c 00 42 8c 2d e8 c0 03 18 00 be df 20 00 bd 67
0x000000ffece33308: 08 00 e0 03 00 00 00 00 e0 ff bd 67 18 00 be ff
0x000000ffece33318: 2d f0 a0 03 2d 10 80 00 00 10 02 00 00 00 c2 af
0x000000ffece33328: 00 00 c2 8f 00 c0 03 3c 2b 10 43 00 01 00 42 38-
0x000000ffece332a8: sd a0, 0x0(fp)
0x000000ffece332ac: daddu sp, fp, zero
0x000000ffece332b0: ld fp, 0x18(sp)
0x000000ffece332b4: daddiu sp, sp, 0x20
0x000000ffece332b8: jr ra
0x000000ffece332bc: nop
0x000000ffece332c0: daddiu sp, sp, 0xfffffff0
0x000000ffece332c4: sd fp, 0x8(sp)
0x000000ffece332c8: daddu fp, sp, zero
0x000000ffece332cc: addiu v0, zero, 0x8
0x000000ffece332d0: daddu sp, fp, zero
0x000000ffece332d4: ld fp, 0x8(sp)
0x000000ffece332d8: daddiu sp, sp, 0x10
0x000000ffece332dc: jr ra
0x000000ffece332e0: nop
0x000000ffece332e4: daddiu sp, sp, 0xffffffe0
0x000000ffece332e8: sd fp, 0x18(sp)
0x000000ffece332ec: daddu fp, sp, zero
0x000000ffece332f0: sd a0, 0x0(fp)
0x000000ffece332f4: ld v0, 0x0(fp)
0x000000ffece332f8: lw v0, 0xc(v0)
0x000000ffece332fc: daddu sp, fp, zero
0x000000ffece33300: ld fp, 0x18(sp)
0x000000ffece33304: daddiu sp, sp, 0x20
0x000000ffece33308: jr ra
0x000000ffece3330c: nop
0x000000ffece33310: daddiu sp, sp, 0xffffffe0
0x000000ffece33314: sd fp, 0x18(sp)
0x000000ffece33318: daddu fp, sp, zero
0x000000ffece3331c: daddu v0, a0, zero
0x000000ffece33320: sll v0, v0, 0
0x000000ffece33324: sw v0, 0x0(fp)
0x000000ffece33328: lw v0, 0x0(fp)
0x000000ffece3332c: lui v1, 0xffffc000
0x000000ffece33330: sltu v0, v0, v1
0x000000ffece33334: xori v0, v0, 0x1
0x000000ffece33338: andi v0, v0, 0xff
0x000000ffece3333c: daddu sp, fp, zero
0x000000ffece33340: ld fp, 0x18(sp)
0x000000ffece33344: daddiu sp, sp, 0x20
| aoqi@1 | 1 | /* |
| aoqi@1 | 2 | * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
| aoqi@1 | 3 | * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. |
| aoqi@1 | 4 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| aoqi@1 | 5 | * |
| aoqi@1 | 6 | * This code is free software; you can redistribute it and/or modify it |
| aoqi@1 | 7 | * under the terms of the GNU General Public License version 2 only, as |
| aoqi@1 | 8 | * published by the Free Software Foundation. |
| aoqi@1 | 9 | * |
| aoqi@1 | 10 | * This code is distributed in the hope that it will be useful, but WITHOUT |
| aoqi@1 | 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| aoqi@1 | 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| aoqi@1 | 13 | * version 2 for more details (a copy is included in the LICENSE file that |
| aoqi@1 | 14 | * accompanied this code). |
| aoqi@1 | 15 | * |
| aoqi@1 | 16 | * You should have received a copy of the GNU General Public License version |
| aoqi@1 | 17 | * 2 along with this work; if not, write to the Free Software Foundation, |
| aoqi@1 | 18 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
| aoqi@1 | 19 | * |
| aoqi@1 | 20 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| aoqi@1 | 21 | * or visit www.oracle.com if you need additional information or have any |
| aoqi@1 | 22 | * questions. |
| aoqi@1 | 23 | * |
| aoqi@1 | 24 | */ |
| aoqi@1 | 25 | |
| aoqi@1 | 26 | #ifndef CPU_MIPS_VM_DISASSEMBLER_MIPS_HPP |
| aoqi@1 | 27 | #define CPU_MIPS_VM_DISASSEMBLER_MIPS_HPP |
| aoqi@1 | 28 | |
| aoqi@1 | 29 | #ifdef USE_PRAGMA_IDENT_HDR |
| aoqi@1 | 30 | #pragma ident "@(#)disassembler_mips.hpp 1.16 03/12/23 16:36:15 JVM" |
| aoqi@1 | 31 | #endif |
| aoqi@1 | 32 | |
| aoqi@1 | 33 | // The disassembler prints out mips32 code annotated |
| aoqi@1 | 34 | // with Java specific information. |
| aoqi@1 | 35 | |
| aoqi@1 | 36 | class Disassembler { |
| aoqi@1 | 37 | private: |
| aoqi@1 | 38 | // decodes one instruction and return the start of the next instruction. |
| aoqi@1 | 39 | static address decode_instruction(address start, DisassemblerEnv* env); |
| aoqi@1 | 40 | public: |
| aoqi@1 | 41 | static bool can_decode() { |
| aoqi@1 | 42 | //return (_decode_instructions != NULL) || load_library(); |
| aoqi@1 | 43 | return true; |
| aoqi@1 | 44 | } |
| aoqi@130 | 45 | static void decode(CodeBlob *cb, outputStream* st = NULL); |
| aoqi@130 | 46 | static void decode(nmethod* nm, outputStream* st = NULL); |
| aoqi@130 | 47 | static void decode(u_char* begin, u_char* end, outputStream* st = NULL); |
| aoqi@1 | 48 | }; |
| aoqi@1 | 49 | |
| aoqi@1 | 50 | #endif // CPU_MIPS_VM_DISASSEMBLER_MIPS_HPP |
| aoqi@1 | 51 |
