src/cpu/mips/vm/disassembler_mips.hpp

Fri, 04 Nov 2016 16:16:16 +0800

author
aoqi
date
Fri, 04 Nov 2016 16:16:16 +0800
changeset 130
b4f2008f15f8
parent 1
2d8a650513c2
child 433
bd82ffa08941
permissions
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Disassembler::decode can be used in product version, therefore Instructions part in JVM crash logs can be shown in disassembly form which is readable.

The Instructions part in a JVM crash log would be like:
Instructions: (pc=0x000000ffece332f8)
0x000000ffece332b8: 08 00 e0 03 00 00 00 00 f0 ff bd 67 08 00 be ff
0x000000ffece332c8: 2d f0 a0 03 08 00 02 24 2d e8 c0 03 08 00 be df
0x000000ffece332d8: 10 00 bd 67 08 00 e0 03 00 00 00 00 e0 ff bd 67
0x000000ffece332e8: 18 00 be ff 2d f0 a0 03 00 00 c4 ff 00 00 c2 df
0x000000ffece332f8: 0c 00 42 8c 2d e8 c0 03 18 00 be df 20 00 bd 67
0x000000ffece33308: 08 00 e0 03 00 00 00 00 e0 ff bd 67 18 00 be ff
0x000000ffece33318: 2d f0 a0 03 2d 10 80 00 00 10 02 00 00 00 c2 af
0x000000ffece33328: 00 00 c2 8f 00 c0 03 3c 2b 10 43 00 01 00 42 38-
0x000000ffece332a8: sd a0, 0x0(fp)
0x000000ffece332ac: daddu sp, fp, zero
0x000000ffece332b0: ld fp, 0x18(sp)
0x000000ffece332b4: daddiu sp, sp, 0x20
0x000000ffece332b8: jr ra
0x000000ffece332bc: nop
0x000000ffece332c0: daddiu sp, sp, 0xfffffff0
0x000000ffece332c4: sd fp, 0x8(sp)
0x000000ffece332c8: daddu fp, sp, zero
0x000000ffece332cc: addiu v0, zero, 0x8
0x000000ffece332d0: daddu sp, fp, zero
0x000000ffece332d4: ld fp, 0x8(sp)
0x000000ffece332d8: daddiu sp, sp, 0x10
0x000000ffece332dc: jr ra
0x000000ffece332e0: nop
0x000000ffece332e4: daddiu sp, sp, 0xffffffe0
0x000000ffece332e8: sd fp, 0x18(sp)
0x000000ffece332ec: daddu fp, sp, zero
0x000000ffece332f0: sd a0, 0x0(fp)
0x000000ffece332f4: ld v0, 0x0(fp)
0x000000ffece332f8: lw v0, 0xc(v0)
0x000000ffece332fc: daddu sp, fp, zero
0x000000ffece33300: ld fp, 0x18(sp)
0x000000ffece33304: daddiu sp, sp, 0x20
0x000000ffece33308: jr ra
0x000000ffece3330c: nop
0x000000ffece33310: daddiu sp, sp, 0xffffffe0
0x000000ffece33314: sd fp, 0x18(sp)
0x000000ffece33318: daddu fp, sp, zero
0x000000ffece3331c: daddu v0, a0, zero
0x000000ffece33320: sll v0, v0, 0
0x000000ffece33324: sw v0, 0x0(fp)
0x000000ffece33328: lw v0, 0x0(fp)
0x000000ffece3332c: lui v1, 0xffffc000
0x000000ffece33330: sltu v0, v0, v1
0x000000ffece33334: xori v0, v0, 0x1
0x000000ffece33338: andi v0, v0, 0xff
0x000000ffece3333c: daddu sp, fp, zero
0x000000ffece33340: ld fp, 0x18(sp)
0x000000ffece33344: daddiu sp, sp, 0x20

     1 /*
     2  * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
     3  * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
     4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     5  *
     6  * This code is free software; you can redistribute it and/or modify it
     7  * under the terms of the GNU General Public License version 2 only, as
     8  * published by the Free Software Foundation.
     9  *
    10  * This code is distributed in the hope that it will be useful, but WITHOUT
    11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    13  * version 2 for more details (a copy is included in the LICENSE file that
    14  * accompanied this code).
    15  *
    16  * You should have received a copy of the GNU General Public License version
    17  * 2 along with this work; if not, write to the Free Software Foundation,
    18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
    19  *
    20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
    21  * or visit www.oracle.com if you need additional information or have any
    22  * questions.
    23  *
    24  */
    26 #ifndef CPU_MIPS_VM_DISASSEMBLER_MIPS_HPP
    27 #define CPU_MIPS_VM_DISASSEMBLER_MIPS_HPP
    29 #ifdef USE_PRAGMA_IDENT_HDR
    30 #pragma ident "@(#)disassembler_mips.hpp	1.16 03/12/23 16:36:15 JVM"
    31 #endif
    33 // The disassembler prints out mips32 code annotated
    34 // with Java specific information.
    36 class Disassembler {
    37  private:
    38   // decodes one instruction and return the start of the next instruction.
    39   static address decode_instruction(address start, DisassemblerEnv* env);
    40  public:
    41   static bool can_decode() {
    42     //return (_decode_instructions != NULL) || load_library();
    43     return true;
    44   }
    45   static void decode(CodeBlob *cb,               outputStream* st = NULL);
    46   static void decode(nmethod* nm,                outputStream* st = NULL);
    47   static void decode(u_char* begin, u_char* end, outputStream* st = NULL);
    48 };
    50 #endif // CPU_MIPS_VM_DISASSEMBLER_MIPS_HPP

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