Tue, 08 Aug 2017 15:57:29 +0800
merge
aoqi@0 | 1 | /* |
aoqi@0 | 2 | * Copyright (c) 2005, 2012, Oracle and/or its affiliates. All rights reserved. |
aoqi@0 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
aoqi@0 | 4 | * |
aoqi@0 | 5 | * This code is free software; you can redistribute it and/or modify it |
aoqi@0 | 6 | * under the terms of the GNU General Public License version 2 only, as |
aoqi@0 | 7 | * published by the Free Software Foundation. |
aoqi@0 | 8 | * |
aoqi@0 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
aoqi@0 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
aoqi@0 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
aoqi@0 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
aoqi@0 | 13 | * accompanied this code). |
aoqi@0 | 14 | * |
aoqi@0 | 15 | * You should have received a copy of the GNU General Public License version |
aoqi@0 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
aoqi@0 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
aoqi@0 | 18 | * |
aoqi@0 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
aoqi@0 | 20 | * or visit www.oracle.com if you need additional information or have any |
aoqi@0 | 21 | * questions. |
aoqi@0 | 22 | * |
aoqi@0 | 23 | */ |
aoqi@0 | 24 | |
aoqi@1 | 25 | /* |
aoqi@1 | 26 | * This file has been modified by Loongson Technology in 2015. These |
aoqi@1 | 27 | * modifications are Copyright (c) 2015 Loongson Technology, and are made |
aoqi@1 | 28 | * available on the same license terms set forth above. |
aoqi@1 | 29 | */ |
aoqi@1 | 30 | |
aoqi@0 | 31 | #ifndef SHARE_VM_C1_C1_LINEARSCAN_HPP |
aoqi@0 | 32 | #define SHARE_VM_C1_C1_LINEARSCAN_HPP |
aoqi@0 | 33 | |
aoqi@0 | 34 | #include "c1/c1_FpuStackSim.hpp" |
aoqi@0 | 35 | #include "c1/c1_FrameMap.hpp" |
aoqi@0 | 36 | #include "c1/c1_IR.hpp" |
aoqi@0 | 37 | #include "c1/c1_Instruction.hpp" |
aoqi@0 | 38 | #include "c1/c1_LIR.hpp" |
aoqi@0 | 39 | #include "c1/c1_LIRGenerator.hpp" |
aoqi@0 | 40 | |
aoqi@0 | 41 | class DebugInfoCache; |
aoqi@0 | 42 | class FpuStackAllocator; |
aoqi@0 | 43 | class IRScopeDebugInfo; |
aoqi@0 | 44 | class Interval; |
aoqi@0 | 45 | class IntervalWalker; |
aoqi@0 | 46 | class LIRGenerator; |
aoqi@0 | 47 | class LinearScan; |
aoqi@0 | 48 | class MoveResolver; |
aoqi@0 | 49 | class Range; |
aoqi@0 | 50 | |
aoqi@0 | 51 | define_array(IntervalArray, Interval*) |
aoqi@0 | 52 | define_stack(IntervalList, IntervalArray) |
aoqi@0 | 53 | |
aoqi@0 | 54 | define_array(IntervalsArray, IntervalList*) |
aoqi@0 | 55 | define_stack(IntervalsList, IntervalsArray) |
aoqi@0 | 56 | |
aoqi@0 | 57 | define_array(OopMapArray, OopMap*) |
aoqi@0 | 58 | define_stack(OopMapList, OopMapArray) |
aoqi@0 | 59 | |
aoqi@0 | 60 | define_array(ScopeValueArray, ScopeValue*) |
aoqi@0 | 61 | |
aoqi@0 | 62 | define_array(LIR_OpListArray, LIR_OpList*); |
aoqi@0 | 63 | define_stack(LIR_OpListStack, LIR_OpListArray); |
aoqi@0 | 64 | |
aoqi@0 | 65 | |
aoqi@0 | 66 | enum IntervalUseKind { |
aoqi@0 | 67 | // priority of use kinds must be ascending |
aoqi@0 | 68 | noUse = 0, |
aoqi@0 | 69 | loopEndMarker = 1, |
aoqi@0 | 70 | shouldHaveRegister = 2, |
aoqi@0 | 71 | mustHaveRegister = 3, |
aoqi@0 | 72 | |
aoqi@0 | 73 | firstValidKind = 1, |
aoqi@0 | 74 | lastValidKind = 3 |
aoqi@0 | 75 | }; |
aoqi@0 | 76 | define_array(UseKindArray, IntervalUseKind) |
aoqi@0 | 77 | define_stack(UseKindStack, UseKindArray) |
aoqi@0 | 78 | |
aoqi@0 | 79 | |
aoqi@0 | 80 | enum IntervalKind { |
aoqi@0 | 81 | fixedKind = 0, // interval pre-colored by LIR_Generator |
aoqi@0 | 82 | anyKind = 1, // no register/memory allocated by LIR_Generator |
aoqi@0 | 83 | nofKinds, |
aoqi@0 | 84 | firstKind = fixedKind |
aoqi@0 | 85 | }; |
aoqi@0 | 86 | |
aoqi@0 | 87 | |
aoqi@0 | 88 | // during linear scan an interval is in one of four states in |
aoqi@0 | 89 | enum IntervalState { |
aoqi@0 | 90 | unhandledState = 0, // unhandled state (not processed yet) |
aoqi@0 | 91 | activeState = 1, // life and is in a physical register |
aoqi@0 | 92 | inactiveState = 2, // in a life time hole and is in a physical register |
aoqi@0 | 93 | handledState = 3, // spilled or not life again |
aoqi@0 | 94 | invalidState = -1 |
aoqi@0 | 95 | }; |
aoqi@0 | 96 | |
aoqi@0 | 97 | |
aoqi@0 | 98 | enum IntervalSpillState { |
aoqi@0 | 99 | noDefinitionFound, // starting state of calculation: no definition found yet |
aoqi@0 | 100 | oneDefinitionFound, // one definition has already been found. |
aoqi@0 | 101 | // Note: two consecutive definitions are treated as one (e.g. consecutive move and add because of two-operand LIR form) |
aoqi@0 | 102 | // the position of this definition is stored in _definition_pos |
aoqi@0 | 103 | oneMoveInserted, // one spill move has already been inserted. |
aoqi@0 | 104 | storeAtDefinition, // the interval should be stored immediately after its definition because otherwise |
aoqi@0 | 105 | // there would be multiple redundant stores |
aoqi@0 | 106 | startInMemory, // the interval starts in memory (e.g. method parameter), so a store is never necessary |
aoqi@0 | 107 | noOptimization // the interval has more then one definition (e.g. resulting from phi moves), so stores to memory are not optimized |
aoqi@0 | 108 | }; |
aoqi@0 | 109 | |
aoqi@0 | 110 | |
aoqi@0 | 111 | #define for_each_interval_kind(kind) \ |
aoqi@0 | 112 | for (IntervalKind kind = firstKind; kind < nofKinds; kind = (IntervalKind)(kind + 1)) |
aoqi@0 | 113 | |
aoqi@0 | 114 | #define for_each_visitor_mode(mode) \ |
aoqi@0 | 115 | for (LIR_OpVisitState::OprMode mode = LIR_OpVisitState::firstMode; mode < LIR_OpVisitState::numModes; mode = (LIR_OpVisitState::OprMode)(mode + 1)) |
aoqi@0 | 116 | |
aoqi@0 | 117 | |
aoqi@0 | 118 | class LinearScan : public CompilationResourceObj { |
aoqi@0 | 119 | // declare classes used by LinearScan as friends because they |
aoqi@0 | 120 | // need a wide variety of functions declared here |
aoqi@0 | 121 | // |
aoqi@0 | 122 | // Only the small interface to the rest of the compiler is public |
aoqi@0 | 123 | friend class Interval; |
aoqi@0 | 124 | friend class IntervalWalker; |
aoqi@0 | 125 | friend class LinearScanWalker; |
aoqi@0 | 126 | friend class FpuStackAllocator; |
aoqi@0 | 127 | friend class MoveResolver; |
aoqi@0 | 128 | friend class LinearScanStatistic; |
aoqi@0 | 129 | friend class LinearScanTimers; |
aoqi@0 | 130 | friend class RegisterVerifier; |
aoqi@0 | 131 | |
aoqi@0 | 132 | public: |
aoqi@0 | 133 | enum { |
aoqi@0 | 134 | any_reg = -1, |
aoqi@0 | 135 | nof_cpu_regs = pd_nof_cpu_regs_linearscan, |
aoqi@0 | 136 | nof_fpu_regs = pd_nof_fpu_regs_linearscan, |
aoqi@0 | 137 | nof_xmm_regs = pd_nof_xmm_regs_linearscan, |
aoqi@0 | 138 | nof_regs = nof_cpu_regs + nof_fpu_regs + nof_xmm_regs |
aoqi@0 | 139 | }; |
aoqi@0 | 140 | |
aoqi@0 | 141 | private: |
aoqi@0 | 142 | Compilation* _compilation; |
aoqi@0 | 143 | IR* _ir; |
aoqi@0 | 144 | LIRGenerator* _gen; |
aoqi@0 | 145 | FrameMap* _frame_map; |
aoqi@0 | 146 | |
aoqi@0 | 147 | BlockList _cached_blocks; // cached list with all blocks in linear-scan order (only correct if original list keeps unchanged) |
aoqi@0 | 148 | int _num_virtual_regs; // number of virtual registers (without new registers introduced because of splitting intervals) |
aoqi@0 | 149 | bool _has_fpu_registers; // true if this method uses any floating point registers (and so fpu stack allocation is necessary) |
aoqi@0 | 150 | int _num_calls; // total number of calls in this method |
aoqi@0 | 151 | int _max_spills; // number of stack slots used for intervals allocated to memory |
aoqi@0 | 152 | int _unused_spill_slot; // unused spill slot for a single-word value because of alignment of a double-word value |
aoqi@0 | 153 | |
aoqi@0 | 154 | IntervalList _intervals; // mapping from register number to interval |
aoqi@0 | 155 | IntervalList* _new_intervals_from_allocation; // list with all intervals created during allocation when an existing interval is split |
aoqi@0 | 156 | IntervalArray* _sorted_intervals; // intervals sorted by Interval::from() |
aoqi@0 | 157 | bool _needs_full_resort; // set to true if an Interval::from() is changed and _sorted_intervals must be resorted |
aoqi@0 | 158 | |
aoqi@0 | 159 | LIR_OpArray _lir_ops; // mapping from LIR_Op id to LIR_Op node |
aoqi@0 | 160 | BlockBeginArray _block_of_op; // mapping from LIR_Op id to the BlockBegin containing this instruction |
aoqi@0 | 161 | BitMap _has_info; // bit set for each LIR_Op id that has a CodeEmitInfo |
aoqi@0 | 162 | BitMap _has_call; // bit set for each LIR_Op id that destroys all caller save registers |
aoqi@0 | 163 | BitMap2D _interval_in_loop; // bit set for each virtual register that is contained in each loop |
aoqi@0 | 164 | |
aoqi@0 | 165 | // cached debug info to prevent multiple creation of same object |
aoqi@0 | 166 | // TODO: cached scope values for registers could be static |
aoqi@0 | 167 | ScopeValueArray _scope_value_cache; |
aoqi@0 | 168 | |
aoqi@0 | 169 | static ConstantOopWriteValue* _oop_null_scope_value; |
aoqi@0 | 170 | static ConstantIntValue* _int_m1_scope_value; |
aoqi@0 | 171 | static ConstantIntValue* _int_0_scope_value; |
aoqi@0 | 172 | static ConstantIntValue* _int_1_scope_value; |
aoqi@0 | 173 | static ConstantIntValue* _int_2_scope_value; |
aoqi@0 | 174 | |
aoqi@0 | 175 | // accessors |
aoqi@0 | 176 | IR* ir() const { return _ir; } |
aoqi@0 | 177 | Compilation* compilation() const { return _compilation; } |
aoqi@0 | 178 | LIRGenerator* gen() const { return _gen; } |
aoqi@0 | 179 | FrameMap* frame_map() const { return _frame_map; } |
aoqi@0 | 180 | |
aoqi@0 | 181 | // unified bailout support |
aoqi@0 | 182 | void bailout(const char* msg) const { compilation()->bailout(msg); } |
aoqi@0 | 183 | bool bailed_out() const { return compilation()->bailed_out(); } |
aoqi@0 | 184 | |
aoqi@0 | 185 | // access to block list (sorted in linear scan order) |
aoqi@0 | 186 | int block_count() const { assert(_cached_blocks.length() == ir()->linear_scan_order()->length(), "invalid cached block list"); return _cached_blocks.length(); } |
aoqi@0 | 187 | BlockBegin* block_at(int idx) const { assert(_cached_blocks.at(idx) == ir()->linear_scan_order()->at(idx), "invalid cached block list"); return _cached_blocks.at(idx); } |
aoqi@0 | 188 | |
aoqi@0 | 189 | int num_virtual_regs() const { return _num_virtual_regs; } |
aoqi@0 | 190 | // size of live_in and live_out sets of BasicBlocks (BitMap needs rounded size for iteration) |
aoqi@0 | 191 | int live_set_size() const { return round_to(_num_virtual_regs, BitsPerWord); } |
aoqi@0 | 192 | bool has_fpu_registers() const { return _has_fpu_registers; } |
aoqi@0 | 193 | int num_loops() const { return ir()->num_loops(); } |
aoqi@0 | 194 | bool is_interval_in_loop(int interval, int loop) const { return _interval_in_loop.at(interval, loop); } |
aoqi@0 | 195 | |
aoqi@0 | 196 | // handling of fpu stack allocation (platform dependent, needed for debug information generation) |
aoqi@0 | 197 | #ifdef X86 |
aoqi@0 | 198 | FpuStackAllocator* _fpu_stack_allocator; |
aoqi@0 | 199 | bool use_fpu_stack_allocation() const { return UseSSE < 2 && has_fpu_registers(); } |
aoqi@0 | 200 | #else |
aoqi@0 | 201 | bool use_fpu_stack_allocation() const { return false; } |
aoqi@0 | 202 | #endif |
aoqi@0 | 203 | |
aoqi@0 | 204 | |
aoqi@0 | 205 | // access to interval list |
aoqi@0 | 206 | int interval_count() const { return _intervals.length(); } |
aoqi@0 | 207 | Interval* interval_at(int reg_num) const { return _intervals.at(reg_num); } |
aoqi@0 | 208 | |
aoqi@0 | 209 | IntervalList* new_intervals_from_allocation() const { return _new_intervals_from_allocation; } |
aoqi@0 | 210 | |
aoqi@0 | 211 | // access to LIR_Ops and Blocks indexed by op_id |
aoqi@0 | 212 | int max_lir_op_id() const { assert(_lir_ops.length() > 0, "no operations"); return (_lir_ops.length() - 1) << 1; } |
aoqi@0 | 213 | LIR_Op* lir_op_with_id(int op_id) const { assert(op_id >= 0 && op_id <= max_lir_op_id() && op_id % 2 == 0, "op_id out of range or not even"); return _lir_ops.at(op_id >> 1); } |
aoqi@0 | 214 | BlockBegin* block_of_op_with_id(int op_id) const { assert(_block_of_op.length() > 0 && op_id >= 0 && op_id <= max_lir_op_id() + 1, "op_id out of range"); return _block_of_op.at(op_id >> 1); } |
aoqi@0 | 215 | |
aoqi@0 | 216 | bool is_block_begin(int op_id) { return op_id == 0 || block_of_op_with_id(op_id) != block_of_op_with_id(op_id - 1); } |
aoqi@0 | 217 | bool covers_block_begin(int op_id_1, int op_id_2) { return block_of_op_with_id(op_id_1) != block_of_op_with_id(op_id_2); } |
aoqi@0 | 218 | |
aoqi@0 | 219 | bool has_call(int op_id) { assert(op_id % 2 == 0, "must be even"); return _has_call.at(op_id >> 1); } |
aoqi@0 | 220 | bool has_info(int op_id) { assert(op_id % 2 == 0, "must be even"); return _has_info.at(op_id >> 1); } |
aoqi@0 | 221 | |
aoqi@0 | 222 | |
aoqi@0 | 223 | // functions for converting LIR-Operands to register numbers |
aoqi@0 | 224 | static bool is_valid_reg_num(int reg_num) { return reg_num >= 0; } |
aoqi@0 | 225 | static int reg_num(LIR_Opr opr); |
aoqi@0 | 226 | static int reg_numHi(LIR_Opr opr); |
aoqi@0 | 227 | |
aoqi@0 | 228 | // functions for classification of intervals |
aoqi@0 | 229 | static bool is_precolored_interval(const Interval* i); |
aoqi@0 | 230 | static bool is_virtual_interval(const Interval* i); |
aoqi@0 | 231 | |
aoqi@0 | 232 | static bool is_precolored_cpu_interval(const Interval* i); |
aoqi@0 | 233 | static bool is_virtual_cpu_interval(const Interval* i); |
aoqi@0 | 234 | static bool is_precolored_fpu_interval(const Interval* i); |
aoqi@0 | 235 | static bool is_virtual_fpu_interval(const Interval* i); |
aoqi@0 | 236 | |
aoqi@0 | 237 | static bool is_in_fpu_register(const Interval* i); |
aoqi@0 | 238 | static bool is_oop_interval(const Interval* i); |
aoqi@0 | 239 | |
aoqi@0 | 240 | |
aoqi@0 | 241 | // General helper functions |
aoqi@0 | 242 | int allocate_spill_slot(bool double_word); |
aoqi@0 | 243 | void assign_spill_slot(Interval* it); |
aoqi@0 | 244 | void propagate_spill_slots(); |
aoqi@0 | 245 | |
aoqi@0 | 246 | Interval* create_interval(int reg_num); |
aoqi@0 | 247 | void append_interval(Interval* it); |
aoqi@0 | 248 | void copy_register_flags(Interval* from, Interval* to); |
aoqi@0 | 249 | |
aoqi@0 | 250 | // platform dependent functions |
aoqi@0 | 251 | static bool is_processed_reg_num(int reg_num); |
aoqi@0 | 252 | static int num_physical_regs(BasicType type); |
aoqi@0 | 253 | static bool requires_adjacent_regs(BasicType type); |
aoqi@0 | 254 | static bool is_caller_save(int assigned_reg); |
aoqi@0 | 255 | |
aoqi@0 | 256 | // spill move optimization: eliminate moves from register to stack if |
aoqi@0 | 257 | // stack slot is known to be correct |
aoqi@0 | 258 | void change_spill_definition_pos(Interval* interval, int def_pos); |
aoqi@0 | 259 | void change_spill_state(Interval* interval, int spill_pos); |
aoqi@0 | 260 | static bool must_store_at_definition(const Interval* i); |
aoqi@0 | 261 | void eliminate_spill_moves(); |
aoqi@0 | 262 | |
aoqi@0 | 263 | // Phase 1: number all instructions in all blocks |
aoqi@0 | 264 | void number_instructions(); |
aoqi@0 | 265 | |
aoqi@0 | 266 | // Phase 2: compute local live sets separately for each block |
aoqi@0 | 267 | // (sets live_gen and live_kill for each block) |
aoqi@0 | 268 | // |
aoqi@0 | 269 | // helper methods used by compute_local_live_sets() |
aoqi@0 | 270 | void set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill); |
aoqi@0 | 271 | |
aoqi@0 | 272 | void compute_local_live_sets(); |
aoqi@0 | 273 | |
aoqi@0 | 274 | // Phase 3: perform a backward dataflow analysis to compute global live sets |
aoqi@0 | 275 | // (sets live_in and live_out for each block) |
aoqi@0 | 276 | void compute_global_live_sets(); |
aoqi@0 | 277 | |
aoqi@0 | 278 | |
aoqi@0 | 279 | // Phase 4: build intervals |
aoqi@0 | 280 | // (fills the list _intervals) |
aoqi@0 | 281 | // |
aoqi@0 | 282 | // helper methods used by build_intervals() |
aoqi@0 | 283 | void add_use (Value value, int from, int to, IntervalUseKind use_kind); |
aoqi@0 | 284 | |
aoqi@0 | 285 | void add_def (LIR_Opr opr, int def_pos, IntervalUseKind use_kind); |
aoqi@0 | 286 | void add_use (LIR_Opr opr, int from, int to, IntervalUseKind use_kind); |
aoqi@0 | 287 | void add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind); |
aoqi@0 | 288 | |
aoqi@0 | 289 | void add_def (int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type); |
aoqi@0 | 290 | void add_use (int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type); |
aoqi@0 | 291 | void add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type); |
aoqi@0 | 292 | |
aoqi@0 | 293 | // Add platform dependent kills for particular LIR ops. Can be used |
aoqi@0 | 294 | // to add platform dependent behaviour for some operations. |
aoqi@0 | 295 | void pd_add_temps(LIR_Op* op); |
aoqi@0 | 296 | |
aoqi@0 | 297 | IntervalUseKind use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr); |
aoqi@0 | 298 | IntervalUseKind use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr); |
aoqi@0 | 299 | void handle_method_arguments(LIR_Op* op); |
aoqi@0 | 300 | void handle_doubleword_moves(LIR_Op* op); |
aoqi@0 | 301 | void add_register_hints(LIR_Op* op); |
aoqi@0 | 302 | |
aoqi@0 | 303 | void build_intervals(); |
aoqi@0 | 304 | |
aoqi@0 | 305 | |
aoqi@0 | 306 | // Phase 5: actual register allocation |
aoqi@0 | 307 | // (Uses LinearScanWalker) |
aoqi@0 | 308 | // |
aoqi@0 | 309 | // helper functions for building a sorted list of intervals |
aoqi@0 | 310 | NOT_PRODUCT(bool is_sorted(IntervalArray* intervals);) |
aoqi@0 | 311 | static int interval_cmp(Interval** a, Interval** b); |
aoqi@0 | 312 | void add_to_list(Interval** first, Interval** prev, Interval* interval); |
aoqi@0 | 313 | void create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)); |
aoqi@0 | 314 | |
aoqi@0 | 315 | void sort_intervals_before_allocation(); |
aoqi@0 | 316 | void sort_intervals_after_allocation(); |
aoqi@0 | 317 | void allocate_registers(); |
aoqi@0 | 318 | |
aoqi@0 | 319 | |
aoqi@0 | 320 | // Phase 6: resolve data flow |
aoqi@0 | 321 | // (insert moves at edges between blocks if intervals have been split) |
aoqi@0 | 322 | // |
aoqi@0 | 323 | // helper functions for resolve_data_flow() |
aoqi@0 | 324 | Interval* split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode); |
aoqi@0 | 325 | Interval* interval_at_block_begin(BlockBegin* block, int reg_num); |
aoqi@0 | 326 | Interval* interval_at_block_end(BlockBegin* block, int reg_num); |
aoqi@0 | 327 | Interval* interval_at_op_id(int reg_num, int op_id); |
aoqi@0 | 328 | void resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver); |
aoqi@0 | 329 | void resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver); |
aoqi@0 | 330 | void resolve_data_flow(); |
aoqi@0 | 331 | |
aoqi@0 | 332 | void resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver); |
aoqi@0 | 333 | void resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver); |
aoqi@0 | 334 | void resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver); |
aoqi@0 | 335 | void resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver); |
aoqi@0 | 336 | void resolve_exception_handlers(); |
aoqi@0 | 337 | |
aoqi@0 | 338 | // Phase 7: assign register numbers back to LIR |
aoqi@0 | 339 | // (includes computation of debug information and oop maps) |
aoqi@0 | 340 | // |
aoqi@0 | 341 | // helper functions for assign_reg_num() |
aoqi@0 | 342 | VMReg vm_reg_for_interval(Interval* interval); |
aoqi@0 | 343 | VMReg vm_reg_for_operand(LIR_Opr opr); |
aoqi@0 | 344 | |
aoqi@0 | 345 | static LIR_Opr operand_for_interval(Interval* interval); |
aoqi@0 | 346 | static LIR_Opr calc_operand_for_interval(const Interval* interval); |
aoqi@0 | 347 | LIR_Opr canonical_spill_opr(Interval* interval); |
aoqi@0 | 348 | |
aoqi@0 | 349 | LIR_Opr color_lir_opr(LIR_Opr opr, int id, LIR_OpVisitState::OprMode); |
aoqi@0 | 350 | |
aoqi@0 | 351 | // methods used for oop map computation |
aoqi@0 | 352 | IntervalWalker* init_compute_oop_maps(); |
aoqi@0 | 353 | OopMap* compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site); |
aoqi@0 | 354 | void compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op); |
aoqi@0 | 355 | |
aoqi@0 | 356 | // methods used for debug information computation |
aoqi@0 | 357 | void init_compute_debug_info(); |
aoqi@0 | 358 | |
aoqi@0 | 359 | MonitorValue* location_for_monitor_index(int monitor_index); |
aoqi@0 | 360 | LocationValue* location_for_name(int name, Location::Type loc_type); |
aoqi@0 | 361 | void set_oop(OopMap* map, VMReg name) { |
aoqi@0 | 362 | if (map->legal_vm_reg_name(name)) { |
aoqi@0 | 363 | map->set_oop(name); |
aoqi@0 | 364 | } else { |
aoqi@0 | 365 | bailout("illegal oopMap register name"); |
aoqi@0 | 366 | } |
aoqi@0 | 367 | } |
aoqi@0 | 368 | |
aoqi@0 | 369 | int append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values); |
aoqi@0 | 370 | int append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values); |
aoqi@0 | 371 | int append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values); |
aoqi@0 | 372 | |
aoqi@0 | 373 | IRScopeDebugInfo* compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state); |
aoqi@0 | 374 | void compute_debug_info(CodeEmitInfo* info, int op_id); |
aoqi@0 | 375 | |
aoqi@0 | 376 | void assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw); |
aoqi@0 | 377 | void assign_reg_num(); |
aoqi@0 | 378 | |
aoqi@0 | 379 | |
aoqi@0 | 380 | // Phase 8: fpu stack allocation |
aoqi@0 | 381 | // (Used only on x86 when fpu operands are present) |
aoqi@0 | 382 | void allocate_fpu_stack(); |
aoqi@0 | 383 | |
aoqi@0 | 384 | |
aoqi@0 | 385 | // helper functions for printing state |
aoqi@0 | 386 | #ifndef PRODUCT |
aoqi@0 | 387 | static void print_bitmap(BitMap& bitmap); |
aoqi@0 | 388 | void print_intervals(const char* label); |
aoqi@0 | 389 | void print_lir(int level, const char* label, bool hir_valid = true); |
aoqi@0 | 390 | #endif |
aoqi@0 | 391 | |
aoqi@0 | 392 | #ifdef ASSERT |
aoqi@0 | 393 | // verification functions for allocation |
aoqi@0 | 394 | // (check that all intervals have a correct register and that no registers are overwritten) |
aoqi@0 | 395 | void verify(); |
aoqi@0 | 396 | void verify_intervals(); |
aoqi@0 | 397 | void verify_no_oops_in_fixed_intervals(); |
aoqi@0 | 398 | void verify_constants(); |
aoqi@0 | 399 | void verify_registers(); |
aoqi@0 | 400 | #endif |
aoqi@0 | 401 | |
aoqi@0 | 402 | public: |
aoqi@0 | 403 | // creation |
aoqi@0 | 404 | LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map); |
aoqi@0 | 405 | |
aoqi@0 | 406 | // main entry function: perform linear scan register allocation |
aoqi@0 | 407 | void do_linear_scan(); |
aoqi@0 | 408 | |
aoqi@0 | 409 | // accessors used by Compilation |
aoqi@0 | 410 | int max_spills() const { return _max_spills; } |
aoqi@0 | 411 | int num_calls() const { assert(_num_calls >= 0, "not set"); return _num_calls; } |
aoqi@0 | 412 | |
aoqi@0 | 413 | // entry functions for printing |
aoqi@0 | 414 | #ifndef PRODUCT |
aoqi@0 | 415 | static void print_statistics(); |
aoqi@0 | 416 | static void print_timers(double total); |
aoqi@0 | 417 | #endif |
aoqi@0 | 418 | }; |
aoqi@0 | 419 | |
aoqi@0 | 420 | |
aoqi@0 | 421 | // Helper class for ordering moves that are inserted at the same position in the LIR |
aoqi@0 | 422 | // When moves between registers are inserted, it is important that the moves are |
aoqi@0 | 423 | // ordered such that no register is overwritten. So moves from register to stack |
aoqi@0 | 424 | // are processed prior to moves from stack to register. When moves have circular |
aoqi@0 | 425 | // dependencies, a temporary stack slot is used to break the circle. |
aoqi@0 | 426 | // The same logic is used in the LinearScanWalker and in LinearScan during resolve_data_flow |
aoqi@0 | 427 | // and therefore factored out in a separate class |
aoqi@0 | 428 | class MoveResolver: public StackObj { |
aoqi@0 | 429 | private: |
aoqi@0 | 430 | LinearScan* _allocator; |
aoqi@0 | 431 | |
aoqi@0 | 432 | LIR_List* _insert_list; |
aoqi@0 | 433 | int _insert_idx; |
aoqi@0 | 434 | LIR_InsertionBuffer _insertion_buffer; // buffer where moves are inserted |
aoqi@0 | 435 | |
aoqi@0 | 436 | IntervalList _mapping_from; |
aoqi@0 | 437 | LIR_OprList _mapping_from_opr; |
aoqi@0 | 438 | IntervalList _mapping_to; |
aoqi@0 | 439 | bool _multiple_reads_allowed; |
aoqi@0 | 440 | int _register_blocked[LinearScan::nof_regs]; |
aoqi@0 | 441 | |
aoqi@0 | 442 | int register_blocked(int reg) { assert(reg >= 0 && reg < LinearScan::nof_regs, "out of bounds"); return _register_blocked[reg]; } |
aoqi@0 | 443 | void set_register_blocked(int reg, int direction) { assert(reg >= 0 && reg < LinearScan::nof_regs, "out of bounds"); assert(direction == 1 || direction == -1, "out of bounds"); _register_blocked[reg] += direction; } |
aoqi@0 | 444 | |
aoqi@0 | 445 | void block_registers(Interval* it); |
aoqi@0 | 446 | void unblock_registers(Interval* it); |
aoqi@0 | 447 | bool save_to_process_move(Interval* from, Interval* to); |
aoqi@0 | 448 | |
aoqi@0 | 449 | void create_insertion_buffer(LIR_List* list); |
aoqi@0 | 450 | void append_insertion_buffer(); |
aoqi@0 | 451 | void insert_move(Interval* from_interval, Interval* to_interval); |
aoqi@0 | 452 | void insert_move(LIR_Opr from_opr, Interval* to_interval); |
aoqi@0 | 453 | |
aoqi@0 | 454 | DEBUG_ONLY(void verify_before_resolve();) |
aoqi@0 | 455 | void resolve_mappings(); |
aoqi@0 | 456 | public: |
aoqi@0 | 457 | MoveResolver(LinearScan* allocator); |
aoqi@0 | 458 | |
aoqi@0 | 459 | DEBUG_ONLY(void check_empty();) |
aoqi@0 | 460 | void set_multiple_reads_allowed() { _multiple_reads_allowed = true; } |
aoqi@0 | 461 | void set_insert_position(LIR_List* insert_list, int insert_idx); |
aoqi@0 | 462 | void move_insert_position(LIR_List* insert_list, int insert_idx); |
aoqi@0 | 463 | void add_mapping(Interval* from, Interval* to); |
aoqi@0 | 464 | void add_mapping(LIR_Opr from, Interval* to); |
aoqi@0 | 465 | void resolve_and_append_moves(); |
aoqi@0 | 466 | |
aoqi@0 | 467 | LinearScan* allocator() { return _allocator; } |
aoqi@0 | 468 | bool has_mappings() { return _mapping_from.length() > 0; } |
aoqi@0 | 469 | }; |
aoqi@0 | 470 | |
aoqi@0 | 471 | |
aoqi@0 | 472 | class Range : public CompilationResourceObj { |
aoqi@0 | 473 | friend class Interval; |
aoqi@0 | 474 | |
aoqi@0 | 475 | private: |
aoqi@0 | 476 | static Range* _end; // sentinel (from == to == max_jint) |
aoqi@0 | 477 | |
aoqi@0 | 478 | int _from; // from (inclusive) |
aoqi@0 | 479 | int _to; // to (exclusive) |
aoqi@0 | 480 | Range* _next; // linear list of Ranges |
aoqi@0 | 481 | |
aoqi@0 | 482 | // used only by class Interval, so hide them |
aoqi@0 | 483 | bool intersects(Range* r) const { return intersects_at(r) != -1; } |
aoqi@0 | 484 | int intersects_at(Range* r) const; |
aoqi@0 | 485 | |
aoqi@0 | 486 | public: |
aoqi@0 | 487 | Range(int from, int to, Range* next); |
aoqi@0 | 488 | |
aoqi@0 | 489 | static void initialize(Arena* arena); |
aoqi@0 | 490 | static Range* end() { return _end; } |
aoqi@0 | 491 | |
aoqi@0 | 492 | int from() const { return _from; } |
aoqi@0 | 493 | int to() const { return _to; } |
aoqi@0 | 494 | Range* next() const { return _next; } |
aoqi@0 | 495 | void set_from(int from) { _from = from; } |
aoqi@0 | 496 | void set_to(int to) { _to = to; } |
aoqi@0 | 497 | void set_next(Range* next) { _next = next; } |
aoqi@0 | 498 | |
aoqi@0 | 499 | // for testing |
aoqi@0 | 500 | void print(outputStream* out = tty) const PRODUCT_RETURN; |
aoqi@0 | 501 | }; |
aoqi@0 | 502 | |
aoqi@0 | 503 | |
aoqi@0 | 504 | // Interval is an ordered list of disjoint ranges. |
aoqi@0 | 505 | |
aoqi@0 | 506 | // For pre-colored double word LIR_Oprs, one interval is created for |
aoqi@0 | 507 | // the low word register and one is created for the hi word register. |
aoqi@0 | 508 | // On Intel for FPU double registers only one interval is created. At |
aoqi@0 | 509 | // all times assigned_reg contains the reg. number of the physical |
aoqi@0 | 510 | // register. |
aoqi@0 | 511 | |
aoqi@0 | 512 | // For LIR_Opr in virtual registers a single interval can represent |
aoqi@0 | 513 | // single and double word values. When a physical register is |
aoqi@0 | 514 | // assigned to the interval, assigned_reg contains the |
aoqi@0 | 515 | // phys. reg. number and for double word values assigned_regHi the |
aoqi@0 | 516 | // phys. reg. number of the hi word if there is any. For spilled |
aoqi@0 | 517 | // intervals assigned_reg contains the stack index. assigned_regHi is |
aoqi@0 | 518 | // always -1. |
aoqi@0 | 519 | |
aoqi@0 | 520 | class Interval : public CompilationResourceObj { |
aoqi@0 | 521 | private: |
aoqi@0 | 522 | static Interval* _end; // sentinel (interval with only range Range::end()) |
aoqi@0 | 523 | |
aoqi@0 | 524 | int _reg_num; |
aoqi@0 | 525 | BasicType _type; // valid only for virtual registers |
aoqi@0 | 526 | Range* _first; // sorted list of Ranges |
aoqi@0 | 527 | intStack _use_pos_and_kinds; // sorted list of use-positions and their according use-kinds |
aoqi@0 | 528 | |
aoqi@0 | 529 | Range* _current; // interval iteration: the current Range |
aoqi@0 | 530 | Interval* _next; // interval iteration: sorted list of Intervals (ends with sentinel) |
aoqi@0 | 531 | IntervalState _state; // interval iteration: to which set belongs this interval |
aoqi@0 | 532 | |
aoqi@0 | 533 | |
aoqi@0 | 534 | int _assigned_reg; |
aoqi@0 | 535 | int _assigned_regHi; |
aoqi@0 | 536 | |
aoqi@0 | 537 | int _cached_to; // cached value: to of last range (-1: not cached) |
aoqi@0 | 538 | LIR_Opr _cached_opr; |
aoqi@0 | 539 | VMReg _cached_vm_reg; |
aoqi@0 | 540 | |
aoqi@0 | 541 | Interval* _split_parent; // the original interval where this interval is derived from |
aoqi@0 | 542 | IntervalList _split_children; // list of all intervals that are split off from this interval (only available for split parents) |
aoqi@0 | 543 | Interval* _current_split_child; // the current split child that has been active or inactive last (always stored in split parents) |
aoqi@0 | 544 | |
aoqi@0 | 545 | int _canonical_spill_slot; // the stack slot where all split parts of this interval are spilled to (always stored in split parents) |
aoqi@0 | 546 | bool _insert_move_when_activated; // true if move is inserted between _current_split_child and this interval when interval gets active the first time |
aoqi@0 | 547 | IntervalSpillState _spill_state; // for spill move optimization |
aoqi@0 | 548 | int _spill_definition_pos; // position where the interval is defined (if defined only once) |
aoqi@0 | 549 | Interval* _register_hint; // this interval should be in the same register as the hint interval |
aoqi@0 | 550 | |
aoqi@0 | 551 | int calc_to(); |
aoqi@0 | 552 | Interval* new_split_child(); |
aoqi@0 | 553 | public: |
aoqi@0 | 554 | Interval(int reg_num); |
aoqi@0 | 555 | |
aoqi@0 | 556 | static void initialize(Arena* arena); |
aoqi@0 | 557 | static Interval* end() { return _end; } |
aoqi@0 | 558 | |
aoqi@0 | 559 | // accessors |
aoqi@0 | 560 | int reg_num() const { return _reg_num; } |
aoqi@0 | 561 | void set_reg_num(int r) { assert(_reg_num == -1, "cannot change reg_num"); _reg_num = r; } |
aoqi@0 | 562 | BasicType type() const { assert(_reg_num == -1 || _reg_num >= LIR_OprDesc::vreg_base, "cannot access type for fixed interval"); return _type; } |
aoqi@0 | 563 | void set_type(BasicType type) { assert(_reg_num < LIR_OprDesc::vreg_base || _type == T_ILLEGAL || _type == type, "overwriting existing type"); _type = type; } |
aoqi@0 | 564 | |
aoqi@0 | 565 | Range* first() const { return _first; } |
aoqi@0 | 566 | int from() const { return _first->from(); } |
aoqi@0 | 567 | int to() { if (_cached_to == -1) _cached_to = calc_to(); assert(_cached_to == calc_to(), "invalid cached value"); return _cached_to; } |
aoqi@0 | 568 | int num_use_positions() const { return _use_pos_and_kinds.length() / 2; } |
aoqi@0 | 569 | |
aoqi@0 | 570 | Interval* next() const { return _next; } |
aoqi@0 | 571 | Interval** next_addr() { return &_next; } |
aoqi@0 | 572 | void set_next(Interval* next) { _next = next; } |
aoqi@0 | 573 | |
aoqi@0 | 574 | int assigned_reg() const { return _assigned_reg; } |
aoqi@0 | 575 | int assigned_regHi() const { return _assigned_regHi; } |
aoqi@0 | 576 | void assign_reg(int reg) { _assigned_reg = reg; _assigned_regHi = LinearScan::any_reg; } |
aoqi@0 | 577 | void assign_reg(int reg,int regHi) { _assigned_reg = reg; _assigned_regHi = regHi; } |
aoqi@0 | 578 | |
aoqi@0 | 579 | Interval* register_hint(bool search_split_child = true) const; // calculation needed |
aoqi@0 | 580 | void set_register_hint(Interval* i) { _register_hint = i; } |
aoqi@0 | 581 | |
aoqi@0 | 582 | int state() const { return _state; } |
aoqi@0 | 583 | void set_state(IntervalState s) { _state = s; } |
aoqi@0 | 584 | |
aoqi@0 | 585 | // access to split parent and split children |
aoqi@0 | 586 | bool is_split_parent() const { return _split_parent == this; } |
aoqi@0 | 587 | bool is_split_child() const { return _split_parent != this; } |
aoqi@0 | 588 | Interval* split_parent() const { assert(_split_parent->is_split_parent(), "must be"); return _split_parent; } |
aoqi@0 | 589 | Interval* split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode); |
aoqi@0 | 590 | Interval* split_child_before_op_id(int op_id); |
aoqi@0 | 591 | bool split_child_covers(int op_id, LIR_OpVisitState::OprMode mode); |
aoqi@0 | 592 | DEBUG_ONLY(void check_split_children();) |
aoqi@0 | 593 | |
aoqi@0 | 594 | // information stored in split parent, but available for all children |
aoqi@0 | 595 | int canonical_spill_slot() const { return split_parent()->_canonical_spill_slot; } |
aoqi@0 | 596 | void set_canonical_spill_slot(int slot) { assert(split_parent()->_canonical_spill_slot == -1, "overwriting existing value"); split_parent()->_canonical_spill_slot = slot; } |
aoqi@0 | 597 | Interval* current_split_child() const { return split_parent()->_current_split_child; } |
aoqi@0 | 598 | void make_current_split_child() { split_parent()->_current_split_child = this; } |
aoqi@0 | 599 | |
aoqi@0 | 600 | bool insert_move_when_activated() const { return _insert_move_when_activated; } |
aoqi@0 | 601 | void set_insert_move_when_activated(bool b) { _insert_move_when_activated = b; } |
aoqi@0 | 602 | |
aoqi@0 | 603 | // for spill optimization |
aoqi@0 | 604 | IntervalSpillState spill_state() const { return split_parent()->_spill_state; } |
aoqi@0 | 605 | int spill_definition_pos() const { return split_parent()->_spill_definition_pos; } |
aoqi@0 | 606 | void set_spill_state(IntervalSpillState state) { assert(state >= spill_state(), "state cannot decrease"); split_parent()->_spill_state = state; } |
aoqi@0 | 607 | void set_spill_definition_pos(int pos) { assert(spill_definition_pos() == -1, "cannot set the position twice"); split_parent()->_spill_definition_pos = pos; } |
aoqi@0 | 608 | // returns true if this interval has a shadow copy on the stack that is always correct |
aoqi@0 | 609 | bool always_in_memory() const { return split_parent()->_spill_state == storeAtDefinition || split_parent()->_spill_state == startInMemory; } |
aoqi@0 | 610 | |
aoqi@0 | 611 | // caching of values that take time to compute and are used multiple times |
aoqi@0 | 612 | LIR_Opr cached_opr() const { return _cached_opr; } |
aoqi@0 | 613 | VMReg cached_vm_reg() const { return _cached_vm_reg; } |
aoqi@0 | 614 | void set_cached_opr(LIR_Opr opr) { _cached_opr = opr; } |
aoqi@0 | 615 | void set_cached_vm_reg(VMReg reg) { _cached_vm_reg = reg; } |
aoqi@0 | 616 | |
aoqi@0 | 617 | // access to use positions |
aoqi@0 | 618 | int first_usage(IntervalUseKind min_use_kind) const; // id of the first operation requiring this interval in a register |
aoqi@0 | 619 | int next_usage(IntervalUseKind min_use_kind, int from) const; // id of next usage seen from the given position |
aoqi@0 | 620 | int next_usage_exact(IntervalUseKind exact_use_kind, int from) const; |
aoqi@0 | 621 | int previous_usage(IntervalUseKind min_use_kind, int from) const; |
aoqi@0 | 622 | |
aoqi@0 | 623 | // manipulating intervals |
aoqi@0 | 624 | void add_use_pos(int pos, IntervalUseKind use_kind); |
aoqi@0 | 625 | void add_range(int from, int to); |
aoqi@0 | 626 | Interval* split(int split_pos); |
aoqi@0 | 627 | Interval* split_from_start(int split_pos); |
aoqi@0 | 628 | void remove_first_use_pos() { _use_pos_and_kinds.truncate(_use_pos_and_kinds.length() - 2); } |
aoqi@0 | 629 | |
aoqi@0 | 630 | // test intersection |
aoqi@0 | 631 | bool covers(int op_id, LIR_OpVisitState::OprMode mode) const; |
aoqi@0 | 632 | bool has_hole_between(int from, int to); |
aoqi@0 | 633 | bool intersects(Interval* i) const { return _first->intersects(i->_first); } |
aoqi@0 | 634 | int intersects_at(Interval* i) const { return _first->intersects_at(i->_first); } |
aoqi@0 | 635 | |
aoqi@0 | 636 | // range iteration |
aoqi@0 | 637 | void rewind_range() { _current = _first; } |
aoqi@0 | 638 | void next_range() { assert(this != _end, "not allowed on sentinel"); _current = _current->next(); } |
aoqi@0 | 639 | int current_from() const { return _current->from(); } |
aoqi@0 | 640 | int current_to() const { return _current->to(); } |
aoqi@0 | 641 | bool current_at_end() const { return _current == Range::end(); } |
aoqi@0 | 642 | bool current_intersects(Interval* it) { return _current->intersects(it->_current); }; |
aoqi@0 | 643 | int current_intersects_at(Interval* it) { return _current->intersects_at(it->_current); }; |
aoqi@0 | 644 | |
aoqi@0 | 645 | // printing |
aoqi@0 | 646 | void print(outputStream* out = tty) const PRODUCT_RETURN; |
aoqi@0 | 647 | }; |
aoqi@0 | 648 | |
aoqi@0 | 649 | |
aoqi@0 | 650 | class IntervalWalker : public CompilationResourceObj { |
aoqi@0 | 651 | protected: |
aoqi@0 | 652 | Compilation* _compilation; |
aoqi@0 | 653 | LinearScan* _allocator; |
aoqi@0 | 654 | |
aoqi@0 | 655 | Interval* _unhandled_first[nofKinds]; // sorted list of intervals, not life before the current position |
aoqi@0 | 656 | Interval* _active_first [nofKinds]; // sorted list of intervals, life at the current position |
aoqi@0 | 657 | Interval* _inactive_first [nofKinds]; // sorted list of intervals, intervals in a life time hole at the current position |
aoqi@0 | 658 | |
aoqi@0 | 659 | Interval* _current; // the current interval coming from unhandled list |
aoqi@0 | 660 | int _current_position; // the current position (intercept point through the intervals) |
aoqi@0 | 661 | IntervalKind _current_kind; // and whether it is fixed_kind or any_kind. |
aoqi@0 | 662 | |
aoqi@0 | 663 | |
aoqi@0 | 664 | Compilation* compilation() const { return _compilation; } |
aoqi@0 | 665 | LinearScan* allocator() const { return _allocator; } |
aoqi@0 | 666 | |
aoqi@0 | 667 | // unified bailout support |
aoqi@0 | 668 | void bailout(const char* msg) const { compilation()->bailout(msg); } |
aoqi@0 | 669 | bool bailed_out() const { return compilation()->bailed_out(); } |
aoqi@0 | 670 | |
aoqi@0 | 671 | void check_bounds(IntervalKind kind) { assert(kind >= fixedKind && kind <= anyKind, "invalid interval_kind"); } |
aoqi@0 | 672 | |
aoqi@0 | 673 | Interval** unhandled_first_addr(IntervalKind kind) { check_bounds(kind); return &_unhandled_first[kind]; } |
aoqi@0 | 674 | Interval** active_first_addr(IntervalKind kind) { check_bounds(kind); return &_active_first[kind]; } |
aoqi@0 | 675 | Interval** inactive_first_addr(IntervalKind kind) { check_bounds(kind); return &_inactive_first[kind]; } |
aoqi@0 | 676 | |
aoqi@0 | 677 | void append_unsorted(Interval** first, Interval* interval); |
aoqi@0 | 678 | void append_sorted(Interval** first, Interval* interval); |
aoqi@0 | 679 | void append_to_unhandled(Interval** list, Interval* interval); |
aoqi@0 | 680 | |
aoqi@0 | 681 | bool remove_from_list(Interval** list, Interval* i); |
aoqi@0 | 682 | void remove_from_list(Interval* i); |
aoqi@0 | 683 | |
aoqi@0 | 684 | void next_interval(); |
aoqi@0 | 685 | Interval* current() const { return _current; } |
aoqi@0 | 686 | IntervalKind current_kind() const { return _current_kind; } |
aoqi@0 | 687 | |
aoqi@0 | 688 | void walk_to(IntervalState state, int from); |
aoqi@0 | 689 | |
aoqi@0 | 690 | // activate_current() is called when an unhandled interval becomes active (in current(), current_kind()). |
aoqi@0 | 691 | // Return false if current() should not be moved the the active interval list. |
aoqi@0 | 692 | // It is safe to append current to any interval list but the unhandled list. |
aoqi@0 | 693 | virtual bool activate_current() { return true; } |
aoqi@0 | 694 | |
aoqi@0 | 695 | // interval_moved() is called whenever an interval moves from one interval list to another. |
aoqi@0 | 696 | // In the implementation of this method it is prohibited to move the interval to any list. |
aoqi@0 | 697 | virtual void interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to); |
aoqi@0 | 698 | |
aoqi@0 | 699 | public: |
aoqi@0 | 700 | IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first); |
aoqi@0 | 701 | |
aoqi@0 | 702 | Interval* unhandled_first(IntervalKind kind) { check_bounds(kind); return _unhandled_first[kind]; } |
aoqi@0 | 703 | Interval* active_first(IntervalKind kind) { check_bounds(kind); return _active_first[kind]; } |
aoqi@0 | 704 | Interval* inactive_first(IntervalKind kind) { check_bounds(kind); return _inactive_first[kind]; } |
aoqi@0 | 705 | |
aoqi@0 | 706 | // active contains the intervals that are live after the lir_op |
aoqi@0 | 707 | void walk_to(int lir_op_id); |
aoqi@0 | 708 | // active contains the intervals that are live before the lir_op |
aoqi@0 | 709 | void walk_before(int lir_op_id) { walk_to(lir_op_id-1); } |
aoqi@0 | 710 | // walk through all intervals |
aoqi@0 | 711 | void walk() { walk_to(max_jint); } |
aoqi@0 | 712 | |
aoqi@0 | 713 | int current_position() { return _current_position; } |
aoqi@0 | 714 | }; |
aoqi@0 | 715 | |
aoqi@0 | 716 | |
aoqi@0 | 717 | // The actual linear scan register allocator |
aoqi@0 | 718 | class LinearScanWalker : public IntervalWalker { |
aoqi@0 | 719 | enum { |
aoqi@0 | 720 | any_reg = LinearScan::any_reg |
aoqi@0 | 721 | }; |
aoqi@0 | 722 | |
aoqi@0 | 723 | private: |
aoqi@0 | 724 | int _first_reg; // the reg. number of the first phys. register |
aoqi@0 | 725 | int _last_reg; // the reg. nmber of the last phys. register |
aoqi@0 | 726 | int _num_phys_regs; // required by current interval |
aoqi@0 | 727 | bool _adjacent_regs; // have lo/hi words of phys. regs be adjacent |
aoqi@0 | 728 | |
aoqi@0 | 729 | int _use_pos[LinearScan::nof_regs]; |
aoqi@0 | 730 | int _block_pos[LinearScan::nof_regs]; |
aoqi@0 | 731 | IntervalList* _spill_intervals[LinearScan::nof_regs]; |
aoqi@0 | 732 | |
aoqi@0 | 733 | MoveResolver _move_resolver; // for ordering spill moves |
aoqi@0 | 734 | |
aoqi@0 | 735 | // accessors mapped to same functions in class LinearScan |
aoqi@0 | 736 | int block_count() const { return allocator()->block_count(); } |
aoqi@0 | 737 | BlockBegin* block_at(int idx) const { return allocator()->block_at(idx); } |
aoqi@0 | 738 | BlockBegin* block_of_op_with_id(int op_id) const { return allocator()->block_of_op_with_id(op_id); } |
aoqi@0 | 739 | |
aoqi@0 | 740 | void init_use_lists(bool only_process_use_pos); |
aoqi@0 | 741 | void exclude_from_use(int reg); |
aoqi@0 | 742 | void exclude_from_use(Interval* i); |
aoqi@0 | 743 | void set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos); |
aoqi@0 | 744 | void set_use_pos(Interval* i, int use_pos, bool only_process_use_pos); |
aoqi@0 | 745 | void set_block_pos(int reg, Interval* i, int block_pos); |
aoqi@0 | 746 | void set_block_pos(Interval* i, int block_pos); |
aoqi@0 | 747 | |
aoqi@0 | 748 | void free_exclude_active_fixed(); |
aoqi@0 | 749 | void free_exclude_active_any(); |
aoqi@0 | 750 | void free_collect_inactive_fixed(Interval* cur); |
aoqi@0 | 751 | void free_collect_inactive_any(Interval* cur); |
aoqi@0 | 752 | void free_collect_unhandled(IntervalKind kind, Interval* cur); |
aoqi@0 | 753 | void spill_exclude_active_fixed(); |
aoqi@0 | 754 | void spill_block_unhandled_fixed(Interval* cur); |
aoqi@0 | 755 | void spill_block_inactive_fixed(Interval* cur); |
aoqi@0 | 756 | void spill_collect_active_any(); |
aoqi@0 | 757 | void spill_collect_inactive_any(Interval* cur); |
aoqi@0 | 758 | |
aoqi@0 | 759 | void insert_move(int op_id, Interval* src_it, Interval* dst_it); |
aoqi@0 | 760 | int find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos); |
aoqi@0 | 761 | int find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization); |
aoqi@0 | 762 | void split_before_usage(Interval* it, int min_split_pos, int max_split_pos); |
aoqi@0 | 763 | void split_for_spilling(Interval* it); |
aoqi@0 | 764 | void split_stack_interval(Interval* it); |
aoqi@0 | 765 | void split_when_partial_register_available(Interval* it, int register_available_until); |
aoqi@0 | 766 | void split_and_spill_interval(Interval* it); |
aoqi@0 | 767 | |
aoqi@0 | 768 | int find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split); |
aoqi@0 | 769 | int find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split); |
aoqi@0 | 770 | bool alloc_free_reg(Interval* cur); |
aoqi@0 | 771 | |
aoqi@0 | 772 | int find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split); |
aoqi@0 | 773 | int find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split); |
aoqi@0 | 774 | void split_and_spill_intersecting_intervals(int reg, int regHi); |
aoqi@0 | 775 | void alloc_locked_reg(Interval* cur); |
aoqi@0 | 776 | |
aoqi@0 | 777 | bool no_allocation_possible(Interval* cur); |
aoqi@0 | 778 | void update_phys_reg_range(bool requires_cpu_register); |
aoqi@0 | 779 | void init_vars_for_alloc(Interval* cur); |
aoqi@0 | 780 | bool pd_init_regs_for_alloc(Interval* cur); |
aoqi@0 | 781 | |
aoqi@0 | 782 | void combine_spilled_intervals(Interval* cur); |
aoqi@0 | 783 | bool is_move(LIR_Op* op, Interval* from, Interval* to); |
aoqi@0 | 784 | |
aoqi@0 | 785 | bool activate_current(); |
aoqi@0 | 786 | |
aoqi@0 | 787 | public: |
aoqi@0 | 788 | LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first); |
aoqi@0 | 789 | |
aoqi@0 | 790 | // must be called when all intervals are allocated |
aoqi@0 | 791 | void finish_allocation() { _move_resolver.resolve_and_append_moves(); } |
aoqi@0 | 792 | }; |
aoqi@0 | 793 | |
aoqi@0 | 794 | |
aoqi@0 | 795 | |
aoqi@0 | 796 | /* |
aoqi@0 | 797 | When a block has more than one predecessor, and all predecessors end with |
aoqi@0 | 798 | the same sequence of move-instructions, than this moves can be placed once |
aoqi@0 | 799 | at the beginning of the block instead of multiple times in the predecessors. |
aoqi@0 | 800 | |
aoqi@0 | 801 | Similarly, when a block has more than one successor, then equal sequences of |
aoqi@0 | 802 | moves at the beginning of the successors can be placed once at the end of |
aoqi@0 | 803 | the block. But because the moves must be inserted before all branch |
aoqi@0 | 804 | instructions, this works only when there is exactly one conditional branch |
aoqi@0 | 805 | at the end of the block (because the moves must be inserted before all |
aoqi@0 | 806 | branches, but after all compares). |
aoqi@0 | 807 | |
aoqi@0 | 808 | This optimization affects all kind of moves (reg->reg, reg->stack and |
aoqi@0 | 809 | stack->reg). Because this optimization works best when a block contains only |
aoqi@0 | 810 | few moves, it has a huge impact on the number of blocks that are totally |
aoqi@0 | 811 | empty. |
aoqi@0 | 812 | */ |
aoqi@0 | 813 | class EdgeMoveOptimizer : public StackObj { |
aoqi@0 | 814 | private: |
aoqi@0 | 815 | // the class maintains a list with all lir-instruction-list of the |
aoqi@0 | 816 | // successors (predecessors) and the current index into the lir-lists |
aoqi@0 | 817 | LIR_OpListStack _edge_instructions; |
aoqi@0 | 818 | intStack _edge_instructions_idx; |
aoqi@0 | 819 | |
aoqi@0 | 820 | void init_instructions(); |
aoqi@0 | 821 | void append_instructions(LIR_OpList* instructions, int instructions_idx); |
aoqi@0 | 822 | LIR_Op* instruction_at(int edge); |
aoqi@0 | 823 | void remove_cur_instruction(int edge, bool decrement_index); |
aoqi@0 | 824 | |
aoqi@0 | 825 | bool operations_different(LIR_Op* op1, LIR_Op* op2); |
aoqi@0 | 826 | |
aoqi@0 | 827 | void optimize_moves_at_block_end(BlockBegin* cur); |
aoqi@0 | 828 | void optimize_moves_at_block_begin(BlockBegin* cur); |
aoqi@0 | 829 | |
aoqi@0 | 830 | EdgeMoveOptimizer(); |
aoqi@0 | 831 | |
aoqi@0 | 832 | public: |
aoqi@0 | 833 | static void optimize(BlockList* code); |
aoqi@0 | 834 | }; |
aoqi@0 | 835 | |
aoqi@0 | 836 | |
aoqi@0 | 837 | |
aoqi@0 | 838 | class ControlFlowOptimizer : public StackObj { |
aoqi@0 | 839 | private: |
aoqi@0 | 840 | BlockList _original_preds; |
aoqi@0 | 841 | |
aoqi@0 | 842 | enum { |
aoqi@0 | 843 | ShortLoopSize = 5 |
aoqi@0 | 844 | }; |
aoqi@0 | 845 | void reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx); |
aoqi@0 | 846 | void reorder_short_loops(BlockList* code); |
aoqi@0 | 847 | |
aoqi@0 | 848 | bool can_delete_block(BlockBegin* cur); |
aoqi@0 | 849 | void substitute_branch_target(BlockBegin* cur, BlockBegin* target_from, BlockBegin* target_to); |
aoqi@0 | 850 | void delete_empty_blocks(BlockList* code); |
aoqi@0 | 851 | |
aoqi@0 | 852 | void delete_unnecessary_jumps(BlockList* code); |
aoqi@0 | 853 | void delete_jumps_to_return(BlockList* code); |
aoqi@0 | 854 | |
aoqi@0 | 855 | DEBUG_ONLY(void verify(BlockList* code);) |
aoqi@0 | 856 | |
aoqi@0 | 857 | ControlFlowOptimizer(); |
aoqi@0 | 858 | public: |
aoqi@0 | 859 | static void optimize(BlockList* code); |
aoqi@0 | 860 | }; |
aoqi@0 | 861 | |
aoqi@0 | 862 | |
aoqi@0 | 863 | #ifndef PRODUCT |
aoqi@0 | 864 | |
aoqi@0 | 865 | // Helper class for collecting statistics of LinearScan |
aoqi@0 | 866 | class LinearScanStatistic : public StackObj { |
aoqi@0 | 867 | public: |
aoqi@0 | 868 | enum Counter { |
aoqi@0 | 869 | // general counters |
aoqi@0 | 870 | counter_method, |
aoqi@0 | 871 | counter_fpu_method, |
aoqi@0 | 872 | counter_loop_method, |
aoqi@0 | 873 | counter_exception_method, |
aoqi@0 | 874 | counter_loop, |
aoqi@0 | 875 | counter_block, |
aoqi@0 | 876 | counter_loop_block, |
aoqi@0 | 877 | counter_exception_block, |
aoqi@0 | 878 | counter_interval, |
aoqi@0 | 879 | counter_fixed_interval, |
aoqi@0 | 880 | counter_range, |
aoqi@0 | 881 | counter_fixed_range, |
aoqi@0 | 882 | counter_use_pos, |
aoqi@0 | 883 | counter_fixed_use_pos, |
aoqi@0 | 884 | counter_spill_slots, |
aoqi@0 | 885 | blank_line_1, |
aoqi@0 | 886 | |
aoqi@0 | 887 | // counter for classes of lir instructions |
aoqi@0 | 888 | counter_instruction, |
aoqi@0 | 889 | counter_label, |
aoqi@0 | 890 | counter_entry, |
aoqi@0 | 891 | counter_return, |
aoqi@0 | 892 | counter_call, |
aoqi@0 | 893 | counter_move, |
aoqi@0 | 894 | counter_cmp, |
aoqi@0 | 895 | counter_cond_branch, |
aoqi@0 | 896 | counter_uncond_branch, |
aoqi@0 | 897 | counter_stub_branch, |
aoqi@0 | 898 | counter_alu, |
aoqi@0 | 899 | counter_alloc, |
aoqi@0 | 900 | counter_sync, |
aoqi@0 | 901 | counter_throw, |
aoqi@0 | 902 | counter_unwind, |
aoqi@0 | 903 | counter_typecheck, |
aoqi@0 | 904 | counter_fpu_stack, |
aoqi@0 | 905 | counter_misc_inst, |
aoqi@0 | 906 | counter_other_inst, |
aoqi@0 | 907 | blank_line_2, |
aoqi@0 | 908 | |
aoqi@0 | 909 | // counter for different types of moves |
aoqi@0 | 910 | counter_move_total, |
aoqi@0 | 911 | counter_move_reg_reg, |
aoqi@0 | 912 | counter_move_reg_stack, |
aoqi@0 | 913 | counter_move_stack_reg, |
aoqi@0 | 914 | counter_move_stack_stack, |
aoqi@0 | 915 | counter_move_reg_mem, |
aoqi@0 | 916 | counter_move_mem_reg, |
aoqi@0 | 917 | counter_move_const_any, |
aoqi@0 | 918 | |
aoqi@0 | 919 | number_of_counters, |
aoqi@0 | 920 | invalid_counter = -1 |
aoqi@0 | 921 | }; |
aoqi@0 | 922 | |
aoqi@0 | 923 | private: |
aoqi@0 | 924 | int _counters_sum[number_of_counters]; |
aoqi@0 | 925 | int _counters_max[number_of_counters]; |
aoqi@0 | 926 | |
aoqi@0 | 927 | void inc_counter(Counter idx, int value = 1) { _counters_sum[idx] += value; } |
aoqi@0 | 928 | |
aoqi@0 | 929 | const char* counter_name(int counter_idx); |
aoqi@0 | 930 | Counter base_counter(int counter_idx); |
aoqi@0 | 931 | |
aoqi@0 | 932 | void sum_up(LinearScanStatistic &method_statistic); |
aoqi@0 | 933 | void collect(LinearScan* allocator); |
aoqi@0 | 934 | |
aoqi@0 | 935 | public: |
aoqi@0 | 936 | LinearScanStatistic(); |
aoqi@0 | 937 | void print(const char* title); |
aoqi@0 | 938 | static void compute(LinearScan* allocator, LinearScanStatistic &global_statistic); |
aoqi@0 | 939 | }; |
aoqi@0 | 940 | |
aoqi@0 | 941 | |
aoqi@0 | 942 | // Helper class for collecting compilation time of LinearScan |
aoqi@0 | 943 | class LinearScanTimers : public StackObj { |
aoqi@0 | 944 | public: |
aoqi@0 | 945 | enum Timer { |
aoqi@0 | 946 | timer_do_nothing, |
aoqi@0 | 947 | timer_number_instructions, |
aoqi@0 | 948 | timer_compute_local_live_sets, |
aoqi@0 | 949 | timer_compute_global_live_sets, |
aoqi@0 | 950 | timer_build_intervals, |
aoqi@0 | 951 | timer_sort_intervals_before, |
aoqi@0 | 952 | timer_allocate_registers, |
aoqi@0 | 953 | timer_resolve_data_flow, |
aoqi@0 | 954 | timer_sort_intervals_after, |
aoqi@0 | 955 | timer_eliminate_spill_moves, |
aoqi@0 | 956 | timer_assign_reg_num, |
aoqi@0 | 957 | timer_allocate_fpu_stack, |
aoqi@0 | 958 | timer_optimize_lir, |
aoqi@0 | 959 | |
aoqi@0 | 960 | number_of_timers |
aoqi@0 | 961 | }; |
aoqi@0 | 962 | |
aoqi@0 | 963 | private: |
aoqi@0 | 964 | elapsedTimer _timers[number_of_timers]; |
aoqi@0 | 965 | const char* timer_name(int idx); |
aoqi@0 | 966 | |
aoqi@0 | 967 | public: |
aoqi@0 | 968 | LinearScanTimers(); |
aoqi@0 | 969 | |
aoqi@0 | 970 | void begin_method(); // called for each method when register allocation starts |
aoqi@0 | 971 | void end_method(LinearScan* allocator); // called for each method when register allocation completed |
aoqi@0 | 972 | void print(double total_time); // called before termination of VM to print global summary |
aoqi@0 | 973 | |
aoqi@0 | 974 | elapsedTimer* timer(int idx) { return &(_timers[idx]); } |
aoqi@0 | 975 | }; |
aoqi@0 | 976 | |
aoqi@0 | 977 | |
aoqi@0 | 978 | #endif // ifndef PRODUCT |
aoqi@0 | 979 | |
aoqi@0 | 980 | |
aoqi@0 | 981 | // Pick up platform-dependent implementation details |
aoqi@0 | 982 | #ifdef TARGET_ARCH_x86 |
aoqi@0 | 983 | # include "c1_LinearScan_x86.hpp" |
aoqi@0 | 984 | #endif |
aoqi@1 | 985 | #ifdef TARGET_ARCH_mips |
aoqi@1 | 986 | # include "c1_LinearScan_mips.hpp" |
aoqi@1 | 987 | #endif |
aoqi@0 | 988 | #ifdef TARGET_ARCH_sparc |
aoqi@0 | 989 | # include "c1_LinearScan_sparc.hpp" |
aoqi@0 | 990 | #endif |
aoqi@0 | 991 | #ifdef TARGET_ARCH_arm |
aoqi@0 | 992 | # include "c1_LinearScan_arm.hpp" |
aoqi@0 | 993 | #endif |
aoqi@0 | 994 | #ifdef TARGET_ARCH_ppc |
aoqi@0 | 995 | # include "c1_LinearScan_ppc.hpp" |
aoqi@0 | 996 | #endif |
aoqi@0 | 997 | |
aoqi@0 | 998 | |
aoqi@0 | 999 | #endif // SHARE_VM_C1_C1_LINEARSCAN_HPP |