aoqi@0: /* aoqi@0: * Copyright (c) 2005, 2012, Oracle and/or its affiliates. All rights reserved. aoqi@0: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. aoqi@0: * aoqi@0: * This code is free software; you can redistribute it and/or modify it aoqi@0: * under the terms of the GNU General Public License version 2 only, as aoqi@0: * published by the Free Software Foundation. aoqi@0: * aoqi@0: * This code is distributed in the hope that it will be useful, but WITHOUT aoqi@0: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or aoqi@0: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License aoqi@0: * version 2 for more details (a copy is included in the LICENSE file that aoqi@0: * accompanied this code). aoqi@0: * aoqi@0: * You should have received a copy of the GNU General Public License version aoqi@0: * 2 along with this work; if not, write to the Free Software Foundation, aoqi@0: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. aoqi@0: * aoqi@0: * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA aoqi@0: * or visit www.oracle.com if you need additional information or have any aoqi@0: * questions. aoqi@0: * aoqi@0: */ aoqi@0: aoqi@1: /* aoqi@1: * This file has been modified by Loongson Technology in 2015. These aoqi@1: * modifications are Copyright (c) 2015 Loongson Technology, and are made aoqi@1: * available on the same license terms set forth above. aoqi@1: */ aoqi@1: aoqi@0: #ifndef SHARE_VM_C1_C1_LINEARSCAN_HPP aoqi@0: #define SHARE_VM_C1_C1_LINEARSCAN_HPP aoqi@0: aoqi@0: #include "c1/c1_FpuStackSim.hpp" aoqi@0: #include "c1/c1_FrameMap.hpp" aoqi@0: #include "c1/c1_IR.hpp" aoqi@0: #include "c1/c1_Instruction.hpp" aoqi@0: #include "c1/c1_LIR.hpp" aoqi@0: #include "c1/c1_LIRGenerator.hpp" aoqi@0: aoqi@0: class DebugInfoCache; aoqi@0: class FpuStackAllocator; aoqi@0: class IRScopeDebugInfo; aoqi@0: class Interval; aoqi@0: class IntervalWalker; aoqi@0: class LIRGenerator; aoqi@0: class LinearScan; aoqi@0: class MoveResolver; aoqi@0: class Range; aoqi@0: aoqi@0: define_array(IntervalArray, Interval*) aoqi@0: define_stack(IntervalList, IntervalArray) aoqi@0: aoqi@0: define_array(IntervalsArray, IntervalList*) aoqi@0: define_stack(IntervalsList, IntervalsArray) aoqi@0: aoqi@0: define_array(OopMapArray, OopMap*) aoqi@0: define_stack(OopMapList, OopMapArray) aoqi@0: aoqi@0: define_array(ScopeValueArray, ScopeValue*) aoqi@0: aoqi@0: define_array(LIR_OpListArray, LIR_OpList*); aoqi@0: define_stack(LIR_OpListStack, LIR_OpListArray); aoqi@0: aoqi@0: aoqi@0: enum IntervalUseKind { aoqi@0: // priority of use kinds must be ascending aoqi@0: noUse = 0, aoqi@0: loopEndMarker = 1, aoqi@0: shouldHaveRegister = 2, aoqi@0: mustHaveRegister = 3, aoqi@0: aoqi@0: firstValidKind = 1, aoqi@0: lastValidKind = 3 aoqi@0: }; aoqi@0: define_array(UseKindArray, IntervalUseKind) aoqi@0: define_stack(UseKindStack, UseKindArray) aoqi@0: aoqi@0: aoqi@0: enum IntervalKind { aoqi@0: fixedKind = 0, // interval pre-colored by LIR_Generator aoqi@0: anyKind = 1, // no register/memory allocated by LIR_Generator aoqi@0: nofKinds, aoqi@0: firstKind = fixedKind aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: // during linear scan an interval is in one of four states in aoqi@0: enum IntervalState { aoqi@0: unhandledState = 0, // unhandled state (not processed yet) aoqi@0: activeState = 1, // life and is in a physical register aoqi@0: inactiveState = 2, // in a life time hole and is in a physical register aoqi@0: handledState = 3, // spilled or not life again aoqi@0: invalidState = -1 aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: enum IntervalSpillState { aoqi@0: noDefinitionFound, // starting state of calculation: no definition found yet aoqi@0: oneDefinitionFound, // one definition has already been found. aoqi@0: // Note: two consecutive definitions are treated as one (e.g. consecutive move and add because of two-operand LIR form) aoqi@0: // the position of this definition is stored in _definition_pos aoqi@0: oneMoveInserted, // one spill move has already been inserted. aoqi@0: storeAtDefinition, // the interval should be stored immediately after its definition because otherwise aoqi@0: // there would be multiple redundant stores aoqi@0: startInMemory, // the interval starts in memory (e.g. method parameter), so a store is never necessary aoqi@0: noOptimization // the interval has more then one definition (e.g. resulting from phi moves), so stores to memory are not optimized aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: #define for_each_interval_kind(kind) \ aoqi@0: for (IntervalKind kind = firstKind; kind < nofKinds; kind = (IntervalKind)(kind + 1)) aoqi@0: aoqi@0: #define for_each_visitor_mode(mode) \ aoqi@0: for (LIR_OpVisitState::OprMode mode = LIR_OpVisitState::firstMode; mode < LIR_OpVisitState::numModes; mode = (LIR_OpVisitState::OprMode)(mode + 1)) aoqi@0: aoqi@0: aoqi@0: class LinearScan : public CompilationResourceObj { aoqi@0: // declare classes used by LinearScan as friends because they aoqi@0: // need a wide variety of functions declared here aoqi@0: // aoqi@0: // Only the small interface to the rest of the compiler is public aoqi@0: friend class Interval; aoqi@0: friend class IntervalWalker; aoqi@0: friend class LinearScanWalker; aoqi@0: friend class FpuStackAllocator; aoqi@0: friend class MoveResolver; aoqi@0: friend class LinearScanStatistic; aoqi@0: friend class LinearScanTimers; aoqi@0: friend class RegisterVerifier; aoqi@0: aoqi@0: public: aoqi@0: enum { aoqi@0: any_reg = -1, aoqi@0: nof_cpu_regs = pd_nof_cpu_regs_linearscan, aoqi@0: nof_fpu_regs = pd_nof_fpu_regs_linearscan, aoqi@0: nof_xmm_regs = pd_nof_xmm_regs_linearscan, aoqi@0: nof_regs = nof_cpu_regs + nof_fpu_regs + nof_xmm_regs aoqi@0: }; aoqi@0: aoqi@0: private: aoqi@0: Compilation* _compilation; aoqi@0: IR* _ir; aoqi@0: LIRGenerator* _gen; aoqi@0: FrameMap* _frame_map; aoqi@0: aoqi@0: BlockList _cached_blocks; // cached list with all blocks in linear-scan order (only correct if original list keeps unchanged) aoqi@0: int _num_virtual_regs; // number of virtual registers (without new registers introduced because of splitting intervals) aoqi@0: bool _has_fpu_registers; // true if this method uses any floating point registers (and so fpu stack allocation is necessary) aoqi@0: int _num_calls; // total number of calls in this method aoqi@0: int _max_spills; // number of stack slots used for intervals allocated to memory aoqi@0: int _unused_spill_slot; // unused spill slot for a single-word value because of alignment of a double-word value aoqi@0: aoqi@0: IntervalList _intervals; // mapping from register number to interval aoqi@0: IntervalList* _new_intervals_from_allocation; // list with all intervals created during allocation when an existing interval is split aoqi@0: IntervalArray* _sorted_intervals; // intervals sorted by Interval::from() aoqi@0: bool _needs_full_resort; // set to true if an Interval::from() is changed and _sorted_intervals must be resorted aoqi@0: aoqi@0: LIR_OpArray _lir_ops; // mapping from LIR_Op id to LIR_Op node aoqi@0: BlockBeginArray _block_of_op; // mapping from LIR_Op id to the BlockBegin containing this instruction aoqi@0: BitMap _has_info; // bit set for each LIR_Op id that has a CodeEmitInfo aoqi@0: BitMap _has_call; // bit set for each LIR_Op id that destroys all caller save registers aoqi@0: BitMap2D _interval_in_loop; // bit set for each virtual register that is contained in each loop aoqi@0: aoqi@0: // cached debug info to prevent multiple creation of same object aoqi@0: // TODO: cached scope values for registers could be static aoqi@0: ScopeValueArray _scope_value_cache; aoqi@0: aoqi@0: static ConstantOopWriteValue* _oop_null_scope_value; aoqi@0: static ConstantIntValue* _int_m1_scope_value; aoqi@0: static ConstantIntValue* _int_0_scope_value; aoqi@0: static ConstantIntValue* _int_1_scope_value; aoqi@0: static ConstantIntValue* _int_2_scope_value; aoqi@0: aoqi@0: // accessors aoqi@0: IR* ir() const { return _ir; } aoqi@0: Compilation* compilation() const { return _compilation; } aoqi@0: LIRGenerator* gen() const { return _gen; } aoqi@0: FrameMap* frame_map() const { return _frame_map; } aoqi@0: aoqi@0: // unified bailout support aoqi@0: void bailout(const char* msg) const { compilation()->bailout(msg); } aoqi@0: bool bailed_out() const { return compilation()->bailed_out(); } aoqi@0: aoqi@0: // access to block list (sorted in linear scan order) aoqi@0: int block_count() const { assert(_cached_blocks.length() == ir()->linear_scan_order()->length(), "invalid cached block list"); return _cached_blocks.length(); } aoqi@0: BlockBegin* block_at(int idx) const { assert(_cached_blocks.at(idx) == ir()->linear_scan_order()->at(idx), "invalid cached block list"); return _cached_blocks.at(idx); } aoqi@0: aoqi@0: int num_virtual_regs() const { return _num_virtual_regs; } aoqi@0: // size of live_in and live_out sets of BasicBlocks (BitMap needs rounded size for iteration) aoqi@0: int live_set_size() const { return round_to(_num_virtual_regs, BitsPerWord); } aoqi@0: bool has_fpu_registers() const { return _has_fpu_registers; } aoqi@0: int num_loops() const { return ir()->num_loops(); } aoqi@0: bool is_interval_in_loop(int interval, int loop) const { return _interval_in_loop.at(interval, loop); } aoqi@0: aoqi@0: // handling of fpu stack allocation (platform dependent, needed for debug information generation) aoqi@0: #ifdef X86 aoqi@0: FpuStackAllocator* _fpu_stack_allocator; aoqi@0: bool use_fpu_stack_allocation() const { return UseSSE < 2 && has_fpu_registers(); } aoqi@0: #else aoqi@0: bool use_fpu_stack_allocation() const { return false; } aoqi@0: #endif aoqi@0: aoqi@0: aoqi@0: // access to interval list aoqi@0: int interval_count() const { return _intervals.length(); } aoqi@0: Interval* interval_at(int reg_num) const { return _intervals.at(reg_num); } aoqi@0: aoqi@0: IntervalList* new_intervals_from_allocation() const { return _new_intervals_from_allocation; } aoqi@0: aoqi@0: // access to LIR_Ops and Blocks indexed by op_id aoqi@0: int max_lir_op_id() const { assert(_lir_ops.length() > 0, "no operations"); return (_lir_ops.length() - 1) << 1; } aoqi@0: LIR_Op* lir_op_with_id(int op_id) const { assert(op_id >= 0 && op_id <= max_lir_op_id() && op_id % 2 == 0, "op_id out of range or not even"); return _lir_ops.at(op_id >> 1); } aoqi@0: BlockBegin* block_of_op_with_id(int op_id) const { assert(_block_of_op.length() > 0 && op_id >= 0 && op_id <= max_lir_op_id() + 1, "op_id out of range"); return _block_of_op.at(op_id >> 1); } aoqi@0: aoqi@0: bool is_block_begin(int op_id) { return op_id == 0 || block_of_op_with_id(op_id) != block_of_op_with_id(op_id - 1); } aoqi@0: bool covers_block_begin(int op_id_1, int op_id_2) { return block_of_op_with_id(op_id_1) != block_of_op_with_id(op_id_2); } aoqi@0: aoqi@0: bool has_call(int op_id) { assert(op_id % 2 == 0, "must be even"); return _has_call.at(op_id >> 1); } aoqi@0: bool has_info(int op_id) { assert(op_id % 2 == 0, "must be even"); return _has_info.at(op_id >> 1); } aoqi@0: aoqi@0: aoqi@0: // functions for converting LIR-Operands to register numbers aoqi@0: static bool is_valid_reg_num(int reg_num) { return reg_num >= 0; } aoqi@0: static int reg_num(LIR_Opr opr); aoqi@0: static int reg_numHi(LIR_Opr opr); aoqi@0: aoqi@0: // functions for classification of intervals aoqi@0: static bool is_precolored_interval(const Interval* i); aoqi@0: static bool is_virtual_interval(const Interval* i); aoqi@0: aoqi@0: static bool is_precolored_cpu_interval(const Interval* i); aoqi@0: static bool is_virtual_cpu_interval(const Interval* i); aoqi@0: static bool is_precolored_fpu_interval(const Interval* i); aoqi@0: static bool is_virtual_fpu_interval(const Interval* i); aoqi@0: aoqi@0: static bool is_in_fpu_register(const Interval* i); aoqi@0: static bool is_oop_interval(const Interval* i); aoqi@0: aoqi@0: aoqi@0: // General helper functions aoqi@0: int allocate_spill_slot(bool double_word); aoqi@0: void assign_spill_slot(Interval* it); aoqi@0: void propagate_spill_slots(); aoqi@0: aoqi@0: Interval* create_interval(int reg_num); aoqi@0: void append_interval(Interval* it); aoqi@0: void copy_register_flags(Interval* from, Interval* to); aoqi@0: aoqi@0: // platform dependent functions aoqi@0: static bool is_processed_reg_num(int reg_num); aoqi@0: static int num_physical_regs(BasicType type); aoqi@0: static bool requires_adjacent_regs(BasicType type); aoqi@0: static bool is_caller_save(int assigned_reg); aoqi@0: aoqi@0: // spill move optimization: eliminate moves from register to stack if aoqi@0: // stack slot is known to be correct aoqi@0: void change_spill_definition_pos(Interval* interval, int def_pos); aoqi@0: void change_spill_state(Interval* interval, int spill_pos); aoqi@0: static bool must_store_at_definition(const Interval* i); aoqi@0: void eliminate_spill_moves(); aoqi@0: aoqi@0: // Phase 1: number all instructions in all blocks aoqi@0: void number_instructions(); aoqi@0: aoqi@0: // Phase 2: compute local live sets separately for each block aoqi@0: // (sets live_gen and live_kill for each block) aoqi@0: // aoqi@0: // helper methods used by compute_local_live_sets() aoqi@0: void set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill); aoqi@0: aoqi@0: void compute_local_live_sets(); aoqi@0: aoqi@0: // Phase 3: perform a backward dataflow analysis to compute global live sets aoqi@0: // (sets live_in and live_out for each block) aoqi@0: void compute_global_live_sets(); aoqi@0: aoqi@0: aoqi@0: // Phase 4: build intervals aoqi@0: // (fills the list _intervals) aoqi@0: // aoqi@0: // helper methods used by build_intervals() aoqi@0: void add_use (Value value, int from, int to, IntervalUseKind use_kind); aoqi@0: aoqi@0: void add_def (LIR_Opr opr, int def_pos, IntervalUseKind use_kind); aoqi@0: void add_use (LIR_Opr opr, int from, int to, IntervalUseKind use_kind); aoqi@0: void add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind); aoqi@0: aoqi@0: void add_def (int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type); aoqi@0: void add_use (int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type); aoqi@0: void add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type); aoqi@0: aoqi@0: // Add platform dependent kills for particular LIR ops. Can be used aoqi@0: // to add platform dependent behaviour for some operations. aoqi@0: void pd_add_temps(LIR_Op* op); aoqi@0: aoqi@0: IntervalUseKind use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr); aoqi@0: IntervalUseKind use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr); aoqi@0: void handle_method_arguments(LIR_Op* op); aoqi@0: void handle_doubleword_moves(LIR_Op* op); aoqi@0: void add_register_hints(LIR_Op* op); aoqi@0: aoqi@0: void build_intervals(); aoqi@0: aoqi@0: aoqi@0: // Phase 5: actual register allocation aoqi@0: // (Uses LinearScanWalker) aoqi@0: // aoqi@0: // helper functions for building a sorted list of intervals aoqi@0: NOT_PRODUCT(bool is_sorted(IntervalArray* intervals);) aoqi@0: static int interval_cmp(Interval** a, Interval** b); aoqi@0: void add_to_list(Interval** first, Interval** prev, Interval* interval); aoqi@0: void create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)); aoqi@0: aoqi@0: void sort_intervals_before_allocation(); aoqi@0: void sort_intervals_after_allocation(); aoqi@0: void allocate_registers(); aoqi@0: aoqi@0: aoqi@0: // Phase 6: resolve data flow aoqi@0: // (insert moves at edges between blocks if intervals have been split) aoqi@0: // aoqi@0: // helper functions for resolve_data_flow() aoqi@0: Interval* split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode); aoqi@0: Interval* interval_at_block_begin(BlockBegin* block, int reg_num); aoqi@0: Interval* interval_at_block_end(BlockBegin* block, int reg_num); aoqi@0: Interval* interval_at_op_id(int reg_num, int op_id); aoqi@0: void resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver); aoqi@0: void resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver); aoqi@0: void resolve_data_flow(); aoqi@0: aoqi@0: void resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver); aoqi@0: void resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver); aoqi@0: void resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver); aoqi@0: void resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver); aoqi@0: void resolve_exception_handlers(); aoqi@0: aoqi@0: // Phase 7: assign register numbers back to LIR aoqi@0: // (includes computation of debug information and oop maps) aoqi@0: // aoqi@0: // helper functions for assign_reg_num() aoqi@0: VMReg vm_reg_for_interval(Interval* interval); aoqi@0: VMReg vm_reg_for_operand(LIR_Opr opr); aoqi@0: aoqi@0: static LIR_Opr operand_for_interval(Interval* interval); aoqi@0: static LIR_Opr calc_operand_for_interval(const Interval* interval); aoqi@0: LIR_Opr canonical_spill_opr(Interval* interval); aoqi@0: aoqi@0: LIR_Opr color_lir_opr(LIR_Opr opr, int id, LIR_OpVisitState::OprMode); aoqi@0: aoqi@0: // methods used for oop map computation aoqi@0: IntervalWalker* init_compute_oop_maps(); aoqi@0: OopMap* compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site); aoqi@0: void compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op); aoqi@0: aoqi@0: // methods used for debug information computation aoqi@0: void init_compute_debug_info(); aoqi@0: aoqi@0: MonitorValue* location_for_monitor_index(int monitor_index); aoqi@0: LocationValue* location_for_name(int name, Location::Type loc_type); aoqi@0: void set_oop(OopMap* map, VMReg name) { aoqi@0: if (map->legal_vm_reg_name(name)) { aoqi@0: map->set_oop(name); aoqi@0: } else { aoqi@0: bailout("illegal oopMap register name"); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: int append_scope_value_for_constant(LIR_Opr opr, GrowableArray* scope_values); aoqi@0: int append_scope_value_for_operand(LIR_Opr opr, GrowableArray* scope_values); aoqi@0: int append_scope_value(int op_id, Value value, GrowableArray* scope_values); aoqi@0: aoqi@0: IRScopeDebugInfo* compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state); aoqi@0: void compute_debug_info(CodeEmitInfo* info, int op_id); aoqi@0: aoqi@0: void assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw); aoqi@0: void assign_reg_num(); aoqi@0: aoqi@0: aoqi@0: // Phase 8: fpu stack allocation aoqi@0: // (Used only on x86 when fpu operands are present) aoqi@0: void allocate_fpu_stack(); aoqi@0: aoqi@0: aoqi@0: // helper functions for printing state aoqi@0: #ifndef PRODUCT aoqi@0: static void print_bitmap(BitMap& bitmap); aoqi@0: void print_intervals(const char* label); aoqi@0: void print_lir(int level, const char* label, bool hir_valid = true); aoqi@0: #endif aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: // verification functions for allocation aoqi@0: // (check that all intervals have a correct register and that no registers are overwritten) aoqi@0: void verify(); aoqi@0: void verify_intervals(); aoqi@0: void verify_no_oops_in_fixed_intervals(); aoqi@0: void verify_constants(); aoqi@0: void verify_registers(); aoqi@0: #endif aoqi@0: aoqi@0: public: aoqi@0: // creation aoqi@0: LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map); aoqi@0: aoqi@0: // main entry function: perform linear scan register allocation aoqi@0: void do_linear_scan(); aoqi@0: aoqi@0: // accessors used by Compilation aoqi@0: int max_spills() const { return _max_spills; } aoqi@0: int num_calls() const { assert(_num_calls >= 0, "not set"); return _num_calls; } aoqi@0: aoqi@0: // entry functions for printing aoqi@0: #ifndef PRODUCT aoqi@0: static void print_statistics(); aoqi@0: static void print_timers(double total); aoqi@0: #endif aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: // Helper class for ordering moves that are inserted at the same position in the LIR aoqi@0: // When moves between registers are inserted, it is important that the moves are aoqi@0: // ordered such that no register is overwritten. So moves from register to stack aoqi@0: // are processed prior to moves from stack to register. When moves have circular aoqi@0: // dependencies, a temporary stack slot is used to break the circle. aoqi@0: // The same logic is used in the LinearScanWalker and in LinearScan during resolve_data_flow aoqi@0: // and therefore factored out in a separate class aoqi@0: class MoveResolver: public StackObj { aoqi@0: private: aoqi@0: LinearScan* _allocator; aoqi@0: aoqi@0: LIR_List* _insert_list; aoqi@0: int _insert_idx; aoqi@0: LIR_InsertionBuffer _insertion_buffer; // buffer where moves are inserted aoqi@0: aoqi@0: IntervalList _mapping_from; aoqi@0: LIR_OprList _mapping_from_opr; aoqi@0: IntervalList _mapping_to; aoqi@0: bool _multiple_reads_allowed; aoqi@0: int _register_blocked[LinearScan::nof_regs]; aoqi@0: aoqi@0: int register_blocked(int reg) { assert(reg >= 0 && reg < LinearScan::nof_regs, "out of bounds"); return _register_blocked[reg]; } aoqi@0: void set_register_blocked(int reg, int direction) { assert(reg >= 0 && reg < LinearScan::nof_regs, "out of bounds"); assert(direction == 1 || direction == -1, "out of bounds"); _register_blocked[reg] += direction; } aoqi@0: aoqi@0: void block_registers(Interval* it); aoqi@0: void unblock_registers(Interval* it); aoqi@0: bool save_to_process_move(Interval* from, Interval* to); aoqi@0: aoqi@0: void create_insertion_buffer(LIR_List* list); aoqi@0: void append_insertion_buffer(); aoqi@0: void insert_move(Interval* from_interval, Interval* to_interval); aoqi@0: void insert_move(LIR_Opr from_opr, Interval* to_interval); aoqi@0: aoqi@0: DEBUG_ONLY(void verify_before_resolve();) aoqi@0: void resolve_mappings(); aoqi@0: public: aoqi@0: MoveResolver(LinearScan* allocator); aoqi@0: aoqi@0: DEBUG_ONLY(void check_empty();) aoqi@0: void set_multiple_reads_allowed() { _multiple_reads_allowed = true; } aoqi@0: void set_insert_position(LIR_List* insert_list, int insert_idx); aoqi@0: void move_insert_position(LIR_List* insert_list, int insert_idx); aoqi@0: void add_mapping(Interval* from, Interval* to); aoqi@0: void add_mapping(LIR_Opr from, Interval* to); aoqi@0: void resolve_and_append_moves(); aoqi@0: aoqi@0: LinearScan* allocator() { return _allocator; } aoqi@0: bool has_mappings() { return _mapping_from.length() > 0; } aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: class Range : public CompilationResourceObj { aoqi@0: friend class Interval; aoqi@0: aoqi@0: private: aoqi@0: static Range* _end; // sentinel (from == to == max_jint) aoqi@0: aoqi@0: int _from; // from (inclusive) aoqi@0: int _to; // to (exclusive) aoqi@0: Range* _next; // linear list of Ranges aoqi@0: aoqi@0: // used only by class Interval, so hide them aoqi@0: bool intersects(Range* r) const { return intersects_at(r) != -1; } aoqi@0: int intersects_at(Range* r) const; aoqi@0: aoqi@0: public: aoqi@0: Range(int from, int to, Range* next); aoqi@0: aoqi@0: static void initialize(Arena* arena); aoqi@0: static Range* end() { return _end; } aoqi@0: aoqi@0: int from() const { return _from; } aoqi@0: int to() const { return _to; } aoqi@0: Range* next() const { return _next; } aoqi@0: void set_from(int from) { _from = from; } aoqi@0: void set_to(int to) { _to = to; } aoqi@0: void set_next(Range* next) { _next = next; } aoqi@0: aoqi@0: // for testing aoqi@0: void print(outputStream* out = tty) const PRODUCT_RETURN; aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: // Interval is an ordered list of disjoint ranges. aoqi@0: aoqi@0: // For pre-colored double word LIR_Oprs, one interval is created for aoqi@0: // the low word register and one is created for the hi word register. aoqi@0: // On Intel for FPU double registers only one interval is created. At aoqi@0: // all times assigned_reg contains the reg. number of the physical aoqi@0: // register. aoqi@0: aoqi@0: // For LIR_Opr in virtual registers a single interval can represent aoqi@0: // single and double word values. When a physical register is aoqi@0: // assigned to the interval, assigned_reg contains the aoqi@0: // phys. reg. number and for double word values assigned_regHi the aoqi@0: // phys. reg. number of the hi word if there is any. For spilled aoqi@0: // intervals assigned_reg contains the stack index. assigned_regHi is aoqi@0: // always -1. aoqi@0: aoqi@0: class Interval : public CompilationResourceObj { aoqi@0: private: aoqi@0: static Interval* _end; // sentinel (interval with only range Range::end()) aoqi@0: aoqi@0: int _reg_num; aoqi@0: BasicType _type; // valid only for virtual registers aoqi@0: Range* _first; // sorted list of Ranges aoqi@0: intStack _use_pos_and_kinds; // sorted list of use-positions and their according use-kinds aoqi@0: aoqi@0: Range* _current; // interval iteration: the current Range aoqi@0: Interval* _next; // interval iteration: sorted list of Intervals (ends with sentinel) aoqi@0: IntervalState _state; // interval iteration: to which set belongs this interval aoqi@0: aoqi@0: aoqi@0: int _assigned_reg; aoqi@0: int _assigned_regHi; aoqi@0: aoqi@0: int _cached_to; // cached value: to of last range (-1: not cached) aoqi@0: LIR_Opr _cached_opr; aoqi@0: VMReg _cached_vm_reg; aoqi@0: aoqi@0: Interval* _split_parent; // the original interval where this interval is derived from aoqi@0: IntervalList _split_children; // list of all intervals that are split off from this interval (only available for split parents) aoqi@0: Interval* _current_split_child; // the current split child that has been active or inactive last (always stored in split parents) aoqi@0: aoqi@0: int _canonical_spill_slot; // the stack slot where all split parts of this interval are spilled to (always stored in split parents) aoqi@0: bool _insert_move_when_activated; // true if move is inserted between _current_split_child and this interval when interval gets active the first time aoqi@0: IntervalSpillState _spill_state; // for spill move optimization aoqi@0: int _spill_definition_pos; // position where the interval is defined (if defined only once) aoqi@0: Interval* _register_hint; // this interval should be in the same register as the hint interval aoqi@0: aoqi@0: int calc_to(); aoqi@0: Interval* new_split_child(); aoqi@0: public: aoqi@0: Interval(int reg_num); aoqi@0: aoqi@0: static void initialize(Arena* arena); aoqi@0: static Interval* end() { return _end; } aoqi@0: aoqi@0: // accessors aoqi@0: int reg_num() const { return _reg_num; } aoqi@0: void set_reg_num(int r) { assert(_reg_num == -1, "cannot change reg_num"); _reg_num = r; } aoqi@0: BasicType type() const { assert(_reg_num == -1 || _reg_num >= LIR_OprDesc::vreg_base, "cannot access type for fixed interval"); return _type; } aoqi@0: void set_type(BasicType type) { assert(_reg_num < LIR_OprDesc::vreg_base || _type == T_ILLEGAL || _type == type, "overwriting existing type"); _type = type; } aoqi@0: aoqi@0: Range* first() const { return _first; } aoqi@0: int from() const { return _first->from(); } aoqi@0: int to() { if (_cached_to == -1) _cached_to = calc_to(); assert(_cached_to == calc_to(), "invalid cached value"); return _cached_to; } aoqi@0: int num_use_positions() const { return _use_pos_and_kinds.length() / 2; } aoqi@0: aoqi@0: Interval* next() const { return _next; } aoqi@0: Interval** next_addr() { return &_next; } aoqi@0: void set_next(Interval* next) { _next = next; } aoqi@0: aoqi@0: int assigned_reg() const { return _assigned_reg; } aoqi@0: int assigned_regHi() const { return _assigned_regHi; } aoqi@0: void assign_reg(int reg) { _assigned_reg = reg; _assigned_regHi = LinearScan::any_reg; } aoqi@0: void assign_reg(int reg,int regHi) { _assigned_reg = reg; _assigned_regHi = regHi; } aoqi@0: aoqi@0: Interval* register_hint(bool search_split_child = true) const; // calculation needed aoqi@0: void set_register_hint(Interval* i) { _register_hint = i; } aoqi@0: aoqi@0: int state() const { return _state; } aoqi@0: void set_state(IntervalState s) { _state = s; } aoqi@0: aoqi@0: // access to split parent and split children aoqi@0: bool is_split_parent() const { return _split_parent == this; } aoqi@0: bool is_split_child() const { return _split_parent != this; } aoqi@0: Interval* split_parent() const { assert(_split_parent->is_split_parent(), "must be"); return _split_parent; } aoqi@0: Interval* split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode); aoqi@0: Interval* split_child_before_op_id(int op_id); aoqi@0: bool split_child_covers(int op_id, LIR_OpVisitState::OprMode mode); aoqi@0: DEBUG_ONLY(void check_split_children();) aoqi@0: aoqi@0: // information stored in split parent, but available for all children aoqi@0: int canonical_spill_slot() const { return split_parent()->_canonical_spill_slot; } aoqi@0: void set_canonical_spill_slot(int slot) { assert(split_parent()->_canonical_spill_slot == -1, "overwriting existing value"); split_parent()->_canonical_spill_slot = slot; } aoqi@0: Interval* current_split_child() const { return split_parent()->_current_split_child; } aoqi@0: void make_current_split_child() { split_parent()->_current_split_child = this; } aoqi@0: aoqi@0: bool insert_move_when_activated() const { return _insert_move_when_activated; } aoqi@0: void set_insert_move_when_activated(bool b) { _insert_move_when_activated = b; } aoqi@0: aoqi@0: // for spill optimization aoqi@0: IntervalSpillState spill_state() const { return split_parent()->_spill_state; } aoqi@0: int spill_definition_pos() const { return split_parent()->_spill_definition_pos; } aoqi@0: void set_spill_state(IntervalSpillState state) { assert(state >= spill_state(), "state cannot decrease"); split_parent()->_spill_state = state; } aoqi@0: void set_spill_definition_pos(int pos) { assert(spill_definition_pos() == -1, "cannot set the position twice"); split_parent()->_spill_definition_pos = pos; } aoqi@0: // returns true if this interval has a shadow copy on the stack that is always correct aoqi@0: bool always_in_memory() const { return split_parent()->_spill_state == storeAtDefinition || split_parent()->_spill_state == startInMemory; } aoqi@0: aoqi@0: // caching of values that take time to compute and are used multiple times aoqi@0: LIR_Opr cached_opr() const { return _cached_opr; } aoqi@0: VMReg cached_vm_reg() const { return _cached_vm_reg; } aoqi@0: void set_cached_opr(LIR_Opr opr) { _cached_opr = opr; } aoqi@0: void set_cached_vm_reg(VMReg reg) { _cached_vm_reg = reg; } aoqi@0: aoqi@0: // access to use positions aoqi@0: int first_usage(IntervalUseKind min_use_kind) const; // id of the first operation requiring this interval in a register aoqi@0: int next_usage(IntervalUseKind min_use_kind, int from) const; // id of next usage seen from the given position aoqi@0: int next_usage_exact(IntervalUseKind exact_use_kind, int from) const; aoqi@0: int previous_usage(IntervalUseKind min_use_kind, int from) const; aoqi@0: aoqi@0: // manipulating intervals aoqi@0: void add_use_pos(int pos, IntervalUseKind use_kind); aoqi@0: void add_range(int from, int to); aoqi@0: Interval* split(int split_pos); aoqi@0: Interval* split_from_start(int split_pos); aoqi@0: void remove_first_use_pos() { _use_pos_and_kinds.truncate(_use_pos_and_kinds.length() - 2); } aoqi@0: aoqi@0: // test intersection aoqi@0: bool covers(int op_id, LIR_OpVisitState::OprMode mode) const; aoqi@0: bool has_hole_between(int from, int to); aoqi@0: bool intersects(Interval* i) const { return _first->intersects(i->_first); } aoqi@0: int intersects_at(Interval* i) const { return _first->intersects_at(i->_first); } aoqi@0: aoqi@0: // range iteration aoqi@0: void rewind_range() { _current = _first; } aoqi@0: void next_range() { assert(this != _end, "not allowed on sentinel"); _current = _current->next(); } aoqi@0: int current_from() const { return _current->from(); } aoqi@0: int current_to() const { return _current->to(); } aoqi@0: bool current_at_end() const { return _current == Range::end(); } aoqi@0: bool current_intersects(Interval* it) { return _current->intersects(it->_current); }; aoqi@0: int current_intersects_at(Interval* it) { return _current->intersects_at(it->_current); }; aoqi@0: aoqi@0: // printing aoqi@0: void print(outputStream* out = tty) const PRODUCT_RETURN; aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: class IntervalWalker : public CompilationResourceObj { aoqi@0: protected: aoqi@0: Compilation* _compilation; aoqi@0: LinearScan* _allocator; aoqi@0: aoqi@0: Interval* _unhandled_first[nofKinds]; // sorted list of intervals, not life before the current position aoqi@0: Interval* _active_first [nofKinds]; // sorted list of intervals, life at the current position aoqi@0: Interval* _inactive_first [nofKinds]; // sorted list of intervals, intervals in a life time hole at the current position aoqi@0: aoqi@0: Interval* _current; // the current interval coming from unhandled list aoqi@0: int _current_position; // the current position (intercept point through the intervals) aoqi@0: IntervalKind _current_kind; // and whether it is fixed_kind or any_kind. aoqi@0: aoqi@0: aoqi@0: Compilation* compilation() const { return _compilation; } aoqi@0: LinearScan* allocator() const { return _allocator; } aoqi@0: aoqi@0: // unified bailout support aoqi@0: void bailout(const char* msg) const { compilation()->bailout(msg); } aoqi@0: bool bailed_out() const { return compilation()->bailed_out(); } aoqi@0: aoqi@0: void check_bounds(IntervalKind kind) { assert(kind >= fixedKind && kind <= anyKind, "invalid interval_kind"); } aoqi@0: aoqi@0: Interval** unhandled_first_addr(IntervalKind kind) { check_bounds(kind); return &_unhandled_first[kind]; } aoqi@0: Interval** active_first_addr(IntervalKind kind) { check_bounds(kind); return &_active_first[kind]; } aoqi@0: Interval** inactive_first_addr(IntervalKind kind) { check_bounds(kind); return &_inactive_first[kind]; } aoqi@0: aoqi@0: void append_unsorted(Interval** first, Interval* interval); aoqi@0: void append_sorted(Interval** first, Interval* interval); aoqi@0: void append_to_unhandled(Interval** list, Interval* interval); aoqi@0: aoqi@0: bool remove_from_list(Interval** list, Interval* i); aoqi@0: void remove_from_list(Interval* i); aoqi@0: aoqi@0: void next_interval(); aoqi@0: Interval* current() const { return _current; } aoqi@0: IntervalKind current_kind() const { return _current_kind; } aoqi@0: aoqi@0: void walk_to(IntervalState state, int from); aoqi@0: aoqi@0: // activate_current() is called when an unhandled interval becomes active (in current(), current_kind()). aoqi@0: // Return false if current() should not be moved the the active interval list. aoqi@0: // It is safe to append current to any interval list but the unhandled list. aoqi@0: virtual bool activate_current() { return true; } aoqi@0: aoqi@0: // interval_moved() is called whenever an interval moves from one interval list to another. aoqi@0: // In the implementation of this method it is prohibited to move the interval to any list. aoqi@0: virtual void interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to); aoqi@0: aoqi@0: public: aoqi@0: IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first); aoqi@0: aoqi@0: Interval* unhandled_first(IntervalKind kind) { check_bounds(kind); return _unhandled_first[kind]; } aoqi@0: Interval* active_first(IntervalKind kind) { check_bounds(kind); return _active_first[kind]; } aoqi@0: Interval* inactive_first(IntervalKind kind) { check_bounds(kind); return _inactive_first[kind]; } aoqi@0: aoqi@0: // active contains the intervals that are live after the lir_op aoqi@0: void walk_to(int lir_op_id); aoqi@0: // active contains the intervals that are live before the lir_op aoqi@0: void walk_before(int lir_op_id) { walk_to(lir_op_id-1); } aoqi@0: // walk through all intervals aoqi@0: void walk() { walk_to(max_jint); } aoqi@0: aoqi@0: int current_position() { return _current_position; } aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: // The actual linear scan register allocator aoqi@0: class LinearScanWalker : public IntervalWalker { aoqi@0: enum { aoqi@0: any_reg = LinearScan::any_reg aoqi@0: }; aoqi@0: aoqi@0: private: aoqi@0: int _first_reg; // the reg. number of the first phys. register aoqi@0: int _last_reg; // the reg. nmber of the last phys. register aoqi@0: int _num_phys_regs; // required by current interval aoqi@0: bool _adjacent_regs; // have lo/hi words of phys. regs be adjacent aoqi@0: aoqi@0: int _use_pos[LinearScan::nof_regs]; aoqi@0: int _block_pos[LinearScan::nof_regs]; aoqi@0: IntervalList* _spill_intervals[LinearScan::nof_regs]; aoqi@0: aoqi@0: MoveResolver _move_resolver; // for ordering spill moves aoqi@0: aoqi@0: // accessors mapped to same functions in class LinearScan aoqi@0: int block_count() const { return allocator()->block_count(); } aoqi@0: BlockBegin* block_at(int idx) const { return allocator()->block_at(idx); } aoqi@0: BlockBegin* block_of_op_with_id(int op_id) const { return allocator()->block_of_op_with_id(op_id); } aoqi@0: aoqi@0: void init_use_lists(bool only_process_use_pos); aoqi@0: void exclude_from_use(int reg); aoqi@0: void exclude_from_use(Interval* i); aoqi@0: void set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos); aoqi@0: void set_use_pos(Interval* i, int use_pos, bool only_process_use_pos); aoqi@0: void set_block_pos(int reg, Interval* i, int block_pos); aoqi@0: void set_block_pos(Interval* i, int block_pos); aoqi@0: aoqi@0: void free_exclude_active_fixed(); aoqi@0: void free_exclude_active_any(); aoqi@0: void free_collect_inactive_fixed(Interval* cur); aoqi@0: void free_collect_inactive_any(Interval* cur); aoqi@0: void free_collect_unhandled(IntervalKind kind, Interval* cur); aoqi@0: void spill_exclude_active_fixed(); aoqi@0: void spill_block_unhandled_fixed(Interval* cur); aoqi@0: void spill_block_inactive_fixed(Interval* cur); aoqi@0: void spill_collect_active_any(); aoqi@0: void spill_collect_inactive_any(Interval* cur); aoqi@0: aoqi@0: void insert_move(int op_id, Interval* src_it, Interval* dst_it); aoqi@0: int find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos); aoqi@0: int find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization); aoqi@0: void split_before_usage(Interval* it, int min_split_pos, int max_split_pos); aoqi@0: void split_for_spilling(Interval* it); aoqi@0: void split_stack_interval(Interval* it); aoqi@0: void split_when_partial_register_available(Interval* it, int register_available_until); aoqi@0: void split_and_spill_interval(Interval* it); aoqi@0: aoqi@0: int find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split); aoqi@0: int find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split); aoqi@0: bool alloc_free_reg(Interval* cur); aoqi@0: aoqi@0: int find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split); aoqi@0: int find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split); aoqi@0: void split_and_spill_intersecting_intervals(int reg, int regHi); aoqi@0: void alloc_locked_reg(Interval* cur); aoqi@0: aoqi@0: bool no_allocation_possible(Interval* cur); aoqi@0: void update_phys_reg_range(bool requires_cpu_register); aoqi@0: void init_vars_for_alloc(Interval* cur); aoqi@0: bool pd_init_regs_for_alloc(Interval* cur); aoqi@0: aoqi@0: void combine_spilled_intervals(Interval* cur); aoqi@0: bool is_move(LIR_Op* op, Interval* from, Interval* to); aoqi@0: aoqi@0: bool activate_current(); aoqi@0: aoqi@0: public: aoqi@0: LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first); aoqi@0: aoqi@0: // must be called when all intervals are allocated aoqi@0: void finish_allocation() { _move_resolver.resolve_and_append_moves(); } aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: aoqi@0: /* aoqi@0: When a block has more than one predecessor, and all predecessors end with aoqi@0: the same sequence of move-instructions, than this moves can be placed once aoqi@0: at the beginning of the block instead of multiple times in the predecessors. aoqi@0: aoqi@0: Similarly, when a block has more than one successor, then equal sequences of aoqi@0: moves at the beginning of the successors can be placed once at the end of aoqi@0: the block. But because the moves must be inserted before all branch aoqi@0: instructions, this works only when there is exactly one conditional branch aoqi@0: at the end of the block (because the moves must be inserted before all aoqi@0: branches, but after all compares). aoqi@0: aoqi@0: This optimization affects all kind of moves (reg->reg, reg->stack and aoqi@0: stack->reg). Because this optimization works best when a block contains only aoqi@0: few moves, it has a huge impact on the number of blocks that are totally aoqi@0: empty. aoqi@0: */ aoqi@0: class EdgeMoveOptimizer : public StackObj { aoqi@0: private: aoqi@0: // the class maintains a list with all lir-instruction-list of the aoqi@0: // successors (predecessors) and the current index into the lir-lists aoqi@0: LIR_OpListStack _edge_instructions; aoqi@0: intStack _edge_instructions_idx; aoqi@0: aoqi@0: void init_instructions(); aoqi@0: void append_instructions(LIR_OpList* instructions, int instructions_idx); aoqi@0: LIR_Op* instruction_at(int edge); aoqi@0: void remove_cur_instruction(int edge, bool decrement_index); aoqi@0: aoqi@0: bool operations_different(LIR_Op* op1, LIR_Op* op2); aoqi@0: aoqi@0: void optimize_moves_at_block_end(BlockBegin* cur); aoqi@0: void optimize_moves_at_block_begin(BlockBegin* cur); aoqi@0: aoqi@0: EdgeMoveOptimizer(); aoqi@0: aoqi@0: public: aoqi@0: static void optimize(BlockList* code); aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: aoqi@0: class ControlFlowOptimizer : public StackObj { aoqi@0: private: aoqi@0: BlockList _original_preds; aoqi@0: aoqi@0: enum { aoqi@0: ShortLoopSize = 5 aoqi@0: }; aoqi@0: void reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx); aoqi@0: void reorder_short_loops(BlockList* code); aoqi@0: aoqi@0: bool can_delete_block(BlockBegin* cur); aoqi@0: void substitute_branch_target(BlockBegin* cur, BlockBegin* target_from, BlockBegin* target_to); aoqi@0: void delete_empty_blocks(BlockList* code); aoqi@0: aoqi@0: void delete_unnecessary_jumps(BlockList* code); aoqi@0: void delete_jumps_to_return(BlockList* code); aoqi@0: aoqi@0: DEBUG_ONLY(void verify(BlockList* code);) aoqi@0: aoqi@0: ControlFlowOptimizer(); aoqi@0: public: aoqi@0: static void optimize(BlockList* code); aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: #ifndef PRODUCT aoqi@0: aoqi@0: // Helper class for collecting statistics of LinearScan aoqi@0: class LinearScanStatistic : public StackObj { aoqi@0: public: aoqi@0: enum Counter { aoqi@0: // general counters aoqi@0: counter_method, aoqi@0: counter_fpu_method, aoqi@0: counter_loop_method, aoqi@0: counter_exception_method, aoqi@0: counter_loop, aoqi@0: counter_block, aoqi@0: counter_loop_block, aoqi@0: counter_exception_block, aoqi@0: counter_interval, aoqi@0: counter_fixed_interval, aoqi@0: counter_range, aoqi@0: counter_fixed_range, aoqi@0: counter_use_pos, aoqi@0: counter_fixed_use_pos, aoqi@0: counter_spill_slots, aoqi@0: blank_line_1, aoqi@0: aoqi@0: // counter for classes of lir instructions aoqi@0: counter_instruction, aoqi@0: counter_label, aoqi@0: counter_entry, aoqi@0: counter_return, aoqi@0: counter_call, aoqi@0: counter_move, aoqi@0: counter_cmp, aoqi@0: counter_cond_branch, aoqi@0: counter_uncond_branch, aoqi@0: counter_stub_branch, aoqi@0: counter_alu, aoqi@0: counter_alloc, aoqi@0: counter_sync, aoqi@0: counter_throw, aoqi@0: counter_unwind, aoqi@0: counter_typecheck, aoqi@0: counter_fpu_stack, aoqi@0: counter_misc_inst, aoqi@0: counter_other_inst, aoqi@0: blank_line_2, aoqi@0: aoqi@0: // counter for different types of moves aoqi@0: counter_move_total, aoqi@0: counter_move_reg_reg, aoqi@0: counter_move_reg_stack, aoqi@0: counter_move_stack_reg, aoqi@0: counter_move_stack_stack, aoqi@0: counter_move_reg_mem, aoqi@0: counter_move_mem_reg, aoqi@0: counter_move_const_any, aoqi@0: aoqi@0: number_of_counters, aoqi@0: invalid_counter = -1 aoqi@0: }; aoqi@0: aoqi@0: private: aoqi@0: int _counters_sum[number_of_counters]; aoqi@0: int _counters_max[number_of_counters]; aoqi@0: aoqi@0: void inc_counter(Counter idx, int value = 1) { _counters_sum[idx] += value; } aoqi@0: aoqi@0: const char* counter_name(int counter_idx); aoqi@0: Counter base_counter(int counter_idx); aoqi@0: aoqi@0: void sum_up(LinearScanStatistic &method_statistic); aoqi@0: void collect(LinearScan* allocator); aoqi@0: aoqi@0: public: aoqi@0: LinearScanStatistic(); aoqi@0: void print(const char* title); aoqi@0: static void compute(LinearScan* allocator, LinearScanStatistic &global_statistic); aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: // Helper class for collecting compilation time of LinearScan aoqi@0: class LinearScanTimers : public StackObj { aoqi@0: public: aoqi@0: enum Timer { aoqi@0: timer_do_nothing, aoqi@0: timer_number_instructions, aoqi@0: timer_compute_local_live_sets, aoqi@0: timer_compute_global_live_sets, aoqi@0: timer_build_intervals, aoqi@0: timer_sort_intervals_before, aoqi@0: timer_allocate_registers, aoqi@0: timer_resolve_data_flow, aoqi@0: timer_sort_intervals_after, aoqi@0: timer_eliminate_spill_moves, aoqi@0: timer_assign_reg_num, aoqi@0: timer_allocate_fpu_stack, aoqi@0: timer_optimize_lir, aoqi@0: aoqi@0: number_of_timers aoqi@0: }; aoqi@0: aoqi@0: private: aoqi@0: elapsedTimer _timers[number_of_timers]; aoqi@0: const char* timer_name(int idx); aoqi@0: aoqi@0: public: aoqi@0: LinearScanTimers(); aoqi@0: aoqi@0: void begin_method(); // called for each method when register allocation starts aoqi@0: void end_method(LinearScan* allocator); // called for each method when register allocation completed aoqi@0: void print(double total_time); // called before termination of VM to print global summary aoqi@0: aoqi@0: elapsedTimer* timer(int idx) { return &(_timers[idx]); } aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: #endif // ifndef PRODUCT aoqi@0: aoqi@0: aoqi@0: // Pick up platform-dependent implementation details aoqi@0: #ifdef TARGET_ARCH_x86 aoqi@0: # include "c1_LinearScan_x86.hpp" aoqi@0: #endif aoqi@1: #ifdef TARGET_ARCH_mips aoqi@1: # include "c1_LinearScan_mips.hpp" aoqi@1: #endif aoqi@0: #ifdef TARGET_ARCH_sparc aoqi@0: # include "c1_LinearScan_sparc.hpp" aoqi@0: #endif aoqi@0: #ifdef TARGET_ARCH_arm aoqi@0: # include "c1_LinearScan_arm.hpp" aoqi@0: #endif aoqi@0: #ifdef TARGET_ARCH_ppc aoqi@0: # include "c1_LinearScan_ppc.hpp" aoqi@0: #endif aoqi@0: aoqi@0: aoqi@0: #endif // SHARE_VM_C1_C1_LINEARSCAN_HPP