Fri, 29 Apr 2011 11:15:30 -0700
Merge
duke@435 | 1 | /* |
iveresov@2441 | 2 | * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
stefank@2314 | 25 | #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP |
stefank@2314 | 26 | #define CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP |
stefank@2314 | 27 | |
stefank@2314 | 28 | #include "asm/assembler.inline.hpp" |
stefank@2314 | 29 | #include "asm/codeBuffer.hpp" |
stefank@2314 | 30 | #include "code/codeCache.hpp" |
stefank@2314 | 31 | #include "runtime/handles.inline.hpp" |
stefank@2314 | 32 | |
duke@435 | 33 | inline void MacroAssembler::pd_patch_instruction(address branch, address target) { |
duke@435 | 34 | jint& stub_inst = *(jint*) branch; |
duke@435 | 35 | stub_inst = patched_branch(target - branch, stub_inst, 0); |
duke@435 | 36 | } |
duke@435 | 37 | |
duke@435 | 38 | #ifndef PRODUCT |
duke@435 | 39 | inline void MacroAssembler::pd_print_patched_instruction(address branch) { |
duke@435 | 40 | jint stub_inst = *(jint*) branch; |
duke@435 | 41 | print_instruction(stub_inst); |
duke@435 | 42 | ::tty->print("%s", " (unresolved)"); |
duke@435 | 43 | } |
duke@435 | 44 | #endif // PRODUCT |
duke@435 | 45 | |
duke@435 | 46 | inline bool Address::is_simm13(int offset) { return Assembler::is_simm13(disp() + offset); } |
duke@435 | 47 | |
duke@435 | 48 | |
twisti@1162 | 49 | inline int AddressLiteral::low10() const { |
twisti@1162 | 50 | return Assembler::low10(value()); |
twisti@1162 | 51 | } |
twisti@1162 | 52 | |
twisti@1162 | 53 | |
duke@435 | 54 | // inlines for SPARC assembler -- dmu 5/97 |
duke@435 | 55 | |
duke@435 | 56 | inline void Assembler::check_delay() { |
duke@435 | 57 | # ifdef CHECK_DELAY |
duke@435 | 58 | guarantee( delay_state != at_delay_slot, "must say delayed() when filling delay slot"); |
duke@435 | 59 | delay_state = no_delay; |
duke@435 | 60 | # endif |
duke@435 | 61 | } |
duke@435 | 62 | |
duke@435 | 63 | inline void Assembler::emit_long(int x) { |
duke@435 | 64 | check_delay(); |
duke@435 | 65 | AbstractAssembler::emit_long(x); |
duke@435 | 66 | } |
duke@435 | 67 | |
duke@435 | 68 | inline void Assembler::emit_data(int x, relocInfo::relocType rtype) { |
duke@435 | 69 | relocate(rtype); |
duke@435 | 70 | emit_long(x); |
duke@435 | 71 | } |
duke@435 | 72 | |
duke@435 | 73 | inline void Assembler::emit_data(int x, RelocationHolder const& rspec) { |
duke@435 | 74 | relocate(rspec); |
duke@435 | 75 | emit_long(x); |
duke@435 | 76 | } |
duke@435 | 77 | |
duke@435 | 78 | |
twisti@1162 | 79 | inline void Assembler::add(Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2) ); } |
twisti@1162 | 80 | inline void Assembler::add(Register s1, int simm13a, Register d, relocInfo::relocType rtype ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rtype ); } |
twisti@1162 | 81 | inline void Assembler::add(Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec ); } |
duke@435 | 82 | |
duke@435 | 83 | inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt); has_delay_slot(); } |
duke@435 | 84 | inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, Label& L) { bpr( c, a, p, s1, target(L)); } |
duke@435 | 85 | |
duke@435 | 86 | inline void Assembler::fb( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); } |
duke@435 | 87 | inline void Assembler::fb( Condition c, bool a, Label& L ) { fb(c, a, target(L)); } |
duke@435 | 88 | |
duke@435 | 89 | inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); } |
duke@435 | 90 | inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { fbp(c, a, cc, p, target(L)); } |
duke@435 | 91 | |
duke@435 | 92 | inline void Assembler::cb( Condition c, bool a, address d, relocInfo::relocType rt ) { v8_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(cb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); } |
duke@435 | 93 | inline void Assembler::cb( Condition c, bool a, Label& L ) { cb(c, a, target(L)); } |
duke@435 | 94 | |
duke@435 | 95 | inline void Assembler::br( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); } |
duke@435 | 96 | inline void Assembler::br( Condition c, bool a, Label& L ) { br(c, a, target(L)); } |
duke@435 | 97 | |
duke@435 | 98 | inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); } |
duke@435 | 99 | inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { bp(c, a, cc, p, target(L)); } |
duke@435 | 100 | |
duke@435 | 101 | inline void Assembler::call( address d, relocInfo::relocType rt ) { emit_data( op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt); has_delay_slot(); assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); } |
duke@435 | 102 | inline void Assembler::call( Label& L, relocInfo::relocType rt ) { call( target(L), rt); } |
duke@435 | 103 | |
duke@435 | 104 | inline void Assembler::flush( Register s1, Register s2) { emit_long( op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); } |
duke@435 | 105 | inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 106 | |
duke@435 | 107 | inline void Assembler::jmpl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); } |
duke@435 | 108 | inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); has_delay_slot(); } |
duke@435 | 109 | |
twisti@1441 | 110 | inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d) { |
twisti@1441 | 111 | if (s2.is_register()) ldf(w, s1, s2.as_register(), d); |
twisti@1441 | 112 | else ldf(w, s1, s2.as_constant(), d); |
twisti@1441 | 113 | } |
twisti@1441 | 114 | |
twisti@1162 | 115 | inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2) ); } |
twisti@1162 | 116 | inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); } |
duke@435 | 117 | |
twisti@1162 | 118 | inline void Assembler::ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset) { relocate(a.rspec(offset)); ldf( w, a.base(), a.disp() + offset, d); } |
duke@435 | 119 | |
duke@435 | 120 | inline void Assembler::ldfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 121 | inline void Assembler::ldfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 122 | inline void Assembler::ldxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 123 | inline void Assembler::ldxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 124 | |
duke@435 | 125 | inline void Assembler::ldc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | rs2(s2) ); } |
duke@435 | 126 | inline void Assembler::ldc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 127 | inline void Assembler::lddc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | rs2(s2) ); } |
duke@435 | 128 | inline void Assembler::lddc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 129 | inline void Assembler::ldcsr( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 130 | inline void Assembler::ldcsr( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 131 | |
duke@435 | 132 | inline void Assembler::ldsb( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 133 | inline void Assembler::ldsb( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 134 | |
duke@435 | 135 | inline void Assembler::ldsh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 136 | inline void Assembler::ldsh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 137 | inline void Assembler::ldsw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 138 | inline void Assembler::ldsw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 139 | inline void Assembler::ldub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 140 | inline void Assembler::ldub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 141 | inline void Assembler::lduh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 142 | inline void Assembler::lduh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 143 | inline void Assembler::lduw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 144 | inline void Assembler::lduw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 145 | |
duke@435 | 146 | inline void Assembler::ldx( Register s1, Register s2, Register d) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 147 | inline void Assembler::ldx( Register s1, int simm13a, Register d) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 148 | inline void Assembler::ldd( Register s1, Register s2, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 149 | inline void Assembler::ldd( Register s1, int simm13a, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 150 | |
duke@435 | 151 | #ifdef _LP64 |
duke@435 | 152 | // Make all 32 bit loads signed so 64 bit registers maintain proper sign |
twisti@1162 | 153 | inline void Assembler::ld( Register s1, Register s2, Register d) { ldsw( s1, s2, d); } |
twisti@1162 | 154 | inline void Assembler::ld( Register s1, int simm13a, Register d) { ldsw( s1, simm13a, d); } |
duke@435 | 155 | #else |
twisti@1162 | 156 | inline void Assembler::ld( Register s1, Register s2, Register d) { lduw( s1, s2, d); } |
twisti@1162 | 157 | inline void Assembler::ld( Register s1, int simm13a, Register d) { lduw( s1, simm13a, d); } |
duke@435 | 158 | #endif |
duke@435 | 159 | |
twisti@1162 | 160 | #ifdef ASSERT |
twisti@1162 | 161 | // ByteSize is only a class when ASSERT is defined, otherwise it's an int. |
twisti@1162 | 162 | # ifdef _LP64 |
twisti@1162 | 163 | inline void Assembler::ld( Register s1, ByteSize simm13a, Register d) { ldsw( s1, in_bytes(simm13a), d); } |
twisti@1162 | 164 | # else |
twisti@1162 | 165 | inline void Assembler::ld( Register s1, ByteSize simm13a, Register d) { lduw( s1, in_bytes(simm13a), d); } |
twisti@1162 | 166 | # endif |
twisti@1162 | 167 | #endif |
twisti@1162 | 168 | |
twisti@1162 | 169 | inline void Assembler::ld( const Address& a, Register d, int offset) { |
twisti@1162 | 170 | if (a.has_index()) { assert(offset == 0, ""); ld( a.base(), a.index(), d); } |
twisti@1162 | 171 | else { ld( a.base(), a.disp() + offset, d); } |
jrose@1057 | 172 | } |
twisti@1162 | 173 | inline void Assembler::ldsb(const Address& a, Register d, int offset) { |
twisti@1162 | 174 | if (a.has_index()) { assert(offset == 0, ""); ldsb(a.base(), a.index(), d); } |
twisti@1162 | 175 | else { ldsb(a.base(), a.disp() + offset, d); } |
jrose@1057 | 176 | } |
twisti@1162 | 177 | inline void Assembler::ldsh(const Address& a, Register d, int offset) { |
twisti@1162 | 178 | if (a.has_index()) { assert(offset == 0, ""); ldsh(a.base(), a.index(), d); } |
twisti@1162 | 179 | else { ldsh(a.base(), a.disp() + offset, d); } |
jrose@1057 | 180 | } |
twisti@1162 | 181 | inline void Assembler::ldsw(const Address& a, Register d, int offset) { |
twisti@1162 | 182 | if (a.has_index()) { assert(offset == 0, ""); ldsw(a.base(), a.index(), d); } |
twisti@1162 | 183 | else { ldsw(a.base(), a.disp() + offset, d); } |
jrose@1057 | 184 | } |
twisti@1162 | 185 | inline void Assembler::ldub(const Address& a, Register d, int offset) { |
twisti@1162 | 186 | if (a.has_index()) { assert(offset == 0, ""); ldub(a.base(), a.index(), d); } |
twisti@1162 | 187 | else { ldub(a.base(), a.disp() + offset, d); } |
jrose@1057 | 188 | } |
twisti@1162 | 189 | inline void Assembler::lduh(const Address& a, Register d, int offset) { |
twisti@1162 | 190 | if (a.has_index()) { assert(offset == 0, ""); lduh(a.base(), a.index(), d); } |
twisti@1162 | 191 | else { lduh(a.base(), a.disp() + offset, d); } |
jrose@1057 | 192 | } |
twisti@1162 | 193 | inline void Assembler::lduw(const Address& a, Register d, int offset) { |
twisti@1162 | 194 | if (a.has_index()) { assert(offset == 0, ""); lduw(a.base(), a.index(), d); } |
twisti@1162 | 195 | else { lduw(a.base(), a.disp() + offset, d); } |
jrose@1057 | 196 | } |
twisti@1162 | 197 | inline void Assembler::ldd( const Address& a, Register d, int offset) { |
twisti@1162 | 198 | if (a.has_index()) { assert(offset == 0, ""); ldd( a.base(), a.index(), d); } |
twisti@1162 | 199 | else { ldd( a.base(), a.disp() + offset, d); } |
jrose@1057 | 200 | } |
twisti@1162 | 201 | inline void Assembler::ldx( const Address& a, Register d, int offset) { |
twisti@1162 | 202 | if (a.has_index()) { assert(offset == 0, ""); ldx( a.base(), a.index(), d); } |
twisti@1162 | 203 | else { ldx( a.base(), a.disp() + offset, d); } |
jrose@1057 | 204 | } |
jrose@1057 | 205 | |
twisti@1162 | 206 | inline void Assembler::ldub(Register s1, RegisterOrConstant s2, Register d) { ldub(Address(s1, s2), d); } |
twisti@1162 | 207 | inline void Assembler::ldsb(Register s1, RegisterOrConstant s2, Register d) { ldsb(Address(s1, s2), d); } |
twisti@1162 | 208 | inline void Assembler::lduh(Register s1, RegisterOrConstant s2, Register d) { lduh(Address(s1, s2), d); } |
twisti@1162 | 209 | inline void Assembler::ldsh(Register s1, RegisterOrConstant s2, Register d) { ldsh(Address(s1, s2), d); } |
twisti@1162 | 210 | inline void Assembler::lduw(Register s1, RegisterOrConstant s2, Register d) { lduw(Address(s1, s2), d); } |
twisti@1162 | 211 | inline void Assembler::ldsw(Register s1, RegisterOrConstant s2, Register d) { ldsw(Address(s1, s2), d); } |
twisti@1162 | 212 | inline void Assembler::ldx( Register s1, RegisterOrConstant s2, Register d) { ldx( Address(s1, s2), d); } |
twisti@1162 | 213 | inline void Assembler::ld( Register s1, RegisterOrConstant s2, Register d) { ld( Address(s1, s2), d); } |
twisti@1162 | 214 | inline void Assembler::ldd( Register s1, RegisterOrConstant s2, Register d) { ldd( Address(s1, s2), d); } |
twisti@1162 | 215 | |
jrose@1057 | 216 | // form effective addresses this way: |
jrose@2266 | 217 | inline void Assembler::add(const Address& a, Register d, int offset) { |
jrose@2266 | 218 | if (a.has_index()) add(a.base(), a.index(), d); |
jrose@2266 | 219 | else { add(a.base(), a.disp() + offset, d, a.rspec(offset)); offset = 0; } |
jrose@2266 | 220 | if (offset != 0) add(d, offset, d); |
jrose@2266 | 221 | } |
twisti@1858 | 222 | inline void Assembler::add(Register s1, RegisterOrConstant s2, Register d, int offset) { |
twisti@1858 | 223 | if (s2.is_register()) add(s1, s2.as_register(), d); |
jrose@1057 | 224 | else { add(s1, s2.as_constant() + offset, d); offset = 0; } |
jrose@1057 | 225 | if (offset != 0) add(d, offset, d); |
jrose@1057 | 226 | } |
duke@435 | 227 | |
twisti@1858 | 228 | inline void Assembler::andn(Register s1, RegisterOrConstant s2, Register d) { |
twisti@1858 | 229 | if (s2.is_register()) andn(s1, s2.as_register(), d); |
twisti@1858 | 230 | else andn(s1, s2.as_constant(), d); |
twisti@1858 | 231 | } |
twisti@1858 | 232 | |
duke@435 | 233 | inline void Assembler::ldstub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 234 | inline void Assembler::ldstub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 235 | |
duke@435 | 236 | |
duke@435 | 237 | inline void Assembler::prefetch(Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 238 | inline void Assembler::prefetch(Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 239 | |
duke@435 | 240 | inline void Assembler::prefetch(const Address& a, PrefetchFcn f, int offset) { v9_only(); relocate(a.rspec(offset)); prefetch(a.base(), a.disp() + offset, f); } |
duke@435 | 241 | |
duke@435 | 242 | |
duke@435 | 243 | inline void Assembler::rett( Register s1, Register s2 ) { emit_long( op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); } |
duke@435 | 244 | inline void Assembler::rett( Register s1, int simm13a, relocInfo::relocType rt) { emit_data( op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt); has_delay_slot(); } |
duke@435 | 245 | |
duke@435 | 246 | inline void Assembler::sethi( int imm22a, Register d, RelocationHolder const& rspec ) { emit_data( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec); } |
duke@435 | 247 | |
duke@435 | 248 | // pp 222 |
duke@435 | 249 | |
twisti@1441 | 250 | inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2) { |
twisti@1441 | 251 | if (s2.is_register()) stf(w, d, s1, s2.as_register()); |
twisti@1441 | 252 | else stf(w, d, s1, s2.as_constant()); |
twisti@1441 | 253 | } |
twisti@1441 | 254 | |
duke@435 | 255 | inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2) ); } |
duke@435 | 256 | inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 257 | |
duke@435 | 258 | inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset) { relocate(a.rspec(offset)); stf(w, d, a.base(), a.disp() + offset); } |
duke@435 | 259 | |
duke@435 | 260 | inline void Assembler::stfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 261 | inline void Assembler::stfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 262 | inline void Assembler::stxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 263 | inline void Assembler::stxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 264 | |
duke@435 | 265 | // p 226 |
duke@435 | 266 | |
duke@435 | 267 | inline void Assembler::stb( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 268 | inline void Assembler::stb( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 269 | inline void Assembler::sth( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 270 | inline void Assembler::sth( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 271 | inline void Assembler::stw( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 272 | inline void Assembler::stw( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 273 | |
duke@435 | 274 | |
duke@435 | 275 | inline void Assembler::stx( Register d, Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 276 | inline void Assembler::stx( Register d, Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 277 | inline void Assembler::std( Register d, Register s1, Register s2) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 278 | inline void Assembler::std( Register d, Register s1, int simm13a) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 279 | |
twisti@1162 | 280 | inline void Assembler::st( Register d, Register s1, Register s2) { stw(d, s1, s2); } |
twisti@1162 | 281 | inline void Assembler::st( Register d, Register s1, int simm13a) { stw(d, s1, simm13a); } |
duke@435 | 282 | |
twisti@1162 | 283 | #ifdef ASSERT |
twisti@1162 | 284 | // ByteSize is only a class when ASSERT is defined, otherwise it's an int. |
twisti@1162 | 285 | inline void Assembler::st( Register d, Register s1, ByteSize simm13a) { stw(d, s1, in_bytes(simm13a)); } |
twisti@1162 | 286 | #endif |
twisti@1162 | 287 | |
twisti@1162 | 288 | inline void Assembler::stb(Register d, const Address& a, int offset) { |
twisti@1162 | 289 | if (a.has_index()) { assert(offset == 0, ""); stb(d, a.base(), a.index() ); } |
twisti@1162 | 290 | else { stb(d, a.base(), a.disp() + offset); } |
jrose@1057 | 291 | } |
twisti@1162 | 292 | inline void Assembler::sth(Register d, const Address& a, int offset) { |
twisti@1162 | 293 | if (a.has_index()) { assert(offset == 0, ""); sth(d, a.base(), a.index() ); } |
twisti@1162 | 294 | else { sth(d, a.base(), a.disp() + offset); } |
jrose@1057 | 295 | } |
twisti@1162 | 296 | inline void Assembler::stw(Register d, const Address& a, int offset) { |
twisti@1162 | 297 | if (a.has_index()) { assert(offset == 0, ""); stw(d, a.base(), a.index() ); } |
twisti@1162 | 298 | else { stw(d, a.base(), a.disp() + offset); } |
jrose@1057 | 299 | } |
twisti@1162 | 300 | inline void Assembler::st( Register d, const Address& a, int offset) { |
twisti@1162 | 301 | if (a.has_index()) { assert(offset == 0, ""); st( d, a.base(), a.index() ); } |
twisti@1162 | 302 | else { st( d, a.base(), a.disp() + offset); } |
jrose@1057 | 303 | } |
twisti@1162 | 304 | inline void Assembler::std(Register d, const Address& a, int offset) { |
twisti@1162 | 305 | if (a.has_index()) { assert(offset == 0, ""); std(d, a.base(), a.index() ); } |
twisti@1162 | 306 | else { std(d, a.base(), a.disp() + offset); } |
twisti@1162 | 307 | } |
twisti@1162 | 308 | inline void Assembler::stx(Register d, const Address& a, int offset) { |
twisti@1162 | 309 | if (a.has_index()) { assert(offset == 0, ""); stx(d, a.base(), a.index() ); } |
twisti@1162 | 310 | else { stx(d, a.base(), a.disp() + offset); } |
jrose@1057 | 311 | } |
jrose@1057 | 312 | |
twisti@1162 | 313 | inline void Assembler::stb(Register d, Register s1, RegisterOrConstant s2) { stb(d, Address(s1, s2)); } |
twisti@1162 | 314 | inline void Assembler::sth(Register d, Register s1, RegisterOrConstant s2) { sth(d, Address(s1, s2)); } |
twisti@1441 | 315 | inline void Assembler::stw(Register d, Register s1, RegisterOrConstant s2) { stw(d, Address(s1, s2)); } |
twisti@1162 | 316 | inline void Assembler::stx(Register d, Register s1, RegisterOrConstant s2) { stx(d, Address(s1, s2)); } |
twisti@1162 | 317 | inline void Assembler::std(Register d, Register s1, RegisterOrConstant s2) { std(d, Address(s1, s2)); } |
twisti@1162 | 318 | inline void Assembler::st( Register d, Register s1, RegisterOrConstant s2) { st( d, Address(s1, s2)); } |
duke@435 | 319 | |
duke@435 | 320 | // v8 p 99 |
duke@435 | 321 | |
duke@435 | 322 | inline void Assembler::stc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | rs2(s2) ); } |
duke@435 | 323 | inline void Assembler::stc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 324 | inline void Assembler::stdc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 325 | inline void Assembler::stdc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 326 | inline void Assembler::stcsr( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 327 | inline void Assembler::stcsr( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 328 | inline void Assembler::stdcq( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 329 | inline void Assembler::stdcq( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 330 | |
twisti@2350 | 331 | inline void Assembler::sub(Register s1, RegisterOrConstant s2, Register d, int offset) { |
twisti@2350 | 332 | if (s2.is_register()) sub(s1, s2.as_register(), d); |
twisti@2350 | 333 | else { sub(s1, s2.as_constant() + offset, d); offset = 0; } |
twisti@2350 | 334 | if (offset != 0) sub(d, offset, d); |
twisti@2350 | 335 | } |
duke@435 | 336 | |
duke@435 | 337 | // pp 231 |
duke@435 | 338 | |
duke@435 | 339 | inline void Assembler::swap( Register s1, Register s2, Register d) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 340 | inline void Assembler::swap( Register s1, int simm13a, Register d) { v9_dep(); emit_data( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 341 | |
duke@435 | 342 | inline void Assembler::swap( Address& a, Register d, int offset ) { relocate(a.rspec(offset)); swap( a.base(), a.disp() + offset, d ); } |
duke@435 | 343 | |
duke@435 | 344 | |
duke@435 | 345 | // Use the right loads/stores for the platform |
duke@435 | 346 | inline void MacroAssembler::ld_ptr( Register s1, Register s2, Register d ) { |
duke@435 | 347 | #ifdef _LP64 |
twisti@1162 | 348 | Assembler::ldx(s1, s2, d); |
duke@435 | 349 | #else |
twisti@1162 | 350 | Assembler::ld( s1, s2, d); |
duke@435 | 351 | #endif |
duke@435 | 352 | } |
duke@435 | 353 | |
duke@435 | 354 | inline void MacroAssembler::ld_ptr( Register s1, int simm13a, Register d ) { |
duke@435 | 355 | #ifdef _LP64 |
twisti@1162 | 356 | Assembler::ldx(s1, simm13a, d); |
duke@435 | 357 | #else |
twisti@1162 | 358 | Assembler::ld( s1, simm13a, d); |
duke@435 | 359 | #endif |
duke@435 | 360 | } |
duke@435 | 361 | |
twisti@1162 | 362 | #ifdef ASSERT |
twisti@1162 | 363 | // ByteSize is only a class when ASSERT is defined, otherwise it's an int. |
twisti@1162 | 364 | inline void MacroAssembler::ld_ptr( Register s1, ByteSize simm13a, Register d ) { |
twisti@1162 | 365 | ld_ptr(s1, in_bytes(simm13a), d); |
twisti@1162 | 366 | } |
twisti@1162 | 367 | #endif |
twisti@1162 | 368 | |
jrose@1100 | 369 | inline void MacroAssembler::ld_ptr( Register s1, RegisterOrConstant s2, Register d ) { |
jrose@1057 | 370 | #ifdef _LP64 |
twisti@1162 | 371 | Assembler::ldx(s1, s2, d); |
jrose@1057 | 372 | #else |
twisti@1162 | 373 | Assembler::ld( s1, s2, d); |
jrose@1057 | 374 | #endif |
jrose@1057 | 375 | } |
jrose@1057 | 376 | |
twisti@1162 | 377 | inline void MacroAssembler::ld_ptr(const Address& a, Register d, int offset) { |
duke@435 | 378 | #ifdef _LP64 |
twisti@1162 | 379 | Assembler::ldx(a, d, offset); |
duke@435 | 380 | #else |
twisti@1162 | 381 | Assembler::ld( a, d, offset); |
duke@435 | 382 | #endif |
duke@435 | 383 | } |
duke@435 | 384 | |
duke@435 | 385 | inline void MacroAssembler::st_ptr( Register d, Register s1, Register s2 ) { |
duke@435 | 386 | #ifdef _LP64 |
twisti@1162 | 387 | Assembler::stx(d, s1, s2); |
duke@435 | 388 | #else |
duke@435 | 389 | Assembler::st( d, s1, s2); |
duke@435 | 390 | #endif |
duke@435 | 391 | } |
duke@435 | 392 | |
duke@435 | 393 | inline void MacroAssembler::st_ptr( Register d, Register s1, int simm13a ) { |
duke@435 | 394 | #ifdef _LP64 |
twisti@1162 | 395 | Assembler::stx(d, s1, simm13a); |
duke@435 | 396 | #else |
duke@435 | 397 | Assembler::st( d, s1, simm13a); |
duke@435 | 398 | #endif |
duke@435 | 399 | } |
duke@435 | 400 | |
twisti@1162 | 401 | #ifdef ASSERT |
twisti@1162 | 402 | // ByteSize is only a class when ASSERT is defined, otherwise it's an int. |
twisti@1162 | 403 | inline void MacroAssembler::st_ptr( Register d, Register s1, ByteSize simm13a ) { |
twisti@1162 | 404 | st_ptr(d, s1, in_bytes(simm13a)); |
twisti@1162 | 405 | } |
twisti@1162 | 406 | #endif |
twisti@1162 | 407 | |
jrose@1100 | 408 | inline void MacroAssembler::st_ptr( Register d, Register s1, RegisterOrConstant s2 ) { |
jrose@1057 | 409 | #ifdef _LP64 |
twisti@1162 | 410 | Assembler::stx(d, s1, s2); |
jrose@1057 | 411 | #else |
jrose@1057 | 412 | Assembler::st( d, s1, s2); |
jrose@1057 | 413 | #endif |
jrose@1057 | 414 | } |
jrose@1057 | 415 | |
twisti@1162 | 416 | inline void MacroAssembler::st_ptr(Register d, const Address& a, int offset) { |
duke@435 | 417 | #ifdef _LP64 |
twisti@1162 | 418 | Assembler::stx(d, a, offset); |
duke@435 | 419 | #else |
twisti@1162 | 420 | Assembler::st( d, a, offset); |
duke@435 | 421 | #endif |
duke@435 | 422 | } |
duke@435 | 423 | |
duke@435 | 424 | // Use the right loads/stores for the platform |
duke@435 | 425 | inline void MacroAssembler::ld_long( Register s1, Register s2, Register d ) { |
duke@435 | 426 | #ifdef _LP64 |
duke@435 | 427 | Assembler::ldx(s1, s2, d); |
duke@435 | 428 | #else |
duke@435 | 429 | Assembler::ldd(s1, s2, d); |
duke@435 | 430 | #endif |
duke@435 | 431 | } |
duke@435 | 432 | |
duke@435 | 433 | inline void MacroAssembler::ld_long( Register s1, int simm13a, Register d ) { |
duke@435 | 434 | #ifdef _LP64 |
duke@435 | 435 | Assembler::ldx(s1, simm13a, d); |
duke@435 | 436 | #else |
duke@435 | 437 | Assembler::ldd(s1, simm13a, d); |
duke@435 | 438 | #endif |
duke@435 | 439 | } |
duke@435 | 440 | |
jrose@1100 | 441 | inline void MacroAssembler::ld_long( Register s1, RegisterOrConstant s2, Register d ) { |
jrose@1057 | 442 | #ifdef _LP64 |
jrose@1057 | 443 | Assembler::ldx(s1, s2, d); |
jrose@1057 | 444 | #else |
jrose@1057 | 445 | Assembler::ldd(s1, s2, d); |
jrose@1057 | 446 | #endif |
jrose@1057 | 447 | } |
jrose@1057 | 448 | |
twisti@1162 | 449 | inline void MacroAssembler::ld_long(const Address& a, Register d, int offset) { |
duke@435 | 450 | #ifdef _LP64 |
twisti@1162 | 451 | Assembler::ldx(a, d, offset); |
duke@435 | 452 | #else |
twisti@1162 | 453 | Assembler::ldd(a, d, offset); |
duke@435 | 454 | #endif |
duke@435 | 455 | } |
duke@435 | 456 | |
duke@435 | 457 | inline void MacroAssembler::st_long( Register d, Register s1, Register s2 ) { |
duke@435 | 458 | #ifdef _LP64 |
duke@435 | 459 | Assembler::stx(d, s1, s2); |
duke@435 | 460 | #else |
duke@435 | 461 | Assembler::std(d, s1, s2); |
duke@435 | 462 | #endif |
duke@435 | 463 | } |
duke@435 | 464 | |
duke@435 | 465 | inline void MacroAssembler::st_long( Register d, Register s1, int simm13a ) { |
duke@435 | 466 | #ifdef _LP64 |
duke@435 | 467 | Assembler::stx(d, s1, simm13a); |
duke@435 | 468 | #else |
duke@435 | 469 | Assembler::std(d, s1, simm13a); |
duke@435 | 470 | #endif |
duke@435 | 471 | } |
duke@435 | 472 | |
jrose@1100 | 473 | inline void MacroAssembler::st_long( Register d, Register s1, RegisterOrConstant s2 ) { |
jrose@1057 | 474 | #ifdef _LP64 |
jrose@1057 | 475 | Assembler::stx(d, s1, s2); |
jrose@1057 | 476 | #else |
jrose@1057 | 477 | Assembler::std(d, s1, s2); |
jrose@1057 | 478 | #endif |
jrose@1057 | 479 | } |
jrose@1057 | 480 | |
duke@435 | 481 | inline void MacroAssembler::st_long( Register d, const Address& a, int offset ) { |
duke@435 | 482 | #ifdef _LP64 |
duke@435 | 483 | Assembler::stx(d, a, offset); |
duke@435 | 484 | #else |
duke@435 | 485 | Assembler::std(d, a, offset); |
duke@435 | 486 | #endif |
duke@435 | 487 | } |
duke@435 | 488 | |
duke@435 | 489 | // Functions for isolating 64 bit shifts for LP64 |
duke@435 | 490 | |
duke@435 | 491 | inline void MacroAssembler::sll_ptr( Register s1, Register s2, Register d ) { |
duke@435 | 492 | #ifdef _LP64 |
duke@435 | 493 | Assembler::sllx(s1, s2, d); |
duke@435 | 494 | #else |
twisti@1162 | 495 | Assembler::sll( s1, s2, d); |
duke@435 | 496 | #endif |
duke@435 | 497 | } |
duke@435 | 498 | |
duke@435 | 499 | inline void MacroAssembler::sll_ptr( Register s1, int imm6a, Register d ) { |
duke@435 | 500 | #ifdef _LP64 |
duke@435 | 501 | Assembler::sllx(s1, imm6a, d); |
duke@435 | 502 | #else |
twisti@1162 | 503 | Assembler::sll( s1, imm6a, d); |
duke@435 | 504 | #endif |
duke@435 | 505 | } |
duke@435 | 506 | |
duke@435 | 507 | inline void MacroAssembler::srl_ptr( Register s1, Register s2, Register d ) { |
duke@435 | 508 | #ifdef _LP64 |
duke@435 | 509 | Assembler::srlx(s1, s2, d); |
duke@435 | 510 | #else |
twisti@1162 | 511 | Assembler::srl( s1, s2, d); |
duke@435 | 512 | #endif |
duke@435 | 513 | } |
duke@435 | 514 | |
duke@435 | 515 | inline void MacroAssembler::srl_ptr( Register s1, int imm6a, Register d ) { |
duke@435 | 516 | #ifdef _LP64 |
duke@435 | 517 | Assembler::srlx(s1, imm6a, d); |
duke@435 | 518 | #else |
twisti@1162 | 519 | Assembler::srl( s1, imm6a, d); |
duke@435 | 520 | #endif |
duke@435 | 521 | } |
duke@435 | 522 | |
jrose@1100 | 523 | inline void MacroAssembler::sll_ptr( Register s1, RegisterOrConstant s2, Register d ) { |
jrose@1058 | 524 | if (s2.is_register()) sll_ptr(s1, s2.as_register(), d); |
jrose@1058 | 525 | else sll_ptr(s1, s2.as_constant(), d); |
jrose@1058 | 526 | } |
jrose@1058 | 527 | |
duke@435 | 528 | // Use the right branch for the platform |
duke@435 | 529 | |
duke@435 | 530 | inline void MacroAssembler::br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) { |
duke@435 | 531 | if (VM_Version::v9_instructions_work()) |
duke@435 | 532 | Assembler::bp(c, a, icc, p, d, rt); |
duke@435 | 533 | else |
duke@435 | 534 | Assembler::br(c, a, d, rt); |
duke@435 | 535 | } |
duke@435 | 536 | |
duke@435 | 537 | inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) { |
duke@435 | 538 | br(c, a, p, target(L)); |
duke@435 | 539 | } |
duke@435 | 540 | |
duke@435 | 541 | |
duke@435 | 542 | // Branch that tests either xcc or icc depending on the |
duke@435 | 543 | // architecture compiled (LP64 or not) |
duke@435 | 544 | inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) { |
duke@435 | 545 | #ifdef _LP64 |
duke@435 | 546 | Assembler::bp(c, a, xcc, p, d, rt); |
duke@435 | 547 | #else |
duke@435 | 548 | MacroAssembler::br(c, a, p, d, rt); |
duke@435 | 549 | #endif |
duke@435 | 550 | } |
duke@435 | 551 | |
duke@435 | 552 | inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) { |
duke@435 | 553 | brx(c, a, p, target(L)); |
duke@435 | 554 | } |
duke@435 | 555 | |
duke@435 | 556 | inline void MacroAssembler::ba( bool a, Label& L ) { |
duke@435 | 557 | br(always, a, pt, L); |
duke@435 | 558 | } |
duke@435 | 559 | |
duke@435 | 560 | // Warning: V9 only functions |
duke@435 | 561 | inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { |
duke@435 | 562 | Assembler::bp(c, a, cc, p, d, rt); |
duke@435 | 563 | } |
duke@435 | 564 | |
duke@435 | 565 | inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { |
duke@435 | 566 | Assembler::bp(c, a, cc, p, L); |
duke@435 | 567 | } |
duke@435 | 568 | |
duke@435 | 569 | inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) { |
duke@435 | 570 | if (VM_Version::v9_instructions_work()) |
duke@435 | 571 | fbp(c, a, fcc0, p, d, rt); |
duke@435 | 572 | else |
duke@435 | 573 | Assembler::fb(c, a, d, rt); |
duke@435 | 574 | } |
duke@435 | 575 | |
duke@435 | 576 | inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) { |
duke@435 | 577 | fb(c, a, p, target(L)); |
duke@435 | 578 | } |
duke@435 | 579 | |
duke@435 | 580 | inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { |
duke@435 | 581 | Assembler::fbp(c, a, cc, p, d, rt); |
duke@435 | 582 | } |
duke@435 | 583 | |
duke@435 | 584 | inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { |
duke@435 | 585 | Assembler::fbp(c, a, cc, p, L); |
duke@435 | 586 | } |
duke@435 | 587 | |
duke@435 | 588 | inline void MacroAssembler::jmp( Register s1, Register s2 ) { jmpl( s1, s2, G0 ); } |
duke@435 | 589 | inline void MacroAssembler::jmp( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, G0, rspec); } |
duke@435 | 590 | |
iveresov@2441 | 591 | inline bool MacroAssembler::is_far_target(address d) { |
iveresov@2441 | 592 | return !is_in_wdisp30_range(d, CodeCache::low_bound()) || !is_in_wdisp30_range(d, CodeCache::high_bound()); |
iveresov@2441 | 593 | } |
iveresov@2441 | 594 | |
duke@435 | 595 | // Call with a check to see if we need to deal with the added |
duke@435 | 596 | // expense of relocation and if we overflow the displacement |
iveresov@2441 | 597 | // of the quick call instruction. |
duke@435 | 598 | inline void MacroAssembler::call( address d, relocInfo::relocType rt ) { |
duke@435 | 599 | #ifdef _LP64 |
duke@435 | 600 | intptr_t disp; |
duke@435 | 601 | // NULL is ok because it will be relocated later. |
duke@435 | 602 | // Must change NULL to a reachable address in order to |
duke@435 | 603 | // pass asserts here and in wdisp. |
duke@435 | 604 | if ( d == NULL ) |
duke@435 | 605 | d = pc(); |
duke@435 | 606 | |
duke@435 | 607 | // Is this address within range of the call instruction? |
duke@435 | 608 | // If not, use the expensive instruction sequence |
iveresov@2441 | 609 | if (is_far_target(d)) { |
duke@435 | 610 | relocate(rt); |
twisti@1162 | 611 | AddressLiteral dest(d); |
twisti@1162 | 612 | jumpl_to(dest, O7, O7); |
iveresov@2441 | 613 | } else { |
iveresov@2441 | 614 | Assembler::call(d, rt); |
duke@435 | 615 | } |
duke@435 | 616 | #else |
duke@435 | 617 | Assembler::call( d, rt ); |
duke@435 | 618 | #endif |
duke@435 | 619 | } |
duke@435 | 620 | |
duke@435 | 621 | inline void MacroAssembler::call( Label& L, relocInfo::relocType rt ) { |
duke@435 | 622 | MacroAssembler::call( target(L), rt); |
duke@435 | 623 | } |
duke@435 | 624 | |
duke@435 | 625 | |
duke@435 | 626 | |
duke@435 | 627 | inline void MacroAssembler::callr( Register s1, Register s2 ) { jmpl( s1, s2, O7 ); } |
duke@435 | 628 | inline void MacroAssembler::callr( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, O7, rspec); } |
duke@435 | 629 | |
duke@435 | 630 | // prefetch instruction |
duke@435 | 631 | inline void MacroAssembler::iprefetch( address d, relocInfo::relocType rt ) { |
duke@435 | 632 | if (VM_Version::v9_instructions_work()) |
duke@435 | 633 | Assembler::bp( never, true, xcc, pt, d, rt ); |
duke@435 | 634 | } |
duke@435 | 635 | inline void MacroAssembler::iprefetch( Label& L) { iprefetch( target(L) ); } |
duke@435 | 636 | |
duke@435 | 637 | |
duke@435 | 638 | // clobbers o7 on V8!! |
duke@435 | 639 | // returns delta from gotten pc to addr after |
duke@435 | 640 | inline int MacroAssembler::get_pc( Register d ) { |
duke@435 | 641 | int x = offset(); |
duke@435 | 642 | if (VM_Version::v9_instructions_work()) |
duke@435 | 643 | rdpc(d); |
duke@435 | 644 | else { |
duke@435 | 645 | Label lbl; |
duke@435 | 646 | Assembler::call(lbl, relocInfo::none); // No relocation as this is call to pc+0x8 |
duke@435 | 647 | if (d == O7) delayed()->nop(); |
duke@435 | 648 | else delayed()->mov(O7, d); |
duke@435 | 649 | bind(lbl); |
duke@435 | 650 | } |
duke@435 | 651 | return offset() - x; |
duke@435 | 652 | } |
duke@435 | 653 | |
duke@435 | 654 | |
duke@435 | 655 | // Note: All MacroAssembler::set_foo functions are defined out-of-line. |
duke@435 | 656 | |
duke@435 | 657 | |
duke@435 | 658 | // Loads the current PC of the following instruction as an immediate value in |
duke@435 | 659 | // 2 instructions. All PCs in the CodeCache are within 2 Gig of each other. |
duke@435 | 660 | inline intptr_t MacroAssembler::load_pc_address( Register reg, int bytes_to_skip ) { |
duke@435 | 661 | intptr_t thepc = (intptr_t)pc() + 2*BytesPerInstWord + bytes_to_skip; |
duke@435 | 662 | #ifdef _LP64 |
duke@435 | 663 | Unimplemented(); |
duke@435 | 664 | #else |
duke@435 | 665 | Assembler::sethi( thepc & ~0x3ff, reg, internal_word_Relocation::spec((address)thepc)); |
duke@435 | 666 | Assembler::add(reg,thepc & 0x3ff, reg, internal_word_Relocation::spec((address)thepc)); |
duke@435 | 667 | #endif |
duke@435 | 668 | return thepc; |
duke@435 | 669 | } |
duke@435 | 670 | |
twisti@1162 | 671 | |
coleenp@2035 | 672 | inline void MacroAssembler::load_contents(const AddressLiteral& addrlit, Register d, int offset) { |
duke@435 | 673 | assert_not_delayed(); |
twisti@1162 | 674 | sethi(addrlit, d); |
twisti@1162 | 675 | ld(d, addrlit.low10() + offset, d); |
duke@435 | 676 | } |
duke@435 | 677 | |
duke@435 | 678 | |
coleenp@2035 | 679 | inline void MacroAssembler::load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset) { |
duke@435 | 680 | assert_not_delayed(); |
twisti@1162 | 681 | sethi(addrlit, d); |
twisti@1162 | 682 | ld_ptr(d, addrlit.low10() + offset, d); |
duke@435 | 683 | } |
duke@435 | 684 | |
duke@435 | 685 | |
coleenp@2035 | 686 | inline void MacroAssembler::store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset) { |
duke@435 | 687 | assert_not_delayed(); |
twisti@1162 | 688 | sethi(addrlit, temp); |
twisti@1162 | 689 | st(s, temp, addrlit.low10() + offset); |
duke@435 | 690 | } |
duke@435 | 691 | |
duke@435 | 692 | |
coleenp@2035 | 693 | inline void MacroAssembler::store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset) { |
duke@435 | 694 | assert_not_delayed(); |
twisti@1162 | 695 | sethi(addrlit, temp); |
twisti@1162 | 696 | st_ptr(s, temp, addrlit.low10() + offset); |
duke@435 | 697 | } |
duke@435 | 698 | |
duke@435 | 699 | |
duke@435 | 700 | // This code sequence is relocatable to any address, even on LP64. |
coleenp@2035 | 701 | inline void MacroAssembler::jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset) { |
duke@435 | 702 | assert_not_delayed(); |
duke@435 | 703 | // Force fixed length sethi because NativeJump and NativeFarCall don't handle |
duke@435 | 704 | // variable length instruction streams. |
twisti@1162 | 705 | patchable_sethi(addrlit, temp); |
twisti@1162 | 706 | jmpl(temp, addrlit.low10() + offset, d); |
duke@435 | 707 | } |
duke@435 | 708 | |
duke@435 | 709 | |
coleenp@2035 | 710 | inline void MacroAssembler::jump_to(const AddressLiteral& addrlit, Register temp, int offset) { |
twisti@1162 | 711 | jumpl_to(addrlit, temp, G0, offset); |
duke@435 | 712 | } |
duke@435 | 713 | |
duke@435 | 714 | |
twisti@1162 | 715 | inline void MacroAssembler::jump_indirect_to(Address& a, Register temp, |
twisti@1162 | 716 | int ld_offset, int jmp_offset) { |
jrose@1145 | 717 | assert_not_delayed(); |
twisti@1162 | 718 | //sethi(al); // sethi is caller responsibility for this one |
jrose@1145 | 719 | ld_ptr(a, temp, ld_offset); |
jrose@1145 | 720 | jmp(temp, jmp_offset); |
jrose@1145 | 721 | } |
jrose@1145 | 722 | |
jrose@1145 | 723 | |
twisti@1162 | 724 | inline void MacroAssembler::set_oop(jobject obj, Register d) { |
twisti@1162 | 725 | set_oop(allocate_oop_address(obj), d); |
duke@435 | 726 | } |
duke@435 | 727 | |
duke@435 | 728 | |
twisti@1162 | 729 | inline void MacroAssembler::set_oop_constant(jobject obj, Register d) { |
twisti@1162 | 730 | set_oop(constant_oop_address(obj), d); |
duke@435 | 731 | } |
duke@435 | 732 | |
duke@435 | 733 | |
jcoomes@1902 | 734 | inline void MacroAssembler::set_oop(const AddressLiteral& obj_addr, Register d) { |
twisti@1162 | 735 | assert(obj_addr.rspec().type() == relocInfo::oop_type, "must be an oop reloc"); |
twisti@1162 | 736 | set(obj_addr, d); |
duke@435 | 737 | } |
duke@435 | 738 | |
duke@435 | 739 | |
duke@435 | 740 | inline void MacroAssembler::load_argument( Argument& a, Register d ) { |
duke@435 | 741 | if (a.is_register()) |
duke@435 | 742 | mov(a.as_register(), d); |
duke@435 | 743 | else |
duke@435 | 744 | ld (a.as_address(), d); |
duke@435 | 745 | } |
duke@435 | 746 | |
duke@435 | 747 | inline void MacroAssembler::store_argument( Register s, Argument& a ) { |
duke@435 | 748 | if (a.is_register()) |
duke@435 | 749 | mov(s, a.as_register()); |
duke@435 | 750 | else |
duke@435 | 751 | st_ptr (s, a.as_address()); // ABI says everything is right justified. |
duke@435 | 752 | } |
duke@435 | 753 | |
duke@435 | 754 | inline void MacroAssembler::store_ptr_argument( Register s, Argument& a ) { |
duke@435 | 755 | if (a.is_register()) |
duke@435 | 756 | mov(s, a.as_register()); |
duke@435 | 757 | else |
duke@435 | 758 | st_ptr (s, a.as_address()); |
duke@435 | 759 | } |
duke@435 | 760 | |
duke@435 | 761 | |
duke@435 | 762 | #ifdef _LP64 |
duke@435 | 763 | inline void MacroAssembler::store_float_argument( FloatRegister s, Argument& a ) { |
duke@435 | 764 | if (a.is_float_register()) |
duke@435 | 765 | // V9 ABI has F1, F3, F5 are used to pass instead of O0, O1, O2 |
duke@435 | 766 | fmov(FloatRegisterImpl::S, s, a.as_float_register() ); |
duke@435 | 767 | else |
duke@435 | 768 | // Floats are stored in the high half of the stack entry |
duke@435 | 769 | // The low half is undefined per the ABI. |
duke@435 | 770 | stf(FloatRegisterImpl::S, s, a.as_address(), sizeof(jfloat)); |
duke@435 | 771 | } |
duke@435 | 772 | |
duke@435 | 773 | inline void MacroAssembler::store_double_argument( FloatRegister s, Argument& a ) { |
duke@435 | 774 | if (a.is_float_register()) |
duke@435 | 775 | // V9 ABI has D0, D2, D4 are used to pass instead of O0, O1, O2 |
duke@435 | 776 | fmov(FloatRegisterImpl::D, s, a.as_double_register() ); |
duke@435 | 777 | else |
duke@435 | 778 | stf(FloatRegisterImpl::D, s, a.as_address()); |
duke@435 | 779 | } |
duke@435 | 780 | |
duke@435 | 781 | inline void MacroAssembler::store_long_argument( Register s, Argument& a ) { |
duke@435 | 782 | if (a.is_register()) |
duke@435 | 783 | mov(s, a.as_register()); |
duke@435 | 784 | else |
duke@435 | 785 | stx(s, a.as_address()); |
duke@435 | 786 | } |
duke@435 | 787 | #endif |
duke@435 | 788 | |
duke@435 | 789 | inline void MacroAssembler::clrb( Register s1, Register s2) { stb( G0, s1, s2 ); } |
duke@435 | 790 | inline void MacroAssembler::clrh( Register s1, Register s2) { sth( G0, s1, s2 ); } |
duke@435 | 791 | inline void MacroAssembler::clr( Register s1, Register s2) { stw( G0, s1, s2 ); } |
duke@435 | 792 | inline void MacroAssembler::clrx( Register s1, Register s2) { stx( G0, s1, s2 ); } |
duke@435 | 793 | |
duke@435 | 794 | inline void MacroAssembler::clrb( Register s1, int simm13a) { stb( G0, s1, simm13a); } |
duke@435 | 795 | inline void MacroAssembler::clrh( Register s1, int simm13a) { sth( G0, s1, simm13a); } |
duke@435 | 796 | inline void MacroAssembler::clr( Register s1, int simm13a) { stw( G0, s1, simm13a); } |
duke@435 | 797 | inline void MacroAssembler::clrx( Register s1, int simm13a) { stx( G0, s1, simm13a); } |
duke@435 | 798 | |
duke@435 | 799 | // returns if membar generates anything, obviously this code should mirror |
duke@435 | 800 | // membar below. |
duke@435 | 801 | inline bool MacroAssembler::membar_has_effect( Membar_mask_bits const7a ) { |
duke@435 | 802 | if( !os::is_MP() ) return false; // Not needed on single CPU |
duke@435 | 803 | if( VM_Version::v9_instructions_work() ) { |
duke@435 | 804 | const Membar_mask_bits effective_mask = |
duke@435 | 805 | Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore)); |
duke@435 | 806 | return (effective_mask != 0); |
duke@435 | 807 | } else { |
duke@435 | 808 | return true; |
duke@435 | 809 | } |
duke@435 | 810 | } |
duke@435 | 811 | |
duke@435 | 812 | inline void MacroAssembler::membar( Membar_mask_bits const7a ) { |
duke@435 | 813 | // Uniprocessors do not need memory barriers |
duke@435 | 814 | if (!os::is_MP()) return; |
duke@435 | 815 | // Weakened for current Sparcs and TSO. See the v9 manual, sections 8.4.3, |
duke@435 | 816 | // 8.4.4.3, a.31 and a.50. |
duke@435 | 817 | if( VM_Version::v9_instructions_work() ) { |
duke@435 | 818 | // Under TSO, setting bit 3, 2, or 0 is redundant, so the only value |
duke@435 | 819 | // of the mmask subfield of const7a that does anything that isn't done |
duke@435 | 820 | // implicitly is StoreLoad. |
duke@435 | 821 | const Membar_mask_bits effective_mask = |
duke@435 | 822 | Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore)); |
duke@435 | 823 | if ( effective_mask != 0 ) { |
duke@435 | 824 | Assembler::membar( effective_mask ); |
duke@435 | 825 | } |
duke@435 | 826 | } else { |
duke@435 | 827 | // stbar is the closest there is on v8. Equivalent to membar(StoreStore). We |
duke@435 | 828 | // do not issue the stbar because to my knowledge all v8 machines implement TSO, |
duke@435 | 829 | // which guarantees that all stores behave as if an stbar were issued just after |
duke@435 | 830 | // each one of them. On these machines, stbar ought to be a nop. There doesn't |
duke@435 | 831 | // appear to be an equivalent of membar(StoreLoad) on v8: TSO doesn't require it, |
duke@435 | 832 | // it can't be specified by stbar, nor have I come up with a way to simulate it. |
duke@435 | 833 | // |
duke@435 | 834 | // Addendum. Dave says that ldstub guarantees a write buffer flush to coherent |
duke@435 | 835 | // space. Put one here to be on the safe side. |
duke@435 | 836 | Assembler::ldstub(SP, 0, G0); |
duke@435 | 837 | } |
duke@435 | 838 | } |
stefank@2314 | 839 | |
stefank@2314 | 840 | #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP |