• file
• revisions
• annotate
• diff
• comparison
• raw

src/cpu/x86/vm/vm_version_x86_32.hpp@2649e5276dd7 (annotated)

src/cpu/x86/vm/vm_version_x86_32.hpp

Tue, 14 Oct 2008 15:10:26 -0700

author

kvn

date

Tue, 14 Oct 2008 15:10:26 -0700

changeset 840

2649e5276dd7

parent 435

a61af66fc99e

child 905

ad8c8ca4ab0f

permissions

-rw-r--r--

6532536: Optimize arraycopy stubs for Intel cpus
Summary: Use SSE2 movdqu in arraycopy stubs on newest Intel's cpus
Reviewed-by: rasbold

duke@435	1	/*
duke@435	2	* Copyright 1997-2006 Sun Microsystems, Inc. All Rights Reserved.
duke@435	3	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435	4	*
duke@435	5	* This code is free software; you can redistribute it and/or modify it
duke@435	6	* under the terms of the GNU General Public License version 2 only, as
duke@435	7	* published by the Free Software Foundation.
duke@435	8	*
duke@435	9	* This code is distributed in the hope that it will be useful, but WITHOUT
duke@435	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435	12	* version 2 for more details (a copy is included in the LICENSE file that
duke@435	13	* accompanied this code).
duke@435	14	*
duke@435	15	* You should have received a copy of the GNU General Public License version
duke@435	16	* 2 along with this work; if not, write to the Free Software Foundation,
duke@435	17	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435	18	*
duke@435	19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@435	20	* CA 95054 USA or visit www.sun.com if you need additional information or
duke@435	21	* have any questions.
duke@435	22	*
duke@435	23	*/
duke@435	24
duke@435	25	class VM_Version: public Abstract_VM_Version {
duke@435	26	public:
duke@435	27	// cpuid result register layouts. These are all unions of a uint32_t
duke@435	28	// (in case anyone wants access to the register as a whole) and a bitfield.
duke@435	29
duke@435	30	union StdCpuid1Eax {
duke@435	31	uint32_t value;
duke@435	32	struct {
duke@435	33	uint32_t stepping : 4,
duke@435	34	model : 4,
duke@435	35	family : 4,
duke@435	36	proc_type : 2,
duke@435	37	: 2,
duke@435	38	ext_model : 4,
duke@435	39	ext_family : 8,
duke@435	40	: 4;
duke@435	41	} bits;
duke@435	42	};
duke@435	43
duke@435	44	union StdCpuid1Ebx { // example, unused
duke@435	45	uint32_t value;
duke@435	46	struct {
duke@435	47	uint32_t brand_id : 8,
duke@435	48	clflush_size : 8,
duke@435	49	threads_per_cpu : 8,
duke@435	50	apic_id : 8;
duke@435	51	} bits;
duke@435	52	};
duke@435	53
duke@435	54	union StdCpuid1Ecx {
duke@435	55	uint32_t value;
duke@435	56	struct {
duke@435	57	uint32_t sse3 : 1,
duke@435	58	: 2,
duke@435	59	monitor : 1,
duke@435	60	: 1,
duke@435	61	vmx : 1,
duke@435	62	: 1,
duke@435	63	est : 1,
duke@435	64	: 1,
duke@435	65	ssse3 : 1,
duke@435	66	cid : 1,
duke@435	67	: 2,
duke@435	68	cmpxchg16: 1,
duke@435	69	: 4,
duke@435	70	dca : 1,
kvn@840	71	sse4_1 : 1,
kvn@840	72	sse4_2 : 1,
kvn@840	73	: 11;
duke@435	74	} bits;
duke@435	75	};
duke@435	76
duke@435	77	union StdCpuid1Edx {
duke@435	78	uint32_t value;
duke@435	79	struct {
duke@435	80	uint32_t : 4,
duke@435	81	tsc : 1,
duke@435	82	: 3,
duke@435	83	cmpxchg8 : 1,
duke@435	84	: 6,
duke@435	85	cmov : 1,
duke@435	86	: 7,
duke@435	87	mmx : 1,
duke@435	88	fxsr : 1,
duke@435	89	sse : 1,
duke@435	90	sse2 : 1,
duke@435	91	: 1,
duke@435	92	ht : 1,
duke@435	93	: 3;
duke@435	94	} bits;
duke@435	95	};
duke@435	96
duke@435	97	union DcpCpuid4Eax {
duke@435	98	uint32_t value;
duke@435	99	struct {
duke@435	100	uint32_t cache_type : 5,
duke@435	101	: 21,
duke@435	102	cores_per_cpu : 6;
duke@435	103	} bits;
duke@435	104	};
duke@435	105
duke@435	106	union DcpCpuid4Ebx {
duke@435	107	uint32_t value;
duke@435	108	struct {
duke@435	109	uint32_t L1_line_size : 12,
duke@435	110	partitions : 10,
duke@435	111	associativity : 10;
duke@435	112	} bits;
duke@435	113	};
duke@435	114
duke@435	115	union ExtCpuid1Ecx {
duke@435	116	uint32_t value;
duke@435	117	struct {
duke@435	118	uint32_t LahfSahf : 1,
duke@435	119	CmpLegacy : 1,
duke@435	120	: 4,
duke@435	121	abm : 1,
duke@435	122	sse4a : 1,
duke@435	123	misalignsse : 1,
duke@435	124	prefetchw : 1,
duke@435	125	: 22;
duke@435	126	} bits;
duke@435	127	};
duke@435	128
duke@435	129	union ExtCpuid1Edx {
duke@435	130	uint32_t value;
duke@435	131	struct {
duke@435	132	uint32_t : 22,
duke@435	133	mmx_amd : 1,
duke@435	134	mmx : 1,
duke@435	135	fxsr : 1,
duke@435	136	: 4,
duke@435	137	long_mode : 1,
duke@435	138	tdnow2 : 1,
duke@435	139	tdnow : 1;
duke@435	140	} bits;
duke@435	141	};
duke@435	142
duke@435	143	union ExtCpuid5Ex {
duke@435	144	uint32_t value;
duke@435	145	struct {
duke@435	146	uint32_t L1_line_size : 8,
duke@435	147	L1_tag_lines : 8,
duke@435	148	L1_assoc : 8,
duke@435	149	L1_size : 8;
duke@435	150	} bits;
duke@435	151	};
duke@435	152
duke@435	153	union ExtCpuid8Ecx {
duke@435	154	uint32_t value;
duke@435	155	struct {
duke@435	156	uint32_t cores_per_cpu : 8,
duke@435	157	: 24;
duke@435	158	} bits;
duke@435	159	};
duke@435	160
duke@435	161	protected:
duke@435	162	static int _cpu;
duke@435	163	static int _model;
duke@435	164	static int _stepping;
duke@435	165	static int _cpuFeatures; // features returned by the "cpuid" instruction
duke@435	166	// 0 if this instruction is not available
duke@435	167	static const char* _features_str;
duke@435	168
duke@435	169	enum {
duke@435	170	CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
duke@435	171	CPU_CMOV = (1 << 1),
duke@435	172	CPU_FXSR = (1 << 2),
duke@435	173	CPU_HT = (1 << 3),
duke@435	174	CPU_MMX = (1 << 4),
duke@435	175	CPU_3DNOW= (1 << 5), // 3DNow comes from cpuid 0x80000001 (EDX)
duke@435	176	CPU_SSE = (1 << 6),
duke@435	177	CPU_SSE2 = (1 << 7),
duke@435	178	CPU_SSE3 = (1 << 8), // sse3 comes from cpuid 1 (ECX)
duke@435	179	CPU_SSSE3= (1 << 9),
kvn@840	180	CPU_SSE4A= (1 <<10),
kvn@840	181	CPU_SSE4_1 = (1 << 11),
kvn@840	182	CPU_SSE4_2 = (1 << 12)
duke@435	183	} cpuFeatureFlags;
duke@435	184
duke@435	185	// cpuid information block. All info derived from executing cpuid with
duke@435	186	// various function numbers is stored here. Intel and AMD info is
duke@435	187	// merged in this block: accessor methods disentangle it.
duke@435	188	//
duke@435	189	// The info block is laid out in subblocks of 4 dwords corresponding to
duke@435	190	// rax, rbx, rcx and rdx, whether or not they contain anything useful.
duke@435	191	struct CpuidInfo {
duke@435	192	// cpuid function 0
duke@435	193	uint32_t std_max_function;
duke@435	194	uint32_t std_vendor_name_0;
duke@435	195	uint32_t std_vendor_name_1;
duke@435	196	uint32_t std_vendor_name_2;
duke@435	197
duke@435	198	// cpuid function 1
duke@435	199	StdCpuid1Eax std_cpuid1_rax;
duke@435	200	StdCpuid1Ebx std_cpuid1_rbx;
duke@435	201	StdCpuid1Ecx std_cpuid1_rcx;
duke@435	202	StdCpuid1Edx std_cpuid1_rdx;
duke@435	203
duke@435	204	// cpuid function 4 (deterministic cache parameters)
duke@435	205	DcpCpuid4Eax dcp_cpuid4_rax;
duke@435	206	DcpCpuid4Ebx dcp_cpuid4_rbx;
duke@435	207	uint32_t dcp_cpuid4_rcx; // unused currently
duke@435	208	uint32_t dcp_cpuid4_rdx; // unused currently
duke@435	209
duke@435	210	// cpuid function 0x80000000 // example, unused
duke@435	211	uint32_t ext_max_function;
duke@435	212	uint32_t ext_vendor_name_0;
duke@435	213	uint32_t ext_vendor_name_1;
duke@435	214	uint32_t ext_vendor_name_2;
duke@435	215
duke@435	216	// cpuid function 0x80000001
duke@435	217	uint32_t ext_cpuid1_rax; // reserved
duke@435	218	uint32_t ext_cpuid1_rbx; // reserved
duke@435	219	ExtCpuid1Ecx ext_cpuid1_rcx;
duke@435	220	ExtCpuid1Edx ext_cpuid1_rdx;
duke@435	221
duke@435	222	// cpuid functions 0x80000002 thru 0x80000004: example, unused
duke@435	223	uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
duke@435	224	uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
duke@435	225	uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
duke@435	226
duke@435	227	// cpuid function 0x80000005 //AMD L1, Intel reserved
duke@435	228	uint32_t ext_cpuid5_rax; // unused currently
duke@435	229	uint32_t ext_cpuid5_rbx; // reserved
duke@435	230	ExtCpuid5Ex ext_cpuid5_rcx; // L1 data cache info (AMD)
duke@435	231	ExtCpuid5Ex ext_cpuid5_rdx; // L1 instruction cache info (AMD)
duke@435	232
duke@435	233	// cpuid function 0x80000008
duke@435	234	uint32_t ext_cpuid8_rax; // unused currently
duke@435	235	uint32_t ext_cpuid8_rbx; // reserved
duke@435	236	ExtCpuid8Ecx ext_cpuid8_rcx;
duke@435	237	uint32_t ext_cpuid8_rdx; // reserved
duke@435	238	};
duke@435	239
duke@435	240	// The actual cpuid info block
duke@435	241	static CpuidInfo _cpuid_info;
duke@435	242
duke@435	243	// Extractors and predicates
duke@435	244	static uint32_t extended_cpu_family() {
duke@435	245	uint32_t result = _cpuid_info.std_cpuid1_rax.bits.family;
kvn@840	246	result += _cpuid_info.std_cpuid1_rax.bits.ext_family;
duke@435	247	return result;
duke@435	248	}
duke@435	249	static uint32_t extended_cpu_model() {
duke@435	250	uint32_t result = _cpuid_info.std_cpuid1_rax.bits.model;
kvn@840	251	result |= _cpuid_info.std_cpuid1_rax.bits.ext_model << 4;
duke@435	252	return result;
duke@435	253	}
duke@435	254	static uint32_t cpu_stepping() {
duke@435	255	uint32_t result = _cpuid_info.std_cpuid1_rax.bits.stepping;
duke@435	256	return result;
duke@435	257	}
duke@435	258	static uint logical_processor_count() {
duke@435	259	uint result = threads_per_core();
duke@435	260	return result;
duke@435	261	}
duke@435	262	static uint32_t feature_flags() {
duke@435	263	uint32_t result = 0;
duke@435	264	if (_cpuid_info.std_cpuid1_rdx.bits.cmpxchg8 != 0)
duke@435	265	result |= CPU_CX8;
duke@435	266	if (_cpuid_info.std_cpuid1_rdx.bits.cmov != 0)
duke@435	267	result |= CPU_CMOV;
duke@435	268	if (_cpuid_info.std_cpuid1_rdx.bits.fxsr != 0 || is_amd() &&
duke@435	269	_cpuid_info.ext_cpuid1_rdx.bits.fxsr != 0)
duke@435	270	result |= CPU_FXSR;
duke@435	271	// HT flag is set for multi-core processors also.
duke@435	272	if (threads_per_core() > 1)
duke@435	273	result |= CPU_HT;
duke@435	274	if (_cpuid_info.std_cpuid1_rdx.bits.mmx != 0 || is_amd() &&
duke@435	275	_cpuid_info.ext_cpuid1_rdx.bits.mmx != 0)
duke@435	276	result |= CPU_MMX;
duke@435	277	if (is_amd() && _cpuid_info.ext_cpuid1_rdx.bits.tdnow != 0)
duke@435	278	result |= CPU_3DNOW;
duke@435	279	if (_cpuid_info.std_cpuid1_rdx.bits.sse != 0)
duke@435	280	result |= CPU_SSE;
duke@435	281	if (_cpuid_info.std_cpuid1_rdx.bits.sse2 != 0)
duke@435	282	result |= CPU_SSE2;
duke@435	283	if (_cpuid_info.std_cpuid1_rcx.bits.sse3 != 0)
duke@435	284	result |= CPU_SSE3;
duke@435	285	if (_cpuid_info.std_cpuid1_rcx.bits.ssse3 != 0)
duke@435	286	result |= CPU_SSSE3;
duke@435	287	if (is_amd() && _cpuid_info.ext_cpuid1_rcx.bits.sse4a != 0)
duke@435	288	result |= CPU_SSE4A;
kvn@840	289	if (_cpuid_info.std_cpuid1_rcx.bits.sse4_1 != 0)
kvn@840	290	result |= CPU_SSE4_1;
kvn@840	291	if (_cpuid_info.std_cpuid1_rcx.bits.sse4_2 != 0)
kvn@840	292	result |= CPU_SSE4_2;
duke@435	293	return result;
duke@435	294	}
duke@435	295
duke@435	296	static void get_processor_features();
duke@435	297
duke@435	298	public:
duke@435	299	// Offsets for cpuid asm stub
duke@435	300	static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
duke@435	301	static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_rax); }
duke@435	302	static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_rax); }
duke@435	303	static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_rax); }
duke@435	304	static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_rax); }
duke@435	305	static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_rax); }
duke@435	306
duke@435	307	// Initialization
duke@435	308	static void initialize();
duke@435	309
duke@435	310	// Asserts
duke@435	311	static void assert_is_initialized() {
duke@435	312	assert(_cpuid_info.std_cpuid1_rax.bits.family != 0, "VM_Version not initialized");
duke@435	313	}
duke@435	314
duke@435	315	//
duke@435	316	// Processor family:
duke@435	317	// 3 - 386
duke@435	318	// 4 - 486
duke@435	319	// 5 - Pentium
duke@435	320	// 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
duke@435	321	// Pentium M, Core Solo, Core Duo, Core2 Duo
duke@435	322	// family 6 model: 9, 13, 14, 15
duke@435	323	// 0x0f - Pentium 4, Opteron
duke@435	324	//
duke@435	325	// Note: The cpu family should be used to select between
duke@435	326	// instruction sequences which are valid on all Intel
duke@435	327	// processors. Use the feature test functions below to
duke@435	328	// determine whether a particular instruction is supported.
duke@435	329	//
duke@435	330	static int cpu_family() { return _cpu;}
duke@435	331	static bool is_P6() { return cpu_family() >= 6; }
duke@435	332
duke@435	333	static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
duke@435	334	static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
duke@435	335
duke@435	336	static uint cores_per_cpu() {
duke@435	337	uint result = 1;
duke@435	338	if (is_intel()) {
duke@435	339	result = (_cpuid_info.dcp_cpuid4_rax.bits.cores_per_cpu + 1);
duke@435	340	} else if (is_amd()) {
duke@435	341	result = (_cpuid_info.ext_cpuid8_rcx.bits.cores_per_cpu + 1);
duke@435	342	}
duke@435	343	return result;
duke@435	344	}
duke@435	345
duke@435	346	static uint threads_per_core() {
duke@435	347	uint result = 1;
duke@435	348	if (_cpuid_info.std_cpuid1_rdx.bits.ht != 0) {
duke@435	349	result = _cpuid_info.std_cpuid1_rbx.bits.threads_per_cpu /
duke@435	350	cores_per_cpu();
duke@435	351	}
duke@435	352	return result;
duke@435	353	}
duke@435	354
duke@435	355	static intx L1_data_cache_line_size() {
duke@435	356	intx result = 0;
duke@435	357	if (is_intel()) {
duke@435	358	result = (_cpuid_info.dcp_cpuid4_rbx.bits.L1_line_size + 1);
duke@435	359	} else if (is_amd()) {
duke@435	360	result = _cpuid_info.ext_cpuid5_rcx.bits.L1_line_size;
duke@435	361	}
duke@435	362	if (result < 32) // not defined ?
duke@435	363	result = 32; // 32 bytes by default on x86
duke@435	364	return result;
duke@435	365	}
duke@435	366
duke@435	367	//
duke@435	368	// Feature identification
duke@435	369	//
duke@435	370	static bool supports_cpuid() { return _cpuFeatures != 0; }
duke@435	371	static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }
duke@435	372	static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; }
duke@435	373	static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; }
duke@435	374	static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; }
duke@435	375	static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; }
duke@435	376	static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; }
duke@435	377	static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; }
duke@435	378	static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; }
duke@435	379	static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; }
kvn@840	380	static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; }
kvn@840	381	static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; }
duke@435	382	//
duke@435	383	// AMD features
duke@435	384	//
duke@435	385	static bool supports_3dnow() { return (_cpuFeatures & CPU_3DNOW) != 0; }
duke@435	386	static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_rdx.bits.mmx_amd != 0; }
duke@435	387	static bool supports_3dnow2() { return is_amd() && _cpuid_info.ext_cpuid1_rdx.bits.tdnow2 != 0; }
duke@435	388	static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; }
duke@435	389
duke@435	390	static bool supports_compare_and_exchange() { return true; }
duke@435	391
duke@435	392	static const char* cpu_features() { return _features_str; }
duke@435	393
duke@435	394	static intx allocate_prefetch_distance() {
duke@435	395	// This method should be called before allocate_prefetch_style().
duke@435	396	//
duke@435	397	// Hardware prefetching (distance/size in bytes):
duke@435	398	// Pentium 3 - 64 / 32
duke@435	399	// Pentium 4 - 256 / 128
duke@435	400	// Athlon - 64 / 32 ????
duke@435	401	// Opteron - 128 / 64 only when 2 sequential cache lines accessed
duke@435	402	// Core - 128 / 64
duke@435	403	//
duke@435	404	// Software prefetching (distance in bytes / instruction with best score):
duke@435	405	// Pentium 3 - 128 / prefetchnta
duke@435	406	// Pentium 4 - 512 / prefetchnta
duke@435	407	// Athlon - 128 / prefetchnta
duke@435	408	// Opteron - 256 / prefetchnta
duke@435	409	// Core - 256 / prefetchnta
duke@435	410	// It will be used only when AllocatePrefetchStyle > 0
duke@435	411
duke@435	412	intx count = AllocatePrefetchDistance;
duke@435	413	if (count < 0) { // default ?
duke@435	414	if (is_amd()) { // AMD
duke@435	415	if (supports_sse2())
duke@435	416	count = 256; // Opteron
duke@435	417	else
duke@435	418	count = 128; // Athlon
duke@435	419	} else { // Intel
duke@435	420	if (supports_sse2())
duke@435	421	if (cpu_family() == 6) {
duke@435	422	count = 256; // Pentium M, Core, Core2
duke@435	423	} else {
duke@435	424	count = 512; // Pentium 4
duke@435	425	}
duke@435	426	else
duke@435	427	count = 128; // Pentium 3 (and all other old CPUs)
duke@435	428	}
duke@435	429	}
duke@435	430	return count;
duke@435	431	}
duke@435	432	static intx allocate_prefetch_style() {
duke@435	433	assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
duke@435	434	// Return 0 if AllocatePrefetchDistance was not defined or
duke@435	435	// prefetch instruction is not supported.
duke@435	436	return (AllocatePrefetchDistance > 0 &&
duke@435	437	(supports_3dnow() || supports_sse())) ? AllocatePrefetchStyle : 0;
duke@435	438	}
duke@435	439	};