duke@435: /*
duke@435:  * Copyright 1997-2006 Sun Microsystems, Inc.  All Rights Reserved.
duke@435:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435:  *
duke@435:  * This code is free software; you can redistribute it and/or modify it
duke@435:  * under the terms of the GNU General Public License version 2 only, as
duke@435:  * published by the Free Software Foundation.
duke@435:  *
duke@435:  * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
duke@435:  * version 2 for more details (a copy is included in the LICENSE file that
duke@435:  * accompanied this code).
duke@435:  *
duke@435:  * You should have received a copy of the GNU General Public License version
duke@435:  * 2 along with this work; if not, write to the Free Software Foundation,
duke@435:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435:  *
duke@435:  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@435:  * CA 95054 USA or visit www.sun.com if you need additional information or
duke@435:  * have any questions.
duke@435:  *
duke@435:  */
duke@435: 
duke@435: class VM_Version: public Abstract_VM_Version {
duke@435: public:
duke@435:   // cpuid result register layouts.  These are all unions of a uint32_t
duke@435:   // (in case anyone wants access to the register as a whole) and a bitfield.
duke@435: 
duke@435:   union StdCpuid1Eax {
duke@435:     uint32_t value;
duke@435:     struct {
duke@435:       uint32_t stepping   : 4,
duke@435:                model      : 4,
duke@435:                family     : 4,
duke@435:                proc_type  : 2,
duke@435:                           : 2,
duke@435:                ext_model  : 4,
duke@435:                ext_family : 8,
duke@435:                           : 4;
duke@435:     } bits;
duke@435:   };
duke@435: 
duke@435:   union StdCpuid1Ebx { // example, unused
duke@435:     uint32_t value;
duke@435:     struct {
duke@435:       uint32_t brand_id         : 8,
duke@435:                clflush_size     : 8,
duke@435:                threads_per_cpu  : 8,
duke@435:                apic_id          : 8;
duke@435:     } bits;
duke@435:   };
duke@435: 
duke@435:   union StdCpuid1Ecx {
duke@435:     uint32_t value;
duke@435:     struct {
duke@435:       uint32_t sse3     : 1,
duke@435:                         : 2,
duke@435:                monitor  : 1,
duke@435:                         : 1,
duke@435:                vmx      : 1,
duke@435:                         : 1,
duke@435:                est      : 1,
duke@435:                         : 1,
duke@435:                ssse3    : 1,
duke@435:                cid      : 1,
duke@435:                         : 2,
duke@435:                cmpxchg16: 1,
duke@435:                         : 4,
duke@435:                dca      : 1,
kvn@840:                sse4_1   : 1,
kvn@840:                sse4_2   : 1,
kvn@840:                         : 11;
duke@435:     } bits;
duke@435:   };
duke@435: 
duke@435:   union StdCpuid1Edx {
duke@435:     uint32_t value;
duke@435:     struct {
duke@435:       uint32_t          : 4,
duke@435:                tsc      : 1,
duke@435:                         : 3,
duke@435:                cmpxchg8 : 1,
duke@435:                         : 6,
duke@435:                cmov     : 1,
duke@435:                         : 7,
duke@435:                mmx      : 1,
duke@435:                fxsr     : 1,
duke@435:                sse      : 1,
duke@435:                sse2     : 1,
duke@435:                         : 1,
duke@435:                ht       : 1,
duke@435:                         : 3;
duke@435:     } bits;
duke@435:   };
duke@435: 
duke@435:   union DcpCpuid4Eax {
duke@435:     uint32_t value;
duke@435:     struct {
duke@435:       uint32_t cache_type    : 5,
duke@435:                              : 21,
duke@435:                cores_per_cpu : 6;
duke@435:     } bits;
duke@435:   };
duke@435: 
duke@435:   union DcpCpuid4Ebx {
duke@435:     uint32_t value;
duke@435:     struct {
duke@435:       uint32_t L1_line_size  : 12,
duke@435:                partitions    : 10,
duke@435:                associativity : 10;
duke@435:     } bits;
duke@435:   };
duke@435: 
duke@435:   union ExtCpuid1Ecx {
duke@435:     uint32_t value;
duke@435:     struct {
duke@435:       uint32_t LahfSahf     : 1,
duke@435:                CmpLegacy    : 1,
duke@435:                             : 4,
duke@435:                abm          : 1,
duke@435:                sse4a        : 1,
duke@435:                misalignsse  : 1,
duke@435:                prefetchw    : 1,
duke@435:                             : 22;
duke@435:     } bits;
duke@435:   };
duke@435: 
duke@435:   union ExtCpuid1Edx {
duke@435:     uint32_t value;
duke@435:     struct {
duke@435:       uint32_t           : 22,
duke@435:                mmx_amd   : 1,
duke@435:                mmx       : 1,
duke@435:                fxsr      : 1,
duke@435:                          : 4,
duke@435:                long_mode : 1,
duke@435:                tdnow2    : 1,
duke@435:                tdnow     : 1;
duke@435:     } bits;
duke@435:   };
duke@435: 
duke@435:   union ExtCpuid5Ex {
duke@435:     uint32_t value;
duke@435:     struct {
duke@435:       uint32_t L1_line_size : 8,
duke@435:                L1_tag_lines : 8,
duke@435:                L1_assoc     : 8,
duke@435:                L1_size      : 8;
duke@435:     } bits;
duke@435:   };
duke@435: 
duke@435:   union ExtCpuid8Ecx {
duke@435:     uint32_t value;
duke@435:     struct {
duke@435:       uint32_t cores_per_cpu : 8,
duke@435:                              : 24;
duke@435:     } bits;
duke@435:   };
duke@435: 
duke@435: protected:
duke@435:    static int _cpu;
duke@435:    static int _model;
duke@435:    static int _stepping;
duke@435:    static int _cpuFeatures;     // features returned by the "cpuid" instruction
duke@435:                                 // 0 if this instruction is not available
duke@435:    static const char* _features_str;
duke@435: 
duke@435:    enum {
duke@435:      CPU_CX8  = (1 << 0), // next bits are from cpuid 1 (EDX)
duke@435:      CPU_CMOV = (1 << 1),
duke@435:      CPU_FXSR = (1 << 2),
duke@435:      CPU_HT   = (1 << 3),
duke@435:      CPU_MMX  = (1 << 4),
duke@435:      CPU_3DNOW= (1 << 5), // 3DNow comes from cpuid 0x80000001 (EDX)
duke@435:      CPU_SSE  = (1 << 6),
duke@435:      CPU_SSE2 = (1 << 7),
duke@435:      CPU_SSE3 = (1 << 8), // sse3  comes from cpuid 1 (ECX)
duke@435:      CPU_SSSE3= (1 << 9),
kvn@840:      CPU_SSE4A= (1 <<10),
kvn@840:      CPU_SSE4_1 = (1 << 11),
kvn@840:      CPU_SSE4_2 = (1 << 12)
duke@435:    } cpuFeatureFlags;
duke@435: 
duke@435:   // cpuid information block.  All info derived from executing cpuid with
duke@435:   // various function numbers is stored here.  Intel and AMD info is
duke@435:   // merged in this block: accessor methods disentangle it.
duke@435:   //
duke@435:   // The info block is laid out in subblocks of 4 dwords corresponding to
duke@435:   // rax, rbx, rcx and rdx, whether or not they contain anything useful.
duke@435:   struct CpuidInfo {
duke@435:     // cpuid function 0
duke@435:     uint32_t std_max_function;
duke@435:     uint32_t std_vendor_name_0;
duke@435:     uint32_t std_vendor_name_1;
duke@435:     uint32_t std_vendor_name_2;
duke@435: 
duke@435:     // cpuid function 1
duke@435:     StdCpuid1Eax std_cpuid1_rax;
duke@435:     StdCpuid1Ebx std_cpuid1_rbx;
duke@435:     StdCpuid1Ecx std_cpuid1_rcx;
duke@435:     StdCpuid1Edx std_cpuid1_rdx;
duke@435: 
duke@435:     // cpuid function 4 (deterministic cache parameters)
duke@435:     DcpCpuid4Eax dcp_cpuid4_rax;
duke@435:     DcpCpuid4Ebx dcp_cpuid4_rbx;
duke@435:     uint32_t     dcp_cpuid4_rcx; // unused currently
duke@435:     uint32_t     dcp_cpuid4_rdx; // unused currently
duke@435: 
duke@435:     // cpuid function 0x80000000 // example, unused
duke@435:     uint32_t ext_max_function;
duke@435:     uint32_t ext_vendor_name_0;
duke@435:     uint32_t ext_vendor_name_1;
duke@435:     uint32_t ext_vendor_name_2;
duke@435: 
duke@435:     // cpuid function 0x80000001
duke@435:     uint32_t     ext_cpuid1_rax; // reserved
duke@435:     uint32_t     ext_cpuid1_rbx; // reserved
duke@435:     ExtCpuid1Ecx ext_cpuid1_rcx;
duke@435:     ExtCpuid1Edx ext_cpuid1_rdx;
duke@435: 
duke@435:     // cpuid functions 0x80000002 thru 0x80000004: example, unused
duke@435:     uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
duke@435:     uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
duke@435:     uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
duke@435: 
duke@435:     // cpuid function 0x80000005 //AMD L1, Intel reserved
duke@435:     uint32_t     ext_cpuid5_rax; // unused currently
duke@435:     uint32_t     ext_cpuid5_rbx; // reserved
duke@435:     ExtCpuid5Ex  ext_cpuid5_rcx; // L1 data cache info (AMD)
duke@435:     ExtCpuid5Ex  ext_cpuid5_rdx; // L1 instruction cache info (AMD)
duke@435: 
duke@435:     // cpuid function 0x80000008
duke@435:     uint32_t     ext_cpuid8_rax; // unused currently
duke@435:     uint32_t     ext_cpuid8_rbx; // reserved
duke@435:     ExtCpuid8Ecx ext_cpuid8_rcx;
duke@435:     uint32_t     ext_cpuid8_rdx; // reserved
duke@435:   };
duke@435: 
duke@435:   // The actual cpuid info block
duke@435:   static CpuidInfo _cpuid_info;
duke@435: 
duke@435:   // Extractors and predicates
duke@435:   static uint32_t extended_cpu_family() {
duke@435:     uint32_t result = _cpuid_info.std_cpuid1_rax.bits.family;
kvn@840:     result += _cpuid_info.std_cpuid1_rax.bits.ext_family;
duke@435:     return result;
duke@435:   }
duke@435:   static uint32_t extended_cpu_model() {
duke@435:     uint32_t result = _cpuid_info.std_cpuid1_rax.bits.model;
kvn@840:     result |= _cpuid_info.std_cpuid1_rax.bits.ext_model << 4;
duke@435:     return result;
duke@435:   }
duke@435:   static uint32_t cpu_stepping() {
duke@435:     uint32_t result = _cpuid_info.std_cpuid1_rax.bits.stepping;
duke@435:     return result;
duke@435:   }
duke@435:   static uint logical_processor_count() {
duke@435:     uint result = threads_per_core();
duke@435:     return result;
duke@435:   }
duke@435:   static uint32_t feature_flags() {
duke@435:     uint32_t result = 0;
duke@435:     if (_cpuid_info.std_cpuid1_rdx.bits.cmpxchg8 != 0)
duke@435:       result |= CPU_CX8;
duke@435:     if (_cpuid_info.std_cpuid1_rdx.bits.cmov != 0)
duke@435:       result |= CPU_CMOV;
duke@435:     if (_cpuid_info.std_cpuid1_rdx.bits.fxsr != 0 || is_amd() &&
duke@435:         _cpuid_info.ext_cpuid1_rdx.bits.fxsr != 0)
duke@435:       result |= CPU_FXSR;
duke@435:     // HT flag is set for multi-core processors also.
duke@435:     if (threads_per_core() > 1)
duke@435:       result |= CPU_HT;
duke@435:     if (_cpuid_info.std_cpuid1_rdx.bits.mmx != 0 || is_amd() &&
duke@435:         _cpuid_info.ext_cpuid1_rdx.bits.mmx != 0)
duke@435:       result |= CPU_MMX;
duke@435:     if (is_amd() && _cpuid_info.ext_cpuid1_rdx.bits.tdnow != 0)
duke@435:       result |= CPU_3DNOW;
duke@435:     if (_cpuid_info.std_cpuid1_rdx.bits.sse != 0)
duke@435:       result |= CPU_SSE;
duke@435:     if (_cpuid_info.std_cpuid1_rdx.bits.sse2 != 0)
duke@435:       result |= CPU_SSE2;
duke@435:     if (_cpuid_info.std_cpuid1_rcx.bits.sse3 != 0)
duke@435:       result |= CPU_SSE3;
duke@435:     if (_cpuid_info.std_cpuid1_rcx.bits.ssse3 != 0)
duke@435:       result |= CPU_SSSE3;
duke@435:     if (is_amd() && _cpuid_info.ext_cpuid1_rcx.bits.sse4a != 0)
duke@435:       result |= CPU_SSE4A;
kvn@840:     if (_cpuid_info.std_cpuid1_rcx.bits.sse4_1 != 0)
kvn@840:       result |= CPU_SSE4_1;
kvn@840:     if (_cpuid_info.std_cpuid1_rcx.bits.sse4_2 != 0)
kvn@840:       result |= CPU_SSE4_2;
duke@435:     return result;
duke@435:   }
duke@435: 
duke@435:   static void get_processor_features();
duke@435: 
duke@435: public:
duke@435:   // Offsets for cpuid asm stub
duke@435:   static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
duke@435:   static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_rax); }
duke@435:   static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_rax); }
duke@435:   static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_rax); }
duke@435:   static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_rax); }
duke@435:   static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_rax); }
duke@435: 
duke@435:   // Initialization
duke@435:   static void initialize();
duke@435: 
duke@435:   // Asserts
duke@435:   static void assert_is_initialized() {
duke@435:     assert(_cpuid_info.std_cpuid1_rax.bits.family != 0, "VM_Version not initialized");
duke@435:   }
duke@435: 
duke@435:   //
duke@435:   // Processor family:
duke@435:   //       3   -  386
duke@435:   //       4   -  486
duke@435:   //       5   -  Pentium
duke@435:   //       6   -  PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
duke@435:   //              Pentium M, Core Solo, Core Duo, Core2 Duo
duke@435:   //    family 6 model:   9,        13,       14,        15
duke@435:   //    0x0f   -  Pentium 4, Opteron
duke@435:   //
duke@435:   // Note: The cpu family should be used to select between
duke@435:   //       instruction sequences which are valid on all Intel
duke@435:   //       processors.  Use the feature test functions below to
duke@435:   //       determine whether a particular instruction is supported.
duke@435:   //
duke@435:   static int  cpu_family()        { return _cpu;}
duke@435:   static bool is_P6()             { return cpu_family() >= 6; }
duke@435: 
duke@435:   static bool is_amd()            { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
duke@435:   static bool is_intel()          { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
duke@435: 
duke@435:   static uint cores_per_cpu()  {
duke@435:     uint result = 1;
duke@435:     if (is_intel()) {
duke@435:       result = (_cpuid_info.dcp_cpuid4_rax.bits.cores_per_cpu + 1);
duke@435:     } else if (is_amd()) {
duke@435:       result = (_cpuid_info.ext_cpuid8_rcx.bits.cores_per_cpu + 1);
duke@435:     }
duke@435:     return result;
duke@435:   }
duke@435: 
duke@435:   static uint threads_per_core()  {
duke@435:     uint result = 1;
duke@435:     if (_cpuid_info.std_cpuid1_rdx.bits.ht != 0) {
duke@435:       result = _cpuid_info.std_cpuid1_rbx.bits.threads_per_cpu /
duke@435:                cores_per_cpu();
duke@435:     }
duke@435:     return result;
duke@435:   }
duke@435: 
duke@435:   static intx L1_data_cache_line_size()  {
duke@435:     intx result = 0;
duke@435:     if (is_intel()) {
duke@435:       result = (_cpuid_info.dcp_cpuid4_rbx.bits.L1_line_size + 1);
duke@435:     } else if (is_amd()) {
duke@435:       result = _cpuid_info.ext_cpuid5_rcx.bits.L1_line_size;
duke@435:     }
duke@435:     if (result < 32) // not defined ?
duke@435:       result = 32;   // 32 bytes by default on x86
duke@435:     return result;
duke@435:   }
duke@435: 
duke@435:   //
duke@435:   // Feature identification
duke@435:   //
duke@435:   static bool supports_cpuid()    { return _cpuFeatures  != 0; }
duke@435:   static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }
duke@435:   static bool supports_cmov()     { return (_cpuFeatures & CPU_CMOV) != 0; }
duke@435:   static bool supports_fxsr()     { return (_cpuFeatures & CPU_FXSR) != 0; }
duke@435:   static bool supports_ht()       { return (_cpuFeatures & CPU_HT) != 0; }
duke@435:   static bool supports_mmx()      { return (_cpuFeatures & CPU_MMX) != 0; }
duke@435:   static bool supports_sse()      { return (_cpuFeatures & CPU_SSE) != 0; }
duke@435:   static bool supports_sse2()     { return (_cpuFeatures & CPU_SSE2) != 0; }
duke@435:   static bool supports_sse3()     { return (_cpuFeatures & CPU_SSE3) != 0; }
duke@435:   static bool supports_ssse3()    { return (_cpuFeatures & CPU_SSSE3)!= 0; }
kvn@840:   static bool supports_sse4_1()   { return (_cpuFeatures & CPU_SSE4_1) != 0; }
kvn@840:   static bool supports_sse4_2()   { return (_cpuFeatures & CPU_SSE4_2) != 0; }
duke@435:   //
duke@435:   // AMD features
duke@435:   //
duke@435:   static bool supports_3dnow()    { return (_cpuFeatures & CPU_3DNOW) != 0; }
duke@435:   static bool supports_mmx_ext()  { return is_amd() && _cpuid_info.ext_cpuid1_rdx.bits.mmx_amd != 0; }
duke@435:   static bool supports_3dnow2()   { return is_amd() && _cpuid_info.ext_cpuid1_rdx.bits.tdnow2 != 0; }
duke@435:   static bool supports_sse4a()    { return (_cpuFeatures & CPU_SSE4A) != 0; }
duke@435: 
duke@435:   static bool supports_compare_and_exchange() { return true; }
duke@435: 
duke@435:   static const char* cpu_features()           { return _features_str; }
duke@435: 
duke@435:   static intx allocate_prefetch_distance() {
duke@435:     // This method should be called before allocate_prefetch_style().
duke@435:     //
duke@435:     // Hardware prefetching (distance/size in bytes):
duke@435:     // Pentium 3 -  64 /  32
duke@435:     // Pentium 4 - 256 / 128
duke@435:     // Athlon    -  64 /  32 ????
duke@435:     // Opteron   - 128 /  64 only when 2 sequential cache lines accessed
duke@435:     // Core      - 128 /  64
duke@435:     //
duke@435:     // Software prefetching (distance in bytes / instruction with best score):
duke@435:     // Pentium 3 - 128 / prefetchnta
duke@435:     // Pentium 4 - 512 / prefetchnta
duke@435:     // Athlon    - 128 / prefetchnta
duke@435:     // Opteron   - 256 / prefetchnta
duke@435:     // Core      - 256 / prefetchnta
duke@435:     // It will be used only when AllocatePrefetchStyle > 0
duke@435: 
duke@435:     intx count = AllocatePrefetchDistance;
duke@435:     if (count < 0) {   // default ?
duke@435:       if (is_amd()) {  // AMD
duke@435:         if (supports_sse2())
duke@435:           count = 256; // Opteron
duke@435:         else
duke@435:           count = 128; // Athlon
duke@435:       } else {         // Intel
duke@435:         if (supports_sse2())
duke@435:           if (cpu_family() == 6) {
duke@435:             count = 256; // Pentium M, Core, Core2
duke@435:           } else {
duke@435:             count = 512; // Pentium 4
duke@435:           }
duke@435:         else
duke@435:           count = 128; // Pentium 3 (and all other old CPUs)
duke@435:       }
duke@435:     }
duke@435:     return count;
duke@435:   }
duke@435:   static intx allocate_prefetch_style() {
duke@435:     assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
duke@435:     // Return 0 if AllocatePrefetchDistance was not defined or
duke@435:     // prefetch instruction is not supported.
duke@435:     return (AllocatePrefetchDistance > 0 &&
duke@435:             (supports_3dnow() || supports_sse())) ? AllocatePrefetchStyle : 0;
duke@435:   }
duke@435: };